Si826x 5 KV LED EMULATOR INPUT, 4.0 A ISOLATED GATE DRIVERS Features Pin-compatible, drop-in upgrades for popular high speed opto-coupled gate drivers Low power diode emulator simplifies design-in process 0.6 and 4.0 Amp peak output drive current Rail-to-rail output voltage Performance and reliability advantages vs. opto-drivers Resistant to temperature and age 10x lower FIT rate for longer service life 14x tighter part-to-part matching Higher common-mode transient immunity: >50 kV/µs typical Robust protection features Multiple UVLO ordering options (5, 8, and 12 V) with hysteresis 60 ns propagation delay, independent of input drive current Wide VDD range: 6.5 to 30 V Up to 5000 VRMS isolation 10 kV surge withstand capability AEC-Q100 qualified Wide operating temperature range –40 to +125 °C RoHS-compliant packages SOIC-8 (Narrow body) DIP8 (Gull-wing) SDIP6 (Stretched SO-6) LGA8 Pin Assignments: See page 22 1 ANODE 2 7 VO CATHODE 3 6 VO NC 4 5 GND SOIC-8, DIP8, LGA8 Industry Standard Pinout 6 VDD 5 VO 4 GND UVLO Applications IGBT/ MOSFET gate drives Industrial, HEV and renewable energy inverters AC, Brushless, and DC motor controls and drives VDD e ANODE 1 8 UVLO Variable speed motor control in consumer white goods Isolated switch mode and UPS power supplies NC 2 e CATHODE 3 SDIP6 Industry Standard Pinout Safety Regulatory Approvals UL 1577 recognized VDE certification conformity Up to 5000 Vrms for 1 minute IEC60747-5-2/VDE0884-10 (basic/reinforced insulation) CSA component notice 5A approval CQC certification approval IEC 60950-1, 61010-1, 60601-1 GB4943.1 (reinforced insulation) Patent pending Description The Si826x isolators are pin-compatible, drop-in upgrades for popular optocoupled gate drivers, such as 0.6 A ACPL-0302/3020, 2.5 A HCPL-3120/ACPL3130, HCNW3120/3130, and similar opto-drivers. The devices are ideal for driving power MOSFETs and IGBTs used in a wide variety of inverter and motor control applications. The Si826x isolated gate drivers utilize Silicon Laboratories' proprietary silicon isolation technology, supporting up to 5.0 kVRMS withstand voltage per UL1577 and 10kV surge protection per IEC60747. This technology enables higher-performance, reduced variation with temperature and age, tighter part-to-part matching, and superior common-mode rejection compared to optocoupled gate drivers. While the input circuit mimics the characteristics of an LED, less drive current is required, resulting in higher efficiency. Propagation delay time is independent of input drive current, resulting in consistently short propagation times, tighter unit-to-unit variation, and greater input circuit design flexibility. As a result, the Si826x series offers longer service life and dramatically higher reliability compared to opto-coupled gate drivers. Rev. 1.3 5/15 Copyright © 2015 by Silicon Laboratories Si826x Si826x Functional Block Diagram Diode Emulator VDD A1 REC XMIT Output Driver OUT IF C1 GND 2 Rev. 1.3 Si826x TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4. Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.1. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.3. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1. Input Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2. Output Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6. Pin Descriptions (SOIC-8, DIP8, LGA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 7. Pin Descriptions (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11. Package Outline: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 12. Land Pattern: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13. Package Outline: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14. Land Pattern: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 15. Package Outline: LGA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 16. Land Pattern: LGA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 17. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17.1. Si826x Top Marking (Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 17.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17.3. Si826x Top Marking (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 17.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 17.5. Si826x Top Marking (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.6. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.7. Si826x Top Marking (LGA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 17.8. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Rev. 1.3 3 Si826x 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Supply Voltage Input Current Operating Temperature (Ambient) Symbol Min Typ Max Unit VDD 6.5 — 30 V IF(ON) (see Figure 1) 6 — 30 mA TA –40 — 125 °C Table 2. Electrical Characteristics 1 VDD = 15 V or 30 V, GND = 0 V, IF = 6 mA, TA = –40 to +125 °C; typical specs at 25 °C Parameter Symbol Test Condition Min Typ Max Unit Supply Voltage2 VDD (VDD – GND) 6.5 — 30 V Supply Current (Output High) IDD IF = 10 mA VDD = 15 V VDD = 30 V — — 1.8 2.0 2.4 2.7 mA mA Supply Current (Output Low) IDD VF = 0 V; IF = 0 mA VDD = 15 V VDD = 30 V — — 1.5 1.7 2.1 2.4 mA mA DC Parameters Input Current Threshold IF(TH) — — 3.6 mA Input Current Hysteresis IHYS — 0.34 — mA Input Forward Voltage (OFF) VF(OFF) Measured at ANODE with respect to CATHODE. — — 1 V Input Forward Voltage (ON) VF(ON) Measured at ANODE with respect to CATHODE. 1.6 — 2.8 V CI f = 100 kHz, VF = 0 V, VF = 2 V — — 15 15 — — pF Si826xAxx devices — 15 — Si826xBxx devices (IOH = -1 A) — 2.6 5.1 Si826xAxx devices — 5 — Si826xBxx devices (IOL = 2 A) — 0.8 2.0 Input Capacitance Output Resistance High (Source)3 Output Resistance Low (Sink)3 ROH ROL Notes: 1. See "8.Ordering Guide" on page 23 for more information. 2. Minimum value of (VDD - GND) decoupling capacitor is 1 µF. 3. Both VO pins are required to be shorted together for 4.0 A compliance. 4. When performing this test, it is recommended that the DUT be soldered down to the PCB to reduce parasitic inductances, which may cause over-stress conditions due to excessive ringing. 5. Guaranteed by characterization. 4 Rev. 1.3 Si826x Table 2. Electrical Characteristics (Continued)1 VDD = 15 V or 30 V, GND = 0 V, IF = 6 mA, TA = –40 to +125 °C; typical specs at 25 °C Parameter Output High Current (Source)3,4 Symbol IOH Test Condition Min Typ Max Si826xAxx devices (IF = 0), (tPW_IOH < 250 ns) (see Figure 3) — 0.4 — Si826xBxx devices (IF = 0), (tPW_IOH < 250 ns), (VDD – VO = 7.5 V) (see Figure 3) Si826xAxx devices (IF = 10 mA), (tPW_IOL < 250 ns) (see Figure 2) Output Low Current (Sink)3,4 High-Level Output Voltage Low-Level Output Voltage IOL VOH VOL Si826xBxx devices (IF = 10 mA), (tPW_IOL < 250 ns), (VO - GND = 4.2 V) (see Figure 2) Unit A 0.5 1.8 — — 0.6 — A 1.2 4.0 — Si826xAxx devices (I OUT = –100 mA) — VDD– 0.4 — Si826xBxx devices (I OUT = –100 mA) VDD– 0.5 VDD– 0.25 — Si826xBxx devices (I OUT = 0 mA), (IF = 0 mA) — VDD — Si826xAxx devices (I OUT = 100 mA), (IF = 10 mA) — 320 — Si826xBxx devices (I OUT = 100 mA), (IF = 10 mA) — 80 200 V mV UVLO Threshold + (Si826xxAx mode) VDDUV+ See Figure 11 on page 16. VDD rising 5 5.6 6.3 V UVLO Threshold – (Si826xxAx mode) VDDUV– See Figure 11 on page 16. VDD falling 4.7 5.3 6.0 V — 300 — mV UVLO lockout hysteresis (Si826xxAx mode) VDDHYS Notes: 1. See "8.Ordering Guide" on page 23 for more information. 2. Minimum value of (VDD - GND) decoupling capacitor is 1 µF. 3. Both VO pins are required to be shorted together for 4.0 A compliance. 4. When performing this test, it is recommended that the DUT be soldered down to the PCB to reduce parasitic inductances, which may cause over-stress conditions due to excessive ringing. 5. Guaranteed by characterization. Rev. 1.3 5 Si826x Table 2. Electrical Characteristics (Continued)1 VDD = 15 V or 30 V, GND = 0 V, IF = 6 mA, TA = –40 to +125 °C; typical specs at 25 °C Parameter Symbol Test Condition Min Typ Max Unit UVLO Threshold + (Si826xxBx mode) VDDUV+ See Figure 12 on page 16. VDD rising 7.5 8.4 9.4 V UVLO Threshold – (Si826xxBx mode) VDDUV– See Figure 12 on page 16. VDD falling 6.9 7.9 8.9 V — 500 — mV UVLO lockout hysteresis (Si826xxBx mode) VDDHYS UVLO Threshold + (Si826xxCx mode) VDDUV+ See Figure 13 on page 16. VDD rising 10.5 12 13.5 V UVLO Threshold – (Si826xxCx mode) VDDUV– See Figure 13 on page 16. VDD falling 9.4 10.7 12.2 V UVLO lockout hysteresis (Si826xxCx mode) VDDHYS — 1.3 — V AC Switching Parameters Input noise filter cut-off pulse width tNFC — — 15 ns Minimum pulse width tPMIN — 30 — ns Propagation delay (Low-to-High) tPLH CL = 200 pF 20 40 60 ns Propagation delay (High-to-Low) tPHL CL = 200 pF 10 30 50 ns Pulse Width Distortion PWD |tPLH – tPHL| — 17 28 ns Propagation Delay Difference5 PDD tPHLMAX – tPLHMIN -1 — 25 ns Rise time tR CL = 200 pF — 5.5 15 ns Fall time tF CL = 200 pF — 8.5 20 ns — 16 30 µs 35 50 — kV/µs Device Startup Time tSTART Common Mode Transient Immunity CMTI Output = low or high (VCM = 1500 V), (IF > 6 mA) (See Figure 4) Notes: 1. See "8.Ordering Guide" on page 23 for more information. 2. Minimum value of (VDD - GND) decoupling capacitor is 1 µF. 3. Both VO pins are required to be shorted together for 4.0 A compliance. 4. When performing this test, it is recommended that the DUT be soldered down to the PCB to reduce parasitic inductances, which may cause over-stress conditions due to excessive ringing. 5. Guaranteed by characterization. 6 Rev. 1.3 Si826x 10 Anode Anode 2.2 V ESD e 700 Cathode Cathode AnodetoCathodeVoltage[V] 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 5 10 15 20 25 30 DiodeEmulatorInputCurrent[mA] Figure 1. Diode Emulator Model and I-V Curve VDD = 15 V VDD IN 10 OUT Si826x SCHOTTKY GND 1 µF 100 µF 9V + _ INPUT 1 µF CER Measure 10 µF EL RSNS 0.1 50 ns IF GND 200 ns INPUT WAVEFORM Figure 2. IOL Sink Current Test Circuit Rev. 1.3 7 Si826x VDD = 15 V VDD IN Si826x 10 OUT SCHOTTKY VSS 1 µF 100 µF 5.5 V INPUT 1 µF CER Measure 10 µF EL RSNS 0.1 50 ns IF GND 200 ns INPUT WAVEFORM Figure 3. IOH Source Current Test Circuit 15 V Supply Si826x 267 Input Signal Switch Anode VDD 5V Isolated Supply VO Oscilloscope Cathode GND Isolated Ground Input High Voltage Differential Probe Output Vcm Surge Output High Voltage Surge Generator Figure 4. Common Mode Transient Immunity Characterization Circuit 8 Rev. 1.3 + _ Si826x 2. Regulatory Information Table 3. Regulatory Information* CSA The Si826x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage. 60950-1: Up to 1000 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. 60601-1: Up to 250 VRMS reinforced insulation working voltage; up to 500 VRMS basic insulation working voltage. VDE The Si826x is certified according to IEC60747 and VDE0884. For more details, see File 5006301-4880-0001. 60747-5-2: Up to 1414 Vpeak for basic insulation working voltage. VDE0884-10: Up to 1414 Vpeak for reinforced insulation working voltage. UL The Si826x is certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 5000 VRMS isolation voltage for basic protection. CQC The Si826x is certified under GB4943.1-2011. For more details, see certificates CQC14001104575, CQC15001121282 and CQC15001121283. Rated up to 1000 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. *Note: Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec. For more information, see "8.Ordering Guide" on page 23. Table 4. Insulation and Safety-Related Specifications Parameter Symbol Test Condition Value SOIC-8 DIP8 SDIP6 LGA8 Unit Nominal Air Gap (Clearance) L(IO1) 4.7 min 7.2 min 9.6 min 10.0 min mm Nominal External Tracking (Creepage) L(IO2) 3.9 min 7.0 min 8.3 min 10.0 min mm 0.016 0.016 0.016 0.016 mm 600 600 600 600 V Minimum Internal Gap (Internal Clearance) Tracking Resistance (Proof Tracking Index) PTI Erosion Depth ED 0.031 0.031 0.057 0.021 mm Resistance (Input-Output)* RIO 1012 1012 1012 1012 Capacitance (Input-Output)* CIO 1 1 1 1 pF IEC60112 f = 1 MHz *Note: To determine resistance and capacitance, the Si826x is converted into a 2-terminal device. Pins 1–4 (1–3, SDIP6) are shorted together to form the first terminal, and pins 5–8 (4–6, SDIP6) are shorted together to form the second terminal. The parameters are then measured between these two terminals. Rev. 1.3 9 Si826x Table 5. IEC 60664-1 (VDE 0884) Ratings Parameter Specification Test Conditions Basic Isolation Group SOIC-8 Material Group Installation Classification DIP8 SDIP6 LGA8 I I I I Rated Mains Voltages < 150 VRMS I-IV I-IV I-IV I-IV Rated Mains Voltages < 300 VRMS I-IV I-IV I-IV I-IV Rated Mains Voltages < 450 VRMS I-III I-III I-IV I-IV Rated Mains Voltages < 600 VRMS I-III I-III I-IV I-IV Rated Mains Voltages < 1000 VRMS I-II I-II I-III I-III Table 6. IEC 60747-5-2 (VDE 0884-10) Insulation Characteristics* Parameter Symbol Maximum Working Insulation Voltage Characteristic Test Condition DIP8 SDIP6 LGA8 630 891 1140 1414 V peak VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) 1181 1671 2138 2652 V peak VIOTM t = 60 sec 6000 6000 8000 8000 V peak 2 2 2 2 >109 >109 >109 >109 VIORM Input to Output Test Voltage Transient Overvoltage Unit SOIC-8 Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V RS *Note: This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The Si826x provides a climate classification of 40/125/21. Table 7. IEC Safety Limiting Values* Parameter Symbol Case Temperature Input Current TS IS Output Power PS Test Condition JA = 110 °C/W (SOIC-8), 110 °C/W (DIP8), 105 °C/W (SDIP6), 220 °C (LGA8), VF = 2.8 V, TJ = 140 °C, TA = 25 °C SOIC-8 140 370 1 Max DIP8 SDIP6 140 140 370 390 1 1 LGA8 140 185 0.5 *Note: Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 5, 6, 7, and 8. 10 Rev. 1.3 Unit °C mA W Si826x Table 8. Thermal Characteristics Parameter JA IC Junction-to-Air Thermal Resistance OutputPo owerͲ Ps,InputCurrentͲ Is Typ Symbol SOIC-8 DIP8 SDIP6 LGA8 110 110 105 220 Unit ºC/W 1200 1000 Ps(mW) 800 600 Is(mA) 400 200 0 0 20 40 60 80 100 120 140 TsͲ CaseTemperature(°C) OutputPo owerͲ Ps,InputCurrentͲ Is Figure 5. (SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 and VDE0884-10 1200 1000 Ps(mW) 800 600 Is(mA) 400 200 0 0 20 40 60 80 100 120 140 TsͲ CaseTemperature(°C) Figure 6. (DIP8) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 and VDE0884-10 Rev. 1.3 11 OutputPo owerͲ Ps,InputCurrentͲ Is Si826x 1200 1000 Ps(mW) 800 600 Is(mA) 400 200 0 0 20 40 60 80 100 120 140 TsͲ CaseTemperature(°C) OutputPo owerͲ Ps,InputCurrentͲ Is Figure 7. (SDIP6) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 and VDE0884-10 600 500 Ps(mW) 400 300 Is(mA) 200 100 0 0 20 40 60 80 100 120 140 TsͲ CaseTemperature(°C) Figure 8. (LGA8) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 and VDE0884-10 12 Rev. 1.3 Si826x Table 9. Absolute Maximum Ratings* Parameter Symbol Min Max Unit TSTG –65 +150 °C Operating Temperature TA –40 +125 °C Junction Temperature TJ — +140 °C IF(AVG) — 30 mA Peak Transient Input Current (< 1 µs pulse width, 300 ps) IFTR — 1 A Reverse Input Voltage VR — 0.3 V Supply Voltage VDD –0.5 36 V Output Voltage VOUT –0.5 36 V Peak Output Current (tPW = 10 µs, duty cycle = 0.2%) (0.6 Amp versions) IOPK — 0.6 A Peak Output Current (tPW = 10 µs, duty cycle = 0.2%) (4.0 Amp versions) IOPK — 4.0 A Input Power Dissipation PI — 75 mW Output Power Dissipation PO — 225 mW Total Power Dissipation (all packages limited by thermal derating curve) PT — 300 mW Lead Solder Temperature (10 s) — 260 °C HBM Rating ESD 4 — kV Machine Model ESD 300 — V CDM 2000 — V Maximum Isolation Voltage (1 s) SOIC-8 — 4500 VRMS Maximum Isolation Voltage (1 s) DIP8 — 6500 VRMS Maximum Isolation Voltage (1 s) SDIP6 — 6500 VRMS Maximum Isolation Voltage (1 s) LGA8 — 6500 VRMS Storage Temperature Average Forward Input Current *Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions specified in the operational sections of this data sheet. Rev. 1.3 13 Si826x 3. Functional Description 3.1. Theory of Operation The Si826x is a functional upgrade for popular opto-isolated drivers, such as the Avago HPCL-3120, HPCL-0302, Toshiba TLP350, and others. The operation of an Si826x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. The Si826x also includes a noise filter that suppresses propagation of any pulse narrower than 15 ns. A simplified block diagram for the Si826x is shown in Figure 9. Transmitter Receiver RF OSCILLATOR VDD A LED Emulator MODULATOR SemiconductorBased Isolation Barrier DEMODULATOR + NOISE FILTER B 0.6 to 4.0 A peak Gnd Figure 9. Simplified Channel Diagram 14 Rev. 1.3 Si826x 4. Technical Description 4.1. Device Behavior Truth tables for the Si826x are summarized in Table 10. Table 10. Si826x Truth Table Summary* Input VDD VO OFF > UVLO LOW OFF < UVLO LOW ON > UVLO HIGH ON < UVLO LOW *Note: This truth table assumes VDD is powered. If VDD is below UVLO, see "4.3.Under Voltage Lockout (UVLO)" on page 16 for more information. 4.2. Device Startup Output VO is held low during power-up until VDD rises above the UVLO+ threshold for a minimum time period of tSTART. Following this, the output is high when the current flowing from anode to cathode is > IF(ON). Device startup, normal operation, and shutdown behavior is shown in Figure 10. UVLO+ UVLO- VDDHYS VDD IF(ON) IHYS IF tSTART tPHL tPLH tSTART VO Figure 10. Si826x Operating Behavior (IF > IF(MIN) when VF > VF(MIN)) Rev. 1.3 15 Si826x 4.3. Under Voltage Lockout (UVLO) The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Referring to Figures 11 through 13, upon power up, the Si826x is maintained in UVLO until VDD rises above VDDUV+. During power down, the Si826x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDDUV+ – VDDHYS). V DDUV+ (Typ) 3.5 Output Voltage (VO) Output Voltage (VO) V DDUV+ (Typ) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 9.5 Supply Voltage (V DD - GND) (V) Output Voltage (VO) 7.0 7.5 8.0 8.5 9.0 9.5 10.0 Supply Voltage (V DD - GND) (V) Figure 12. Si826xxBX UVLO Response (8 V) 16 12.0 12.5 13.0 Figure 13. Si826xxCx UVLO Response (12 V) V DDUV+ (Typ) 6.5 10.5 11.0 11.5 Supply Voltage (V DD - GND) (V) Figure 11. Si826xxAx UVLO Response (5 V) 6.0 10.0 Rev. 1.3 Si826x 5. Applications The following sections detail the input and output circuits necessary for proper operation. Power dissipation and layout considerations are also discussed. 5.1. Input Circuit Design Opto driver manufacturers typically recommend the circuits shown in Figures 14 and 15. These circuits are specifically designed to improve opto-coupler input common-mode rejection and increase noise immunity. Si826x Vext 1 N/C R1 2 ANODE 3 CATHODE Control Input Open Drain or Collector 4 N/C Figure 14. Si826x Input Circuit Vext Si826x 1 N/C 2 ANODE Control Input Q1 3 CATHODE R1 4 N/C Figure 15. High CMR Si826x Input Circuit The optically-coupled driver circuit of Figure 14 turns the LED on when the control input is high. However, internal capacitive coupling from the LED to the power and ground conductors can momentarily force the LED into its off state when the anode and cathode inputs are subjected to a high common-mode transient. The circuit shown in Figure 15 addresses this issue by using a value of R1 sufficiently low to overdrive the LED, ensuring it remains on during an input common-mode transient. Q1 shorts the LED off in the low output state, again increasing commonmode transient immunity. Some opto driver applications recommend reverse-biasing the LED when the control input is off to prevent coupled noise from energizing the LED. The Si826x input circuit requires less current and has twice the off-state noise margin compared to opto couplers. However, high CMR opto coupler designs that overdrive the LED (see Figure 15) may require increasing the value of R1 to limit input current IF to its maximum rating when using the Si826x. In addition, there is no benefit in driving the Si826x input diode into reverse bias when in the off state. Rev. 1.3 17 Si826x Consequently, opto coupler circuits using this technique should either leave the negative bias circuitry unpopulated or modify the circuitry (e.g., add a clamp diode or current limiting resistor) to ensure that the anode pin of the Si826x is no more than –0.3 V with respect to the cathode when reverse-biased. New designs should consider the input circuit configurations of Figure 16, which are more efficient than those of Figures 14 and 15. As shown, S1 and S2 represent any suitable switch, such as a BJT or MOSFET, analog transmission gate, processor I/O, etc. Also, note that the Si826x input can be driven from the I/O port of any MCU or FPGA capable of sourcing a minimum of 6 mA (see Figure 16C). Additionally, note that the Si826x propagation delay and output drive do not significantly change for values of IF between IF(MIN) and IF(MAX). Si826x Vext 1 N/C 2 ANODE Control Input R1 3 CATHODE 4 N/C Control Input S1 See Text Si826x Si826x Vext S1 R1 1 N/C 2 ANODE S2 3 4 1 N/C 2 ANODE CATHODE 3 CATHODE N/C 4 N/C MCU I/O Port pin B A R1 C Figure 16. Si826x Other Input Circuit Configurations 5.2. Output Circuit Design GND can be biased at, above, or below ground as long as the voltage on VDD with respect to GND is a maximum of 30 V. VDD decoupling capacitors should be placed as close to the package pins as possible. The optimum values for these capacitors depend on load current and the distance between the chip and its power source. It is recommended that 0.1 and 10 µF bypass capacitors be used to reduce high-frequency noise and maximize performance. 5.3. Layout Considerations It is most important to minimize ringing in the drive path and noise on the VDD lines. Care must be taken to minimize parasitic inductance in these paths by locating the Si826x as close as possible to the device it is driving. In addition, the VDD supply and ground trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground plane system having separate ground and VDD planes for power devices and small signal components provides the best overall noise performance. 18 Rev. 1.3 Si826x 5.4. Power Dissipation Considerations Proper system design must assure that the Si826x operates within safe thermal limits across the entire load range. The Si826x total power dissipation is the sum of the power dissipated by bias supply current, internal switching losses, and power delivered to the load, as shown in Equation 1. P D = I F V F DC + V DD I DDQ + Q d + C L V DD f where: P D is the total device power dissipation (W) I F is the diode current (30 mA max) VF is the diode anode to cathode voltage (2.8 V max) DC is duty cycle (0.5 typical) VDD is the driver-side supply voltage (30 V max) I DDQ is the driver maximum bias current (2.5 mA) Q d is 3 nC C L is the load capacitance f is the switching frequency (Hz) Equation 1. The maximum allowable power dissipation for the Si826x is a function of the package thermal resistance, ambient temperature, and maximum allowable junction temperature, as shown in Equation 2. T jmax – T A P Dmax -------------------------- ja where: P Dmax is the maximum allowable power dissipation (W) T jmax is the maximum junction temperature (140 °C) T A is the ambient temperature (°C) ja is the package junction-to-air thermal resistance (110 °C/W) Equation 2. Substituting values for PDmax Tjmax, TA, and ja into Equation 2 results in a maximum allowable total power dissipation of 1.0 W. Note that the maximum allowable load is found by substituting this limit and the appropriate datasheet values from Table 2 on page 4 into Equation 1 and simplifying. Graphs are shown in Figures 17 and 18. All points along the load lines in these graphs represent the package dissipation-limited value of CL for the corresponding switching frequency. Rev. 1.3 19 Si826x 10000.0 1000.0 7V 12V 18V 100.0 MaxLoad(nF) 30V 10.0 1.0 0.1 10 100 1000 Frequency(kHz) Figure 17. (SOIC-8, DIP8, SDIP6) Maximum Load vs. Switching Frequency (25 °C) 10000.0 1000.0 7V 12V 18V 100.0 MaxLoad(nF) 30V 10.0 1.0 0.1 10 100 1000 Frequency(kHz) Figure 18. (LGA8) Maximum Load vs. Switching Frequency (25 °C) 20 Rev. 1.3 Si826x 6. Pin Descriptions (SOIC-8, DIP8, LGA8) NC 1 8 VDD 7 VO UVLO ANODE 2 e CATHODE 3 6 VO NC 4 5 GND SOIC-8, DIP8, LGA8 Industry Standard Pinout Figure 19. Pin Configuration Table 11. Pin Descriptions (SOIC-8, DIP8, LGA8) Pin Name 1 NC* 2 ANODE 3 Description No connect. Anode of LED emulator. VO follows the signal applied to this input with respect to the CATHODE input. CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input. 4 NC* No connect. 5 GND External MOSFET source connection and ground reference for VDD. This terminal is typically connected to ground but may be tied to a negative or positive voltage. 6 VO Output signal. Both VO pins are required to be shorted together for 4.0 A compliance. 7 VO Output signal. Both VO pins are required to be shorted together for 4.0 A compliance. 8 VDD Output-side power supply input referenced to GND (30 V max). *Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be connected to the ground plane. Rev. 1.3 21 Si826x 7. Pin Descriptions (SDIP6) ANODE 1 6 VDD 5 VO 4 GND UVLO NC 2 e CATHODE 3 SDIP6 Industry Standard Pinout Figure 20. Pin Configuration Table 12. Pin Descriptions (SDIP6) Pin Name 1 ANODE 2 NC* 3 Description Anode of LED emulator. VO follows the signal applied to this input with respect to the CATHODE input. No connect. CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input. External MOSFET source connection and ground reference for VDD. This terminal is typically connected to ground but may be tied to a negative or positive voltage. 4 GND 5 VO Output signal. 6 VDD Output-side power supply input referenced to GND (30 V max). *Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be connected to the ground plane. 22 Rev. 1.3 Si826x 8. Ordering Guide Table 13. Si826x Ordering Guide1,2,3 Ordering Options New Ordering Part Number (OPN) Output Configuration Cross Reference UVLO Voltage Insulation Rating Temp Range Pkg Type Si8261AAC-C-IS 0.6 A driver HCPL-0314 5V 3.75 kVrms –40 to +125 °C SOIC-8 Si8261BAC-C-IS 4.0 A driver — 5V 3.75 kVrms –40 to +125 °C SOIC-8 Si8261AAC-C-IP 0.6 A driver HCPL-3140 5V 3.75 kVrms –40 to +125 °C DIP8/GW Si8261BAC-C-IP 4.0 A driver TLP 350 HCPL-3120 5V 3.75 kVrms –40 to +125 °C DIP8/GW Si8261AAD-C-IS 0.6 A driver ACPL-W314 5V 5.0 kVrms –40 to +125 °C SDIP6 Si8261BAD-C-IS 4.0 A driver TLP 700F 5V 5.0 kVrms –40 to +125 °C SDIP6 Si8261AAD-C-IM 0.6 A driver — 5V 5.0 kVrms –40 to +125 °C LGA8 Si8261BAD-C-IM 4.0 A driver HCNW-3120 5V 5.0 kVrms –40 to +125 °C LGA8 Notes: 1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry standard classifications. 2. “Si” and “SI” are used interchangeably. 3. AEC-Q100 qualified. Rev. 1.3 23 Si826x Table 13. Si826x Ordering Guide1,2,3 Ordering Options New Ordering Part Number (OPN) Output Configuration Cross Reference UVLO Voltage Insulation Rating Temp Range Pkg Type Si8261ABC-C-IS 0.6 A driver HCPL-0314 8V 3.75 kVrms –40 to +125 °C SOIC-8 Si8261BBC-C-IS 4.0 A driver — 8V 3.75 kVrms –40 to +125 °C SOIC-8 Si8261ABC-C-IP 0.6 A driver HCPL-3140 8V 3.75 kVrms –40 to +125 °C DIP8/GW Si8261BBC-C-IP 4.0 A driver TLP 350 HCPL-3120 8V 3.75 kVrms –40 to +125 °C DIP8/GW Si8261ABD-C-IS 0.6 A driver ACPL-W314 8V 5.0 kVrms –40 to +125 °C SDIP6 Si8261BBD-C-IS 4.0 A driver TLP 700F 8V 5.0 kVrms –40 to +125 °C SDIP6 Si8261ABD-C-IM 0.6 A driver — 8V 5.0 kVrms –40 to +125 °C LGA8 Si8261BBD-C-IM 4.0 A driver HCNW-3120 8V 5.0 kVrms –40 to +125 °C LGA8 Notes: 1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry standard classifications. 2. “Si” and “SI” are used interchangeably. 3. AEC-Q100 qualified. 24 Rev. 1.3 Si826x Table 13. Si826x Ordering Guide1,2,3 Ordering Options New Ordering Part Number (OPN) Output Configuration Cross Reference UVLO Voltage Insulation Rating Temp Range Pkg Type Si8261ACC-C-IS 0.6 A driver HCPL-0314 12 V 3.75 kVrms –40 to +125 °C SOIC-8 Si8261BCC-C-IS 4.0 A driver — 12 V 3.75 kVrms –40 to +125 °C SOIC-8 Si8261ACC-C-IP 0.6 A driver HCPL-3140 12 V 3.75 kVrms –40 to +125 °C DIP8/GW Si8261BCC-C-IP 4.0 A driver TLP 350 HCPL-3120 12 V 3.75 kVrms –40 to +125 °C DIP8/GW Si8261ACD-C-IS 0.6 A driver ACPL-W314 12 V 5.0 kVrms –40 to +125 °C SDIP6 Si8261BCD-C-IS 4.0 A driver TLP 700F 12 V 5.0 kVrms –40 to +125 °C SDIP6 Si8261ACD-C-IM 0.6 A driver — 12 V 5.0 kVrms –40 to +125 °C LGA8 Si8261BCD-C-IM 4.0 A driver HCNW-3120 12 V 5.0 kVrms –40 to +125 °C LGA8 Notes: 1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry standard classifications. 2. “Si” and “SI” are used interchangeably. 3. AEC-Q100 qualified. Rev. 1.3 25 Si826x 9. Package Outline: 8-Pin Narrow Body SOIC Figure 21 illustrates the package details for the Si826x in an 8-pin narrow-body SOIC package. Table 14 lists the values for the dimensions shown in the illustration. Figure 21. 8-Pin Narrow Body SOIC Package Table 14. 8-Pin Narrow Body SOIC Package Diagram Dimensions Symbol Millimeters Min Max A 1.35 1.75 A1 0.10 0.25 A2 1.40 REF 1.55 REF B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 26 1.27 BSC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Rev. 1.3 Si826x 10. Land Pattern: 8-Pin Narrow Body SOIC Figure 22 illustrates the recommended land pattern details for the Si826x in an 8-pin narrow-body SOIC. Table 15 lists the values for the dimensions shown in the illustration. Figure 22. 8-Pin Narrow Body SOIC Land Pattern Table 15. 8-Pin Narrow Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. Rev. 1.3 27 Si826x 11. Package Outline: DIP8 Figure 23 illustrates the package details for the Si826x in a DIP8 package. Table 16 lists the values for the dimensions shown in the illustration. Figure 23. DIP8 Package Table 16. DIP8 Package Diagram Dimensions Dimension Min Max A — 4.19 A1 0.55 0.75 A2 3.17 3.43 b 0.35 0.55 b2 1.14 1.78 b3 0.76 1.14 c 0.20 0.33 D 9.40 9.90 E 7.37 7.87 E1 6.10 6.60 E2 9.40 9.90 e 2.54 BSC. L 0.38 0.89 aaa — 0.25 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 28 Rev. 1.3 Si826x 12. Land Pattern: DIP8 Figure 24 illustrates the recommended land pattern details for the Si826x in a DIP8 package. Table 17 lists the values for the dimensions shown in the illustration. Figure 24. DIP8 Land Pattern Table 17. DIP8 Land Pattern Dimensions* Dimension Min Max C 8.85 8.90 E 2.54 BSC X 0.60 0.65 Y 1.65 1.70 *Note: This Land Pattern Design is based on the IPC-7351 specification. Rev. 1.3 29 Si826x 13. Package Outline: SDIP6 Figure 25 illustrates the package details for the Si826x in an SDIP6 package. Table 18 lists the values for the dimensions shown in the illustration. Figure 25. SDIP6 Package Table 18. SDIP6 Package Diagram Dimensions Dimension Min Max A — 2.65 A1 0.10 0.30 A2 2.05 — b 0.31 0.51 c 0.20 0.33 D 4.58 BSC E 11.50 BSC E1 7.50 BSC e 1.27 BSC Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 30 Rev. 1.3 Si826x Table 18. SDIP6 Package Diagram Dimensions (Continued) Dimension Min Max L 0.40 1.27 h 0.25 0.75 θ 0° 8° aaa — 0.10 bbb — 0.33 ccc — 0.10 ddd — 0.25 eee — 0.10 fff — 0.20 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. Rev. 1.3 31 Si826x 14. Land Pattern: SDIP6 Figure 26 illustrates the recommended land pattern details for the Si826x in an SDIP6 package. Table 19 lists the values for the dimensions shown in the illustration. Figure 26. SDIP6 Land Pattern Table 19. SDIP6 Land Pattern Dimensions* Dimension Min Max C 10.45 10.50 E 1.27 BSC X 0.55 0.60 Y 2.00 2.05 *Note: This Land Pattern Design is based on the IPC-7351 specification. 32 Rev. 1.3 Si826x 15. Package Outline: LGA8 Figure 27 illustrates the package details for the Si826x in an LGA8 package. Table 20 lists the values for the dimensions shown in the illustration. Figure 27. LGA8 Package Table 20. Package Diagram Dimensions Dimension Min Nom Max A 0.74 0.84 0.94 b 1.15 1.20 1.25 D 10.00 BSC. e 2.54 BSC. E 12.50 BSC. L 1.05 1.10 1.15 L1 0.05 0.10 0.15 aaa — — 0.10 bbb — — 0.10 ccc — — 0.10 ddd — — 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.3 33 Si826x 16. Land Pattern: LGA8 Figure 28 illustrates the recommended land pattern details for the Si826x in an LGA8 package. Table 21 lists the values for the dimensions shown in the illustration. Figure 28. LGA8 Land Pattern Table 21. LGA8 Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 11.80 E Pad Row Pitch 2.54 X1 Pad Width 1.30 Y1 Pad Length 1.80 Notes: 1. This Land Pattern Design is based on IPC-7351 specifications. 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. 34 Rev. 1.3 Si826x 17. Top Markings 17.1. Si826x Top Marking (Narrow Body SOIC) 17.2. Top Marking Explanation Customer Part Number 826 = ISOdriver product series C = Input configuration 1 = Opto input type I = Peak output current A = 0.6 A; B = 4.0 A U = UVLO level A = 5 V; B = 8 V; C = 12 V V = Isolation rating C = 3.75 kV; D = 5.0 kV RTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form. “R” indicates revision. Circle = 43 mils Diameter Left-Justified “e4” Pb-Free Symbol YY = Year WW = Work Week Assigned by the Assembly House. Corresponds to the year and work week of the mold date. Line 1 Marking: Line 2 Marking: Line 3 Marking: Rev. 1.3 35 Si826x 17.3. Si826x Top Marking (DIP8) 17.4. Top Marking Explanation Customer Part Number Si826 = ISOdriver product series C = Input configuration 1 = Opto input type I = Peak output current A = 0.6 A; B = 4.0 A U = UVLO level A = 5 V; B = 8 V; C = 12 V V = Isolation rating C = 3.75 kV; D = 5.0 kV YY = Year WW = Work Week Assigned by the Assembly House. Corresponds to the year and work week of the mold date. RTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form. “R” indicates revision. Circle = 51 mils Diameter Center-Justified “e4” Pb-Free Symbol CO = Country of Origin Country of Origin ISO Code Abbreviation Line 1 Marking: Line 2 Marking: Line 3 Marking: 36 Rev. 1.3 Si826x 17.5. Si826x Top Marking (SDIP6) 17.6. Top Marking Explanation Device Si826 = ISOdriver product series C = Input configuration 1 = Opto input type Device Rating I = Peak output current A = 0.6 A; B = 4.0 A U = UVLO level A = 5 V; B = 8 V; C = 12 V V = Isolation rating C = 3.75 kV; D = 5.0 kV RTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form. “R” indicates revision. YY = Year WW = Work Week Assigned by the Assembly House. Corresponds to the year and work week of the mold date. Line 1 Marking: Line 2 Marking: Line 3 Marking: Line 4 Marking: Rev. 1.3 37 Si826x 17.7. Si826x Top Marking (LGA8) 17.8. Top Marking Explanation Device Part Number Si826 = ISOdriver product series C = Input configuration 1 = Opto input type I = Peak output current A = 0.6 A; B = 4.0 A U = UVLO level A = 5 V; B = 8 V; C = 12 V V = Isolation rating C = 3.75 kV; D = 5.0 kV YY = Year WW = Work Week Assigned by the Assembly House. Corresponds to the year and work week of the assembly release. RTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form. “R” indicates revision. Circle = 1.6 mm Diameter Center-Justified “e4” Pb-Free Symbol CO = Country of Origin Country of Origin ISO Code Abbreviation Circle = 0.75 mm Diameter Lower Left-Justified Pin 1 Identifier Line 1 Marking: Line 2 Marking: Line 3 Marking: Line 4 Marking: 38 Rev. 1.3 Si826x DOCUMENT CHANGE LIST Revision 0.9 to Revision 1.0 Updated Table 2 on page 4. Added Figure 1 on page 7. Updated "3.1.Theory of Operation" on page 14. Updated Figures 11, 12, and 13 on page 16. Removed “5.5. Parametric Differences between Si826x and HCPL-0302 and HCPL-3120 Opto Drivers”. Revision 1.0 to Revision 1.1 Updated Figure 1 on page 7. Updated Ordering Guide Table 13 on page 23. Removed references to moisture sensitivity levels from table note. Revision 1.1 to Revision 1.2 Removed “Sampling” from Ordering Guide Table 13 on page 23. Revision 1.2 to Revision 1.3 Updated Table 3 on page 9. Added CQC certificate numbers. Updated Table 5 on page 10. Updated Rated Mains Voltage for 1000 VRMS ratings. Updated Table 6 on page 10. Removed VIOSM specification. Updated Table 9 on page 13. Replaced IO with Peak Output Current IOPK. Updated Figure 14 on page 17. Updated Figure 15 on page 17. Updated Figure 16 on page 18. Changed VDD minimum throughout document to reflect 6.5 V, not 5 V, as normal operation. Rev. 1.3 39 Si826x CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.siliconlabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. 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