Si860x B IDIRECTIONAL I 2 C I SOLA TORS WITH U NIDIRECTIONAL D IGITA L C HANNELS Features Independent, bidirectional SDA and SCL isolation channels Open drain outputs with 35 mA sink current High electromagnetic immunity Wide operating supply voltage 3.0 to 5.5 V Wide temperature range –40 to +125 °C I2C clocks up to 1.7 MHz Transient immunity 50 kV/µs Unidirectional isolation channels support additional system signals AEC-Q100 qualification (Si8605, Si8606) RoHS-compliant packages Up to 5000 VRMS isolation SOIC-8 narrow body SOIC-16 wide body UL, CSA, VDE, CQC recognition SOIC-16 narrow body 60-year life at rated working voltage Supports Applications Isolated I2C, PMBus, SMBus Power over Ethernet Motor Control Systems Hot-swap applications Intelligent Power systems Isolated SMPS systems with PMBus interfaces Description The Si860x series of isolators are single-package galvanic isolation solutions for I2C and SMBus serial port applications. These products are based on Silicon Labs proprietary RF isolation technology and offer shorter propagation delays, lower power consumption, smaller installed size, and more stable operation with temperature and age versus opto couplers or other digital isolators. All devices in this family include hot-swap, bidirectional SDA and/or SCL isolation channels with open-drain, 35 mA sink capability that operate to a maximum frequency of 1.7 MHz. The 8-pin version (Si8600) supports bidirectional SDA and SCL isolation; the Si8602 supports bidirectional SDA and unidirectional SCL isolation, and the 16-pin versions (Si8605, Si8606) feature two unidirectional isolation channels to support additional system signals, such as interrupts or resets. All versions contain protection circuits to guard against data errors when an unpowered device is inserted into a powered system. Small size, low installed cost, low power consumption, and short propagation delays make the Si860x family the optimum solution for isolating I2C and SMBus serial ports. Ordering Information: See page 27. Safety Regulatory Approval VDE certification conformity IEC 60747-5-2 (VDE0884 Part 2) EN60950-1 (reinforced insulation) UL 1577 recognized Up to 5000 VRMS for 1 minute CSA component notice 5A approval CQC certification approval IEC 60950-1, 61010-1, 60601-1 (reinforced insulation) GB4943.1 Rev. 1.4 6/15 Copyright © 2015 by Silicon Laboratories Si860x Si860x 2 Rev. 1.4 Si860x TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. Typical Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1. I2C Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2. I2C Isolator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3. I2C Isolator Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4. I2C Isolator Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5. Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3. Input and Output Characteristics for Non-I2C Digital Channels . . . . . . . . . . . . . . . . 21 4.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 13. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13.1. Si860x Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 36 13.3. Si860x Top Marking (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 13.4. Top Marking Explanation (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 37 13.5. Si860x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 13.6. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . 38 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Rev. 1.4 3 Si860x 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Operating Temperature* Supply Voltage Symbol Min Typ Max Unit TA AVDD BVDD –40 3.0 3.0 25 — — 125* 5.5 5.5 °C V V *Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage. Table 2. Si860x Power Characteristics* 3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C (See Figures 2 and 10 for test diagrams.) Parameter Symbol Test Condition Min Typ Max Unit AVDD Current BVDD Current Idda Iddb All channels = 0 dc — — 5.4 4.3 7.6 6.5 mA mA AVDD Current BVDD Current Idda Iddb All channels = 1 dc — — 2.6 1.9 3.9 2.9 mA mA AVDD Current BVDD Current Idda Iddb All channels = 1.7 MHz — — 3.3 2.6 5.0 3.9 mA mA AVDD Current BVDD Current Idda Iddb All channels = 0 dc — — 1.8 1.8 2.7 2.7 mA mA AVDD Current BVDD Current Idda Iddb All channels = 1 dc — — 4.7 3.1 7.1 4.7 mA mA AVDD Current BVDD Current Idda Iddb All channels = 1.7 MHz — — 2.5 2.1 3.8 3.2 mA mA AVDD Current BVDD Current Idda Iddb All non-I2C channels = 0 All I2C channels = 1 — — 3.4 2.7 5.1 4.1 mA mA AVDD Current BVDD Current Idda Iddb All non-I2C channels = 1 All I2C channels = 0 — — 7.2 6.2 10.1 8.7 mA mA AVDD Current BVDD Current Idda Iddb All non-I2C channels = 5 MHz All I2C channels = 1.7 MHz — — 4.2 3.6 6.3 5.4 mA mA Si8600 Supply Current Si8602 Supply Current Si8605 Supply Current *Note: All voltages are relative to respective ground. 4 Rev. 1.4 Si860x Table 2. Si860x Power Characteristics* (Continued) 3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C (See Figures 2 and 10 for test diagrams.) Parameter Symbol Test Condition Min Typ Max Unit AVDD Current BVDD Current Idda Iddb All non-I2C channels = 0 All I2C channels = 1 — — 2.8 3.0 4.2 4.5 mA mA AVDD Current BVDD Current Idda Iddb All non-I2C channels = 1 All I2C channels = 0 — — 8.3 5.5 11.6 7.7 mA mA AVDD Current BVDD Current Idda Iddb All non-I2C channels = 5 MHz All I2C channels = 1.7 MHz — — 4.1 3.5 6.2 5.3 mA mA Si8606 Supply Current *Note: All voltages are relative to respective ground. Table 3. Si8600/02/05/06 Electrical Characteristics for Bidirectional I2C Channels1 3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C unless otherwise noted. Parameter Min Typ Max Unit 410 540 — — 540 800 I2CV (Side A) 50 — — mV mV mV mV Logic Levels Side B Logic Low Input Voltage Logic High Input Voltage Logic Low Output Voltage I2CVIL (Side B) I2CVIH (Side B) I2CVOL (Side B) ISCLB = 35 mA — 2.0 — — — — 0.8 — 500 V V mV SCL and SDA Logic High Leakage Isdaa, Isdab Iscla, Isclb SDAA, SCLA = VSSA SDAB, SCLB = VSSB — 2.0 10 µA — — 10 10 — — pF pF Logic Levels Side A Logic Input Threshold2 Logic Low Output Voltages Input/Output Logic Low Level Difference3 Pin Capacitance SDAA, SCLA, SDAB, SDBB Symbol I2CVT (Side A) I CVOL (Side A) 2 Test Condition ISDAA, ISCLA (>0.5 mA, <3.0 mA) CA CB Notes: 1. All voltages are relative to respective ground. 2. VIL < 0.410 V, VIH > 0.540 V. 3. I2CV (Side A) = I2CVOL (Side A) – I2CVT (Side A). To ensure no latch-up on a given bus, I2CV (Side A) is the minimum difference between the output logic low level of the driving device and the input logic threshold. 4. Side A measured at 0.6 V. Rev. 1.4 5 Si860x Table 3. Si8600/02/05/06 Electrical Characteristics for Bidirectional I2C Channels1 (Continued) 3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C unless otherwise noted. Parameter Symbol Test Condition Min Typ Max Unit — — 1.7 MHz Timing Specifications (Measured at 1.40 V Unless Otherwise Specified) Maximum I2C Bus Frequency Propagation Delay 5 V Operation Side A to Side B Rising4 Side A to Side B Falling4 Side B to Side A Rising Side B to Side A Falling 3.3 V Operation Side A to Side B Rising4 Side A to Side B Falling4 Side B to Side A Rising Side B to Side A Falling Pulse Width Distortion 5V Side A Low to Side B Low4 Side B Low to Side A Low 3.3 V Side A Low to Side B Low4 Side B Low to Side A Low Fmax Tphab Tplab Tphba Tplba No bus capacitance, R1 = 1400, R2 = 499, See Figure 2 — — — — 38 15 33 11 45 26 46 22 ns ns ns ns Tphab Tplab Tphba Tplba R1 = 806 R2 = 499 — — — — 44 17 30 14 55 29 40 27 ns ns ns ns PWDAB PWDBA No bus capacitance, R1 = 1400, R2 = 499, See Figure 2 — — 22 21 32 32 ns ns PWDAB PWDBA R1 = 806, R2 = 499 — — 27 15 35 25 ns ns Notes: 1. All voltages are relative to respective ground. 2. VIL < 0.410 V, VIH > 0.540 V. 3. I2CV (Side A) = I2CVOL (Side A) – I2CVT (Side A). To ensure no latch-up on a given bus, I2CV (Side A) is the minimum difference between the output logic low level of the driving device and the input logic threshold. 4. Side A measured at 0.6 V. 6 Rev. 1.4 Si860x Table 4. Electrical Characteristics for Unidirectional Non-I2C Digital Channels (Si8602/05/06) 3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C Parameter Symbol Test Condition Min Typ Max Unit Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V Negative-Going Input Threshold VT– All inputs falling 1.0 1.23 1.4 V Input Hysteresis VHYS 0.38 0.44 0.50 V High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA AVDD, BVDD –0.4 4.8 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V IL — — ±10 µA ZO — 50 — Maximum Data Rate 0 — 10 Mbps Minimum Pulse Width — — 40 ns Input Leakage Current 1 Output Impedance Timing Characteristics Propagation Delay Pulse Width Distortion |tPLH – tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH See Figure 1 — — 20 ns PWD See Figure 1 — — 12 ns tPSK(P-P) — — 20 ns tPSK — — 10 ns Output Rise Time tr C3 = 15 pF See Figure 1 and Figure 2 — 2.5 4.0 ns Output Fall Time tf C3 = 15 pF See Figure 1 and Figure 2 — 2.5 4.0 ns — 350 — ps Peak Eye Diagram Jitter tJIT(PK) Notes: 1. The nominal output impedance of a non-I2C isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. Rev. 1.4 7 Si860x Table 5. Electrical Characteristics for All I2C and Non-I2C Channels 3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV 35 50 — kV/µs Common Mode Transient Immunity CMTI VI = VDD or 0 V VCM = 1500 V (see Figure 3) Shut Down Time from UVLO tSD — 3.0 — µs * tSTART — 15 40 µs Start-up Time *Note: Start-up time is the time period from the application of power to valid data at the output. 1.4 V Typical Input tPLH tPHL 90% 90% 10% 10% 1.4 V Typical Output tr tf Figure 1. Propagation Delay Timing (Non-I2C Channels) 8 Rev. 1.4 Si860x 1.1. Test Circuits Figure 2 depicts the timing test diagram; Figure 3 depicts the CMTI test diagram. AVDD R1 C1 R1 C1 BVDD NC C3 R2 NC ASDA BSDA ADIN BDOUT ADOUT BDIN ASCL BSCL NC NC AGND BGND Si8605 C3 C2 R2 C2 Figure 2. Simplified Timing Test Diagram 3 to 5 V Supply Si86xx Input Signal Switch 3 to 5 V Isolated Supply AVDD BVDD INPUT OUTPUT Oscilloscope AGND BGND Isolated Ground Input High Voltage Differential Probe Output Vcm Surge Output High Voltage Surge Generator Figure 3. Common Mode Transient Immunity Test Circuit Rev. 1.4 9 Si860x Table 6. Regulatory Information* CSA The Si860x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. 60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage. VDE The Si860x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. 60747-5-2: Up to 1200 Vpeak for basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. UL The Si860x is certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 5000 VRMS isolation voltage for basic protection. CQC The Si860x is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and CQC13001096239. Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. *Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec. For more information, see "6.Ordering Guide" on page 27. 10 Rev. 1.4 Si860x Table 7. Insulation and Safety-Related Specifications Value Parameter Symbol Nominal Air Gap (Clearance)1 Nominal External Tracking (Creepage)1 Test Condition NB SOIC-8 NB SOIC-16 WB SOIC-16 Unit L(1O1) 4.9 4.9 8.0 mm L(1O2) 4.01 4.01 8.0 mm 0.014 0.014 0.014 mm 600 600 600 Minimum Internal Gap (Internal Clearance) Tracking Resistance (Proof Tracking Index) PTI Erosion Depth ED 0.040 0.019 0.019 mm Resistance (Input-Output)2 RIO 1012 1012 1012 Capacitance (Input-Output)2 CIO 1.0 2.0 2.0 pF 4.0 4.0 4.0 pF 10 10 10 pF Input Capacitance3 CI IEC60112 f = 1 MHz Non-I2C Channel I2C Channel VRMS Notes: 1. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-8 and SOIC-16 packages and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-8 and SOIC-16 packages and 7.6 mm minimum for the WB SOIC-16 package. 2. To determine resistance and capacitance, the Si860x, SO-16, is converted into a 2-terminal device. Pins 1–8 (1–4, SO8) are shorted together to form the first terminal and pins 9–16 (5–8, SO-8) are shorted together to form the second terminal. The parameters are then measured between these two terminals. 3. Measured from input pin to ground. Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings Specification Parameter Basic Isolation Group Installation Classification Test Conditions NB SOIC-8 SOIC-16 WB SOIC-16 I I Rated Mains Voltages < 150 VRMS I-IV I-IV Rated Mains Voltages < 300 VRMS I-III I-IV Rated Mains Voltages < 400 VRMS I-II I-III Rated Mains Voltages < 600 VRMS I-II I-III Material Group Rev. 1.4 11 Si860x Table 9. IEC 60747-5-2 Insulation Characteristics for Si86xxxx* Characteristic Parameter Symbol Maximum Working Insulation Voltage Test Condition WB SOIC-16 NB SOIC-8 SOIC-16 Unit 1200 630 Vpeak VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) 2250 1182 Vpeak VIOTM t = 60 sec 6000 6000 Vpeak 2 2 >109 >109 VIORM Input to Output Test Voltage Transient Overvoltage Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V RS *Note: Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21. Table 10. IEC Safety Limiting Values1 Parameter Case Temperature Symbol Test Condition TS Safety Input Current IS Device Power Dissipation2 PD JA = 100 °C/W (WB SOIC-16), 105 °C/W (NB SOIC-16), 140 °C/W (NB SOIC-8) AVDD, BVDD = 5.5 V, TJ = 150 °C, TA = 25 °C NB NB SOIC-8 SOIC-16 WB SOIC-16 Unit 150 150 150 °C 160 210 220 mA 220 275 275 mW Notes: 1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figures 4, 5, and 6. 2. The Si86xx is tested with AVDD, BVDD = 5.5 V; TJ = 150 ºC; C1, C2 = 0.1 µF; C3 = 15 pF; R1, R2 = 3kinput 1 MHz 50% duty cycle square wave. 12 Rev. 1.4 Si860x Table 11. Thermal Characteristics Parameter Safety-Limiting Values (mA) IC Junction-to-Air Thermal Resistance Symbol NB SOIC8 NB SOIC16 WB SOIC16 Unit JA 140 105 100 °C/W 400 300 270 200 AVDD, BVDD = 3.6 V 160 AVDD, BVDD = 5.5 V 100 0 0 50 100 150 Case Temperature (ºC) 200 Figure 4. NB SOIC-8 Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Safety-Limiting Current (mA) 500 400 350 300 AVDD , BVDD = 3.6 V 210 200 AVDD , BVDD = 5.5 V 100 0 0 50 100 Temperature (ºC) 150 200 Figure 5. NB SOIC-16 Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Rev. 1.4 13 Si860x Safety-Limiting Current (mA) 500 400 350 300 AVDD , BVDD = 3.6 V 220 200 AVDD , BVDD = 5.5 V 100 0 0 50 100 Temperature (ºC) 150 200 Figure 6. WB SOIC-16 Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Table 12. Absolute Maximum Ratings1 Parameter Symbol Min Max Unit TSTG –65 150 ºC Ambient Temperature Under Bias TA –40 125 ºC Junction Temperature TJ — 150 °C VDD –0.5 7.0 V VI –0.5 VDD + 0.5 V VO –0.5 VDD + 0.5 V Output Current Drive (non-I C channels) IO — ±10 mA Side A output current drive (I2C channels) IO — ±15 mA IO — ±75 mA Lead Solder Temperature (10 s) — 260 ºC Maximum Isolation (Input to Output) (1 sec) NB SOIC-8, SOIC-16 — 4500 VRMS Maximum Isolation (Input to Output) (1 sec) WB SOIC-16 — 6500 VRMS Storage Temperature 2 Supply Voltage Input Voltage Output Voltage 2 2 Side B output current drive (I C channels) Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. VDE certifies storage temperature from –40 to 150 °C. 14 Rev. 1.4 Si860x 2. Functional Description 2.1. Theory of Operation The operation of an Si86xx channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single unidirectional Si86xx channel is shown in Figure 7. Transmitter Receiver RF OSCILLATOR A MODULATOR SemiconductorBased Isolation Barrier DEMODULATOR B Figure 7. Simplified Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See Figure 8 for more details. Input Signal Modulation Signal Output Signal Figure 8. Modulation Scheme Rev. 1.4 15 Si860x 3. Typical Application Overview 3.1. I2C Background In many applications, I2C, SMBus, and PMBus interfaces require galvanic isolation for safety or ground loop elimination. For example, Power over Ethernet (PoE) applications typically use an I2C interface for communication between the PoE power sourcing device (PSE), and the earth ground referenced system controller. Galvanic isolation is required both by standard and also as a practical matter to prevent ground loops in Ethernet connected equipment. The physical interface consists of two wires: serial data (SDA) and serial clock (SCL). These wires are connected to open collector drivers that serve as both inputs and outputs. At first glance, it appears that SDA and SCL can be isolated simply by placing two unidirectional isolators in parallel, and in opposite directions. However, this technique creates feedback that latches the bus line low when a logic low asserted by either master or slave. This problem can be remedied by adding anti-latch circuits, but results in a larger and more expensive solution. The Si860x products offer a single-chip, anti-latch solution to the problem of isolating I2C/SMBus applications and require no external components except the I2C/SMBus pull-up resistors. In addition, they provide isolation to a maximum of 5.0 kVRMS, support I2C clock stretching, and operate to a maximum I2C bus speed of 1.7 Mbps. 3.2. I2C Isolator Operation Without anti-latch protection, bidirectional I2C isolators latch when an isolator output logic low propagates back through an adjacent isolator channel creating a stable latched low condition on both sides. Anti-latch protection is typically added to one side of the isolator to avoid this condition (the “A” side for the Si8600/02/05/06). The following examples illustrate typical circuit configurations using the Si8600/02/05/06. Si8600/02/05/06 I2C/SMBus Unit 1 + - VIL I2C/SMBus Unit 2 ISO1 V OL V IL V OL B Side A Side ISO2 Figure 9. Isolated Bus Overview (I2C Channels Only) The “A side” output low (VOL) and input low (VIL) levels are designed such that the isolator VOL is greater than the isolator VIL to prevent the latch condition. 16 Rev. 1.4 Si860x 3.3. I2C Isolator Design Constraints Table 13 lists the I2C isolator design constraints. Table 13. Design Constraints Design Constraint To prevent the latch condition, the isolator output low level must be greater than the isolator input low level. The bus output low must be less than the isolator input low logic level. The isolator output low must be less than the bus input low. Data Sheet Values Effect of Bus Pull-up Strength and Temperature Isolator VOL 0.7 V typical Isolator VIL 0.5 V typical This is normally guaranteed by the isolator data sheet. However, if the pull up strength is too weak, the output low voltage will fall and can get Input/Output Logic Low Level too close to the input low logic level. Difference ∆VSDA1, ∆VSCL1 = 50 mV minimum These track over temperature. Bus VOL = 0.4 V maximum Isolator VIL = 0.41 V minimum If the pull up strength is too large, the devices on the bus might not pull the voltage below the input low range. These have opposite temperature coefficients. Worst case is hot temperature. If the pull up strength is too large, the isolator might not pull below the Bus VIL 0.3 x VDD = 1.0 V minimum for bus input low voltage. VDD = 3.3 V Si8600/02/05/06 Vol: –1.8 mV/C CMOS buffer: –0.6 mV/C Isolator VOL = 0.8 V maximum This provides some temperature tracking, but worst case is cold temperature. 3.4. I2C Isolator Design Considerations The first step in applying an I2C isolator is to choose which side of the bus will be connected to the isolator A side. Ideally, it should be the side which: 1. Is compatible with the range of bus pull up specified by the manufacturer. For example, the Si8600/02/05/06 isolators are normally used with a pull up of 0.5 mA to 3 mA. 2. Has the highest input low level for devices on the bus. Some devices may specify an input low of 0.9 V and other devices might require an input low of 0.3 x Vdd. Assuming a 3.3 V minimum power supply, the side with an input low of 0.3 x Vdd is the better side because this side has an input low level of 1.0 V. 3. Have devices on the bus that can pull down below the isolator input low level. For example, the Si860x input level is 0.41 V. As most CMOS devices can pull to within 0.4 V of GND this is generally not an issue. 4. Has the lowest noise. Due to the special logic levels, noise margins can be as low as 50 mV. Rev. 1.4 17 Si860x 3.5. Typical Application Schematics Figures 10 through 15 illustrate typical circuit configurations using the Si8600, Si8602, Si8605, and Si8606. AVDD 3k 3k 0.1 µF 0.1 µF ASDA BVDD 8 1 2 3k 3k BSDA 7 ASCL 3 6 AGND 4 5 BSCL I2C Bus BGND Si8600 Figure 10. Typical Si8600 Application Diagram AVDD 3k 0.1 µF 0.1 µF ASDA BVDD 8 1 2 3k BSDA 7 ASCL 3 6 AGND 4 5 BSCL I2C Bus BGND Si8602 Figure 11. Typical Si8602 Application Diagram AGND AVDD 1 16 2 15 33 14 4 13 0.1 µF 3k 3k BGND BVDD 0.1 µF 3k 3k ASDA 5 12 BSDA ASCL 6 11 BSCL AGND 7 10 8 Si8600 9 BGND Figure 12. Typical Si8600 Application Diagram 18 Rev. 1.4 I2C Bus Si860x BGND 1 16 2 15 33 14 4 13 ASDA 5 12 BSDA ASCL 6 11 BSCL AGND 7 10 AGND AVDD 0.1 µF 3k 8 Si8602 BVDD 0.1 µF 3k I2C Bus BGND 9 Figure 13. Typical Si8602 Application Diagram AVDD 0.1 µF 3k 3k ASDA RESET Microcontroller ASCL 1 16 2 15 33 14 4 13 5 12 6 11 7 10 8 AGND Si8605 BVDD 0.1 µF 3k 3k BSDA Microcontroller I2C Bus INT BSCL BGND 9 Figure 14. Typical Si8605 Application Diagram 1 16 2 15 ASDA 33 14 RESET 4 13 INT 5 12 ASCL 6 11 7 10 AVDD 0.1 µF 3k AGND 3k 8 Si8606 9 BVDD 0.1 µF 3k 3k BSDA Microcontroller I2C Bus BSCL BGND Figure 15. Typical Si8606 Application Diagram Rev. 1.4 19 Si860x 4. Device Operation Device behavior during start-up, normal operation, and shutdown is shown in Figure 16, where UVLO+ and UVLOare the positive-going and negative-going thresholds respectively. Refer to Table 14 to determine outputs when power supply (VDD) is not present. 4.1. Device Startup Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow the states of inputs. 4.2. Undervoltage Lockout Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally enters UVLO when AVDD falls below AVDDUVLO– and exits UVLO when AVDD rises above AVDDUVLO+. Side B operates the same as Side A with respect to its BVDD supply. UVLO+ UVLO- AVDD UVLO+ UVLO- BVDD INPUT tSTART tSD tSTART tSTART tPHL OUTPUT Figure 16. Device Behavior during Normal Operation 20 Rev. 1.4 tPLH Si860x 4.3. Input and Output Characteristics for Non-I2C Digital Channels The unidirectional Si86xx inputs and outputs are standard CMOS drivers/receivers. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. Table 14 details powered and unpowered operation of the Si86xx’s non-I2C digital channels. Table 14. Si86xx Operation Table VI Input1,4 VDDI State1,2,3 VDDO State1,2,3 VO Output1,4 H P P H L P P L X5 UP P L6 X5 P UP Comments Normal operation. Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 µs. Upon transition of VDDO from unpowered to powUndetermined ered, VO returns to the same state as VI within 1 µs. Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. 2. Powered (P) state is defined as 3.0 V < VDD < 5.5 V. 3. Unpowered (UP) state is defined as VDD = 0 V. 4. X = not applicable; H = Logic High; L = Logic Low. 5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current. 6. For I2C channels, the outputs for a given side go to Hi-Z when power is lost on the opposite side. Rev. 1.4 21 Si860x 4.4. Layout Recommendations To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 6 on page 10 and Table 7 on page 11 detail the working voltage and creepage/clearance capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. 4.4.1. Supply Bypass The Si860x family requires a 0.1 µF bypass capacitor between AVDD and AGND and BVDD and BGND. The capacitor should be placed as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 ) in series with the inputs and outputs if the system is excessively noisy. 4.4.2. Output Pin Termination The nominal output impedance of an non-I2C isolator channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 22 Rev. 1.4 Si860x 4.5. Typical Performance Characteristics The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to Tables 2, 3, 4, and 5 for actual specification limits. Side A Side B Side B Side A Figure 20. I2C Side A Pulling Up, Side B Following Figure 17. I2C Side A Pulling Down (1100 Pull-Up) 10.0 Side A Side B Delay (ns) 9.0 8.0 7.0 6.0 5.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110120 Temperature (Degrees C) Figure 21. Non I2C Channel Propagation Delay vs. Temperature Figure 18. I2C Side B Pulling Down Side A Side B Figure 19. I2C Side B Pulling Up, Side A Following Rev. 1.4 23 Si860x 5. Pin Descriptions AVDD 1 8 BVDD AVDD 1 8 BVDD ASDA 2 Bidirectional Isolator Channel 7 BSDA ASDA 2 Bidirectional Isolator Channel 7 BSDA ASCL 3 Bidirectional Isolator Channel 6 BSCL ASCL 3 Unidirectional Isolator Channel 6 BSCL 5 BGND AGND 4 AGND 4 Si8600 Si8602 Table 15. Si8600/02 in SOIC-8 Package Pin Name 1 AVDD Side A power supply terminal; connect to a source of 3.0 to 5.5 V. 2 ASDA Side A data (open drain) input or output. 3 ASCL Side A clock input or output. Open drain I/O for Si8600. Standard CMOS input for Si8602. 4 AGND Side A ground terminal. 5 BGND Side B ground terminal. 6 BSCL Side B clock input or output. Open drain I/O for Si8600. Push-pull output for Si8602. 7 BSDA Side B data (open drain) input or output. 8 BVDD Side B power supply terminal; connect to a source of 3.0 to 5.5 V. 24 Description Rev. 1.4 5 BGND Si860x 16 BGND AGND 1 NC 2 15 NC AVDD 3 NC 2 14 BVDD NC 4 13 NC 12 BSDA ASDA 5 ASCL 6 Bidirectional Isolator Channel 11 BSCL ASCL 6 10 NC AGND 7 Si8600 14 BVDD NC 4 ASDA 5 NC 8 15 NC AVDD 3 Bidirectional Isolator Channel AGND 7 16 BGND AGND 1 9 BGND NC 8 13 NC Bidirectional Isolator Channel Unidirectional Isolator Channel 12 BSDA 11 BSCL 10 NC Si8602 9 BGND Table 16. Si8600/02 in Narrow and Wide-Body SOIC-16 Packages Pin Name Description 1 AGND 2 NC 3 AVDD 4 NC 5 ASDA Side A data open drain input or output. 6 ASCL Side A data open drain input or output. 7 AGND Side A Ground Terminal. 8 NC 9 BGND 10 NC 11 BSCL Side B data open drain input or output. 12 BSDA Side B data open drain input or output. 13 NC 14 BVDD 15 NC 16 BGND Side A Ground Terminal. No connection. Side A power supply terminal. Connect to a source of 3.0 to 5.5 V. No connection. No connection. Side B Ground Terminal. No connection. No connection. Side B power supply terminal. Connect to a source of 3.0 to 5.5 V. No connection. Side B Ground Terminal. Rev. 1.4 25 Si860x 16 BVDD AVDD 1 15 NC NC 2 ASDA 3 ADIN 4 ADOUT 5 ASCL 6 Bidirectional Isolator Channel Unidirectional Isolator Channel Unidirectional Isolator Channel Bidirectional Isolator Channel NC 7 AGND 8 NC 2 ASDA 3 14 BSDA 13 BDOUT ADIN1 4 12 BDIN ADIN2 5 11 BSCL ASCL 6 15 NC Bidirectional Isolator Channel Unidirectional Isolator Channel Unidirectional Isolator Channel Bidirectional Isolator Channel NC 7 10 NC Si8605 16 BVDD AVDD 1 AGND 8 9 BGND 14 BSDA 13 BDOUT1 12 BDOUT2 11 BSCL 10 NC Si8606 9 BGND Table 17. Si8605/06 in Narrow and Wide-Body SOIC-16 Packages 26 Pin Name Description 1 AVDD 2 NC 3 ASDA 4 ADIN/ADIN1 5 ADOUT/ADIN2 6 ASCL 7 NC 8 AGND Side A Ground Terminal. 9 BGND Side B Ground Terminal. 10 NC 11 BSCL 12 BDIN/BDOUT2 Side B digital input/output (non I2C) Standard CMOS digital input for Si8605. Push-Pull output for Si8606. 13 BDOUT/BDOUT1 Side B digital push-pull output (non I2C). 14 BSDA 15 NC 16 BVDD Side A power supply terminal. Connect to a source of 3.0 to 5.5 V. No connection. Side A data (open drain) input or output. Side A standard CMOS digital input (non I2C). Side A digital input/output (non I2C) Standard CMOS digital input for Si8606. Push-Pull output for Si8605. Side A clock input or output. Open drain I/O for Si8605/06. No connection. No connection. Side B clock input or output. Open drain I/O for Si8605/06. Side B data open drain input or output. No connection. Side B power supply terminal. Connect to a source of 3.0 to 5.5 V. Rev. 1.4 Si860x 6. Ordering Guide Table 18. Ordering Guide1,2 Number of Max Data Rate Isolation Unidirectional of Ratings (kVrms) Non-I2C Non-I2C Channels Unidirectional Channels (Mbps) Ordering Part Number (OPN) Number of Bidirectional I2C Channels Max I2C Bus Speed (MHz) Si8600AB-B-IS 2 1.7 0 — Si8600AC-B-IS 2 1.7 0 Si8600AD-B-IS 2 1.7 Si8602AB-B-IS 1 Si8602AC-B-IS Temp Range (C) Package 2.5 –40 to 125 NB SOIC-8 — 3.75 –40 to 125 NB SOIC-8 0 — 5.0 –40 to 125 WB SOIC-16 1.7 1 10 2.5 –40 to 125 NB SOIC-8 1 1.7 1 10 3.75 –40 to 125 NB SOIC-8 Si8602AD-B-IS 1 1.7 1 10 5.0 –40 to 125 WB SOIC-16 Si8605AB-B-IS1 2 1.7 1 Forward 1 Reverse 10 2.5 –40 to 125 NB SOIC-16 Si8605AC-B-IS1 2 1.7 1 Forward 1 Reverse 10 3.75 –40 to 125 NB SOIC-16 Si8605AD-B-IS 2 1.7 1 Forward 1 Reverse 10 5.0 –40 to 125 WB SOIC-16 Si8606AC-B-IS1 2 1.7 2 Forward 10 3.75 –40 to 125 NB SOIC-16 Si8606AD-B-IS 2 1.7 2 Forward 10 5.0 –40 to 125 WB SOIC-16 Notes: 1. All packages are RoHS-compliant with peak reflow temperature of 260 °C according to the JEDEC industry standard classifications and peak solder temperature. 2. “Si” and “SI” are used interchangeably. Rev. 1.4 27 Si860x 7. Package Outline: 16-Pin Wide Body SOIC Figure 22 illustrates the package details for the Si860x Digital Isolator. Table 19 lists the values for the dimensions shown in the illustration. Figure 22. 16-Pin Wide Body SOIC 28 Rev. 1.4 Si860x Table 19. Package Diagram Dimensions Dimension Min Max A — 2.65 A1 0.10 0.30 A2 2.05 — b 0.31 0.51 c 0.20 0.33 D 10.30 BSC E 10.30 BSC E1 7.50 BSC e 1.27 BSC L 0.40 1.27 h 0.25 0.75 0° 8° aaa — — 0.10 0.33 0.10 ddd — — 0.25 eee — 0.10 fff — 0.20 bbb ccc Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Outline MS-013, Variation AA. 4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components. Rev. 1.4 29 Si860x 8. Land Pattern: 16-Pin Wide-Body SOIC Figure 23 illustrates the recommended land pattern details for the Si860x in a 16-pin wide-body SOIC. Table 20 lists the values for the dimensions shown in the illustration. Figure 23. 16-Pin SOIC Land Pattern Table 20. 16-Pin Wide Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 9.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.90 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. 30 Rev. 1.4 Si860x 9. Package Outline: 8-Pin Narrow Body SOIC Figure 24 illustrates the package details for the Si860x in an 8-pin SOIC (SO-8). Table 21 lists the values for the dimensions shown in the illustration. Figure 24. 8-pin Small Outline Integrated Circuit (SOIC) Package Table 21. Package Diagram Dimensions Symbol Millimeters Min Max A 1.35 1.75 A1 0.10 0.25 A2 1.40 REF 1.55 REF B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Rev. 1.4 31 Si860x 10. Land Pattern: 8-Pin Narrow Body SOIC Figure 25 illustrates the recommended land pattern details for the Si860x in an 8-pin narrow-body SOIC. Table 22 lists the values for the dimensions shown in the illustration. Figure 25. PCB Land Pattern: 8-Pin Narrow Body SOIC Table 22. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC) Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. 32 Rev. 1.4 Si860x 11. Package Outline: 16-Pin Narrow Body SOIC Figure 26 illustrates the package details for the Si860x in a 16-pin narrow-body SOIC (SO-16). Table 23 lists the values for the dimensions shown in the illustration. Figure 26. 16-pin Small Outline Integrated Circuit (SOIC) Package Rev. 1.4 33 Si860x Table 23. Package Diagram Dimensions Dimension Min Max A — 1.75 A1 0.10 0.25 A2 1.25 — b 0.31 0.51 c 0.17 0.25 D 9.90 BSC E 6.00 BSC E1 3.90 BSC e 1.27 BSC L 0.40 L2 1.27 0.25 BSC h 0.25 0.50 θ 0° 8° aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 34 Rev. 1.4 Si860x 12. Land Pattern: 16-Pin Narrow Body SOIC Figure 27 illustrates the recommended land pattern details for the Si860x in a 16-pin narrow-body SOIC. Table 24 lists the values for the dimensions shown in the illustration. Figure 27. 16-Pin Narrow Body SOIC PCB Land Pattern Table 24. 16-Pin Narrow Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. Rev. 1.4 35 Si860x 13. Top Markings 13.1. Si860x Top Marking (16-Pin Wide Body SOIC) Si86XYSV YYWWRTTTTT e4 TW 13.2. Top Marking Explanation (16-Pin Wide Body SOIC) Si86 = Isolator product series XY = Channel Configuration 05 = Bidirectional SCL, SDA; 1- forward and (See Ordering Guide for more 1-reverse unidirectional channel information). 06 = Bidirectional SCL, SDA; 2- forward unidirectional channels S = Speed Grade A = 1.7 Mbps V = Isolation rating A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV Line 1 Marking: Base Part Number Ordering Options Line 2 Marking: YY = Year WW = Workweek Assigned by assembly subcontractor. Corresponds to the year and workweek of the mold date. RTTTTT = Mfg Code Manufacturing code from assembly house “R” indicates revision Circle = 1.7 mm Diameter (Center-Justified) “e4” Pb-Free Symbol Country of Origin ISO Code Abbreviation TW = Taiwan Line 3 Marking: 36 Rev. 1.4 Si860x 13.3. Si860x Top Marking (8-Pin Narrow Body SOIC) Si86XYSV YYWWRF e3 AIXX 13.4. Top Marking Explanation (8-Pin Narrow Body SOIC) Line 1 Marking: Base Part Number Ordering Options (See Ordering Guide for more information). Line 2 Marking: Line 3 Marking: Si86 = Isolator I2C Product Series: XY = Channel Configuration 00 = Bidirectional SCL and SDA channels 02 = Bidirectional SDA channel; Unidirectional SCL channel S = Speed Grade A = 1.7 Mbps V = Isolation rating A = 1 kV; B = 2.5 kV; C = 3.75 kV YY = Year WW = Work week Assigned by assembly contractor. Corresponds to the year and work week of the mold date. R = Product Rev F = Wafer Fab First two characters of the manufacturing code from Assembly. Circle = 1.1 mm Diameter Left-Justified “e3” Pb-Free Symbol A = Assembly Site I = Internal Code XX = Serial Lot Number Last four characters of the manufacturing code from assembly. Rev. 1.4 37 Si860x 13.5. Si860x Top Marking (16-Pin Narrow Body SOIC) e3 Si86XYSV YYWWRTTTTT 13.6. Top Marking Explanation (16-Pin Narrow Body SOIC) Line 1 Marking: Base Part Number Ordering Options Si86 = Isolator product series XY = Channel Configuration 05 = Bidirectional SCL, SDA; 1- forward and 1-reverse unidirectional channel 06 = Bidirectional SCL, SDA; 2- forward unidirectional channels S = Speed Grade A = 1.7 Mbps V = Isolation rating A = 1 kV; B = 2.5 kV; C = 3.75 kV Line 2 Marking: Circle = 1.2 mm Diameter “e3” Pb-Free Symbol YY = Year WW = Work Week Assigned by the Assembly House. Corresponds to the year and work week of the mold date. RTTTTT = Mfg Code Manufacturing code from assembly house “R” indicates revision Circle = 1.2 mm diameter “e3” Pb-Free Symbol. 38 Rev. 1.4 Si860x DOCUMENT CHANGE LIST Revision 1.1 to Revision 1.2 Revision 0.1 to Revision 0.2 Added Si8601 replaced by Si8602 throughout. Added chip graphics on page 1. Moved Table 12 to page 14. Updated Table 3, “Si8600/02/05/06 Electrical Characteristics for Bidirectional I2C Channels1,” on page 5. Updated Table 7, “Insulation and Safety-Related Specifications,” on page 11. Updated Table 9, “IEC 60747-5-2 Insulation Characteristics for Si86xxxx*,” on page 12. Moved “3. Typical Application Overview” to page 16. Moved “Typical Performance Characteristics” to page 23. Updated "5.Pin Descriptions" on page 24. Updated "6.Ordering Guide" on page 27. Added chip graphics on page 1. Moved Tables 1 and 2 to page 4. Updated Table 7, “Insulation and Safety-Related Specifications,” on page 11. Updated Table 9, “IEC 60747-5-2 Insulation Characteristics for Si86xxxx*,” on page 12. Moved Table 13 to page 17. Moved Table 14 to page 21. Updated "5.Pin Descriptions" on page 24. Updated "6.Ordering Guide" on page 27. junction temperature spec. Updated "4.4.1.Supply Bypass" on page 22. Updated "6.Ordering Guide" on page 27. Removed Rev A devices. Updated "7.Package Outline: 16-Pin Wide Body SOIC" on page 28. Updated Top Marks. Added revision description. Revision 1.2 to Revision 1.3 Revision 0.2 to Revision 0.3 Updated Table 12 on page 14. Added Figure 3, “Common Mode Transient Immunity Test Circuit,” on page 9. Added references to CQC throughout. Added references to 2.5 kVRMS devices throughout. Removed Fail-safe operating mode throughout. Updated "6.Ordering Guide" on page 27. Updated "13.1.Si860x Top Marking (16-Pin Wide Body SOIC)" on page 36. Revision 1.3 to Revision 1.4 Updated Table 6 on page 10. Added CQC certificate numbers. Corrected Device Power Dissipation units in Table 10 on page 12. Updated "6.Ordering Guide" on page 27. Removed Removed references to moisture sensitivity levels. Note 2. Revision 0.3 to Revision 1.0 Reordered spec tables to conform to new convention. Removed “pending” throughout document. Revision 1.0 to Revision 1.1 Updated Figures 12 and 13. Updated Pin 7 AGND connection. Updated "6.Ordering Guide" on page 27 to include MSL2A. Rev. 1.4 39 Si860x CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 40 Rev. 1.4