Data Sheet Rev. 1.03 / March 2013 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device Power Management Power and Precision ZSPM9000 Ultra-Compact, High-Performance DrMOS Device Brief Description Features The ZSPM9000 DrMOS is a fully optimized, ultracompact, integrated MOSFET plus driver powerstage solution for high-current, high-frequency, synchronous buck DC-DC applications. The device incorporates a driver IC, two power MOSFETs, and a bootstrap Schottky diode in a thermally enhanced, ultra-compact 6mmx6mm PQFN40 package. With an integrated approach, the ZSPM9000’s complete switching power stage is optimized for driver and MOSFET dynamic performance, system inductance, and power MOSFET RDS(ON). It uses innovative high-performance MOSFET technology, which dramatically reduces switch ringing, eliminating the snubber circuit in most buck converter applications. An innovative driver IC with reduced dead times and propagation delays further enhances performance. An internal 12V to 5V linear regulator enables the ZSPM9000 to operate from a single 12V supply. A thermal warning function (THWN) warns of potential over-temperature situations. The ZSPM9000 also incorporates features such as Skip Mode (SMOD) for improved light-load efficiency and a tri-state 3.3V pulse-width modulation (PWM) input for compatibility with a wide range of PWM controllers. The ZSPM9000 DrMOS is ideally compatible with ZMDI’s ZSPM1000, a leading-edge configurable digital power-management system controller for nonisolated point-of-load (POL) supplies. Available Support ZSPM8000-KIT: Closed Loop Evaluation Kit combined for the ZSPM9000 and ZSPM1000 Physical Characteristics Benefits Fully optimized system efficiency: >93% peak Clean switching waveforms with minimal ringing 72% space-saving compared to conventional discrete solutions Ideally compatible with ZMDI’s ZSPM1000 true digital PWM controller Based on the Intel® 4.0 DrMOS standard Internal 12V to 5V linear regulator (LDO) High-current handling: up to 50A High-performance copper-clip package Tri-state 3.3V PWM input driver Skip Mode (low-side gate turn off) input (SMOD#) Warning flag for over-temperature conditions Driver output disable function (DISB# pin) Internal pull-up and pull-down for SMOD# and DISB# inputs, respectively Integrated Schottky diode technology in the low-side MOSFET Integrated bootstrap Schottky diode Adaptive gate drive timing for shoot-through protection Under-voltage lockout (UVLO) Optimized for switching frequencies up to 1MHz Operation temperature: -40°C to +125°C VIN: 8V to 15V (typical 12V) IOUT: 40A (average), 50A (maximum) Low-profile SMD package: 6mmx6mm PQFN40 ZMDI green packaging and RoHS compliant Typical Application © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 — March 8, 2013. All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. For more information, contact ZMDI via [email protected]. ZSPM9000 Ultra-Compact, High-Performance DrMOS Device ZSPM9000 Block Diagram VDRV VCIN BOOT VIN DBoot VIN UVLO 5V LDO VCC UVLO GH Logic DISB# GH Level Shift (Q1) HS Power MOSFET GH 10µA 30k Typical Applications Telecom switches Servers and storage Desktop computers Workstations High-performance gaming motherboards Base stations Network routers Industrial applications VCIN PHASE R UP_PWM Dead Time Control Input Tri-State Logic PWM VSWH R DN_PWM VCIN GL GL Logic THWN# (Q2) LS Power MOSFET VCIN GL Temp Sense 30k 10µA CGND SMOD# PGND Ordering Information Product Sales Code Description Package ZSPM9000AI1R ZSPM9000 Lead-free PQFN40 — Temperature range: -40°C to +125°C Reel ZSPM8000-KIT Integrated Evaluation Kit for ZSPM9000 and ZSPM1000 Kit Sales and Further Information www.zmdi.com [email protected] Zentrum Mikroelektronik Dresden AG Global Headquarters Grenzstrasse 28 01109 Dresden, Germany ZMD America, Inc. 1525 McCarthy Blvd., #212 Milpitas, CA 95035-7453 USA Central Office: Phone +49.351.8822.306 Fax +49.351.8822.337 USA Phone 1.855.275.9634 Phone +1.408.883.6310 Fax +1.408.883.6358 European Technical Support Phone +49.351.8822.7.772 Fax +49.351.8822.87.772 DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise. European Sales (Stuttgart) Phone +49.711.674517.55 Fax +49.711.674517.87955 Zentrum Mikroelektronik Dresden AG, Japan Office 2nd Floor, Shinbashi Tokyu Bldg. 4-21-3, Shinbashi, Minato-ku Tokyo, 105-0004 Japan ZMD FAR EAST, Ltd. 3F, No. 51, Sec. 2, Keelung Road 11052 Taipei Taiwan Phone +81.3.6895.7410 Fax +81.3.6895.7301 Phone +886.2.2377.8189 Fax +886.2.2377.8199 Zentrum Mikroelektronik Dresden AG, Korea Office U-space 1 Building 11th Floor, Unit JA-1102 670 Sampyeong-dong Bundang-gu, Seongnam-si Gyeonggi-do, 463-400 Korea Phone +82.31.950.7679 Fax +82.504.841.3026 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.03 — March 8, 2013 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. ZSPM9000 Ultra-Compact, High-Performance DrMOS Device Contents List of Figures .......................................................................................................................................................... 4 List of Tables ........................................................................................................................................................... 5 1 IC Characteristics ............................................................................................................................................. 6 1.1. Absolute Maximum Ratings ....................................................................................................................... 6 1.2. Recommended Operating Conditions ....................................................................................................... 7 1.3. Electrical Parameters ................................................................................................................................ 7 1.4. Typical Performance Characteristics ....................................................................................................... 10 2 Functional Description .................................................................................................................................... 15 2.1. VDRV and Disable (DISB#) ..................................................................................................................... 16 2.2. Thermal Warning Flag (THWN#) ............................................................................................................. 17 2.3. Tri-state PWM Input ................................................................................................................................. 17 2.4. Adaptive Gate Drive Circuit ..................................................................................................................... 18 2.5. Skip Mode (SMOD#) ............................................................................................................................... 19 2.6. PWM ........................................................................................................................................................ 21 3 Application Design .......................................................................................................................................... 22 3.1. 5V Linear Regulator Capacitor Selection ................................................................................................ 22 3.2. Bootstrap Circuit ...................................................................................................................................... 22 3.3. Power Loss and Efficiency Testing Procedures ...................................................................................... 22 4 Pin Configuration and Package ...................................................................................................................... 24 4.1. Available Packages ................................................................................................................................. 24 4.2. Pin Description......................................................................................................................................... 25 4.3. Package Dimensions ............................................................................................................................... 26 5 Circuit Board Layout Considerations .............................................................................................................. 27 6 Ordering Information ...................................................................................................................................... 29 7 Related Documents ........................................................................................................................................ 29 8 Document Revision History ............................................................................................................................ 29 List of Figures Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Figure 1.5 Figure 1.6 Figure 1.7 Figure 1.8 Figure 1.9 Figure 1.10 Figure 1.11 Data Sheet March 8, 2013 Safe Operating Area ......................................................................................................................... 10 Module Power Loss vs. Output Current ............................................................................................ 10 Power Loss vs. Switching Frequency ............................................................................................... 10 Power Loss vs. Input Voltage ........................................................................................................... 10 Power Loss vs. Driver Supply Voltage ............................................................................................. 11 Power Loss vs. Output Voltage ........................................................................................................ 11 Power Loss vs. Output Inductance ................................................................................................... 11 Driver Supply Current vs. Frequency ............................................................................................... 11 Driver Supply Current vs. Driver Supply Voltage ............................................................................. 12 Driver Supply Current vs. Output Current ......................................................................................... 12 PWM Thresholds vs. Driver Supply Voltage ..................................................................................... 12 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 4 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device Figure 1.12 Figure 1.13 Figure 1.14 Figure 1.15 Figure 1.16 Figure 1.17 Figure 1.18 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 3.1 Figure 4.1 Figure 4.2 Figure 5.1 PWM Thresholds vs. Temperature ................................................................................................... 12 SMOD# Thresholds vs. Driver Supply Voltage ................................................................................ 13 SMOD# Thresholds vs. Temperature ............................................................................................... 13 SMOD# Pull-Up Current vs. Temperature ........................................................................................ 13 Disable Thresholds vs. Driver Supply Voltage ................................................................................. 13 Disable Thresholds vs. Temperature ................................................................................................ 14 Disable Pull-Down Current vs. Temperature .................................................................................... 14 Typical Application Circuit with PWM Control ................................................................................... 15 ZSPM9000 Block Diagram ............................................................................................................... 16 THWN# Operation ............................................................................................................................ 17 PWM and Tri-state Timing Diagram ................................................................................................. 18 SMOD# Timing Diagram ................................................................................................................... 20 PWM Timing ..................................................................................................................................... 21 Power Loss Measurement Block Diagram ....................................................................................... 23 Pin-out PQFN40 Package ................................................................................................................ 24 PQFN40 Physical Dimensions and Recommended Footprint .......................................................... 26 PCB Layout Example ........................................................................................................................ 28 List of Tables Table 2.1 Table 2.2 Data Sheet March 8, 2013 UVLO and Disable Logic .................................................................................................................. 17 SMOD# Logic.................................................................................................................................... 19 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 5 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device 1 IC Characteristics 1.1. Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. The device might not function or be operable above the recommended operating conditions. Stresses exceeding the absolute maximum ratings might also damage the device. In addition, extended exposure to stresses above the recommended operating conditions might affect device reliability. ZMDI does not recommend designing to the “Absolute Maximum Ratings.” PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Maximum Voltage to CGND – VCIN, DISB#, PWM, SMOD#, GL, THWN# pins -0.3 6.0 V Maximum Voltage to PGND or CGND – VIN pin -0.3 25.0 V 16.0 V Maximum Voltage to PGND or CGND – VDRV pin Maximum Voltage to VSWH or PHASE – BOOT, GH pins -0.3 6.0 V Maximum Voltage to CGND – BOOT, PHASE, GH pins -0.3 25.0 V Maximum Voltage to CGND/PGND – VSWH pin DC only -0.3 25.0 V Maximum Voltage to PGND – VSWH pin < 20ns -8.0 25.0 V 22.0 V 7.0 mA fSW=350kHz, VIN=12V, VOUT=1.0V 45 A fSW=1MHz, VIN=12V, VOUT=1.0V 42 A 3.5 °C/W +125 °C +150 °C +150 °C Maximum Voltage to VCIN – BOOT pin Maximum Sink Current – THWN# pin Maximum Average Output Current 1) IOUT(AV) Junction-to-PCB Thermal Resistance θJPCB Ambient Temperature Range TAMB Maximum Junction Temperature TjMAX Storage Temperature Range TSTOR Electrostatic Discharge Protection 1) -0.1 ITHWN# -40 -55 Human Body Model, JESD22A114 2000 V Charged Device Model, JESD22-C101 1000 V ESD IOUT(AV) is rated using DrMOS Evaluation Board, TAMB = 25°C, natural convection cooling. This rating is limited by the peak DrMOS temperature, TjMAX = 150°C, and varies depending on operating conditions, PCB layout, and PCB board to ambient thermal resistance. Data Sheet March 8, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 6 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device 1.2. Recommended Operating Conditions The “Recommended Operating Conditions” table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ZMDI does not recommend exceeding them or designing to the “Absolute Maximum Ratings.” PARAMETER SYMBOL Gate Drive Circuit Supply Voltage Output Stage Supply Voltage 1.3. CONDITIONS MIN TYP MAX UNITS VDRV 8 12 15 V VIN 3 12 15 V TYP MAX UNITS IQ=IVDRV, PWM=LOW or HIGH or float 2 5 mA 36 Electrical Parameters Typical values are VIN = 12V, VDRV = 12V, and TAMB = +25°C unless otherwise noted. PARAMETER SYMBOL CONDITIONS MIN Basic Operation Quiescent Current IQ Internal 5V Linear Regulator Input Current IVDRV 8V<VDRV<14V, fSW=1MHz Output Voltage VCIN VDRV =8V, ILOAD=5mA Power Dissipation PVDRV VDRV =12V, fSW=1MHz VCIN Bypass Capacitor CVCIN X7R or X5R Ceramic 4.8 5.0 mA 5.2 250 1 V mW 10 µF Line Regulation 8V<VDRV<14V, ILOAD=5mA 20 mV Load Regulation VDRV=8V, 5mA<ILOAD<100mA 75 mV Short-Circuit Current Limit 8V<VDRV<14V 200 mA UVLO Threshold UVLO VDRV rising 6.8 7.3 7.8 V UVLO Hysteresis UVLO_Hyst 435 mV Pull-Up Impedance RUP_PWM 26 kΩ Pull-Down Impedance RDN_PWM 12 kΩ PWM High-Level Voltage VIH_PWM 2.01 2.25 2.48 V Tri-state Upper Threshold VTRI_HI 1.96 2.20 2.44 V Tri-state Lower Threshold VTRI_LO 0.76 0.95 1.14 V PWM Low-Level Voltage VIL_PWM 0.67 0.85 1.08 V 160 200 ns 1.6 1.9 V PWM Input Tri-state Shutoff Time tD_HOLD-OFF Tri-state Open Voltage VHiZ_PWM Data Sheet March 8, 2013 1.4 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 7 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DISB# Input High-Level Input Voltage VIH_DISB# Low-Level Input Voltage VIL_DISB# Pull-Down Current 2 V 0.8 IPLD V 10 µA Propagation Delay DISB#, GL Transition from HIGH to LOW tPD_DISBL PWM=GND, LSE=1 25 ns Propagation Delay DISB#, GL Transition from LOW to HIGH tPD_DISBH PWM=GND, LSE=1 25 ns SMOD# Input High-Level Input Voltage VIH_SMOD# Low-Level Input Voltage VIL_SMOD# Pull-Up Current 2 V 0.8 IPLU V 10 µA Propagation Delay SMOD#, GL Transition from HIGH to LOW tPD_SLGLL PWM=GND, DISB#=1 10 ns Propagation Delay SMOD#, GL Transition from LOW to HIGH tPD_SHGLH PWM=GND, DISB#=1 10 ns Thermal Warning Flag Activation Temperature TACT 150 °C Reset Temperature TRST 135 °C IPLD=5mA 30 Ω VSWH =0V 250 ns Pull-Down Resistance RTHWN 250ns Timeout Circuit Timeout Delay Between GH Transition from HIGH to LOW and GL Transition from LOW to HIGH Data Sheet March 8, 2013 tD_TIMEOUT © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 8 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS High-Side Driver Output Impedance, Sourcing Output Impedance, Sinking RSOURCE_GH Source Current=100mA RSINK_GH Sink Current=100mA 1 Ω 0.8 Ω Rise Time for GH=10% to 90% tR_GH 6 ns Fall Time for GH=90% to 10% tF_GH 5 ns LS to HS Deadband Time: GL going LOW to GH going HIGH, 1V GL to 10 % GH tD_DEADON 10 ns PWM LOW Propagation Delay: PWM going LOW to GH going LOW, VIL_PWM to 90% GH tPD_PLGHL 16 PWM HIGH Propagation Delay with SMOD# Held LOW: PWM going HIGH to GH going HIGH, VIH_PWM to 10% GH tPD_PHGHH Propagation Delay Exiting Tri-state: PWM (from Tri-state) going HIGH to GH going HIGH, VIH_PWM to 10% GH tPD_TSGHH SMOD# = LOW 30 ns 30 ns 30 ns 1 Ω 0.5 Ω Low-Side Driver Output Impedance, Sourcing Output Impedance, Sinking RSOURCE_GL Source Current=100mA RSINK_GL Sink Current=100mA Rise Time for GL = 10% to 90% tR_GL 20 ns Fall Time for GL = 90% to 10% tF_GL 13 ns HS to LS Deadband Time: SW going LOW to GL going HIGH, 2.2V SW to 10% GL tD_DEADOFF 12 ns PWM-HIGH Propagation Delay: PWM going HIGH to GL going LOW, VIH_PWM to 90% GL tPD_PHGLL 9 Propagation Delay Exiting Tri-state: PWM (from Tri-state) going LOW to GL going HIGH, VIL_PWM to 10% GL tPD_TSGLH 20 ns 0.35 V 25 ns Boot Diode Forward-Voltage Drop VF IF=10mA Breakdown Voltage VR IR=1mA Data Sheet March 8, 2013 22 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. V 9 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device 1.4. Typical Performance Characteristics Test conditions: VIN=12V, VOUT=1.0V, VCIN=5V, VDRV=5V, LOUT=320nH, TAMB=25°C, and natural convection cooling, unless otherwise specified. Figure 1.1 Safe Operating Area Figure 1.2 Module Power Loss vs. Output Current Figure 1.3 Power Loss vs. Switching Frequency Figure 1.4 Power Loss vs. Input Voltage Data Sheet March 8, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 10 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device Figure 1.5 Power Loss vs. Driver Supply Voltage Figure 1.6 Power Loss vs. Output Voltage Figure 1.7 Power Loss vs. Output Inductance Figure 1.8 Driver Supply Current vs. Frequency Data Sheet March 8, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 11 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device Figure 1.9 Driver Supply Current vs. Driver Supply Voltage Figure 1.10 Driver Supply Current vs. Output Current . Figure 1.11 Figure 1.12 PWM Thresholds vs. Driver Supply Voltage PWM Thresholds vs. Temperature 3.0 VCIN = 5V 3.0 PWM Threshold Voltage (V) 2.5 2.5 PWM Threshold Voltage (V) VIH_PWM 2.0 VTRI_Hi VHiZ_PWM 1.5 VTRI_LO 1.0 VIH_PWM 2.0 VTRI_HI 1.5 VTRI_LO 1.0 VIL_PWM 0.5 VIL_PWM 0.5 0.0 -50 0.0 4.80 4.90 5.00 5.10 -25 0 25 50 75 Temperature (oC) 100 125 5.20 Driver Supply Voltage (V) Data Sheet March 8, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 12 of 29 150 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device Figure 1.13 SMOD# Thresholds vs. Driver Supply Voltage Figure 1.14 SMOD# Thresholds vs. Temperature 2.00 2.2 VCIN = 5V TA = 25oC 1.90 SMOD# Threshold Voltage (V) SMOD# Threshold Voltage (V) 2.0 VIH_SMOD# 1.8 1.6 VIL_SMOD# 1.4 1.80 VIH_SMOD# 1.70 1.60 VIL_SMOD# 1.50 1.40 1.30 1.2 4.80 4.90 Figure 1.15 5.00 Driver Supply Voltage (V) 5.10 -50 5.20 -25 Figure 1.16 SMOD# Pull-Up Current vs. Temperature 0 25 50 75 Temperature (oC) 100 125 150 Disable Thresholds vs. Driver Supply Voltage 2.2 TA = 25oC -9.0 DISB# Threshold Voltage (V) 2.0 SMOD# Pull-up Current (µA) -9.5 -10.0 -10.5 -11.0 VIH_DISB# 1.8 VIL_DISB# 1.6 1.4 -11.5 1.2 4.80 -12.0 -50 -25 Data Sheet March 8, 2013 0 25 50 75 Temperature (oC) 100 125 150 4.90 5.00 Driver Supply Voltage (V) © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 5.10 5.20 13 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device Figure 1.17 Disable Thresholds vs. Temperature Figure 1.18 2.00 VCIN = 5V Disable Pull-Down Current vs. Temperature 12.0 1.90 DISB# Pull-down Current (µA) DISB# Threshold Voltage (V) 11.5 VIH_DISB# 1.80 1.70 1.60 VIL_DISB# 1.50 11.0 10.5 10.0 9.5 9.0 8.5 1.40 -50 -25 Data Sheet March 8, 2013 0 25 50 75 Temperature (oC) 100 125 150 8.0 -50 -25 0 25 50 75 Temperature (oC) © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 100 125 14 of 29 150 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device 2 Functional Description The ZSPM9000 is a driver-plus-FET module optimized for the synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. It is capable of driving speeds up to 1MHz. Figure 2.1 Typical Application Circuit with PWM Control VCIN THWN# VDRV = 8V to 14V VDRV CVDRV 5V LINEAR REGULATOR TEMP SENSE VIN VIN =3V to 14V CVIN DBoot BOOT VCIN CVCIN HDRV CGND (Q1) HS Power MOSFET CBOOT LOUT VOUT PHASE Enabled SMOD# LDRV ON CGND March 8, 2013 VSWH VCIN DISB# Data Sheet COUT CONTROL OFF Disabled ZSPM9000 PWM PWM CONTROL (Q2) LS Power MOSFET PGND © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 15 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device Figure 2.2 ZSPM9000 Block Diagram VDRV VCIN BOOT VIN DBoot VIN UVLO 5V LDO VCC UVLO GH Logic DISB# GH Level Shift (Q1) HS Power MOSFET GH 10µA 30k VCIN PHASE R UP_PWM Dead Time Control Input Tri-State Logic PWM VSWH R DN_PWM VCIN GL Logic THWN# GL (Q2) LS Power MOSFET VCIN GL Temp Sense 30k 10µA CGND 2.1. SMOD# PGND VDRV and Disable (DISB#) The VDRV pin is monitored by an under-voltage lockout (UVLO) circuit. When VDRV rises above ~7.5V, the driver is enabled. When VDRV falls below ~7.0V, the driver is disabled (GH, GL= 0; see Figure 2.2 and section 4.2). The driver can also be disabled by pulling the DISB# pin LOW (DISB# < VIL_DISB#), which holds both GL and GH LOW regardless of the PWM input state. The driver can be enabled by raising the DISB# pin voltage HIGH (DISB# > VIH_DISB#). Data Sheet March 8, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 16 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device Table 2.1 UVLO and Disable Logic Note: DISB# internal pull-down current source is 10µA (typical). UVLO DISB# Driver State 0 X Disabled (GH=0, GL=0) 1 0 Disabled (GH=0, GL=0) 1 1 Enabled (see Table 2.2 ) 1 Open Disabled (GH=0, GL=0) 2.2. Thermal Warning Flag (THWN#) The ZSPM9000 provides a thermal warning flag (THWN#) to indicate over-temperature conditions. The thermal warning flag uses an open-drain output that pulls to CGND when the activation temperature (150°C) is reached. The THWN# output returns to the high-impedance state if the temperature falls to the reset temperature (135°C). For use, the THWN# output requires a pull-up resistor, which can be connected to VCIN. Note that THWN# does NOT disable the DrMOS module. THWN# Operation Voltage at THWN# Figure 2.3 Reset Temperature Activation Temperature High Normal Operation Thermal Warning Low 135°C 150°C TJ_driverIC 2.3. Tri-state PWM Input The ZSPM9000 incorporates a tri-state 3.3V PWM input gate drive design. The tri-state gate drive has a logic HIGH level, logic LOW level, and a tri-state shutdown voltage window. When the PWM input signal enters and remains within the tri-state voltage window for a defined hold-off time (tD_HOLD-OFF), both GL and GH are pulled LOW. This feature enables the gate drive to shut down both high and low side MOSFETs using only one control signal. For example, this can be used for phase shedding in multi-phase voltage regulators. When exiting a valid tri-state condition, the ZSPM9000 follows the PWM input command. If the PWM input goes from tri-state to LOW, the low-side MOSFET is turned on. If the PWM input goes from tri-state to HIGH, the highside MOSFET is turned on, as illustrated in Figure 2.4. The ZSPM9000’s design allows for short propagation delays when exiting the tri-state window (see section 1.3). Data Sheet March 8, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 17 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device Figure 2.4 PWM and Tri-state Timing Diagram V IH_PWM V IH_PWM V IH_PWM V IH_PWM V TRI_HI V TRI_HI t HOLD- OFF V TRI_LO VVIL_PWM VVIL_PWM IL_PW t R_GH PWM ttFF_GHS _GH 9 0% GH to V SWH 1 0% VIN CCM DCM DCM V OUT 2.2V VSWH tR_GL GL tF_GL 90% 9 0% 1 0% 1.0V tPD_PHGLL tD_DEADON 1 0% tPD_PLGHL tPD_TSGHH tHOLD-OFF tPD_TSGHH tHOLD-OFF tPD_TSGLH tD_DEADOFF Enter Enter 3 - state Tri-state Exit Exit 3 - state Tri-state Enter Enter 3 - state Tri-state Exit Exit 3 - state Tri-state Enter Enter Tri-state 3 - state Exit Exit Tri-state 3 - state Notes: tPD_xxx tD_xxx = Propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal; example: tPD_PHGLL = PWM going HIGH to LS VGS (GL) going LOW = Delay from IC generated signal to IC generated signal; example: t D_DEADON = LS VGS LOW to HS VGS HIGH PWM Exiting Tri-state tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS tPD_TSGHH = PWM tri-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS tPD_TSGLH = PWM tri-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (assumes SMOD held Low) SMOD (See Figure 2.5) tPD_SLGLL = SMOD fall to LS VGS fall, 90% to 90% LS VGS tPD_SHGLH = SMOD rise to LS VGS rise, 10% to 10% LS VGS 2.4. Dead Times tD_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value to 10% HS VGS tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value to 10% LS VGS Adaptive Gate Drive Circuit The low-side driver (GL) is designed to drive the ground-referenced low RDS(ON) N-channel MOSFET (Q2). The bias for GL is internally connected between VDRV and CGND. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB#=0V), GL is held LOW. The high-side driver (GH) is designed to drive a floating N-channel MOSFET (Q1). The bias voltage for the highside driver is developed by a bootstrap supply circuit consisting of the internal Schottky diode and external bootstrap capacitor (CBOOT). During startup, the VSWH pin is held at PGND, allowing CBOOT (see section 3.2) to charge to VDRV through the internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from CBOOT and delivered to the gate of Q1. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN + VBOOT, which provides sufficient VGS Data Sheet March 8, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 18 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling GH to VSWH. CBOOT is then recharged to VDRV when VSWH falls to PGND. The GH output is in-phase with the PWM input. The high-side gate is held LOW when the driver is disabled or the PWM signal is held within the tri-state window for longer than the tristate hold-off time, tD_HOLD-OFF (see Figure 2.4). The driver IC design ensures minimum MOSFET dead time while eliminating potential shoot-through (crossconduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to prevent simultaneous conduction. Figure 2.4 provides the relevant timing waveforms. To prevent overlap during the LOWto-HIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes HIGH, Q2 begins to turn off after a propagation delay (t PD_PHGLL). Once the GL pin is discharged below ~1V, Q1 begins to turn on after adaptive delay tD_DEADON. To prevent overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the VSWH pin. When the PWM signal goes LOW, Q1 begins to turn off after a propagation delay (tPD_PLGHL). Once the VSWH pin falls below approx. 2.2V, Q2 begins to turn on after adaptive delay tD_DEADOFF. VGS(Q1) is also monitored. When VGS(Q1) is discharged below approx. 1.2V, a secondary adaptive delay is initiated that results in Q2 being driven on after tD_TIMEOUT, regardless of VSWH state. This function is implemented to ensure CBOOT is recharged each switching cycle in the event that the VSWH voltage does not fall below the 2.2V adaptive threshold. Secondary delay t D_TIMEOUT is longer than tD_DEADOFF. 2.5. Skip Mode (SMOD#) The SMOD function allows higher converter efficiency under light-load conditions. During SMOD, the low-side FET gate signal is disabled (held LOW), preventing discharging of the output capacitors as the filter inductor current attempts reverse current flow – also known as Diode Emulation Mode. When the SMOD# pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode. This mode allows gating on the low-side FET. When the SMOD# pin is pulled LOW, the low-side FET is gated off. If the SMOD# pin is connected to the PWM controller, the controller can actively enable or disable SMOD when the controller detects light-load operation. Table 2.2 SMOD# Logic Note: The SMOD feature is intended to have a low propagation delay between the SMOD signal and the low-side FET VGS response time to control diode emulation on a cycle-by-cycle basis. DISB# PWM SMOD# GH GL 0 X X 0 0 1 Tri-state X 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 Data Sheet March 8, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 19 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device Figure 2.5 SMOD# Timing Diagram See Figure 2.4 for the definitions of the timing parameters. SMOD# V IH_SMOD V IL_SMOD V IH_PWM V IH_PWM VVIL_PWM IL_PW M PWM 90% GH to VSWH 1 0% 1 0% DCM V OUT CCM CCM 2.2V VSWH GL 90% 2.2V 1 0% tPD_PLGHL t PD_PHGLL t D_DEADON tD_DEADOFF 1 0% t PD_PHGHH t PD_SLGLL Delay from SMOD# going Delay from SMOD# going LOW to LS VGS LOW LOW to LS V GS LOW t PD_SHGLH Delay SMOD# going Delayfrom from SMOD# going HIGH to LS VGS HIGH HIGH to LS VGS HIGH HSturn turn-on HS withSMOD# SMOD#LOW LOW - onwith Data Sheet March 8, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 20 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device 2.6. PWM Figure 2.6 PWM Timing V IH_PWM V IL_PWM PWM 90% GL 1.0V 10% 90% GH to VSWH 1.2V 10% 2.2V VSWH t PD_PHGLL t D_DEADON Data Sheet March 8, 2013 t D_TIMEOUT ( 250ns Timeout) t PD_PLGHL t D_DEADOFF © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 21 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device 3 3.1. Application Design 5V Linear Regulator Capacitor Selection For the linear regulator output (VCIN), a local ceramic bypass capacitor is required for linear regulator stability. This capacitor is also needed to reduce noise and is used to supply the peak power MOSFET low-side gate current and boot capacitor charging current. Use at least a 1µF capacitor with an X7R or X5R dielectric. Keep this capacitor close to the VCIN pin and connect it to the CGND ground plane with vias. A 1µF bypass capacitor with an X7R or X5R dielectric is also recommended from VDRV to CGND. 3.2. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (C BOOT), as shown in Figure 3.1. A bootstrap capacitance of 100nF using an X7R or X5R capacitor is typically adequate. A series bootstrap resistor may be needed for specific applications to improve switching noise immunity. The boot resistor may be required when operating near the maximum rated VIN and is effective at controlling the high-side MOSFET turn-on slew rate and VSWH overshoot. Typical RBOOT values from 0.5Ω to 2.0Ω are effective in reducing VSWH overshoot. 3.3. Power Loss and Efficiency Testing Procedures The circuit in Figure 3.1 has been used to measure power losses. The efficiency has been calculated based on the equations below. Power loss calculations: PIN VIN IIN V5 V I5 V (1) PSW VSW IOUT (2) POUT VOUT IOUT (3) PLOSS _ MODULE PIN PSW (4) PLOSS _ BOARD PIN POUT (5) Data Sheet March 8, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 22 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device Efficiency calculations: P EFFMODULE 100 SW PIN % P EFFBOARD 100 OUT PIN % Figure 3.1 (6) (7) Power Loss Measurement Block Diagram Open Drain Output THWN# VDRV A VIN CVIN IVDRV VIN IIN VDRV A BOOT VCIN CVDRV RBOOT CVCIN CGND CBOOT ZSPM9000 PWM Input LOUT PWM VOUT A PHASE OFF IOUT SMOD# ON VSWH COUT DISB DISB# v VSW PGND Data Sheet March 8, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 23 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device 4 4.1. Pin Configuration and Package Available Packages The ZSPM9000 is available in a 40-lead clip-bond PQFN package. The pin-out is shown in Figure 4.1. See Figure 4.2 for the mechanical drawing of the package. 11 40 12 39 38 37 VSWH VSWH 36 GL PGND PGND 35 VSWH PGND PGND 34 VSWH PGND PGND 33 VSWH PGND PGND 32 VSWH PGND PGND 31 VIN 13 VIN 14 NC VSWH VIN 42 CGND 41 VSWH 43 21 21 22 23 PGND PGND CGND 15 PHASE PGND VIN 16 GH PGND THWN# VIN 17 CGND PGND VIN 18 BOOT PGND DISB# VIN 19 VDRV PGND PWM VIN 20 VCIN VIN VIN 24 25 26 27 28 29 30 VSWH PGND VIN VSWH VSWH SMOD# 1 PGND March 8, 2013 VCIN Data Sheet 2 PGND Bottom View 22 VDRV 23 3 PGND 24 BOOT 25 4 PGND 26 5 PGND 27 6 PGND 28 7 PGND 29 8 PGND 30 CGND VSWH 43 GH 31 VIN 42 9 20 32 CGND 41 PHASE 10 NC 10 VIN VIN 9 19 33 VSWH 8 18 34 VSWH 7 17 35 VSWH 6 16 36 VSWH 5 15 37 VSWH 4 14 38 GL 3 13 39 CGND 2 12 40 THWN# 1 11 PWM DISB# SMOD# Pin-out PQFN40 Package VSWH Figure 4.1 Top View © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 24 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device 4.2. Pin Description Pin Name Description 1 SMOD# When SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW, the low-side driver is disabled. This pin has a 10µA internal pull-up current source. Do not add a noise filter capacitor. 2 VCIN Linear regulator 5V output. Minimum 1µF X5R/X7R ceramic capacitor to CGND is required. 3 VDRV Linear regulator input. Minimum 1µF X5R/X7R ceramic capacitor to CGND is required. 4 BOOT Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a bootstrap capacitor from this pin to PHASE. 5, 37, 41 CGND Ground return for driver IC. 6 GH 7 PHASE 8 NC No connection. The pin is not electrically connected internally but can be connected to VIN for convenience. 9 - 14, 42 VIN Input power voltage (output stage supply voltage). 15, 29 - 35, 43 VSWH Switch node. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection. 16 – 28 PGND Power ground (output stage ground). Source pin of the low-side MOSFET. 36 GL 38 THWN# 39 DISB# Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter capacitor. 40 PWM PWM signal input. This pin accepts a tri-state 3.3V PWM signal from the controller. Data Sheet March 8, 2013 Gate high. For manufacturing test only. This pin must float: it must not be connected. Switch node pin for bootstrap capacitor routing; electrically shorted to VSWH pin. Gate low. For manufacturing test only. This pin must float. It must not be connected. Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module. © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 25 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device 4.3. Package Dimensions Figure 4.2 PQFN40 Physical Dimensions and Recommended Footprint B 0.10 C PIN#1 INDICATOR 6.00 2X 5.80 A 4.50 30 21 31 6.00 20 2.50 0.40 0.65 0.25 1.60 0.10 C 11 40 2X 1 SEE 0.60 DETAIL 'A' 0.50 TYP TOP VIEW 10 0.35 0.15 2.10 0.40 21 FRONT VIEW 4.40±0.10 (2.20) 0.10 C A B 0.05 C 0.30 30 0.20 (40X) 31 2.10 LAND PATTERN RECOMMENDATION 20 0.50 2.40±0.10 (0.70) 0.20 PIN #1 INDICATOR 1.50±0.10 11 10 0.40 2.00±0.10 (0.20) 40 1 2.00±0.10 0.50 NOTES: UNLESS OTHERWISE SPECIFIED (0.20) BOTTOM VIEW 1.10 0.90 0.10 C 0.08 C 0.30 0.20 0.50 (40X) 0.30 0.05 0.00 DETAIL 'A' C A) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO-220, DATED MAY/2005. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) DRAWING FILE NAME: PQFN40AREV2 SEATING PLANE SCALE: 2:1 Data Sheet March 8, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 26 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device 5 Circuit Board Layout Considerations Figure 5.1 provides an example of a proper layout for the ZSPM9000 and critical components. All of the highcurrent paths, such as VIN, VSWH, VOUT, and GND copper traces, should be short and wide for low inductance and resistance. This technique achieves a more stable and evenly distributed current flow with enhanced heat radiation and system performance. The following guidelines are recommendations for the printed circuit board (PCB) designer: 1. Input ceramic bypass capacitors must be placed close to the VIN and PGND pins. This helps reduce the highcurrent power loop inductance and the input current ripple induced by the power MOSFET switching operation. 2. The VSWH copper trace serves two purposes. In addition to being the high-frequency current path from the DrMOS package to the output inductor, it also serves as a heat sink for the low-side MOSFET in the DrMOS package. The trace should be short and wide enough to present a low-impedance path for the highfrequency, high-current flow between the DrMOS and inductor to minimize losses and temperature rise. Note that the VSWH node is a high-voltage and high-frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace also acts as a heat sink for the lower FET, balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission. 3. An output inductor should be located close to the ZSPM9000 to minimize the power loss due to the VSWH copper trace. Care should also be taken so the inductor dissipation does not heat the DrMOS. 4. The power MOSFETs used in the output stage are effective at minimizing ringing due to fast switching. In most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and PGND pins. The resistor and capacitor must be the proper size for the power dissipation. 5. VCIN, VDRV, and BOOT capacitors should be placed as close as possible to the respective pins to ensure clean and stable power. Routing width and length should be considered as well. 6. Include a trace from PHASE to VSWH to improve the noise margin. Keep the trace as short as possible. 7. The layout should include a placeholder to insert a small-value series boot resistor (RBOOT) between the boot capacitor (CBOOT) and DrMOS BOOT pin. The BOOT-to-VSWH loop size, including RBOOT and CBOOT, should be as small as possible. The boot resistor may be required when operating near the maximum rated V IN. The boot resistor is effective at controlling the high-side MOSFET turn-on slew rate and VSWH overshoot. RBOOT can improve the noise operating margin in synchronous buck designs that might have noise issues due to ground bounce or high positive and negative VSWH ringing. However, inserting a boot resistance lowers the DrMOS efficiency. Efficiency versus noise trade-offs must be considered. RBOOT values from 0.5Ω to 2.0Ω are typically effective in reducing VSWH overshoot. 8. The VIN and PGND pins handle large current transients with frequency components greater than 100MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. Added inductance in series with the VIN or PGND pin degrades system noise immunity by increasing positive and negative VSWH ringing. 9. CGND pad and PGND pins should be connected to the GND plane copper with multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead to faulty operation of the gate driver and MOSFETs. Data Sheet March 8, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 27 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device 10. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add a capacitor from BOOT to ground; this may lead to excess current flow through the BOOT diode. 11. The SMOD# and DISB# pins have weak internal pull-up and pull-down current sources, respectively. Do NOT float these pins if avoidable. These pins should not have any noise filter capacitors. 12. Use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute current flow and heat conduction. Vias should be relatively large and of reasonably low inductance. Critical highfrequency components, such as RBOOT, CBOOT, the RC snubber, and bypass capacitors should be located as close to the respective DrMOS module pins as possible on the top layer of the PCB. If this is not feasible, they should be connected from the backside through a network of low-inductance vias. Figure 5.1 PCB Layout Example Top View Data Sheet March 8, 2013 Bottom View © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 28 of 29 ZSPM9000 Ultra-Compact, High-Performance DrMOS Device 6 Ordering Information Product Sales Code Description Package ZSPM9000AI1R ZSPM9000 Lead-free PQFN40 — Temperature range: -40°C to +125°C Reel ZSPM8000-KIT Integrated Evaluation Kit for ZSPM9000 and ZSPM1000 Kit 7 Related Documents Note: X_xy refers to the latest version of the document. Document File Name ZSPM8000-KIT Evaluation Kit Description ZSPM8000_Eval_Kit_Rev_X_xy Visit ZMDI’s website www.zmdi.com or contact your nearest sales office for the latest version of these documents. 8 Document Revision History Revision Date Description 1.00 September 22, 2011 First release 1.01 March 12, 2012 Minor edits to text and figures. Update for ZMDI contact information. 1.02 November 19, 2012 Minor edits. Update for ZMDI contact information. 1.03 March 8, 2013 Updates for cover and header imagery and contact table. Sales and Further Information www.zmdi.com [email protected] Zentrum Mikroelektronik Dresden AG Global Headquarters Grenzstrasse 28 01109 Dresden, Germany ZMD America, Inc. 1525 McCarthy Blvd., #212 Milpitas, CA 95035-7453 USA Central Office: Phone +49.351.8822.306 Fax +49.351.8822.337 USA Phone 1.855.275.9634 Phone +1.408.883.6310 Fax +1.408.883.6358 European Technical Support Phone +49.351.8822.7.772 Fax +49.351.8822.87.772 DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise. European Sales (Stuttgart) Phone +49.711.674517.55 Fax +49.711.674517.87955 Data Sheet March 8, 2013 Zentrum Mikroelektronik Dresden AG, Japan Office 2nd Floor, Shinbashi Tokyu Bldg. 4-21-3, Shinbashi, Minato-ku Tokyo, 105-0004 Japan ZMD FAR EAST, Ltd. 3F, No. 51, Sec. 2, Keelung Road 11052 Taipei Taiwan Phone +81.3.6895.7410 Fax +81.3.6895.7301 Phone +886.2.2377.8189 Fax +886.2.2377.8199 Zentrum Mikroelektronik Dresden AG, Korea Office U-space 1 Building 11th Floor, Unit JA-1102 670 Sampyeong-dong Bundang-gu, Seongnam-si Gyeonggi-do, 463-400 Korea Phone +82.31.950.7679 Fax +82.504.841.3026 © 2013 Zentrum Mikroelektronik Dresden AG — Rev.1.03 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 29 of 29