FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Benefits Description Ultra-Compact 6x6mm PQFN, 72% Space-Saving Compared to Conventional Discrete Solutions Fully Optimized System Efficiency The XS™ DrMOS family is Fairchild’s next-generation, fully optimized, ultra-compact, integrated MOSFET plus driver power stage solution for high-current, highfrequency, synchronous buck DC-DC applications. The FDMF6824A integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact 6x6 mm package. Clean Switching Waveforms with Minimal Ringing High-Current Handling Features With an integrated approach, the complete switching power stage is optimized with regard to driver and MOSFET dynamic performance, system inductance, and power MOSFET RDS(ON). XS™ DrMOS uses Fairchild's high-performance PowerTrench® MOSFET technology, which dramatically reduces switch ringing, eliminating the need for snubber circuit in most buck converter applications. Over 93% Peak-Efficiency Driver Output Disable Function (DISB# Pin) Internal Pull-Up and Pull-Down for SMOD# and DISB# Inputs, Respectively A driver IC with reduced dead times and propagation delays further enhances the performance. A thermal warning function warns of a potential over-temperature situation. The FDMF6824A also incorporates a Skip Mode (SMOD#) for improved light-load efficiency. The FDMF6824A also provides a 3-state 5 V PWM input for compatibility with a wide range of PWM controllers. Fairchild PowerTrench® Technology MOSFETs for Clean Voltage Waveforms and Reduced Ringing Applications Fairchild SyncFET™ (Integrated Schottky Diode) Technology in Low-Side MOSFET High-Performance Gaming Motherboards Integrated Bootstrap Schottky Diode Adaptive Gate Drive Timing for Shoot-Through Protection Desktop Computers, V-Core and Non-V-Core DC-DC Converters Under-Voltage Lockout (UVLO) Workstations Small Form-Factor Voltage Regulator Modules High-Current Handling: 60 A High-Performance PQFN Copper-Clip Package 3-State 5 V PWM Input Driver Skip-Mode SMOD# (Low-Side Gate Turn Off) Input Thermal Warning Flag for Over-Temperature Condition Optimized for Switching Frequencies up to 1 MHz Low-Profile SMD Package Fairchild Green Packaging and RoHS Compliance Based on the Intel® 4.0 DrMOS Standard Compact Blade Servers, V-Core and Non-V-Core DC-DC Converters High-Current DC-DC Point-of-Load Converters Networking and Telecom Microprocessor Voltage Regulators Ordering Information Part Number Current Rating Package Top Mark FDMF6824A 60 A 40-Lead, Clipbond PQFN DrMOS, 6.0 mm x 6.0 mm Package FDMF6824A © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 www.fairchildsemi.com FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module May 2013 V5V VIN 3V ~ 16V RVCIN C VCIN C VDRV VDRV DISB# VCIN C VIN VIN RBOOT DISB# BOOT PWM Input PWM C BOOT FDMF6824A OFF PHASE SMOD# ON OpenDrain Output VSWH THWN# VOUT L OUT CGND Figure 1. COUT PGND Typical Application Circuit DrMOS Block Diagram VDRV VCIN VIN BOOT UVLO Q1 HS Power MOSFET DBoot DISB# GH Level-Shift GH Logic 10µA 30k PHASE VCIN Dead-Time RUP_PWM Input 3-State Logic PWM Control FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Application Circuit VSWH VDRV RDN_PWM GL GL Logic THWN# VCIN 30k Temp. Sense Q2 LS Power MOSFET 10µA CGND Figure 2. © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 PGND SMOD# DrMOS Block Diagram www.fairchildsemi.com 2 11 40 12 39 13 38 14 37 15 36 16 35 34 VSWH PGND 33 VSWH PGND 32 VSWH PGND 31 VSWH VCIN VDRV BOOT CGND GH PHASE NC VIN VIN PGND PGND PGND PGND PGND PGND PGND 26 PGND PGND 25 Figure 4. 27 28 29 30 VSWH 24 VSWH 23 PGND 22 PGND 21 PGND Bottom View VSWH 43 PGND PGND 18 PGND 19 PGND 20 VSWH 17 SMOD# SMOD# PGND CGND 41 PGND VSWH VCIN GL PGND VIN 42 PGND VSWH VDRV VSWH 20 21 BOOT CGND VSWH 19 22 CGND THWN# 31 23 1 VIN 32 Figure 3. 24 2 VIN PGND 25 3 DISB# VSWH 26 4 VIN PGND 27 5 VIN VSWH 28 6 PWM PGND 29 7 VIN VSWH 30 8 VIN 33 VSWH 43 9 VIN 18 VIN 42 10 VIN 17 34 CGND 41 GH 10 PHASE 9 NC 8 VIN 7 16 35 VSWH 6 15 36 VSWH 5 14 37 GL 4 13 38 CGND 3 12 39 THWN# 2 11 40 DISB# 1 VIN PWM Top View Pin Definitions Pin # 1 Name Description When SMOD#=HIGH, the low-side driver is the inverse of the PWM input. When SMOD# SMOD#=LOW, the low-side driver is disabled. This pin has a 10 µA internal pull-up current source. Do not add a noise filter capacitor. 2 VCIN IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND. 3 VDRV Power for the gate driver. Minimum 1 µF ceramic capacitor is recommended to be connected as close as possible from this pin to CGND. 4 BOOT Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a bootstrap capacitor from this pin to PHASE. 5, 37, 41 CGND IC ground. Ground return for driver IC. 6 GH 7 FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Pin Configuration For manufacturing test only. This pin must float; it must not be connected to any pin. PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin. 8 NC No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience. 9 - 14, 42 VIN Power input. Output stage supply voltage. 15, 29 35, 43 VSWH Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection. 16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET. 36 GL 38 THWN# 39 DISB# Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are held LOW). This pin has a 10 µA internal pull-down current source. Do not add a noise filter capacitor. 40 PWM PWM signal input. This pin accepts a three-state 5 V PWM signal from the controller. For manufacturing test only. This pin must float; it must not be connected to any pin. Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module. © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 www.fairchildsemi.com 3 Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCIN Supply Voltage Referenced to CGND -0.3 6.0 V VDRV Drive Voltage Referenced to CGND -0.3 6.0 V VDISB# Output Disable Referenced to CGND -0.3 6.0 V VPWM PWM Signal Input Referenced to CGND -0.3 6.0 V Skip Mode Input Referenced to CGND -0.3 6.0 V Low Gate Manufacturing Test Pin Referenced to CGND -0.3 6.0 V Thermal Warning Flag Referenced to CGND -0.3 6.0 V Power Input Referenced to PGND, CGND -0.3 25.0 V Referenced to VSWH, PHASE -0.3 6.0 V Referenced to CGND -0.3 25.0 V Referenced to VSWH, PHASE -0.3 6.0 V Referenced to CGND -0.3 25.0 V Referenced to CGND -0.3 25.0 V Referenced to PGND, CGND (DC Only) -0.3 25.0 V Referenced to PGND, <20 ns -8.0 28.0 V Referenced to VDRV 22.0 V Referenced to VDRV, <20 ns 25.0 V 7.0 mA VSMOD# VGL VTHWN# VIN VBOOT Bootstrap Supply VGH High Gate Manufacturing Test Pin VPHS PHASE VSWH Switch Node Input VBOOT Bootstrap Supply ITHWN# THWN# Sink Current -0.1 (1) fSW=300 kHz, VIN=12 V, VO=1.0 V 60 fSW=1 MHz, VIN=12 V, VO=1.0 V 55 IO(AV) Output Current θJPCB Junction-to-PCB Thermal Resistance TA Ambient Temperature Range TJ Maximum Junction Temperature TSTG Storage Temperature Range ESD Electrostatic Discharge Protection -40 -55 Human Body Model, JESD22-A114 2000 Charged Device Model, JESD22-C101 2500 A 2.7 °C/W +125 °C +150 °C +150 °C V FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Absolute Maximum Ratings Note: 1. IO(AV) is rated using Fairchild’s DrMOS evaluation board, at TA = 25°C, with natural convection cooling. This rating is limited by the peak DrMOS temperature, TJ = 150°C, and varies depending on operating conditions and PCB layout. This rating can be changed with different application settings. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit VCIN Control Circuit Supply Voltage 4.5 5.0 5.5 V VDRV Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V (2) VIN Output Stage Supply Voltage 3.0 12.0 16.0 V Note: 2. Operating at high VIN can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional information. © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 www.fairchildsemi.com 4 Typical values are VIN = 12 V, VCIN = 5 V, VDRV = 5 V, and TA = TJ = +25°C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit Basic Operation IQ Quiescent Current IQ=IVCIN+IVDRV, PWM=LOW or HIGH or Float VUVLO UVLO Threshold VCIN Rising VUVLO_Hys UVLO Hysteresis 2.9 3.1 2 mA 3.3 V 0.4 V PWM Input (VCIN = VDRV = 5 V ±10%) RUP_PWM Pull-Up Impedance VPWM=5 V 10 kΩ RDN_PWM Pull-Down Impedance VPWM=0 V 10 kΩ VIH_PWM PWM High Level Voltage 3.04 3.55 4.05 V VTRI_HI 3-State Upper Threshold 2.95 3.45 3.94 V VTRI_LO 3-State Lower Threshold 0.98 1.25 1.52 V VIL_PWM PWM Low Level Voltage 0.84 1.15 1.42 V 160 200 ns 2.50 2.80 V tD_HOLD-OFF 3-State Shut-Off Time VHiZ_PWM 3-State Open Voltage 2.20 PWM Input (VCIN = VDRV = 5 V ±5%) RUP_PWM Pull-Up Impedance VPWM=5 V 10 kΩ RDN_PWM Pull-Down Impedance VPWM=0 V 10 kΩ VIH_PWM PWM High Level Voltage 3.22 3.55 3.87 V VTRI_HI 3-State Upper Threshold 3.13 3.45 3.77 V VTRI_LO 3-State Lower Threshold 1.04 1.25 1.46 V VIL_PWM PWM Low Level Voltage 0.90 1.15 1.36 V 160 200 ns 2.30 2.50 2.70 V tD_HOLD-OFF 3-State Shut-Off Time VHiZ_PWM 3-State Open Voltage DISB# Input VIH_DISB High-Level Input Voltage VIL_DISB Low-Level Input Voltage IPLD 2 V 0.8 Pull-Down Current tPD_DISBL Propagation Delay PWM=GND, Delay Between DISB# from HIGH to LOW to GL from HIGH to LOW tPD_DISBH Propagation Delay PWM=GND, Delay Between DISB# from LOW to HIGH to GL from LOW to HIGH V 10 µA 25 ns 25 ns FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Electrical Characteristics SMOD# Input VIH_SMOD High-Level Input Voltage VIL_SMOD Low-Level Input Voltage IPLU 2 V 0.8 Pull-Up Current V 10 µA tPD_SLGLL Propagation Delay PWM=GND, Delay Between SMOD# from HIGH to LOW to GL from HIGH to LOW 10 ns tPD_SHGLH Propagation Delay PWM=GND, Delay Between SMOD# from LOW to HIGH to GL from LOW to HIGH 10 ns Continued on the following page… © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 www.fairchildsemi.com 5 Typical values are VIN = 12 V, VCIN = 5 V, VDRV = 5 V, and TA = TJ = +25°C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit Thermal Warning Flag TACT Activation Temperature TRST Reset Temperature RTHWN Pull-Down Resistance IPLD=5 mA 150 °C 135 °C 30 Ω 1 Ω High-Side Driver (fSW = 1000 kHz, IOUT = 30 A, TA = +25°C) RSOURCE_GH Output Impedance, Sourcing Source Current=100 mA Output Impedance, Sinking Sink Current=100 mA 0.8 Ω tR_GH Rise Time GH=10% to 90% 10 ns tF_GH Fall Time GH=90% to 10% 10 ns tD_DEADON LS to HS Deadband Time GL Going LOW to GH Going HIGH, 1.0 V GL to 10% GH 15 ns tPD_PLGHL PWM LOW Propagation Delay PWM Going LOW to GH Going LOW, VIL_PWM to 90% GH 20 tPD_PHGHH PWM HIGH Propagation Delay (SMOD# =0) PWM Going HIGH to GH Going HIGH, VIH_PWM to 10% GH (SMOD# =0, ID_LS>0) 30 ns tPD_TSGHH Exiting 3-State Propagation Delay PWM (From 3-State) Going HIGH to GH Going HIGH, VIH_PWM to 10% GH 30 ns RSINK_GH 30 ns Low-Side Driver (fSW = 1000 kHz, IOUT = 30 A, TA = +25°C) 1 Ω Output Impedance, Sinking Sink Current=10 0mA 0.5 Ω tR_GL Rise Time GL=10% to 90% 30 ns tF_GL Fall Time GL=90% to 10% 15 ns SW Going LOW to GL Going HIGH, 2.2 V SW to 10% GL 15 ns RSOURCE_GL Output Impedance, Sourcing Source Current=100 mA RSINK_GL tD_DEADOFF HS to LS Deadband Time tPD_PHGLL PWM-HIGH Propagation Delay PWM Going HIGH to GL Going LOW, VIH_PWM to 90% GL 10 tPD_TSGLH Exiting 3-State Propagation Delay PWM (From 3-State) Going LOW to GL Going HIGH, VIL_PWM to 10% GL 20 ns VF Forward-Voltage Drop IF=20 mA 0.3 V VR Breakdown Voltage IR=1 mA 25 ns Boot Diode © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 22 FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Electrical Characteristics V www.fairchildsemi.com 6 V IH_PWM V IL_PWM PWM 90% GL 1.0V 10% 90% GH to VSWH 1.2V 10% 2.2V VSWH t PD_PLGHL t PD_PHGLL t D_DEADOFF t D_DEADON Figure 5. © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 PWM Timing Diagram FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Timing Diagram www.fairchildsemi.com 7 60 11 55 10 50 9 45 Module Power Loss, PLMOD (W) Module Output Current, IOUT (A) Test Conditions: VIN=12 V, VOUT=1 V, VCIN=5 V, VDRV=5 V, LOUT=250 nH, TA=25°C, and natural convection cooling, unless otherwise specified. FSW = 300kHz 40 35 30 FSW = 1000kHz 25 20 15 10 VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V 5 8 VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V 5 15 20 25 30 35 40 Module Output Current, IOUT (A) 7 6 5 4 3 2 1 0 0 0 25 50 75 100 PCB Temperature, T PCB ( C) Figure 6. 125 0 150 Safe Operating Area 10 Figure 7. 1.7 45 50 55 Power Loss vs. Output Current 1.12 VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V, IOUT = 30A VDRV & VCIN = 5V, VOUT = 1V, FSW = 300kHz, IOUT = 30A 1.6 1.10 Normalized Module Power Loss Normalized Module Power Loss 300kHz 500kHz 800kHz 1000kHz 1.5 1.4 1.3 1.2 1.1 1.0 0.9 1.08 1.06 1.04 1.02 1.00 0.98 100 200 Figure 8. 300 400 500 600 700 800 900 Module Switching Frequency, F SW (kHz) 1000 1100 4 Power Loss vs. Switching Frequency 6 Figure 9. 1.15 8 10 12 14 Module Input Voltage, VIN (V) 16 18 Power Loss vs. Input Voltage FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics 2.0 1.8 1.10 Normalized Module Power Loss Normalized Module Power Loss VIN = 12V, VOUT = 1V, FSW = 300kHz, IOUT = 30A 1.05 1.00 0.95 1.6 1.4 1.2 1.0 VIN = 12V, VDRV & VCIN = 5V, FSW = 300kHz, IOUT = 30A 0.90 0.8 4.0 4.5 5.0 5.5 Driver Supply Voltage, VDRV & VCIN (V) 6.0 0.5 Figure 10. Power Loss vs. Driver Supply Voltage © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 1.0 1.5 2.0 2.5 3.0 Module Output Voltage, VOUT (V) 3.5 4.0 Figure 11. Power Loss vs. Output Voltage www.fairchildsemi.com 8 Test Conditions: VIN=12 V, VOUT=1 V, VCIN=5 V, VDRV=5 V, LOUT=250 nH, TA=25°C, and natural convection cooling, unless otherwise specified. 1.005 70 VIN = 12V, VDRV & VCIN = 5V, FSW = 300kHz, VOUT = 1V, IOUT = 30A VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V, IOUT = 0A Driver Supply Current, I DRV & ICIN (mA) Normalized Module Power Loss 1.000 0.995 0.990 0.985 0.980 0.975 200 250 Figure 12. 300 350 400 Output Inductor, L OUT (nH) 450 60 50 40 30 20 10 100 500 Power Loss vs. Output Inductor 200 Figure 13. 26 Driver Supply Current vs. Switching Frequency VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V 1.02 Normalized Driver Supply Current 24 22 20 18 16 FSW = 300kHz 1.01 1.00 FSW = 1000kHz 0.99 0.98 0.97 14 4.0 4.5 5.0 5.5 Driver Supply Voltage, VDRV & VCIN (V) Figure 14. 0 6.0 5 Driver Supply Current vs. Driver Supply Figure 15. Voltage 3.2 10 15 20 25 30 35 40 Module Output Current, IOUT (A) 45 50 55 Driver Supply Current vs. Output Current 4.5 TA = 25°C UVLOUP VIH_PWM 4.0 PWM Threshold Voltage, VPWM (V) 3.1 Driver IC Supply Voltage, VCIN (V) 1000 1100 1.03 VIN = 12V, VOUT = 1V, FSW = 300kHz, IOUT = 0A Driver Supply Current, IDRV & ICIN (mA) 300 400 500 600 700 800 900 Module Switching Frequency, F SW (kHz) FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics 3.0 2.9 2.8 2.7 UVLODN 2.6 3.5 VTRI_HI 3.0 VHIZ_PWM 2.5 2.0 VTRI_LO 1.5 VIL_PWM 1.0 0.5 -55 Figure 16. 0 25 55 100 125 Driver IC Junction Temperature, T J (oC) 150 UVLO Threshold vs. Temperature © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 4.50 Figure 17. 4.75 5.00 5.25 Driver IC Supply Voltage, VCIN (V) 5.50 PWM Threshold vs. Driver Supply Voltage www.fairchildsemi.com 9 Test Conditions: VCIN=5 V, VDRV=5 V, TA=25°C, and natural convection cooling, unless otherwise specified. 4.5 2.2 TA = 25°C VCIN = 5V SMOD# Threshold Voltage, VSMOD (V) PWM Threshold Voltage, VPWM (V) 4.0 VIH_PWM 3.5 VTRI_HI 3.0 VHIZ_PWM 2.5 2.0 1.5 VTRI_LO 1.0 VIL_PWM 0.5 VIH_SMOD# 2.0 1.8 1.6 VIL_SMOD# 1.4 1.2 -55 0 25 55 100 125 Driver IC Junction Temperature, T J (oC) Figure 18. 150 4.50 PWM Threshold vs. Temperature Figure 19. 2.2 SMOD# Threshold vs. Driver Supply Voltage VCIN = 5V SMOD# Pull-Up Current, IPLU (uA) SMOD# Threshold Voltage, VSMOD (V) 5.50 -9.0 VCIN = 5V 2 VIH_SMOD# 1.8 1.6 VIL_SMOD# 1.4 1.2 -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 -55 Figure 20. 0 25 55 100 125 Driver IC Junction Temperature, T J (oC) 150 SMOD# Threshold vs. Temperature -55 Figure 21. 2.2 0 25 55 100 125 Driver IC Junction Temperature, T J (oC) 150 SMOD# Pull-Up Current vs. Temperature 2.2 VCIN = 5V TA = 25°C VIH_DISB# DISB# Threshold Voltage, VDISB (V) DISB# Threshold Voltage, V DISB (V) 4.75 5.00 5.25 Driver IC Supply Voltage, VCIN (V) FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics 2.0 1.8 1.6 VIL_DISB# 1.4 2.0 VIH_DISB# 1.8 1.6 VIL_DISB# 1.4 1.2 1.2 4.50 Figure 22. 4.75 5.00 5.25 Driver IC Supply Voltage, VCIN (V) -55 5.50 DISB# Threshold vs. Driver Supply Voltage © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 Figure 23. 0 25 55 100 125 Driver IC Junction Temperature, T J (oC) 150 DISB# Threshold vs. Temperature www.fairchildsemi.com 10 Test Conditions: VCIN=5 V, VDRV=5 V, TA=25°C, and natural convection cooling, unless otherwise specified. 12.0 500 VCIN = 5V IF = 20mA 11.5 Boot Diode Forward Voltage, V F (mV) DISB# Pull-Down Current, IPLD (uA) 450 11.0 10.5 10.0 9.5 400 350 300 250 200 150 100 9.0 -55 Figure 24. 0 25 55 100 125 Driver IC Junction Temperature, T J (oC) -55 150 DISB# Pull-Down Current vs. Temperature © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 0 25 55 100 125 150 Driver IC Junction Temperature, T J (oC) Figure 25. Boot Diode Forward Voltage vs. Temperature FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics www.fairchildsemi.com 11 The FDMF6824A is a driver-plus-FET module optimized for the synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 1 MHz. Three-State PWM Input The FDMF6824A incorporates a three-state 5 V PWM input gate drive design. The three-state gate drive has both logic HIGH level and LOW level, along with a three-state shutdown window. When the PWM input signal enters and remains within the three-state window for a defined hold-off time (tD_HOLD-OFF), both GL and GH are pulled LOW. This enables the gate drive to shut down both high-side and low-side MOSFETs to support features such as phase shedding, which is common on multi-phase voltage regulators. VCIN and Disable (DISB#) The VCIN pin is monitored by an Under-Voltage Lockout (UVLO) circuit. When VCIN rises above ~3.1 V, the driver is enabled. When VCIN falls below ~2.7 V, the driver is disabled (GH, GL=0). The driver can also be disabled by pulling the DISB# pin LOW (DISB# < VIL_DISB), which holds both GL and GH LOW regardless of the PWM input state. The driver can be enabled by raising the DISB# pin voltage HIGH (DISB# > VIH_DISB). Table 1. Exiting Three-State Condition When exiting a valid three-state condition, the FDMF6824A follows the PWM input command. If the PWM input goes from three-state to LOW, the low-side MOSFET is turned on. If the PWM input goes from three-state to HIGH, the high-side MOSFET is turned on. This is illustrated in Figure 1. The FDMF6824A design allows for short propagation delays when exiting the three-state window (see Electrical Characteristics). UVLO and Disable Logic UVLO DISB# Driver State 0 X Disabled (GH, GL=0) 1 0 Disabled (GH, GL=0) 1 1 Enabled (see Table 2) 1 Open Disabled (GH, GL=0) Low-Side Driver The low-side driver (GL) is designed to drive a groundreferenced, low-RDS(ON), N-channel MOSFET. The bias for GL is internally connected between the VDRV and CGND pins. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB#=0 V), GL is held LOW. Note: 3. DISB# internal pull-down current source is 10 µA. Thermal Warning Flag (THWN#) The FDMF6824A provides a thermal warning flag (THWN#) to warn of over-temperature conditions. The thermal warning flag uses an open-drain output that pulls to CGND when the activation temperature (150°C) is reached. The THWN# output returns to a highimpedance state once the temperature falls to the reset temperature (135°C). For use, the THWN# output requires a pull-up resistor, which can be connected to VCIN. THWN# does NOT disable the DrMOS module. HIGH THWN# Logic State High-Side Driver The high-side driver (GH) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit consisting of the internal Schottky diode and external bootstrap capacitor (CBOOT). During startup, VSWH is held at PGND, allowing CBOOT to charge to VDRV through the internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from CBOOT and delivered to the gate of Q1. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN + VBOOT, which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling GH to VSWH. CBOOT is then recharged to VDRV when VSWH falls to PGND. GH output is in-phase with the PWM input. The high-side gate is held LOW when the driver is disabled or the PWM signal is held within the three-state window for longer than the three-state hold-off time, tD_HOLD-OFF. 135°C Reset 150°C Temperature Activation Temperature Normal Operation Thermal Warning LOW FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Functional Description TJ_driver IC Figure 26. THWN Operation © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 www.fairchildsemi.com 12 The driver IC advanced design ensures minimum MOSFET dead-time, while eliminating potential shootthrough (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to ensure they do not conduct simultaneously. Figure 1 provides the relevant timing waveforms. To prevent overlap during the LOW-to-HIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes V IH_PWM To preclude overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the GH-to-PHASE pin pair. When the PWM signal goes LOW, Q1 begins to turn off after a propagation delay (tPD_PLGHL). Once the voltage across GH-to-PHASE falls below 2.2 V, Q2 begins to turn on after adaptive delay tD_DEADOFF. V IH_PWM V IH_PWM V IH_PWM V TRI_HI V TRI_HI tD_HOLD-OFF V TRI_LO V IL_PWM V IL_PWM tR_GH PWM tF_GH 9 0% GH to VSWH 1 0% V IN DCM DCM CCM V OUT 2.2V VSWH tR_GL GL tF_GL 90% 9 0% 1.0V tPD_PHGLL tD_DEADON 1 0% 1 0% tPD_PLGHL tPD_TSGHH tD_HOLD-OFF t PD_TSGHH tD_HOLD-OFF tPD_TSGLH tD_DEADOFF Exit 3 -state Enter 3 -state Enter 3 -state Exit 3 -state Enter 3 -state Exit 3 -state Notes: tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal. Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW) tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH) PWM tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW) Exiting 3-state tPD_TSGHH = PWM 3-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS tPD_TSGLH = PWM 3-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS SMOD# tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS Dead Times tD_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS Figure 27. © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module HIGH, Q2 begins to turn off after a propagation delay (tPD_PHGLL). Once the GL pin is discharged below 1.0 V, Q1 begins to turn on after adaptive delay tD_DEADON. Adaptive Gate Drive Circuit PWM and 3-StateTiming Diagram www.fairchildsemi.com 13 The Skip Mode function allows for higher converter efficiency when operated in light-load conditions. When SMOD# is pulled LOW, the low-side MOSFET gate signal is disabled (held LOW), preventing discharge of the output capacitors as the filter inductor current attempts reverse current flow – known as “Diode Emulation” Mode. Table 2. SMOD# Logic DISB# PWM SMOD# GH GL 0 X X 0 0 1 3-State X 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 Note: 4. The SMOD# feature is intended to have a short propagation delay between the SMOD# signal and the low-side FET VGS response time to control diode emulation on a cycle-by-cycle basis. SMOD# V IH_SMOD V IL_SMOD V IH_PWM V IH_PWM V IL_PWM PWM 90% GH to VSWH 1 0% 1 0% DCM V OUT CCM CCM 2.2V FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module When the SMOD# pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode. This mode allows for gating on the Low Side MOSFET. When the SMOD# pin is pulled LOW, the low-side MOSFET is gated off. If the SMOD# pin is connected to the PWM controller, the controller can actively enable or disable SMOD# when the controller detects light-load condition from output current sensing. Normally this pin is active LOW. See Figure 28 for timing delays. Skip Mode (SMOD#) VSWH GL 90% 1.0V tPD_PHGLL tD_DEADON 1 0% 1 0% tPD_PLGHL tPD_PHGHH tPD_SLGLL tD_DEADOFF Delay from SMOD# going LOW to LS VGS LOW tPD_SHGLH Delay from SMOD# going HIGH to LS V GS HIGH HS turn -on with SMOD# LOW Figure 28. © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 SMOD# Timing Diagram www.fairchildsemi.com 14 VCIN Filter Supply Capacitor Selection The VDRV pin provides power to the gate drive of the high-side and low-side power MOSFET. In most cases, it can be connected directly to VCIN, the pin that provides power to the logic section of the driver. For additional noise immunity, an RC filter can be inserted between the VDRV and VCIN pins. Recommended values would be 10 Ω and 1 µF. For the supply inputs (VCIN), a local ceramic bypass capacitor is recommended to reduce noise and to supply the peak current. Use at least a 1 µF X7R or X5R capacitor. Keep this capacitor close to the VCIN pin and connect it to the GND plane with vias. Bootstrap Circuit Power Loss and Efficiency The bootstrap circuit uses a charge storage capacitor (CBOOT), as shown in Figure 30. A bootstrap capacitance of 100 nF X7R or X5R capacitor is usually adequate. A series bootstrap resistor may be needed for specific applications to improve switching noise immunity. The boot resistor may be required when operating above 15 VIN and is effective at controlling the high-side MOSFET turn-on slew rate and VSHW overshoot. RBOOT values from 0.5 to 3.0 Ω are typically effective in reducing VSWH overshoot. V5V A I5V RVCIN CVDRV PIN=(VIN x IIN) + (V5V x I5V) (W) (1) PSW=VSW x IOUT (W) (2) POUT=VOUT x IOUT (W) (3) PLOSS_MODULE=PIN - PSW (W) (4) PLOSS_BOARD=PIN - POUT (W) (5) EFFMODULE=100 x PSW/PIN (%) (6) EFFBOARD=100 x POUT/PIN (%) (7) CVIN CVCIN VDRV DISB# Measurement and Calculation Refer to Figure 30 for power loss testing method. Power loss calculations are: A IIN VIN VCIN VIN DISB# RBOOT PWM Input BOOT PWM OFF SMOD# ON Open Drain Output FDMF6824A FDM 67 5 F 0 CBOOT IOUT VSWH A LOUT PHASE THWN# Figure 29. V5V A RVCIN PWM Input VCIN VIN IIN C VCIN C VDRV VDRV DISB# COUT Block Diagram With VCIN Filter A I5V VOUT V VSW PGND CGND FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Application Information C VIN VIN RBOOT DISB# BOOT PWM C BOOT FDMF6824A OFF PHASE ON OpenDrain Output SMOD# IOUT VSWH L OUT CGND Figure 30. © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 A THWN# PGND V VOUT COUT VSW Power Loss Measurement www.fairchildsemi.com 15 Figure 31 and Figure 32 provide an example of a proper layout for the FDMF6824A and critical components. All of the high-current paths, such as VIN, VSWH, VOUT, and GND copper, should be short and wide for low inductance and resistance. This aids in achieving a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. noise issues due to ground bounce or high positive and negative VSWH ringing. Inserting a boot resistance lowers the DrMOS efficiency. Efficiency versus noise trade-offs must be considered. RBOOT values from 0.5 to 3.0 are typically effective in reducing VSWH overshoot. 8. The VIN and PGND pins handle large current transients with frequency components greater than 100MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. This added inductance in series with either the VIN or PGND pin degrades system noise immunity by increasing positive and negative VSWH ringing. Recommendations for PCB Designers 1. Input ceramic bypass capacitors must be placed close to the VIN and PGND pins. This helps reduce the high-current power loop inductance and the input current ripple induced by the power MOSFET switching operation. 2. The VSWH copper trace serves two purposes. In addition to being the high-frequency current path from the DrMOS package to the output inductor, it serves as a heat sink for the low-side MOSFET in the DrMOS package. The trace should be short and wide enough to present a low-impedance path for the high-frequency, high-current flow between the DrMOS and inductor. The short and wide trace minimizes electrical losses as well as the DrMOS temperature rise. Note that the VSWH node is a highvoltage and high-frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace acts as a heat sink for the lower MOSFET, balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission. 9. GND pad and PGND pins should be connected to the GND copper plane with multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead to faulty operation of the gate driver and MOSFETs. 10. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add an additional BOOT to the PGND capacitor. This may lead to excess current flow through the BOOT diode. 11. The SMOD# and DISB# pins have weak internal pull-up and pull-down current sources, respectively. These pins should not have any noise filter capacitors. Do not to float these pins unless absolutely necessary. 3. An output inductor should be located close to the FDMF6824A to minimize the power loss due to the VSWH copper trace. Care should also be taken so the inductor dissipation does not heat the DrMOS. 12. Use multiple vias on the VIN and VOUT copper areas to interconnect top, inner, and bottom layers to distribute current flow and heat conduction. Do not put many vias on the VSWH copper to avoid extra parasitic inductance and noise on the switching waveform. As long as efficiency and thermal performance are acceptable, place only one VSWH copper on the top layer and use no vias on the VSWH copper to minimize switch node parasitic noise. Vias should be relatively large and of reasonably low inductance. Critical highfrequency components, such as RBOOT, CBOOT, RC snubber, and bypass capacitors; should be located as close to the respective DrMOS module pins as possible on the top layer of the PCB. If this is not feasible, they can be connected from the backside through a network of low-inductance vias. ® 4. PowerTrench MOSFETs are used in the output stage and are effective at minimizing ringing due to fast switching. In most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and PGND pins. The selected resistor and capacitor need to be the proper size for power dissipation. 5. VCIN, VDRV, and BOOT capacitors should be placed as close as possible to the VCIN-to-CGND, VDRV-to-CGND, and BOOT-to-PHASE pin pairs to ensure clean and stable power. Routing width and length should be considered as well. 6. Include a trace from the PHASE pin to the VSWH pin to improve noise margin. Keep this trace as short as possible. FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module PCB Layout Guidelines 7. The layout should include the option to insert a small-value series boot resistor between the boot capacitor and BOOT pin. The boot-loop size, including RBOOT and CBOOT, should be as small as possible. The boot resistor may be required when operating above 15 VIN and is effective at controlling the high-side MOSFET turn-on slew rate and VSHW overshoot. RBOOT can improve noise operating margin in synchronous buck designs that may have © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 www.fairchildsemi.com 16 Figure 32. © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 PCB Layout Example (Top View) FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Figure 31. PCB Layout Example (Bottom View) www.fairchildsemi.com 17 FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module Physical Dimensions B 0.10 C PIN#1 INDICATOR 6.00 2X 5.80 A 4.50 30 21 31 6.00 20 0.40 2.50 0.65 0.25 1.60 0.10 C 11 40 2X 1 SEE 0.60 DETAIL 'A' 0.50 TYP TOP VIEW 10 0.35 0.15 2.10 0.40 21 FRONT VIEW 4.40±0.10 (2.20) 0.10 C A B 0.05 C 0.30 30 0.20 (40X) 31 20 0.50 PIN #1 INDICATOR 0.20 MAY APPEAR AS OPTIONAL 2.40±0.10 (0.70) 1.50±0.10 11 10 0.40 2.00±0.10 (0.20) 0.50 (40X) 0.30 40 1 2.00±0.10 0.50 NOTES: UNLESS OTHERWISE SPECIFIED (0.20) BOTTOM VIEW A) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO-220, DATED MAY/2005. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) DRAWING FILE NAME: PQFN40AREV3 1.10 0.90 0.10 C 0.08 C 0.30 0.20 2.10 LAND PATTERN RECOMMENDATION 0.05 0.00 DETAIL 'A' C SEATING PLANE SCALE: 2:1 Figure 33. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0 mm Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 www.fairchildsemi.com 18 FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module © 2013 Fairchild Semiconductor Corporation FDMF6824A • Rev. 1.0.1 www.fairchildsemi.com 19