SPECIFICATION Date : 23.09.2003 DETAIL SPECIFICATION ELMOS Part Nr : 910.01B Page 1 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 SPECIFICATION Date : 23.09.2003 Contents 1 Project Summary 3 1.1 Purpose of Specification 3 1.2 Life Support Policy/Product Liability 3 1.3 General Information 3 1.4 Brief Functional Description 4 1.5 Related ELMOS Documents 4 1.6 Other Related Documents 4 1.7 Marking 4 2 General Device Specification 5 2.1 Absolute Maximum Ratings (Non - operating) 5 2.2 Recommended Operating Conditions 5 2.3 Package Outline 6 2.4 Package Pin-Out 7 2.5 Package Pin Definition 7 3 Detailed Electrical Description 8 3.1 Characteristics 3.1.1 DC Characteristics 3.1.2 Safe Operating Area of OUTx 3.1.3 AC Characteristics 8 8 9 9 4 Functional Description 11 4.1 Block Diagram 11 4.2 Detailed Functional Description 12 4.3 Protection Functions 13 4.4 Application Circuit 15 4.5 Timing Diagram 4.5.1 Operating Mode 4.5.2 RESET Mode (Sleep Mode) 4.5.3 Thermal Cut-off 4.5.4 Short Circuit Condition 16 16 16 17 17 4.6 Noise Immunity 18 4.7 ESD Protection Circuit 4.7.1 Test Method 18 18 5 Life Test Circuit 19 6 Record of Revisions 20 Page 2 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 SPECIFICATION 1 Date : 23.09.2003 Project Summary 1.1 Purpose of Specification The purpose of this specification is to define the mechanical, environmental and electrical characteristics for Application Specific integrated circuits supplied by ELMOS. All parts which comply with this specification shall be considered to meet the customers requirements. Any parameters which are left undefined will be processed in accordance with ELMOS´ standard Quality Control procedures. This document is intended to take precedence of any applicable customer documents. When agreed by the customer and ELMOS, no changes or additions may be made without the written agreement of both the customer and ELMOS. 1.2 Life Support Policy/Product Liability ELMOS products are not designed for use in Life Support Appliances, Devices or Systems where malfunction of an ELMOS product can be reasonably expected to result in personal injury. ELMOS customers using or selling ELMOS products for use in such applications do so at their own risk, and agree to full indemnify ELMOS for any damage resulting from such improper use or sale. 1.3 General Information Elmos Project Name : 910.01 Revision Status : B Package Type : 20PDIP / 20SOICW Page 3 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 SPECIFICATION Date : 23.09.2003 1.4 Brief Functional Description The IC E91001 is a 8-Way Power Driver (low side) with serial interface and interrogateable Output status. The device incorporates the following features : · · · · · · · · · · Low standby current Serial structure for direct MPU interfacing Cascadable Interrogateable TTL- compatible input levels with hysteresis 8 high current outputs (RON typ. 1.5 W) Wide output operating voltage range Output open- and short-circuit protection Individual output short-circuit protection Thermal overstress protection 1.5 Related ELMOS Documents QM-Nr:: 07PL0009.XX QM-Nr : 07SP0001.XX QM-Nr : 07VA0013E.XX QM-Nr : 07VA0005.XX QM-Nr : 02SP0028.XX Standard Qualification Plan Reliability Test Methods Reliability Testing Finalpart Release for Shipment (Warenausgangsprüfung) Taping of Devices 1.6 Other Related Documents None 1.7 Marking Topside : ELMOS 91001B XXX# YWW * Where : 91001B XXX # YWW * Part Number Lot Number Assembler Code Year and work week of assembly Mask Revision status Backside None. Page 4 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 SPECIFICATION 2 Date : 23.09.2003 General Device Specification 2.1 Absolute Maximum Ratings (Non - operating) Continuous operation of the device at or above these ratings is not permitted. Absolute Maximum Ratings : Parameter Logic supply voltage Transient Output Voltage (Maximum 500 ms) (Maximum 500 µs) Output current Output Current (Schaffner Pulses Type 2) Input Voltage Power dissipation DIP 20 TA = 85 °C Power dissipation SO 20 TA = 85 °C Thermal resistance DIL 20 (Junction to Ambient) Thermal resistance SO 20 (Junction to Ambient) Junction temperature Operating temperature range Storage temperature Symbol VDD VOUT VOUT IOUT |IOUT P| VIN P0 P0 RThJ-A min -0.3 -0.3 - max 7.0 40.0 50.0 350.0 600.0 VDD + 0.3 1000.0 800.0 65.0 Unit V V V mA mA V mW mW K/W RThJ-A - 80.0 K/W TJ TOPT TSTG -40.0 -55.0 + 150.0 + 125.0 + 150.0 °C °C °C 2.2 Recommended Operating Conditions The following conditions apply unless otherwise stated. All of the following parameters are valid for an operating temperature range of -40°C up to 105°C (production test max limit is at 85°C), a supply voltage range of 4.5V < VDD < 5.5V, an output current IOUT £ 300mA and an output voltage range of 5.5V to 25V, unless otherwise specified. Voltage reference is GND, if not otherwise specified. The current values are positive, if flowing into the circuit. Page 5 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 SPECIFICATION Date : 23.09.2003 2.3 Package Outline DIM a1 B b b1 D E e e3 F I L Z DIM a2 b b1 C c1 D E e e3 F G L M min mm typ .254 1.39 max min 1.65 .010 .055 0.46 0.25 inch typ max .065 .018 .010 25.40 1.00 8.5 2.54 22.86 .335 .100 .900 7.1 3.93 .280 .155 3.3 .130 1.34 min mm typ 0.35 0.23 max 2.45 0.49 0.32 .053 inch min typ .013 .009 0.5 1.27 11.43 7.4 8.8 0.5 max .096 .019 .012 .020 45° typ 13.0 .496 10.65 .393 12.6 10.0 DIL 20 (300 mil JEDEC-STD) .512 .419 .050 .450 7.6 9.15 1.27 0.75 .291 .346 .019 .300 .360 .050 .029 SO 20 (300 mil JEDEC-STD) Page 6 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 SPECIFICATION Date : 23.09.2003 2.4 Package Pin-Out GND GND GND TEST NC TEST NC OUT3 OUT4 OUT3 OUT4 OUT2 OUT5 OUT2 OUT5 OUT1 OUT6 OUT1 OUT6 OUT0 OUT7 OUT0 OUT7 CE RESET SCLK RESET VDD SI SO GND CE SCLK VDD SI GND SO GND GND GND DIL 20 SO 20 2.5 Package Pin Definition VDD GND OUT0-7 SI SO SCLK CE Power Supply Voltage Ground Open-Drain Low-Side Driver Serial Data Input Serial Data Output (High impedance when CE = High) Serial Data Input/Output Clock. (Data are clocked by the falling edge of the pulse.) Chip Enable - Active LOW. (Output Data is read back on the falling edge of the pulse, and only after 8 x n falling edges on SCLK is the output data clocked on the next rising edge.) RESET TEST Page 7 of 20 External Reset - Active LOW, or'd with internal Power On Reset. Test Mode Enable - Active HIGH > 3V : Test Mode 1 > 16V : Test Mode 2 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 Date : 23.09.2003 SPECIFICATION 3 Detailed Electrical Description 3.1 Characteristics 3.1.1 DC Characteristics Ref.Nr. Parameter 1 Power Supply Current 2 3 4 5 6 Symbol Condition IVDD min - typ - max 2.0 Unit mA Power Supply Current (Sleep Mode) Power On Reset Threshold IVDD VOUTX > 1.0V - <1.0 5.0 µA PORon VDD: 0V --> 5V 3) - - 3.6 V Thermal Cut-off Threshold THSoff TJ > THS 2) 3) 150.0 165.0 185.0 oC Thermal Cut-off Reset Threshold Thermal Surveillance Hysteresis THSon TJ > THS 2) 3) 125.0 140.0 155.0 oC 3) 20.0 40.0 60.0 oC THShys 3.1.1.1 Input Characteristics Ref. Pin LOW-Level HIGH-Level Hysteresis 3) Pull up Pull down Nr. min max min max min max min max min max 1 SI -0.3V 0.3VDD 0.75VDD VDD+0.3V 0.9V 1.7V - 1.0µA 1.0µA 2 SCLK -0.3V 0.3VDD 0.75VDD VDD+0.3V 0.9V 1.7V - 1.0µA 1.0µA 3 CE -0.3V 0.3VDD 0.75VDD VDD+0.3V 0.9V 1.7V - 1.0µA 1.0µA 4 RESET -0.3V 0.3VDD 0.75VDD VDD+0.3V 0.9V 1.7V - 5 TEST 0.3VDD 0.75VDD 8V 4) - - - - 10.0µA 50.0µA 16V 17V 5) - - 3.5V VOUT - - - - 30.0µA 90.0µA -0.3V 6 7 OUTx -0.3V 2.5V 10.0µA 50.0µA 3.1.1.2 Output Characteristics Ref.Nr. Pin Parameter Symbol Condition LOW Level Output Voltage VSOL 2 HIGH Level Output Voltage 3 Tristate-Leakage Current 1 4 SO OUTx Short Circuit Output Current min typ max Unit ISO = 1.6mA - - 0.4 V VSOH ISO = -1.0mA VDD -1,3V - VDD V ISOtri 0 < VSO < VDD -5.0 - 5.0 µA ISC VOUTX = 3V 0.35 0.6 0.9 A 36.0 - 50.0 V TSCL=20 ms Output Voltage Limit VOUTx OUT=HIGH 6 Output Resistance ROUT Out = LOW, 0<IOUT<200 mA - 1.5 3.0 W 7 Residual Output Current IOUTLx Out=HIGH 0 1.0 10.0 µA 5 Page 8 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 Date : 23.09.2003 SPECIFICATION 3.1.2 Safe Operating Area of OUTx Only one driver active (T=25°C): 1.0 All drivers active (T=25°C): SOA Curve 1 1.0 IDS i,0 Drivercurrent [A] Drivercurrent [A] IDS i,0 IDS i,1 IDS i,2 SOA Curve 1 0.1 IDS i,3 0.01 IDS i,1 IDS i,2 0.1 IDS i,3 0.01 0.01 0.1 1 0.1 10 100 VDS 0.01 100 i Voltagedrop over Driver [V] 0.1 1 0.1 10 100 VDS 100 i Voltagedrop over Driver [V] DC 1s single pulse 10ms single pulse 100us single pulse DC 1s single pulse 10ms single pulse 100us single pulse 3.1.3 AC Characteristics Ref.Nr. Pin Parameter SCLK 1 Input capacitance SI RESET CE TEST Symbol Condition typ 3) 2 SO 3 RESET RESET Pulse Width tRESon 4 OUTx Rate of Change of Output Voltage dVOUT/dt RL = 1kW Output Capacitance COUT 5 min Output marginal delay 3) RESET -> L 3) Out=HIGH, max 5 Unit pF 0.5 ns/pF 0.31 0.62 0.93 ms - 10.0 - V/µs - 40.0 60.0 pF - 30.0 45.0 pF 18.5 37.0 55.5 ms - 10.0 20.0 µs 2 MHz VOUT= 5V 3) Out=HIGH, 6 VOUT=15V 3) 7 Duration of Output Short T SCL Circuit Limit IOUT>ISCL 1) 8 Propagation Delay Time tN see Fig.4 CE --> OUTx RL = 1kW 9 SCLK Clock frequency Page 9 of 20 fSCLK 3) 3) E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 Date : 23.09.2003 SPECIFICATION 3.1.3.1 Interface Timing Symbol TLSO min 3) 20 Parameter Time between falling edge (10%) or rising edge (90%) of the CE signal and active (90%) or high impedance state of the SO output. Load capacitance at SO < 20pF. Time between falling edge (10%) of the CE signal and the first rising edge (10%) of the SCLK clock. Time between rising edge (10%) of the SCLK clock and the new data at SO output (10% or 90%). Load capacitance at SO <20pF. Time between stable data at SI (90% or 10%) and falling edge at SCLK (90%) to clock the data in: Data setup time. Time between falling edge at SCLK (90%) and changing of the data at SI (10% or 90%): Data hold time Time between two load cycles: CE at high level (90%). Time between falling edge of SCLK (90%) and rising edge of CE (90%) signal. TLCF TCSO TDS TDH TLL TLCR max 3) Unit 100 ns 150 ns 10 60 ns 40 ns 20 ns 150 20 ns ns CE TLL SI D7 TLCF D6 TDS D5 D4 D3 D2 D1 D0 TLCR T DH SCLK TLSO SO zz D7o TLSO TCSO D6o D5o D4o D3o D2o D1o D0o zz Notes: 1) When the output current exceeds the value of ISCL an internal timer is initiated and the current limit is activated. If the current limit is still active after the time TSCL the individual output is disabled by resetting the input latch. 2) As long as the thermal cut-off threshold THS is exceeded, all output drivers are in a high impedance condition. The contents of the latch are unaffected. 3) Not tested in production. 4) Test Mode 1 5) Test Mode 2 Page 10 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 Date : 23.09.2003 SPECIFICATION 4 Functional Description 4.1 Block Diagram Thermal Protection Oscillator RESET CE Control logic PowerOn-Reset SCLK SI Driver (Current Limited) OUT0 Overload timer Channel 0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 SO Figure 4.1-1 Page 11 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 SPECIFICATION Date : 23.09.2003 4.2 Detailed Functional Description This IC was specially developed for Automobile applications. Application areas include driving relays, Lamps, bus systems etc. with medium power consumption. The 910.01 comprises a serial data bus and 8 identical power drivers. All outputs are short circuit protected, and a thermal cut-off protects the devices from thermal overstress. By means of the RESET signal (RESET=Low) the IC can be switched into a low current consumption mode (Sleep Mode). In this mode all current consumption is disabled. There are two possible data transfer protocols: a) Parallel data input (see Figure 4.2-1 and Figure 4.5-1) SI and SO are tied together and the device is activated by means of the chip enable (CE) line. On the falling edge of the CE signal the data is loaded into the shift register and SO goes to the low impedance state. With each rising edge of SCLK the data beginning with Bit 7 (D7) is clocked out at SO and with each falling edge new data is clocked from SI. On the rising edge of CE the data from the shift register is clocked through to the outputs. SO goes to the high impedance state (Tri-State as long as CE remains inactive HIGH). A LOW level on the input produces a LOW level on the open drain driver which switches to the low impedance state. OUT[7:0] OUT[7:0] E91001 E91001 SI CE RESET SCLK SI CE RESET SCLK SO OUT[7:0] E91001 SO SI CE RESET SCLK SO RESET CE1 CE2 CE3 SCLK SI SO Figure 4.2-1 b) Serial data input (see Figure 4.2-2 and Figure 4.4-1) The complete Daisy Chain of drivers are enabled in parallel by CE and clocked out by SCLK. On the falling edge of CE the status of each output is clocked into the shift register. On each rising edge of SCLK data is clocked out of SO, and with each falling edge of SCLK new data is clocked into SI. After 8 x n clock cycles new data has been read in and existing data clocked out. On the rising edge of CE new data is clocked through to the outputs. SO goes to the high impedance state (Tri-state as long as CE remains inactive HIGH). A LOW level on the input produces a LOW level on the open drain driver which switches to the low impedance state. Page 12 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 Date : 23.09.2003 SPECIFICATION OUT[7:0] E91001 SI CE RESET SCLK SO OUT[7:0] E91001 SI CE RESET SCLK SO OUT[7:0] E91001 SI CE SO RESET SCLK RESET CE SCLK SI SO Figure 4.2-2 4.3 Protection Functions In addition to the Power on reset function the IC incorporates three other protection functions; over temperature protection, short-circuit protection and open output recognition. No special failure status bit is provided for indicating failures since this information is not available on the 8 bit interface. Power-On-Reset: After the application of the supply voltage all data latches and the timer are reset, and the outputs are disabled (inactive HIGH). The internal Power On Reset is OR'd with the external RESET input. In the RESET Mode the serial data output SO is inactive (LOW), as long as CE is active (LOW). Whereas SO goes into the high impedance Tri-State, if CE is inactive (HIGH). The external RESET is only invoked, if the pulse width exceeds the time tRESon.(see Figure 4.5-2) Short Circuit Protection: If the voltage drop across the output driver exceeds the short circuit threshold of 1V (RDSON ca. 1,5W), the current limit is activated and after approximately 40ms, the output is disabled. After disabling the output, the short circuit memory is cleared and it is possible to re-activate the outputs by writing LOW bits into the shift register via the serial data input SI. In the event that a short circuit is still present the current limit is again activated and the output is again disabled after 40 ms. After output disable due to the presence of a short circuit (OUTx = inactive HIGH) the serial output SO goes to a HIGH level, since SO always indicates the actual output status. Interrogating the SO status is the only way of establishing if a short circuit exists. When the output OUTx is selected by a LOW level on the SI serial data input (output OUTx enabled) and a HIGH level appears on the data output SO the presence of a short circuit on the enabled output is clear. At switch on the output is operated as a constant current source by the internal limiting. When used with lamps they may be safely switched on because the internal limit operates for approximately 40 ms and disables the outputs. (see Figure 4.5-4) Open Output Recognition: In the event of an open output the output voltage of OUTx is set to definite LOW level by the pull down transistor (OUTx = LOW). A LOW level also appears at the data output SO: The actual method of establishing that an output is open is by interrogating the state of the data output SO. When an output OUTx is selected by means of a HIGH level on the SI pin (output OUTx disabled) a LOW level appears on the SO pin. Thus the open condition of the output is indicated. This function is the inverse of the short circuit condition above. Page 13 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 SPECIFICATION Date : 23.09.2003 Over temperature Protection: If the chip temperature exceeds the protection threshold of typically 165°C all output drivers are disabled and the data stored in the latches are retained. When the temperature drops below the protection threshold of typically 140°C the previously stored condition is restored providing no new data have been loaded into the shift register by SI during this protection condition otherwise the stored data is overridden. This is also the case, when a RESET signal is received or when a falling edge on CE causes the shift register to be read. (see Figure 4.5-3) The actual method of establishing that the device is in thermal protection shut down is by interrogating the state of the data output SO. When an output OUTx is selected by means of a LOW level on the SI pin (output OUTx enabled) a HIGH level appears on the SO pin for all outputs. Thus the thermal shutdown condition is indicated. It is highly unlikely that a short circuit condition can occur in all outputs simultaneously. Test Modes: If a voltage of greater than 3V and lower than 8V is applied to the TEST input, the device will switch into the Test Mode 1. In this mode the counter chain following the internal RC oscillator is shortened. The oscillator signal (divided by 2) appears on the output SO. Test mode 2: If the voltage at the TEST input is greater than 16V additionally the over temperature protection circuit is set between 25°C and 85°C. Page 14 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 Date : 23.09.2003 SPECIFICATION 4.4 Application Circuit Vbat = 12V VBAT OUT[7] D15 IC2 CE RESET TEST SO GND SI E910.01 SCLK VDD TEST IC1 CE RESET VDD E910.01 GND R D8 SO VDD OUT[0:7] SI OUT[0] VDD R D7 OUT[7] D0 SCLK VDD = 5V R = 1k R OUT[0] R RESET CE MICRO- SCLK CONTROLLER SI SO CE SCLK SI SO XX D15 D14 D 13 D12 D 11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ZZ oD oD oD oD oD oD oD oD oD oD oD oD oD oD oD oD XX ZZ XX D15’ D14’ D13’ D12’ D11’ D10’ O UT15 O UT14 O UT13 O UT12 O UT11 O UT10 Etc. Figure 4.4-1 Page 15 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 Date : 23.09.2003 SPECIFICATION 4.5 Timing Diagram 4.5.1 Operating Mode CE SCLK SI xx D7 D6 D5 D4 D3 SO zz oD7 oD6 oD5 oD4 oD3 D2 D1 oD2 oD1 D0 xx oD0 zz D7n D7' D5n D6n D6' D5' OUT7 Old Data OUT7 New Data OUT7 OUT6 Old Data OUT6 New Data OUT6 OUT5 Old Data OUT5 New Data OUT5 OUT4 Old Data OUT4 New Data OUT4 OUT3 Old Data OUT3 New Data OUT3 OUT2 Old Data OUT2 New Data OUT2 OUT1 Old Data OUT1 New Data OUT1 OUT0 Old Data OUT0 New Data OUT0 D4n D3n D4' D3' D2n D2' D1n D1' D0n xx D0' zz RES Figure 4.5-1 4.5.2 RESET Mode (Sleep Mode) CE SCLK SI xx D7 D6 D5 D4 D3 SO zz oD7 oD6 oD5 oD4 oD3 D2 oD2 D1 oD1 D0 xx oD0 zz D7n D7' D6n D6' OUT7 Old Data OUT7 New Data OUT7 OUT6 Old Data OUT6 New Data OUT6 OUT5 Old Data OUT5 New Data OUT5 OUT4 Old Data OUT4 New Data OUT4 OUT3 Old Data OUT3 New Data OUT3 OUT2 Old Data OUT2 New Data OUT2 OUT1 Old Data OUT1 New Data OUT1 OUT0 Old Data OUT0 New Data OUT0 D5n D5' D2n D1n D0n xx zz RES t RESon Figure 4.5-2 Page 16 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 Date : 23.09.2003 SPECIFICATION 4.5.3 Thermal Cut-off CE SCLK SI D6 D5 D4 D3 D2 D1 D0 xx Da Db Dc Dd De Df Dg Dh Di Dj SO oD oD oD oD oD oD oD zz D7' D6' D5' D4' D3' D2' D1' D0' Da' Db' OUT7 Old Data OUT7 New Data OUT7 Restored Data OUT7 OUT6 Old Data OUT6 New Data OUT6 Restored Data OUT6 OUT5 Old Data OUT5 New Data OUT5 Restored Data OUT5 OUT4 Old Data OUT4 New Data OUT4 Restored Data OUT4 OUT3 Old Data OUT3 New Data OUT3 Restored Data OUT3 OUT2 Old Data OUT2 New Data OUT2 Restored Data OUT2 OUT1 Old Data OUT1 New Data OUT1 Restored Data OUT1 OUT0 Old Data OUT0 New Data OUT0 Restored Data OUT0 RES therm. Cut-Off Figure 4.5-3 4.5.4 Short Circuit Condition CE SCLK SI xx D7 D6 D5 D4 D3 SO zz oD7 oD6 oD5 oD4 oD3 D2 oD2 D1 D0 oD1 oD0 xx zz D7a D7' D6a D6' D5a D3d D2d D1d D0d xx zz D5' OUT7 Old Data OUT7 New Data OUT7 OUT7c OUT7d OUT6 Old Data OUT6 New Data OUT6 OUT6c OUT6d OUT5 Old Data OUT5 New Data OUT5 OUT5c OUT5d OUT4 Old Data OUT4 New Data OUT4 OUT4c OUT4d OUT3 Old Data OUT3 New Data OUT3 OUT3c OUT3d OUT2 Old Data OUT2 New Data OUT2 OUT2c OUT2d OUT1 Old Data OUT1 New Data OUT1 OUT1c OUT1d OUT0 Old Data OUT0 New Data OUT0 RES OUT0 switched off OUT0d TSCL Short Circuit at OUT0 Figure 4.5-4 Page 17 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 SPECIFICATION Date : 23.09.2003 4.6 Noise Immunity The 910.01 device meets the following requirements of DIN 40 839 part 1, when used in an application according to this specification : Parameter Test pulse 1 Condition t1 = 5s / US = -100V 100 pulses Test pulse 2 t1 = 0,5s / US = 100V 1000 pulses Test pulse 3a/b DIN 40 839 Part 3 US = -150V / US = 100V Us =-6V Ua =-5V t8 = 5s 1000 Bursts Ri = 2_ tD = 250ms tr = 0,1ms UP+US= 40V 10 pulses at 1 minute intervals Test pulse 4 Test pulse 5 10 pulses 4.7 ESD Protection Circuit VDD VDD VDD TEST RESET SCLK CE SI SO GND GND GND Lowside-Driver: OUT7,..,OUT0 GND 4.7.1 Test Method The ESD Protection circuitry is measured using MIL-STD-883C Method 3015 (Human Body Model) with the following conditions : VIN = 2000 Volt REXT = 1500 Ohm CEXT = 100 pF Page 18 of 20 E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 Date : 23.09.2003 SPECIFICATION 5 Life Test Circuit GND GND R1 47K TEST 10K OUT3 OUT4 10K 10K OUT2 OUT5 10K 10K OUT1 OUT6 10K VS 10K OUT0 OUT7 10K RESET 47K CE 47K CE SCLK 47K SCLK SI 47K SI GND N.C. E91001 VDD SO VDD 10K GND VDD = 5V VS = 12V CE 12.5 kHz SCLK 100 kHz SI 6.25 kHz Phasenlage wichtig ! Life Test conditions Temperature Condition Page 19 of 20 : : 125 °C Dynamic E910.01B 8-Way Output Driver QM-Nr.: 03SP0111E.01 Date : 23.09.2003 SPECIFICATION 6 Record of Revisions CHAPTER 1.5 2.2 2.2 3.1.1.2 3.1.3 3.1.3 5-8 REASON FOR AND DESCRIPTION OF CHANGE REV 00 New format, B version 00 Safe operating area 00 Interface Timing 00 In/Output Capacitance 00 Introduction of Test mode 2 00 Correction of timing diagram for application 00 ..Parameters numbered 01 Update of related ELMOS documents 01 Recommended Operating Conditions: max limit changed from 85°C to 105°C plus remark for production test. 01 Recommended Operating Conditions: output current Iout £ 300mA 01 Ref. Nr. 6: condition updated (Iout < 200mA limit has been erased because of chap. 2.2) 01 Ref. Nr. 4; condition updated RL=1kW 01 Ref. Nr. 9 added: max. fSCLK=2MHz 01 Update/Erase of chapters 5-7 Page 20 of 20 E910.01B 8-Way Output Driver DATE APPROVAL 20.04.99 20.04.99 20.04.99 20.04.99 20.04.99 21.04.99 07.07.99 23.09.03 11.09.03 ELMOS LK LK LK LK LK JoF JoF JoF JoF 11.09.03 JoF 11.09.03 JoF 11.09.03 11.09.03 23.09.03 JoF JoF JoF/FPe QM-Nr.: 03SP0111E.01 CUST