1.125Gb: x18, x36 TwinDie RLDRAM 3

1.125Gb: x18, x36 TwinDie RLDRAM 3
Features
TwinDie™ RLDRAM 3
MT44K64M18 – 2 Meg x 18 x 16 Banks x 2 Ranks
MT44K32M36 – 2 Meg x 36 x 16 Banks
Features
Options
Marking
• 168-ball FBGA package
– 1.07ns and tRC (MIN) = 8ns
(RL3-1866)
– 1.07ns and tRC (MIN) = 10ns
(RL3-1866)
– 1.25ns and tRC (MIN) = 10ns
(RL3-1600)
– 1.25ns and tRC (MIN) = 12ns
(RL3-1600)
• Configuration
– 64 Meg x 18
– 32 Meg x 36
• Operating temperature
– Commercial (TC = 0° to +95°C)
– Industrial (TC = –40°C to +95°C)
• Package
– 168-ball FBGA (Pb-free)
• Uses 576Mb Micron RLDRAM 3 die
• Organization
– 32 Meg x 18 x 2 ranks
– 32 Meg x 36 x 1 rank
– 16 banks per die
– Common I/O (CIO)
• 1.2V center-terminated push/pull I/O
• 2.5V V EXT, 1.35V V DD, 1.2V V DDQ I/O
Description
The 1Gb (TwinDie™) RLDRAM 3 uses Micron’s 576Mb
RLDRAM 3 die. Refer to Micron’s 576Mb RLDRAM 3
data sheet for the specifications not included in this
document. Specifications for base part number
MT44K32M18 correlate to both TwinDie manufacturing part numbers MT44K64M18 and MT44K32M36.
-107E
-107
-125E
-125
64M18
32M36
None
IT
RCT
Figure 1: 1Gb RLDRAM 3 Part Numbers
Example Part Number: MT44K32M36RCT-125E:A
MT44K
:
Speed Temp
Configuration Package
Rev
Revision
:A
Rev. A
Configuration
64 Meg x 18
64M18
32 Meg x 36
32M36
Temperature
Commercial
Industrial
Package
168-ball FBGA (Pb-free)
None
IT
Speed Grade
RCT
-107E tCK = 1.07ns (8ns t RC)
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
1
-107
tCK
= 1.07ns (10ns t RC)
-125E
tCK
= 1.25ns (10ns tRC)
-125
tCK
= 1.25ns (12ns tRC)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1.125Gb: x18, x36 TwinDie RLDRAM 3
Features
BGA Part Marking Decoder
Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s BGA Part Marking Decoder is available on Micron’s Web site at www.micron.com.
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
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© 2013 Micron Technology, Inc. All rights reserved.
1.125Gb: x18, x36 TwinDie RLDRAM 3
Features
Contents
General Description ......................................................................................................................................... 6
Functional Block Diagrams ............................................................................................................................... 7
Ball Assignments and Descriptions ................................................................................................................... 9
Package Dimensions ....................................................................................................................................... 12
Electrical Characteristics - IDD Specifications ................................................................................................... 13
Electrical Specifications – Absolute Ratings and I/O Capacitance ..................................................................... 15
Absolute Maximum Ratings ........................................................................................................................ 15
Input/Output Capacitance .......................................................................................................................... 15
ODT Characteristics ....................................................................................................................................... 16
ODT Resistors ............................................................................................................................................ 16
ODT Sensitivity .......................................................................................................................................... 18
Output Driver Impedance ............................................................................................................................... 18
Output Driver Sensitivity ............................................................................................................................ 20
Output Characteristics and Operating Conditions ............................................................................................ 21
Timing Adjustments ....................................................................................................................................... 22
Thermal Impedance Characteristics ................................................................................................................ 23
Commands .................................................................................................................................................... 24
Mode Register 0 (MR0) .................................................................................................................................... 26
tRC ............................................................................................................................................................. 26
Data Latency .............................................................................................................................................. 26
DLL Enable/Disable ................................................................................................................................... 26
Address Multiplexing .................................................................................................................................. 27
DDP Selection. ............................................................................................................................................ 27
Mode Register 1 (MR1) .................................................................................................................................... 28
Output Drive Impedance ............................................................................................................................ 28
On-Die Termination (ODT) ......................................................................................................................... 28
ZQ Calibration ............................................................................................................................................ 29
AUTO REFRESH Protocol ............................................................................................................................ 30
Mode Register 2 (MR2) .................................................................................................................................... 31
Dual Die Package - On Die Termination ....................................................................................................... 31
READ Training Register ............................................................................................................................... 31
INITIALIZATION Operation ............................................................................................................................ 34
READ Operation ............................................................................................................................................. 36
Multiplexed Address Mode .............................................................................................................................. 37
Mirror Function ............................................................................................................................................. 40
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1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Features
List of Figures
Figure 1: 1Gb RLDRAM 3 Part Numbers ........................................................................................................... 1
Figure 2: 64 Meg x 18 Functional Block Diagram ............................................................................................... 7
Figure 3: 32 Meg x 36 Functional Block Diagram ............................................................................................... 8
Figure 4: 168-Ball FBGA ................................................................................................................................. 12
Figure 5: Output Driver ................................................................................................................................. 19
Figure 6: MR0 Definition for Non-Multiplexed Address Mode .......................................................................... 26
Figure 7: MR1 Definition for Non-Multiplexed Address Mode .......................................................................... 28
Figure 8: ZQ Calibration Timing (ZQCL and ZQCS) ......................................................................................... 30
Figure 9: MR2 Definition for Non-Multiplexed Address Mode .......................................................................... 31
Figure 10: READ Training Function - x18 Die Interleave Training ..................................................................... 33
Figure 11: Power-Up/Initialization Sequence ................................................................................................. 35
Figure 12: x18 Consecutive Die Interleave READ Bursts (BL = 2) ...................................................................... 36
Figure 13: x18 Non-Consecutive Die Interleave READ Bursts (BL = 2) ............................................................... 36
Figure 14: MR0 Definition for Multiplexed Address Mode ................................................................................ 37
Figure 15: MR1 Definition for Multiplexed Address Mode ................................................................................ 38
Figure 16: MR2 Definition for Multiplexed Address Mode ................................................................................ 39
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1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Features
List of Tables
Table 1: 64 Meg x 18 Ball Assignments – 168-Ball FBGA (Top View) .................................................................... 9
Table 2: 32 Meg x 36 Ball Assignments – 168-Ball FBGA (Top View) .................................................................... 9
Table 3: Ball Descriptions .............................................................................................................................. 10
Table 4: x18 IDD Operating Conditions and Maximum Limits .......................................................................... 13
Table 5: x36 IDD Operating Conditions and Maximum Limits .......................................................................... 14
Table 6: Absolute Maximum Ratings .............................................................................................................. 15
Table 7: Input/Output Capacitance ................................................................................................................ 15
Table 8: RTT Effective Impedances .................................................................................................................. 16
Table 9: RTT Effective Impedance Ranges ........................................................................................................ 16
Table 10: ODT Sensitivity Definition .............................................................................................................. 18
Table 11: ODT Temperature and Voltage Sensitivity ........................................................................................ 18
Table 12: Driver Pull-Up and Pull-Down Impedance Calculations ................................................................... 19
Table 13: Output Driver Sensitivity Definition ................................................................................................. 20
Table 14: Output Driver Voltage and Temperature Sensitivity .......................................................................... 20
Table 15: Single-Ended Output Driver Characteristics ..................................................................................... 21
Table 16: Differential Output Driver Characteristics ........................................................................................ 21
Table 17: DDP Timing adjustments ................................................................................................................ 22
Table 18: Thermal Impedance ........................................................................................................................ 23
Table 19: Command Descriptions .................................................................................................................. 24
Table 20: x18 Command Table ....................................................................................................................... 25
Table 21: x36 Command Table ....................................................................................................................... 25
Table 22: Address Mapping in Multiplexed Address Mode ............................................................................... 39
Table 23: 64 Meg x 18 Ball Assignments with MF Ball Tied HIGH ...................................................................... 40
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1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
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1.125Gb: x18, x36 TwinDie RLDRAM 3
General Description
General Description
The 1Gb Micron® TwinDie RLDRAM® 3 is a high-speed memory device designed for
high-bandwidth data storage—telecommunications, networking, cache applications,
and so forth. Both the x18 and x36 configurations are composed of two 16-bank 576Mb
RLDRAM 3 x18 devices. The TwinDie x18 RLDRAM 3 is a 2-rank device that shares address, control, and data signals between both die in the package. Separate CS# pins enable each of the ranks within the package. The TwinDie x36 RLDRAM 3 is a single-rank
device that shares command, address, and control signals, but not the data bus.
The DDR I/O interface transfers two data bits per clock cycle at the I/O balls. Output
data is referenced to the READ strobes.
Commands, addresses, and control signals are also registered at every positive edge of
the differential input clock, while input data is registered at both positive and negative
edges of the input data strobes.
Read and write accesses to the RL3 device are burst-oriented. The burst length (BL) is
programmable to 2, 4, or 8 by a setting in the mode register.
The device is supplied with 1.35V for the core and 1.2V for the output drivers. The 2.5V
supply is used for an internal supply.
Bank-scheduled refresh is supported, with the row address generated internally.
The 168-ball FBGA package is used to enable ultra-high-speed data transfer rates.
This data sheet provides a general description, package dimensions, and ballout as well
as specifications that differ from the monolithic RLDRAM3 device. Refer to the Micron
576Mb RLDRAM 3 data sheet for complete information on power-up and initialization,
command descriptions, and die operation.
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1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Functional Block Diagrams
Functional Block Diagrams
Figure 2: 64 Meg x 18 Functional Block Diagram
Die 1 (Rank 1)
(2 Meg x 18 x 16 banks)
Die 0 (Rank 0)
(2 Meg x 18 x 16 banks)
CS1#
CS0#
TDI
REF#
A[19:0]
BA[3:0]
WE#
MF
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QK[1:0], DQ[0:17]
QK[1:0]#
QVLD0
TCK,TMS
CK/CK#
Note:
TDO
RESET#
ZQ
DM[1:0]
DK[1:0], DK[1:0]#
1. Example for BL = 2; address bus width will be reduced with an increase in burst length.
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Functional Block Diagrams
Figure 3: 32 Meg x 36 Functional Block Diagram
Die 1
(2 Meg x 18 x 16 banks)
Die 0
(2 Meg x 18 x 16 banks)
TDI
CS#
DQ[35:18] QK[3:2],
QK[3:2]#
QVLD1
A[19:0]
BA[3:0]
REF#
WE#
MF
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QK[1:0], DQ[17:0]
QK[1:0]#
QVLD0
TCK,TMS
CK/CK#
Note:
TDO
RESET#
ZQ
DM[1:0]
DK[1:0],DK[1:0]#
1. Example for BL = 2; address bus width will be reduced with an increase in burst length.
8
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Table 1: 64 Meg x 18 Ball Assignments – 168-Ball FBGA (Top View)
1
A
2
3
VSS
4
VDD
NC
5
6
7
8
9
10
11
12
13
VDDQ
NC1
VREF
DQ7
VDDQ
DQ8
VDD
VSS
RESET#
B
VEXT
VSS
NC
VSSQ
NC
VDDQ
DM0
VDDQ
DQ5
VSSQ
DQ6
VSS
VEXT
C
VDD
NC
VDDQ
NC
VSSQ
NC
DK0#
DQ2
VSSQ
DQ3
VDDQ
DQ4
VDD
D
A11
VSSQ
NC
VDDQ
NC
VSSQ
DK0
VSSQ
QK0
VDDQ
DQ0
VSSQ
A13
VDDQ
NC
MF2
QK0#
VDDQ
DQ1
VSSQ
CS0#
VSS
E
VSS
A0
VSSQ
NC
F
A7
CS1#
VDD
A2
A1
WE#
ZQ
REF#
A3
A4
VDD
A5
A9
G
VSS
A15
A6
VSS
BA1
VSS
CK#
VSS
BA0
VSS
A8
A18
VSS
H
A19
VDD
A14
A16
VDD
BA3
CK
BA2
VDD
A17
A12
VDD
A10
J
VDDQ
NC
VSSQ
NC
VDDQ
NC
VSS
QK1#
VDDQ
DQ9
VSSQ
QVLD
VDDQ
K
NC
VSSQ
NC
VDDQ
NC
VSSQ
DK1
VSSQ
QK1
VDDQ
DQ10
VSSQ
DQ11
L
VDD
NC
VDDQ
NC
VSSQ
NC
DK1#
DQ12
VSSQ
DQ13
VDDQ
DQ14
VDD
M
VEXT
VSS
NC
VSSQ
NC
VDDQ
DM1
VDDQ
DQ15
VSSQ
DQ16
VSS
VEXT
N
VSS
TCK
VDD
TDO
VDDQ
NC
VREF
DQ17
VDDQ
TDI
VDD
TMS
VSS
Notes:
1. NC balls for the x18 configuration are not connected to the DRAM die but do have parasitic capacitance associated with the package substrate. Balls may be connected to VSSQ.
2. MF is assumed to be tied LOW for this ball assignment.
Table 2: 32 Meg x 36 Ball Assignments – 168-Ball FBGA (Top View)
1
A
2
3
4
5
6
7
8
9
10
11
12
13
VSS
VDD
DQ26
VDDQ
DQ25
VREF
DQ7
VDDQ
DQ8
VDD
VSS
RESET#
B
VEXT
VSS
DQ24
VSSQ
DQ23
VDDQ
DM0
VDDQ
DQ5
VSSQ
DQ6
VSS
VEXT
C
VDD
DQ22
VDDQ
DQ21
VSSQ
DQ20
DK0#
DQ2
VSSQ
DQ3
VDDQ
DQ4
VDD
D
A11
VSSQ
DQ18
VDDQ
QK2
VSSQ
DK0
VSSQ
QK0
VDDQ
DQ0
VSSQ
A13
E
VSS
A0
VSSQ
DQ19
VDDQ
QK2#
MF2
QK0#
VDDQ
DQ1
VSSQ
CS#
VSS
1
F
A7
NF(CS1)
VDD
A2
A1
WE#
ZQ
REF#
A3
A4
VDD
A5
A9
G
VSS
A15
A6
VSS
BA1
VSS
CK#
VSS
BA0
VSS
A8
A18
VSS
H
A19
VDD
A14
A16
VDD
BA3
CK
BA2
VDD
A17
A12
VDD
A10
J
VDDQ
QVLD1
VSSQ
DQ27
VDDQ
QK3#
VSS
QK1#
VDDQ
DQ9
VSSQ
QVLD0
VDDQ
K
DQ29
VSSQ
DQ28
VDDQ
QK3
VSSQ
DK1
VSSQ
QK1
VDDQ
DQ10
VSSQ
DQ11
L
VDD
DQ32
VDDQ
DQ31
VSSQ
DQ30
DK1#
DQ12
VSSQ
DQ13
VDDQ
DQ14
VDD
M
VEXT
VSS
DQ34
VSSQ
DQ33
VDDQ
DM1
VDDQ
DQ15
VSSQ
DQ16
VSS
VEXT
N
VSS
TCK
VDD
TDO
VDDQ
DQ35
VREF
DQ17
VDDQ
TDI
VDD
TMS
VSS
Notes:
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1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
1. The location of the additional chip select (CS1) is required on the 1Gb RLDRAM 3 x18
DDP configuration. It is internally connected so it can mirror with the address signal, A5,
when MF is asserted HIGH. It also has the parasitic characteristics of an address pin.
2. MF is assumed to be tied LOW for this ball assignment.
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Ball Assignments and Descriptions
Table 3: Ball Descriptions
Symbol
Type
Description
A[19:0]
Input
Address inputs: A[19:0] define the row and column addresses for READ and WRITE operations.
During a MODE REGISTER SET, the address inputs define the register settings, along with
BA[3:0]. They are sampled at the rising edge of CK.
BA[3:0]
Input
Bank address inputs: Select the internal bank to which a command is being applied.
CK/CK#
Input
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on
the rising edge of CK.
CS[0:1]#
Input
Chip select: CS[0:1]# enables the command decoder when LOW and disables it when HIGH. The
TwinDie x18 device uses CS0# and CS1# to enable and disable the command decoder of each
rank. The TwinDie x36 device has only a single CS# pin whereby the command decoder of both
die are enabled and disabled simultaneously. When the command decoder is disabled, new commands are ignored, but internal operations continue.
DQ[35:0]
I/O
Data input: The DQ signals form the 36-bit data bus. During READ commands, the data is referenced to both edges of QK. During WRITE commands, the data is sampled at both edges of DK.
DKx, DKx#
Input
Input data clock: DKx and DKx# are differential input data clocks. All input data is referenced
to both edges of DKx. For the x36 device, DQ[8:0] and DQ[26:18] are referenced to DK0 and
DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1 and DK1#. For the x18 device, DQ[8:0]
are referenced to DK0 and DK0#, and DQ[17:9] are referenced to DK1 and DK1#. DKx and DKx#
are free-running signals and must always be supplied to the device.
DM[1:0]
Input
Input data mask: DM is the input mask signal for WRITE data. Input data is masked when DM
is sampled HIGH. DM0 is used to mask the lower byte for the x18 device and DQ[8:0] and
DQ[26:18] for the x36 device. DM1 is used to mask the upper byte for the x18 device and
DQ[17:9] and DQ[35:27] for the x36 device. Tie DM[1:0] to VSS if not used.
TCK
Input
IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used.
TMS, TDI
Input
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
WE#, REF#
Input
Command inputs: Sampled at the positive edge of CK, WE# and REF# (together with CS#) define the command to be executed.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. RESET# assertion and deassertion
are asynchronous. RESET# is a CMOS input defined with DC HIGH ≥ 0.8 x VDDQ and DC LOW ≤ 0.2
x VDDQ.
ZQ
Input
External impedance: This signal is used to tune the device’s output impedance and ODT. RZQ
needs to be 240Ω, where RZQ is a resistor from this signal to ground.
QKx, QKx#
Output
Output data clocks: QK and QK# are opposite-polarity output data clocks. They are free-running signals and during READ commands are edge-aligned with the DQs. For the x36 device,
QK0, QK0# align with DQ[8:0]; QK1, QK1# align with DQ[17:9]; QK2, QK2# align with DQ[26:18];
and QK3, QK3# align with DQ[35:27]. For the x18 device, QK0, QK0# align with DQ[8:0]; QK1,
QK1# align with DQ[17:9].
QVLDx
Output
Data valid: The QVLD ball indicates that valid output data will be available on the subsequent
rising clock edge. There is a single QVLD ball for the x18 device and two, QVLD0 and QVLD1, for
the x36 device. QVLD0 aligns with DQ[17:0]; QVLD1 aligns with DQ[35:18].
MF
Input
Mirror function: The mirror function ball is a DC input used to create mirrored ballouts for simple dual-loaded clamshell mounting. If the ball is tied to VSS, the address and command balls are
in their true layout. If the ball is tied to VDDQ, they are in the complement location. MF must be
tied HIGH or LOW and cannot be left floating. MF is a CMOS input defined with DC HIGH ≥ 0.8 x
VDD and DC LOW ≤ 0.2 x VDDQ.
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Ball Assignments and Descriptions
Table 3: Ball Descriptions (Continued)
Symbol
Type
TDO
Output
IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function
is not used.
VDD
Supply
Power supply: 1.35V nominal.
VDDQ
Supply
DQ power supply: 1.2V nominal. Isolated on the device for improved noise immunity.
VEXT
Supply
Power supply: 2.5V nominal.
VREF
Supply
Input reference voltage: VDDQ/2 nominal. Provides a reference voltage for the input buffers.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
NC
-
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1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
Description
No connect: These balls are not connected to the DRAM.
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Package Dimensions
Package Dimensions
Figure 4: 168-Ball FBGA
Seating plane
A
168X Ø0.55
Dimensions
apply to solder
balls post-reflow
on Ø0.4 NSMD
ball pads.
0.12 A
Ball A1 ID
(covered by SR)
13 12 11 10
9
8
7
6
5
4
3
2
Ball A1 ID
1
A
B
C
D
13.5 ±0.1
E
F
G
12 CTR
H
J
K
L
M
1 TYP
N
1 TYP
1.35 ±0.1
12 CTR
0.3 MIN
13.5 ±0.1
Note:
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
1. All dimensions are in millimeters.
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Electrical Characteristics - IDD Specifications
Electrical Characteristics - IDD Specifications
Table 4: x18 IDD Operating Conditions and Maximum Limits
Combined Symbol
Individual Die Status
-107E
-107
-125E
-125
Units
ICSB1 (VDD) x18
ICSB1 = ISB1 + ISB1
250
250
250
250
mA
60
60
60
60
ICSB2 = ISB2 + ISB2
1630
1630
1450
1450
60
60
60
60
ICDD1 = IDD1 + ISB2
1915
1860
1665
1640
65
65
65
65
ICDD2 = IDD2 + ISB2
1945
1890
1695
1670
65
65
65
65
ICDD3 = IDD3 + ISB2
2015
1945
1755
1725
65
65
65
65
ICREF1 = IREF1 + ISB2
2215
2215
1955
1955
105
105
100
100
ICREF2 = IREF2 + ISB2
1635
1635
1435
1435
60
60
60
60
ICMBREF4 = IMBREF4 + ISB2
2845
2625
2610
2370
145
145
135
135
ICDD2W = IDD2W + ISB2
2725
2725
2390
2390
105
105
100
100
ICDD4W = IDD4W + ISB2
2405
2405
2120
2120
85
85
80
80
ICDD8W = IDD8W + ISB2
2150
2150
1915
1915
70
70
70
70
ICDBWR = IDBWR + ISB2
2985
2985
2610
2610
105
105
100
100
ICQBWR = IQBWR + ISB2
3705
3705
3250
3250
145
145
130
130
ICDD2R = IDDR2 + ISB2
2860
2860
2510
2510
105
105
100
100
ICDD4R = IDDR4 + ISB2
2410
2410
2125
2125
85
85
80
80
ICDD8R = IDDR8 + ISB2
2130
2130
1900
1900
70
70
70
70
ICSB1 (VEXT) x18
ICSB2 (VDD) x18
ICSB2 (VEXT) x18
ICDD1 (VDD) x18
ICDD1 (VEXT) x18
ICDD2 (VDD) x18
ICDD2 (VEXT) x18
ICDD3 (VDD) x18
ICDD3 (VEXT) x18
ICREF1 (VDD) x18
ICREF1 (VEXT) x18
ICREF2 (VDD) x18
ICREF2 (VEXT) x18
ICMBREF4 (VDD) x18
ICMBREF4 (VEXT) x18
ICDD2W (VDD) x18
ICDD2W (VEXT) x18
ICDD4W (VDD) x18
ICDD4W (VEXT) x18
ICDD8W (VDD) x18
ICDD8W (VEXT) x18
ICDBWR (VDD) x18
ICDBWR (VEXT) x18
ICQBWR (VDD) x18
ICQBWR (VEXT) x18
ICDD2R (VDD) x18
ICDD2R (VEXT) x18
ICDD4R (VDD) x18
ICDD4R (VEXT) x18
ICDD8R (VDD) x18
ICDD8R (VEXT) x18
Note:
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1. ICDD values reflect the combined current of both individual die. IDDx and ISBx represent
individual die values.
13
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Electrical Characteristics - IDD Specifications
Table 5: x36 IDD Operating Conditions and Maximum Limits
Combined Symbol
Individual Die Status
ICSB1 (VDD) x36
ICSB1 = ISB1 + ISB1
-107E
-107
-125E
-125
Units
250
250
250
250
mA
60
60
60
60
ICSB2 = ISB2 + ISB2
1670
1670
1480
1480
60
60
60
60
ICDD1 = IDD1 + IDD1
2220
2110
1880
1830
70
70
70
70
ICDD2 = IDD2 + IDD2
2160
2060
1940
1890
70
70
70
70
ICDD3 = IDD3 + IDD3
NA
NA
NA
NA
NA
NA
NA
NA
ICREF1 = IREF1 + IREF1
2840
2840
2460
2460
150
150
140
140
ICREF2 = IREF2 + IREF2
1635
1635
1485
1485
60
60
60
60
ICMBREF4 = IMBREF4 + IMBREF4
4100
3660
3770
3290
230
230
210
210
ICDD2W = IDD2W + IDD2W
4140
4140
3330
3330
150
150
140
140
3330
3330
2790
2790
110
110
100
100
NA
NA
NA
NA
NA
NA
NA
NA
ICDBWR = IDBWR + IDBWR
4500
4500
3770
3770
150
150
140
140
ICQBWR = IQBWR + IQBWR
6000
6000
5050
5050
230
230
200
200
ICDD2R = IDD2R + IDD2R
4360
4360
3570
3570
150
150
140
140
ICDD4R = IDD4R + IDD4R
3370
3370
2800
2800
110
110
100
100
NA
NA
NA
NA
NA
NA
NA
NA
ICSB1 (VEXT) x36
ICSB2 (VDD) x36
ICSB2 (VEXT) x36
ICDD1 (VDD) x36
ICDD1 (VEXT) x36
ICDD2 (VDD) x36
ICDD2 (VEXT) x36
ICDD3 (VDD) x36
ICDD3 (VEXT) x36
ICREF1 (VDD) x36
ICREF1 (VEXT) x36
ICREF2 (VDD) x36
ICREF2 (VEXT) x36
ICMBREF4 (VDD) x36
ICMBREF4 (VEXT) x36
ICDD2W (VDD) x36
ICDD2W (VEXT) x36
ICDD4W (VDD) x36
ICDD4W = IDD4W + IDD4W
ICDD4W (VEXT) x36
ICDD8W (VDD) x36
ICDD8W = IDD8W + IDD8W
ICDD8W (VEXT) x36
ICDBWR (VDD) x36
ICDBWR (VEXT) x36
ICQBWR (VDD) x36
ICQBWR (VEXT) x36
ICDD2R (VDD) x36
ICDD2R (VEXT) x36
ICDD4R (VDD) x36
ICDD4R (VEXT) x36
ICDD8R (VDD) x36
ICDD8R = IDD8R + IDD8R
ICDD8R (VEXT) x36
Note:
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1. ICDD values reflect the combined current of both individual die. IDDx and ISBx represent
individual die values.
14
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Electrical Specifications – Absolute Ratings and I/O Capacitance
Electrical Specifications – Absolute Ratings and I/O Capacitance
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 6: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VDDQ
Voltage on VDDQ supply relative to VSS
–0.4
1.66
V
Voltage on any ball relative to VSS
–0.4
1.66
V
Voltage on VEXT supply relative to VSS
–0.4
2.8
V
VIN,VOUT
VEXT
Input/Output Capacitance
Table 7: Input/Output Capacitance
Notes 1 and 2 apply to entire table
x18 DDP - 1600
x36 DDP - 1600
Symbol
Min
Max
Min
CK/CK#
CCK
4.25
5.5
4.25
5.5
pF
ΔC: CK to CK#
CDCK
0
0.15
0
0.15
pF
Single-ended I/O: DQ
CIO
5.25
7.0
3.0
4.5
pF
Single-ended I/O: DM
CIO
5.25
7.0
5.25
7.0
pF
Input strobe: DK/DK#
CIO
5.25
7.0
5.25
7.0
pF
Output strobe: QK/QK#, QVLD
CIO
5.25
7.0
3.0
4.5
pF
ΔC: DK to DK#
CDDK
0
0.15
0
0.15
pF
ΔC: QK to QK#
CDQK
0
0.15
0
0.15
pF
ΔC: DQ to QK
CDIO
–0.5
0.3
–0.5
0.3
pF
3
ΔC: DQ to DK
CDIO
–0.5
0.3
–3.6
–3.05
pF
3
CI
4.25
6.0
4.25
6.0
pF
4
CDI_CMD_ADDR
–0.5
0.8
–0.5
0.8
pF
5
CJTAG
2.9
4.9
2.9
4.9
pF
6
CI
–
5.5
–
5.5
pF
Capacitance Parameters
Inputs (CMD, ADDR)
ΔC: CMD_ADDR to CK
JTAG balls
RESET#, MF balls
Notes:
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
Max
Units
Notes
1. +1.28V ≤ VDD ≤ +1.42V, +1.14V ≤ VDDQ ≤ 1.26V, +2.38V ≤ VEXT ≤ +2.63V, VREF = VSS, f = 100
MHz, TC = 25°C, VOUT(DC) = 0.5 × VDDQ, VOUT (peak-to-peak) = 0.1V.
2. Capacitance is not tested on the ZQ ball.
3. CDIO = CIO(DQ) - 0.5 × (CIO [QK/DK] + CIO [QK#/DK#]).
4. Includes CS#, REF#, WE#, A[19:0], and BA[3:0].
5. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 × (CCK [CK] + CCK [CK#]).
6. JTAG balls are tested at 50 MHz.
15
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1.125Gb: x18, x36 TwinDie RLDRAM 3
ODT Characteristics
ODT Characteristics
ODT Resistors
The following tables provide an overview of the ODT DC electrical characteristics. Note
that 10Ω is added to account for the RDL needed to stack the die. The 10Ω is constant
across V OUT. The 10Ω RDL addition is an advance estimate and will need characterization data for more accurate values. The values provided are not specification requirements; however, they can be used as design guidelines to indicate what RTT is targeted
to provide:
• RTT of 130Ω is made up of RTT120(PD240) and RTT120(PU240) plus 10Ω from RDL needed to
stack die.
• RTT of 125Ω is made up of RTT120(PD240) plus 10Ω from RDL needed to stack die and
RTT120(PU240) plus 10Ω from RDL needed to stack die.
• RTT of 70Ω is made up of RTT60(PD120) and RTT60(PU120) plus 10Ω from RDL needed to
stack die.
• RTT of 65Ω is made up of RTT60(PD120) plus 10Ω from RDL needed to stack die and
RTT60(PU120) plus 10Ω from RDL needed to stack die.
• RTT of 50Ω is made up of RTT40(PD80) and RTT40(PU80) and 10Ω from RDL needed to
stack die.
Table 8: RTT Effective Impedances
Selected
Termination Configuration
40
60
120
DDP-ODT
(MR2[9:8])
Effective DQ
Termination
Effective DM
Termination
Effective DK
Termination
Units
x18
11
Reserved
Reserved
Reserved
Ω
x36
00
50
65
65
Ω
x18
11
70
70
65
Ω
x36
00
70
65
65
Ω
x18
11
130
130
125
Ω
x36
00
130
125
125
Ω
Table 9: RTT Effective Impedance Ranges
RTT
Resistor
VOUT
Min
Nom
Max
Units
130Ω
RTT120(PD240)
0.2 x VDDQ
164
260
284
Ω
0.5 x VDDQ
236
260
284
Ω
0.8 x VDDQ
236
260
356
Ω
0.2 x VDDQ
236
260
356
Ω
0.5 x VDDQ
236
260
284
Ω
0.8 x VDDQ
164
260
284
Ω
VIL(AC) to VIH(AC)
118
130
202
Ω
RTT120(PU240)
130Ω
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
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1.125Gb: x18, x36 TwinDie RLDRAM 3
ODT Characteristics
Table 9: RTT Effective Impedance Ranges (Continued)
RTT
Resistor
VOUT
Min
Nom
Max
Units
125Ω
RTT120(PD240)
0.2 x VDDQ
154
250
274
Ω
0.5 x VDDQ
226
250
274
Ω
0.8 x VDDQ
226
250
346
Ω
RTT120(PU240)
125Ω
70Ω
RTT60(PD120)
RTT60(PU120)
70Ω
65Ω
RTT60(PD120)
RTT60(PU120)
65Ω
50Ω
RTT40(PD80)
RTT40(PU80)
50Ω
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
0.2 x VDDQ
226
250
346
Ω
0.5 x VDDQ
226
250
274
Ω
0.8 x VDDQ
154
250
274
Ω
VIL(AC) to VIH(AC)
113
125
197
Ω
0.2 x VDDQ
92
140
152
Ω
0.5 x VDDQ
128
140
152
Ω
0.8 x VDDQ
128
140
188
Ω
0.2 x VDDQ
128
140
188
Ω
0.5 x VDDQ
128
140
152
Ω
0.8 x VDDQ
92
140
152
Ω
VIL(AC) to VIH(AC)
64
70
106
Ω
0.2 x VDDQ
82
130
142
Ω
0.5 x VDDQ
118
130
142
Ω
0.8 x VDDQ
118
130
178
Ω
0.2 x VDDQ
118
130
178
Ω
0.5 x VDDQ
118
130
142
Ω
0.8 x VDDQ
82
130
142
Ω
VIL(AC) to VIH(AC)
59
65
101
Ω
0.2 x VDDQ
68
100
108
Ω
0.5 x VDDQ
92
100
108
Ω
0.8 x VDDQ
92
100
132
Ω
0.2 x VDDQ
92
100
132
Ω
0.5 x VDDQ
92
100
108
Ω
0.8 x VDDQ
68
100
108
Ω
VIL(AC) to VIH(AC)
46
50
74
Ω
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Output Driver Impedance
ODT Sensitivity
If either temperature or voltage changes after I/O calibration, then the tolerance limits
listed in Table 9 (page 16) can be expected to widen according to Table 10 (page 18)
and Table 11 (page 18).
Table 10: ODT Sensitivity Definition
Symbol
Min
Max
Units
RTT
0.9 - dRTTdT × |DT| - dRTTdV × |DV|
1.6 + dRTTdT × |DT| + dRTTdV × |
DV|
RZQ/(2,4,6)
Note:
1. DT = T - T(@ calibration), DV = VDDQ - VDDQ(@ calibration) or VDD - VDD(@ calibration).
Table 11: ODT Temperature and Voltage Sensitivity
Change
Min
Max
Units
dRTTdT
0
1.5
%/°C
dRTTdV
0
0.15
%/mV
Output Driver Impedance
The output driver impedance is selected by MR1[1:0] during initialization. The selected
value is able to maintain the tight tolerances specified if proper ZQ calibration is performed.
Output specifications refer to the default output driver unless specifically stated otherwise. A functional representation of the output buffer is shown below. The output driver
impedance RON is defined by the value of the external reference resistor RZQ plus 10Ω
RDL resistance from stacking the die. The 10Ω RDL addition is an advance estimate and
will need characterization data for more accurate values.
• RON,x = RZQ/y + 10Ω (with RZQ = 240Ω ±1%; x = 34.3Ω or 48Ω with y = 7 or 5, respectively)
The individual pull-up and pull-down resistors (RON(PU) and RON(PD)) are defined as follows:
• RON(PU) = (VDDQ - V OUT)/|IOUT|, when RON(PD) is turned off
• RON(PD) = (VOUT)/|IOUT|, when RON(PU) is turned off
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Output Driver Impedance
Figure 5: Output Driver
Chip in drive mode
Output Driver
VDDQ
IPU
RON(PU)
To
other
circuitry
such as
RCV, . . .
IOUT
RON(PD)
DQ
VOUT
IPD
VSSQ
Table 12: Driver Pull-Up and Pull-Down Impedance Calculations
RON
Min
Nom
Max
Units
RZQ/7 = (240Ω ±1%)/7 + 10Ω
43.9
44.3
44.6
Ω
RZQ/5 = (240Ω ±1%)/5 + 10Ω
57.5
58
58.5
Ω
Min
Nom
Max
Units
Driver
VOUT
44.3Ω pull-down
0.2 × VDDQ
30.6
44.3
47.7
Ω
0.5 × VDDQ
40.9
44.3
47.7
Ω
0.8 × VDDQ
40.9
44.3
58.0
Ω
0.2 × VDDQ
40.9
44.3
58.0
Ω
44.3Ω pull-up
58Ω pull-down
58Ω pull-up
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
0.5 × VDDQ
40.9
44.3
47.7
Ω
0.8 × VDDQ
30.6
44.3
47.7
Ω
0.2 × VDDQ
38.8
58
62.8
Ω
0.5 × VDDQ
53.2
58
62.8
Ω
0.8 × VDDQ
53.2
58
77.2
Ω
0.2 × VDDQ
53.2
58
77.2
Ω
0.5 × VDDQ
53.2
58
62.8
Ω
0.8 × VDDQ
38.8
58
62.8
Ω
19
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Output Driver Impedance
Output Driver Sensitivity
If either the temperature or the voltage changes after ZQ calibration, then the tolerance
limits listed in Table 12 (page 19) can be expected to widen according to Table 13
(page 20) and Table 14 (page 20).
Table 13: Output Driver Sensitivity Definition
Symbol
Min
Max
Units
RON(PD) @ 0.2 x VDDQ
0.6 - dRONdTH x DT - dRONdVH x DV
1.1 + dRONdTH x DT + dRONdVH x DV RZQ/(7,5)+10Ω
1.1 + dRONdTM x DT + dRONdVM x DV RZQ/(7,5)+10Ω
RON(PD) @ 0.5 x VDDQ
0.9 - dRONdTM x DT - dRONdVM x DV
RON(PD) @ 0.8 x VDDQ
0.9 - dRONdTL x DT - dRONdVL x DV
RON(PU) @ 0.2 x VDDQ
0.9 - dRONdTH x DT - dRONdVH x DV
1.4 + dRONdTH x DT + dRONdVH x DV RZQ/(7,5)+10Ω
RON(PU) @ 0.5 x VDDQ
0.9 - dRONdTM x DT - dRONdVM x DV
1.1 + dRONdTM x DT + dRONdVM x DV RZQ/(7,5)+10Ω
RON(PU) @ 0.8 x VDDQ
0.6 - dRONdTL x DT - dRONdVL x DV
Note:
1.4 + dRONdTL x DT + dRONdVL x D
1.1 + dRONdTL x DT + dRONdVL x DV
RZQ/(7,5)+10Ω
RZQ/(7,5)+10Ω
1. DT = T - T(@ calibration), DV = VDDQ - VDDQ(@ calibration) or VDD - VDD(@ calibration).
Table 14: Output Driver Voltage and Temperature Sensitivity
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
Change
Min
Max
Unit
dRONdTM
0
1.5
%/°C
dRONdVM
0
0.15
%/mV
dRONdTL
0
1.5
%/°C
dRONdVL
0
0.15
%/mV
dRONdTH
0
1.5
%/°C
dRONdVH
0
0.15
%/mV
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Output Characteristics and Operating Conditions
Output Characteristics and Operating Conditions
Table 15: Single-Ended Output Driver Characteristics
Note 1–4 apply to entire table
Parameter/Condition
Symbol
Output slew rate: Single-ended; For rising and falling
edges, measures between VOL(AC) = VREF - 0.1 × VDDQ and
VOH(AC) = VREF + 0.1 × VDDQ
Notes:
SRQSE
Min
Max
Units
x18
1.0
2.5
V/ns
x36
2.5
6
V/ns
1. All voltages are referenced to VSS.
2. RZQ is 240Ω (±1%) and is applicable after proper ZQ calibration has been performed at
a stable temperature and voltage.
3. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from
HIGH to LOW or LOW to HIGH, while the remaining DQ signals in the same byte lane
are all either static or switching to the opposite direction. For all other DQ signal-switching combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns.
4. These slew rate specifications are defined for a 1.875ns tCK.
Table 16: Differential Output Driver Characteristics
Notes 1–3 apply to entire table
Parameter/Condition
Symbol
Output slew rate: Differential; For rising and
falling edges, measures between VOL,diff(AC) =
–0.2 × VDDQ and VOH,diff(AC) = +0.2 × VDDQ
Notes:
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
SRQdiff
Min
Max
Units
x18
2.0
5.0
V/ns
x36
5
12
V/ns
1. All voltages are referenced to VSS.
2. RZQ is 240Ω (±1%) and is applicable after proper ZQ calibration has been performed at
a stable temperature and voltage.
3. These slew rate specifications are defined for a 1.875ns tCK.
21
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Timing Adjustments
Timing Adjustments
Table 17: DDP Timing adjustments
RL3-1866
Parameter
Symbol
Min
RL3-1600
Max
Min
Max
Units Notes
35
–
60
–
ps
1, 2
185
–
210
–
ps
2, 3
70
–
95
–
ps
1, 2
170
–
195
–
ps
ps
DQ Input Timing
Data setup time to
DK, DK#
Base
(specification)
tDS(AC150)
VREF
@ 1 V/ns
Data hold time from
DK, DK#
Base
(specification)
tDH(DC100)
VREF
@ 1 V/ns
DQ Output Timing
tQKQ
x
QK, QK# edge to output data
edge within byte group
QK, QK# edge to any output data
edge within specific data-word
grouping (for x36 only)
x18
–
105
–
120
x36
–
85
–
100
–
N/A
–
N/A
ps
ps
6
ps
5
tQKQ02,
tQKQ13
Input and Output Strobe Timing
QK (rising), QK# (falling) edge to
CK (rising), CK# (falling) edge
tCKQK
x18
–140 5%tCK
140 +
5%tCK
–160 5%tCK
160 + 5%
tCK
x36
–140 5%tCK
140 +
5%tCK
–160 5%tCK
160 + 5%
tCK
x18
–
155
–
170
x36
–
135
–
150
–
512
–
QK (falling), QK# (rising) edge to
QVLD edge
tQKVLD
ZQCL: Long calibration time
tZQinit
x18
512
x36
1024
–
1024
–
CK
tZQoper
x18
256
–
256
–
CK
x36
512
–
512
–
CK
x18
64
–
64
–
CK
x36
128
–
128
–
CK
Calibration Timing
ZQCS: Short calibration time
Notes:
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tZQcs
CK
1. tDS(base) and tDH(base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns differential DK, DK# slew rate.
2. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DK, DK#) crossing.
3. The setup and hold times are listed converting the base specification values (to which
derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate
of 1 V/ns, are for reference only.
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Thermal Impedance Characteristics
4. When the device is operated with input clock jitter, this parameter needs to be derated
by the actual tJIT(per) (the larger of tJIT(per), MIN or tJIT(per), MAX of the input clock;
output deratings are relative to the SDRAM input clock).
5. For the x36 device, this specification references the skew between the falling edge of
QK0 and QK1 to QVLD0 and the falling edge of QK2 and QK3 to QVLD1.
6. The DRAM output timing is aligned to the nominal or average clock. The following output parameters must be derated by the actual jitter error when input clock jitter is
present, even when within specification. This results in each parameter's becoming larger. The following parameters are required to be derated by subtracting tERR(10per),
MAX: tCKQK(MIN), and tLZ(MIN). The following parameters are required to be derated
by subtracting tERR(10per), MIN: tCKQK(MAX), tHZ(MAX), and tLZ(MAX).
Thermal Impedance Characteristics
Table 18: Thermal Impedance
θ JA (°C/W)
Airflow = 0 m/s
θ JA (°C/W)
Airflow = 1 m/s
θ JA (°C/W)
Airflow = 2 m/s
θ JB (°C/W)
θ JC (°C/W)
2-layer
41.3
29.8
26.2
NA
2.0
4-layer
24.0
18.8
17.3
7.6
Package Substrate
FBGA
Note:
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1. Thermal impedance data is based on a number of samples from multiple lots and should
be viewed as a typical number.
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Commands
Commands
The following table provides descriptions of the valid commands of the RLDRAM 3 device. All command and address inputs must meet setup and hold times with respect to
the rising edge of CK.
Table 19: Command Descriptions
Command
Description
NOP
The NOP command prevents new commands from being executed by the DRAM.
Operations already in progress are not affected by NOP commands. Output values depend on command history.
MRS
Mode registers MR0, MR1, and MR2 are used to define various modes of programmable operations of
the DRAM. A mode register is programmed via the MODE REGISTER SET (MRS) command during initialization and retains the stored information until it is reprogrammed, RESET# goes LOW, or until the
device loses power. The MRS command can be issued only when all banks are idle, and no bursts are
in progress.
READ
The READ command is used to initiate a burst read access to a bank. The BA[3:0] inputs select a bank,
and the address provided on inputs A[19:0] select a specific location within a bank.
WRITE
The WRITE command is used to initiate a burst write access to a bank (or banks). MRS bits MR2[4:3]
select a single-, dual-, or quad-bank WRITE protocol. The BA[x:0] inputs select the bank(s) (x = 3, 2, or
1 for a single-, dual-, or quad-bank WRITE, respectively). The address provided on inputs A[19:0] selects a specific location within the bank. Input data appearing on the DQ is written to the memory
array subject to the DM input logic level appearing coincident with the data. If the DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH,
the corresponding data inputs will be ignored (that is, this part of the data word will not be written).
AREF
The AREF command is used during normal operation of the RLDRAM 3 to refresh the memory content of a bank. There are two methods by which the RLDRAM 3 can be refreshed, both of which are
selected within the mode register. The first method, bank address-controlled AREF, is identical to the
method used in RLDRAM 2. The second method, multibank AREF, enables refreshing of up to four
banks simultaneously. More information is available in the Auto Refresh section. For both methods,
the command is nonpersistent, so it must be issued each time a refresh is required.
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Commands
Table 20: x18 Command Table
Notes 1 and 2 apply to entire table; notes appear after x36 Command Table
Operation
Code
CS0#
CS1#
WE#
REF#
A[19:0]
BA[3:0]
NOP
NOP
H
H
X
L
X
X
MRS
MRSboth
L
L
L
L
OPCODE
OPCODE
MRS0
L
H
L
L
OPCODE
OPCODE
MRS1
H
L
L
L
OPCODE
OPCODE
READ0
L
H
H
H
A
BA
READ1
H
L
H
H
A
BA
WRITE0
L
H
L
H
A
BA
WRITE1
H
L
L
H
A
BA
AREFboth
L
L
H
L
A
BA
AREF0
L
H
H
L
A
BA
AREF1
H
L
H
L
A
BA
READ
WRITE
AUTO REFRESH
Notes
3
3
4
Table 21: x36 Command Table
Note 1 applies to entire table
Operation
Code
CS#
WE#
REF#
A[19:0]
BA[3:0]
NOP
NOP
H
X
X
X
X
MRS
MRS
L
L
L
OPCODE
OPCODE
READ
READ
L
H
H
A
BA
3
WRITE
WRITE
L
L
H
A
BA
3
AREF
L
H
L
A
BA
4
AUTO REFRESH
Notes:
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Notes
1. X = “Don’t Care;” H = logic HIGH; L = logic LOW; A = valid address; BA = valid bank address; OPCODE = mode register bits
2. Subscripts on command codes (both, 0, and 1) refer to the die being accessed. 0 = die 0,
1 = die 1, and both = both die simultaneously.
3. Address width varies with burst length and configuration; see the Address Widths of
Different Burst Lengths table for more information.
4. Bank address signals (BA) are used only during bank address-controlled AREF; address
signals (A) are used only during multibank AREF.
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Mode Register 0 (MR0)
Mode Register 0 (MR0)
Figure 6: MR0 Definition for Non-Multiplexed Address Mode
BA3 BA2 BA1 BA0 A17...A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
10 9 8 7 6 5 4
21 20 19 18
17–11
Reserved DDP AM DLL Data Latency
01 01 MRS
3
2
1
0
Address Bus
Mode Register (Mx)
tRC_MRS
M7 M6 M5 M4 Data Latency (RL & WL)
M10
DDP Selection
0
X36 DDP
1
M8
0
X18 DDP
1
M19 M18
Mode Register Definition
t RC_MRS
0
0
0
RL = 3 ; WL = 4
0
0
0
0
22, 3
DLL Enable
0
0
0
1
RL = 4 ; WL = 5
0
0
0
1
32
Enable
0
0
1
0
RL = 5 ; WL = 6
0
0
1
0
42
Disable
0
0
1
1
RL = 6 ; WL = 7
0
0
1
1
5
0
1
0
0
RL = 7 ; WL = 8
0
1
0
0
6
0
1
0
1
RL = 8 ; WL = 9
0
1
0
1
7
0
1
1
0
RL = 9 ; WL = 10
0
1
1
0
8
0
1
1
0
1
0
1
0
RL = 10 ; WL = 11
RL = 11 ; WL = 12
0
1
1
0
1
0
1
0
9
10
1
0
0
1
RL = 12 ; WL = 13
1
0
0
1
11
1
0
1
0
1
0
1
0
12
1
0
1
1
RL = 13 ; WL = 14
RL = 14 ; WL = 15
1
0
1
1
Reserved
1
1
0
0
RL = 15 ; WL = 16
1
1
0
0
Reserved
1
1
0
1
RL = 16 ; WL = 17
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
1
1
1
1
Reserved
M9
Address MUX
0
0
Mode Register 0 (MR0)
0
Non-multiplexed
0
1
Mode Register 1 (MR1)
1
Multiplexed
1
0
Mode Register 2 (MR2)
1
1
Reserved
Notes:
M3 M2 M1 M0
0
1. BA2, BA3, and all address balls corresponding to Reserved must be held LOW during the
MRS command.
2. BL8 not allowed.
3. BL4 not allowed.
tRC
Bits MR0[3:0] select the number of clock cycles required to satisfy the tRC specifications.
After a READ, WRITE, or AREF command is issued to a bank, a subsequent READ,
WRITE, or AREF cannot be issued to the same bank until tRC has passed. tRC should be
divided by the clock period and rounded up to the next whole number to determine the
earliest clock edge that the subsequent command can be issued to the bank.
Note that the min tCK value for a given RL/WL parameter must be used to determine
the tRC mode register setting.
Data Latency
The data latency register uses MR0[7:4] to set both the READ and WRITE latency (RL
and WL). The valid operating frequencies for each data latency register setting can be
found in the MT6L32M18 datasheet.
DLL Enable/Disable
Through the programming of MR0[8], the DLL can be enabled or disabled.
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Mode Register 0 (MR0)
The DLL must be enabled for normal operation. The DLL must be enabled during the
initialization routine and upon returning to normal operation after having disabled the
DLL for the purpose of debugging or evaluation. To operate with the DLL disabled, the
tRC MRS setting must equal the Read Latency (RL) setting. For example if the tRC setting is 7, the Read Latency must also be set to 7. Enabling the DLL should always be followed by resetting the DLL by using the appropriate MR1 command.
Address Multiplexing
Although the RLDRAM has the ability to operate similar to an SRAM interface by accepting the entire address in one clock (non-multiplexed, or broadside addressing),
MR0[9] can be set to 1 so that it functions with multiplexed addressing, similar to a traditional DRAM. In multiplexed address mode, the address is provided to the RLDRAM
in two parts that are latched into the memory with two consecutive rising edges of CK.
When in multiplexed address mode, only 11 address balls are required to control the
RLDRAM, as opposed to 20 address balls when in non-multiplexed address mode. The
data bus efficiency in continuous burst mode is only affected when using the BL = 2 setting since the device requires two clocks to read and write data. During multiplexed
mode, the bank addresses as well as WRITE and READ commands are issued during the
first address part, Ax. The Address Mapping in Multiplexed Address Mode table shows
the addresses needed for both the first and second rising clock edges (Ax and Ay, respectively).
After MR0[9] is set HIGH, READ, WRITE, and MRS commands follow the format described in the Command Description in Multiplexed Address Mode figure. Refer to Multiplexed Address Mode for further information on operation with multiplexed addressing.
DDP Selection.
This mode register setting properly configures a DDP device based upon the IO configuration.
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Mode Register 1 (MR1)
Mode Register 1 (MR1)
Figure 7: MR1 Definition for Non-Multiplexed Address Mode
BA3 BA2 BA1 BA0 A17.. A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
21 20
01 01
M19 M18
19 18 17–11 10 9 8 7 6 5
MRS Reserved BL Ref ZQe ZQ DLL
4 3
ODT
2
1
0
Mode Register (Mx)
Drive
Mode Register Definition
M5 DLL Reset
M4 M3 M2
ODT
M1 M0 Output Drive
0
0
Mode Register 0 (MR0)
0
1
Mode Register 1 (MR1)
0
No
0
0
0
Off
0
0
1
0
Mode Register 2 (MR2)
1
Yes
0
0
1
40Ω
0
1
58Ω
1
1
Reserved
0
1
0
60Ω
1
0
Reserved
0
1
1
120Ω
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M10 M9
Note:
M6
ZQ Calibration Selection
Burst Length
0
0
0
Short ZQ Calibration
2
0
1
1
Long ZQ Calibration
4
1
0
8
1
1
M7
Reserved
0
Disabled - Default
1
Enable
ZQ Calibration Enable
M8
AREF Protocol
0
Bank Address Control
1
Multibank
44.3Ω
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
Output Drive Impedance
The RLDRAM 3 uses programmable impedance output buffers. This enables a user to
match the driver impedance to the system. MR1[0] and MR1[1] are used to select 44.3Ω
or 58Ω output impedance. The drivers have symmetrical output impedance. The device
will power-up with an output impedance of 44.3Ω. To calibrate the impedance, a 240Ω
±1% external precision resistor (RZQ) is connected between the ZQ ball and V SSQ.
The output impedance is calibrated during initialization through the ZQCL command.
Subsequent periodic calibrations (ZQCS) may be performed to compensate for shifts in
output impedance due to changes in temperature and voltage. More detailed information on calibration can be found in the ZQ Calibration section.
On-Die Termination (ODT)
MR1[4:2] are used to select the value of the on-die termination (ODT) for the DQ, DKx,
and DM balls. When enabled, ODT terminates these balls to V DDQ/2. The TwinDie
RLDRAM 3 ODT values differ depending on the configuration and the pin. See the ODT
Characteristics section for the effective impedances. The ODT function is dynamically
switched off when a DQ begins to drive after a READ command has been issued. Simi-
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Mode Register 1 (MR1)
larly, ODT is designed to switch on at the DQs after the RLDRAM has issued the last
piece of data. The DM and DKx balls are always terminated after ODT is enabled.
The ODT is calibrated during initialization through the ZQCL command. Subsequent
periodic calibrations (ZQCS) may be performed to compensate for shifts in termination
due to changes in temperature and voltage. More detailed information on calibration
can be found in the ZQ Calibration section.
ZQ Calibration
The ZQ CALIBRATION mode register command is used to calibrate the DRAM output
drivers (RON) and ODT values (RTT) over process, voltage, and temperature, provided a
dedicated 240Ω (±1%) external resistor is connected from the DRAM’s RZQ ball to V SSQ.
Bit MR1[6] selects between ZQ calibration long (ZQCL) and ZQ calibration short
(ZQCS), each of which are described in detail below. When bit MR1[7] is set HIGH, it
enables the calibration sequence. Upon completion of the ZQ calibration sequence,
MR1[7] automatically resets LOW.
The RLDRAM 3 needs a longer time to calibrate RON and ODT at power-up initialization
and a relatively shorter time to perform periodic calibrations. An example of ZQ calibration timing is shown below.
All banks must have tRC met before ZQCL or ZQCS commands can be issued to the
DRAM. No other activities (other than another ZQCL or ZQCS command issued to another DRAM) can be performed on the DRAM channel by the controller for the duration
of tZQinit or tZQoper. The quiet time on the DRAM channel helps accurately calibrate
RON and ODT. After DRAM calibration is achieved, the DRAM disables the ZQ ball’s current consumption path to reduce power.
Because the two ranks within the x18 configuration TwinDie device share a ZQ resistor,
only NOP commands are permitted for the duration of tZQinit, tZQoper, or tZQcs. Both
ranks must be calibrated independently.
For the x36 configuration TwinDie device, the calibration timing is twice that of the x18
configuration because a single ZQ CALIBRATION mode register command calibrates
one die in the stacked package and then the other.
ZQ CALIBRATION commands can be issued in parallel to DLL reset and locking time.
In systems that share the ZQ resistor between devices, the controller must not allow
overlap of tZQinit, tZQoper, or tZQcs between devices. This is true of the two ranks in the
x18 configuration TwinDie device, as well.
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Mode Register 1 (MR1)
Figure 8: ZQ Calibration Timing (ZQCL and ZQCS)
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
Command
MRS
NOP
NOP
NOP
Valid
Valid
MRS
NOP
NOP
NOP
Valid
Address
ZQCL
Valid
Valid
ZQCS
CK#
CK
DQ
Valid
Activities
Activities
Activities
Activities
QK#
QK
QVLD
tZQinit or tZQoper
tZQCS
Indicates a break in
time scale
Notes:
Don’t Care
or Unknown
1. All devices connected to the DQ bus should be held High-Z during calibration.
2. The state of QK and QK# are unknown during ZQ calibration.
3. tMRSC after loading the MR1 settings, QVLD output drive strength will be at the value
selected or higher (lower resistance) until ZQ calibration is complete.
AUTO REFRESH Protocol
The AUTO REFRESH (AREF) protocol is selected with bit MR1[8]. There are two ways in
which AREF commands can be issued to the RLDRAM. Depending upon how bit
MR1[8] is programmed, the memory controller can either issue bank address-controlled or multibank AREF commands. A bank address-controlled AREF uses the BA[3:0] inputs to refresh a single bank per command. A multibank AUTO REFRESH is enabled by
setting bit MR1[8] HIGH during an MRS command. This refresh protocol allows for the
simultaneous refreshing of a row in up to four banks. In this method, the address pins
A[15:0] represent banks 0–15, respectively. More information on both AREF protocols
may be found in the MT44K32M18 data sheet.
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Mode Register 2 (MR2)
Mode Register 2 (MR2)
Figure 9: MR2 Definition for Non-Multiplexed Address Mode
BA3 BA2 BA1 BA0 A17 ... A10 A9
A8 A7 ... A5 A4 A3 A2 A1 A0 Address Bus
21 20 19 18
17-10
9-8
7-5
4 3 2
01 01 MRS Reserved DDP-ODT Reserved WRITE En
M19 M18
1 0
RTR
Mode Register (Mx)
Mode Register Definition
0
0
Mode Register 0 (MR0)
0
1
Mode Register 1 (MR1)
0
0
X36 DDP
1
Reserved
0
0
0-1-0-1 on all DQs
M9 M8
DDP - ODT
M1 M0
READ Training Register
1
0
Mode Register 2 (MR2)
0
1
1
Reserved
1
0
Reserved
0
1
Even DQs: 0-1-0-1 ; Odd DQs: 1-0-1-0
1
1
X18 DDP
1
0
Reserved
1
1
Reserved
M4 M3
Note:
WRITE Protocol
0
0
Single Bank
0
1
Dual Bank
1
0
Quad Bank
1
1
Reserved
M2 READ Training Register Enable
0
Normal RLDRAM Operation
1
READ Training Enabled
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
Dual Die Package - On Die Termination
The dual die package - on die termination (DDP-ODT) controlled through MR2[9:8]. Is
used to adjust the internal ODT settings based upon the configuration width of the device.
READ Training Register
The READ training register (RTR) is controlled through MR2[2:0]. It is used to output a
predefined bit sequence on the output balls to aid in system timing calibration. MR2[2]
is the master bit that enables or disables access to the READ training register, and
MR2[1:0] determine which predefined pattern for system calibration is selected. If
MR2[2] is set to 0, the RTR is disabled, and the DRAM operates in normal mode. When
MR2[2] is set to 1, the DRAM no longer outputs normal read data, but a predefined pattern that is defined by MR2[1:0].
Prior to enabling the RTR, all banks must be in the idle state (tRC met). When the RTR is
enabled, all subsequent READ commands will output four bits of a predefined sequence from the RTR on all DQs. The READ latency during RTR is defined with the data
latency bits in MR0. To loop on the predefined pattern when the RTR is enabled, successive READ commands must be issued and satisfy tRTRS. x18 devices should issue interleaved READ commands (a READ to die 0, followed by a READ to die 1 as shown in Figure 10 (page 33)) to ensure proper READ training for both die. Address balls A[19:0]
are considered "Don't Care" during RTR READ commands. Bank address bits BA[3:0]
must access Bank 0 with each RTR READ command. tRC does not need to be met in between RTR READ commands to Bank 0. When the RTR is enabled, only READ commands are allowed. When the last RTR READ burst has completed and tRTRE has been
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1.125Gb: x18, x36 TwinDie RLDRAM 3
Mode Register 2 (MR2)
satisfied, an MRS command can be issued to exit the RTR. Standard RLDRAM3 operation may then start after tMRSC has been met. The RESET function is supported when
the RTR is enabled.
If MR2[1:0] is set to 00, a 0-1-0-1 pattern will be output on all DQs with each RTR READ
command. If MR2[1:0] is set to 01, a 0-1-0-1 pattern will output on all even DQs, and the
opposite pattern, a 1-0-1-0, will output on all odd DQs with each RTR READ command.
Enabling RTR may corrupt previously written data.
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Figure 10: READ Training Function - x18 Die Interleave Training
CK#
T0
T1
T3
T2
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
MRSboth
VALID
CK
Command
MRSboth
Address
MR2[17:0]
Bank
MR2[21:18]
NOP
READ0
READ1
NOP
READ0
NOP
READ1
NOP
READ
NOP 0
NOP
NOP
MR2[17:0]
BANK 0
BANK 0
BANK 0
BANK 0
MR2[21:18]
BANK 0
DM
QK#
QK
DK#
(
DK
RL
tMRSC
tRTRS
tRTRS
tRTRS
tRTRE
tRTRS
tMRSC
QVLD
DQ
Transitioning Data
33
Note:
Don’t Care
Indicates a break
in time scale
1. RL = READ latency defined with data latency MR0 setting.
1.125Gb: x18, x36 TwinDie RLDRAM 3
Mode Register 2 (MR2)
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1.125Gb: x18, x36 TwinDie RLDRAM 3
INITIALIZATION Operation
INITIALIZATION Operation
The RLDRAM 3 device must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operations or
permanent damage to the device.
The following sequence is used for power-up:
1. Apply power (VEXT, V DD, V DDQ). Apply V DD and V EXT before, or at the same time as,
VDDQ. V DD must not exceed V EXT during power supply ramp. V EXT, V DD, V DDQ must
all ramp to their respective minimum DC levels within 200ms.
2. Ensure that RESET# is below 0.2 × V DDQ during power ramp to ensure the outputs
remain disabled (High-Z) and ODT is off (RTT is also High-Z). DQs and QK signals
will remain High-Z until the MR0 command is issued. All other inputs may be undefined during the power ramp.
3. After the power is stable, RESET# must be LOW for at least 200µs to begin the initialization process.
4. After 100 or more stable input clock cycles with NOP commands, bring RESET#
HIGH.
5. After RESET# goes HIGH, a stable clock must be applied in conjunction with NOP
commands, and all address pins (A[19:0] and BA[3:0]) must be held LOW for
10,000 cycles.
6. Load the desired settings into MR0. The x18 DDP device should have both CSx#
asserted for this step.
7. tMRSC after loading the MR0 settings, load the operating parameters into MR1, including DLL reset and long ZQ calibration. This step must be done on each die of
the x18 DDP independently.
8. After the DLL is reset and long ZQ calibration is enabled, the input clock must be
stable for 512 clock cycles for x18 devices and 1024 clock cycles for x36 devices,
while NOPs are issued.
9. Load the desired settings into MR2. The x18 DDP device should have both CSx#
asserted for this step. If READ training is being used for the x18 device, follow the
procedure outlined in the READ Training Function – x18 Die Interleave Training
figure contained in this data sheet prior to entering normal operation; for the x36
device, refer to the READ Training Function - Back-to-Back Training figure located
in the Micron 576Mb RLDRAM3 data sheet.
10. The RLDRAM 3 is now ready for normal operation.
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
34
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
1.125Gb: x18, x36 TwinDie RLDRAM 3
INITIALIZATION Operation
Figure 11: Power-Up/Initialization Sequence
T (MAX) = 200ms
VDD
See power-up
conditions
in the
initialization
sequence text
VDDQ
VEXT
VREF
Power-up
ramp
Stable and
valid clock
tCK
CK#
CK
tCH
100 cycles
tIOZ
tCL
= 20ns
RESET#
tDK
DK#
DK
tDKH
Command
NOP
NOP
NOP
tDKL
MRS
MRS
MR0
MR1
MRS
Valid
DM
Address
MR2
Valid
QK#
QK
QVLD1
DQ
RTT
T = 200µs (MIN)
10,000 CK cycles (MIN)
All voltage
supplies valid
and stable
Notes:
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
Indicates a break in
time scale
tMRSC
Don’t Care
or Unknown
512 clock cycles READ Training
for each X18 die, register specs
apply
1024 clock cycles
for x36 device
DLL RESET and
ZQ calibration
Normal
operation
1. QVLD output drive status during power-up and initialization:
a. QVLD will remain at High-Z while RESET# is LOW.
b. After RESET# goes HIGH, QVLD will transition LOW after approximately 20ns.
c. QVLD will then continue to drive LOW with 40Ω or lower until MR0 is enabled.
Once MR0 has been enabled, the state of QVLD becomes unknown.
35
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
1.125Gb: x18, x36 TwinDie RLDRAM 3
READ Operation
d. QVLD will meet the output drive strength specifications when the ZQ calibration is
complete.
2. After MR2 has been issued, RTT is either High-Z or enabled to the ODT value selected in
MR1.
READ Operation
Figure 12: x18 Consecutive Die Interleave READ Bursts (BL = 2)
T5n
T6n
T0
T1
T2
T3
Command
READ0
READ1
READ0
READ1
READ0
READ1
READ0
Address
Bank a
Add n
Bank b
Add n
Bank c
Add n
Bank d
Add n
Bank e
Add n
Bank f
Add n
Bank g
Add n
CK#
T4
T4n
T5
T6
CK
RL = 4
QVLD
QK#
QK
DO
an
DQ
DO
bn
DO
cn
Transitioning Data
Note:
Don’t Care
1. DO an (or bn, cn) = data-out from bank a (or bank b, c) and address n.
Figure 13: x18 Non-Consecutive Die Interleave READ Bursts (BL = 2)
T0
T1
T2
Command
READ0
NOP
READ1
Address
Bank a
Add n
CK#
T3
T4
T4n
T5
T5n
T6n
T6
CK
NOP
Bank b
Add n
READ0
NOP
Bank c
Add n
READ1
Bank d
Add n
RL = 4
QVLD
QK#
QK
DO
an
DQ
Transitioning Data
Note:
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
DO
bn
Don’t Care
1. DO an (or bn) = data-out from bank a (or bank b) and address n.
36
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© 2013 Micron Technology, Inc. All rights reserved.
1.125Gb: x18, x36 TwinDie RLDRAM 3
Multiplexed Address Mode
Multiplexed Address Mode
Figure 14: MR0 Definition for Multiplexed Address Mode
A5 A4 A3
Ax A18.......A13 A10 A9 A8
A0
Ay A18.......A13
A9 A8
A4 A3
Address Bus
BA3 BA2 BA1 BA0
21 20 19 18
01 01 MRS
17-11
Reserved
10 9 8 7 6 5 4
DDP AM DLL Data Latency
3
2
1
0
Mode Register (Mx)
tRC_MRS
M7 M6 M5 M4 Data Latency (RL & WL)
M19 M18
0
0
0
0
RL = 3 ; WL = 4
DLL Enable
0
0
0
1
RL = 4 ; WL = 5
0
Enable
0
0
1
0
RL = 5 ; WL = 6
1
Disable
0
0
1
1
RL = 6 ; WL = 7
0
1
0
0
RL = 7 ; WL = 8
0
1
0
1
RL = 8 ; WL = 9
Address MUX
0
1
1
0
RL = 9 ; WL = 10
0
1
1
0
1
0
1
0
RL = 10 ; WL = 11
RL = 11 ; WL = 12
1
0
0
1
RL = 12 ; WL = 13
1
0
1
0
RL = 13 ; WL = 14
1
0
1
1
RL = 14 ; WL = 15
1
1
0
0
RL = 15 ; WL = 16
1
1
0
1
RL = 16 ; WL = 17
1
1
1
0
Reserved
1
1
1
1
Reserved
M10
DDP Selection
0
X36 DDP
M8
1
X18 DDP
Mode Register Definition
M9
0
0
Mode Register 0 (MR0)
0
Non-multiplexed
0
1
Mode Register 1 (MR1)
1
Multiplexed
1
0
Mode Register 2 (MR2)
1
1
Reserved
Notes:
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
M3 M2 M1 M0
t RC_MRS
0
0
0
0
22,3
0
0
0
1
32
0
0
1
0
42
0
0
1
1
5
0
1
0
0
6
0
1
0
1
7
0
1
1
0
8
0
1
1
0
1
0
1
0
10
1
0
0
1
1
0
1
0
11
12
1
0
1
1
Reserved
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
9
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
2. BL8 not available in x36.
37
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
1.125Gb: x18, x36 TwinDie RLDRAM 3
Multiplexed Address Mode
Figure 15: MR1 Definition for Multiplexed Address Mode
Ax A18.......A13
Ay A18.......A13
A10 A9 A8
A5 A4 A3
A0
A4 A3
A9 A8
Address Bus
BA3 BA2 BA1 BA0
21 20 19 18 17-11
MRS Reserved
01 01
M19 M18
Mode Register Definition
0
Mode Register 0 (MR0)
0
1
Mode Register 1 (MR1)
0
1
0
Mode Register 2 (MR2)
1
1
1
Reserved
1
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
0
4 3
ODT
M5 DLL Reset
M10 M9 Burst Length
0
Notes:
10 9 8 7 6 5
BL Ref ZQe ZQ DLL
2
1
0
Mode Register (Mx)
Drive
M4 M3 M2
ODT
M1 M0 Output Drive
44.3 W
2
0
No
0
0
0
Off
0
0
1
4
1
Yes
0
0
1
40W
0
1
58 W
0
8
0
1
0
60W
1
0
Reserved
1
Reserved
M6 ZQ Calibration Selection
0
1
1
120W
1
1
Reserved
0
Short ZQ Calibration
1
0
0
Reserved
1
Long ZQ Calibration
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
0
M8
AREF Protocol
M7
0
Bank Address Control
0
Disabled - Default
1
Multibank
1
Enable
ZQ Calibration Enable
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
2. BL8 not available in x36.
38
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© 2013 Micron Technology, Inc. All rights reserved.
1.125Gb: x18, x36 TwinDie RLDRAM 3
Multiplexed Address Mode
Figure 16: MR2 Definition for Multiplexed Address Mode
Ax A18...A10
Ay A18...A10
A9 A8
A7...A5
A7...A5
A0
A4 A3
A4 A3
Address Bus
BA3 BA2 BA1 BA0
21 20 19 18
17-10
9-8
7-5
4 3 2
01 01 MRS Reserved DDP - ODT Reserved WRITE En
M19 M18
1 0
RTR
Mode Register (Mx)
Mode Register Definition
0
0
Mode Register 0 (MR0)
0
1
Mode Register 1 (MR1)
1
0
Mode Register 2 (MR2)
0
0
0-1-0-1 on all DQs
1
1
Reserved
0
1
Even DQs: 0-1-0-1 ; Odd DQs: 1-0-1-0
1
0
Reserved
1
1
Reserved
DDP - ODT
M9 M8
M1 M0
M4 M3
WRITE Protocol
0
0
X36 DDP
0
1
0
0
Single Bank
1
0
0
1
Dual Bank
1
1
Reserved
Reserved
X18 DDP
1
0
Quad Bank
1
1
Reserved
Note:
READ Training Register
M2 READ Training Register Enable
0
Normal RLDRAM Operation
1
READ Training Enabled
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
Table 22: Address Mapping in Multiplexed Address Mode
Address
Data
Width
Burst
Length
Ball
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
x36
2
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
X
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
4
x18
2
4
8
Note:
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
1. X = “Don’t Care”
39
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© 2013 Micron Technology, Inc. All rights reserved.
1.125Gb: x18, x36 TwinDie RLDRAM 3
Mirror Function
Mirror Function
The mirror function ball (MF) is a DC input used to create mirrored ballouts for simple
dual-loaded clamshell mounting. If the MF ball is tied LOW, the address and command
balls are in their true layout. If the MF ball is tied HIGH, the address and command balls
are mirrored around the central y-axis (column 7). The following table shows the ball
assignments when the MF ball is tied HIGH for a x18 device. Compare this table to Table 1 (page 9) to see how the address and command balls are mirrored. The same balls
are mirrored on the x36 device.
Table 23: 64 Meg x 18 Ball Assignments with MF Ball Tied HIGH
1
A
2
3
4
5
6
7
8
9
10
11
12
13
VSS
VDD
NC
VDDQ
NC
VREF
DQ7
VDDQ
DQ8
VDD
VSS
RESET#
B
VEXT
VSS
NC
VSSQ
NC
VDDQ
DM0
VDDQ
DQ5
VSSQ
DQ6
VSS
VEXT
C
VDD
NC
VDDQ
NC
VSSQ
NC
DK0#
DQ2
VSSQ
DQ3
VDDQ
DQ4
VDD
D
A13
VSSQ
NC
VDDQ
NC
VSSQ
DK0
VSSQ
QK0
VDDQ
DQ0
VSSQ
A11
E
VSS
CS0#1
VSSQ
NC
VDDQ
NC
MF
QK0#
VDDQ
DQ1
VSSQ
A0
VSS
A7
F
A9
A5
VDD
A4
A3
REF#
ZQ
WE#
A1
A2
VDD
CS1#1
G
VSS
A18
A8
VSS
BA0
VSS
CK#
VSS
BA1
VSS
A6
A15
VSS
H
A10
VDD
A12
A17
VDD
BA2
CK
BA3
VDD
A16
A14
VDD
A191
J
VDDQ
NC
VSSQ
NC
VDDQ
NC
VSS
QK1#
VDDQ
DQ9
VSSQ
QVLD
VDDQ
K
NC
VSSQ
NC
VDDQ
NC
VSSQ
DK1
VSSQ
QK1
VDDQ
DQ10
VSSQ
DQ11
L
VDD
NC
VDDQ
NC
VSSQ
NC
DK1#
DQ12
VSSQ
DQ13
VDDQ
DQ14
VDD
M
VEXT
VSS
NC
VSSQ
NC
VDDQ
DM1
VDDQ
DQ15
VSSQ
DQ16
VSS
VEXT
N
VSS
TCK
VDD
TDO
VDDQ
NC
VREF
DQ17
VDDQ
TDI
VDD
TMS
VSS
Note:
1. This table shows the mirrored pinout for the x18 device. The x36 device mirrors in the
same manner, but has the following changes: CS0# is CS#, CS1# is NF, A19 is NF, and DQs
are as shown in Table 2 (page 9).
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000
www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef84ebb323
1Gb_TwinDie_rldram3.pdf – Rev. F 8/14 EN
40
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.