288Mb: x18 SIO RLDRAM 2

288Mb: x18 SIO RLDRAM 2
Features
SIO RLDRAM 2
MT49H16M18C – 16 Meg x 18 x 8 banks
MT49H64M9C – 64 Meg x 9 x 8 banks
Features
Options
• Clock cycle timing
– 1.875ns @ tRC = 15ns
– 2.5ns @ tRC = 15ns
– 2.5ns @ tRC = 20ns
– 3.3ns @ tRC = 20ns
• Configuration
– 16 Meg x 18
• Operating temperature range
– Commercial (0° to +95°C)
– Industrial (TC = –40°C to +95°C; T A =
–40°C to +85°C)
• Package
– 144-ball μBGA
– 144-ball μBGA (Pb-free)
– 144-ball FBGA
– 144-ball FBGA (Pb-free)
• Revision
• 533 MHz DDR operation (1.067 Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock
frequency)
• Organization
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
– 16 Meg x 18 separate I/O
– 8 banks
Cyclic bank switching for maximum bandwidth
Reduced cycle time (15ns at 533 MHz)
Nonmultiplexed addresses (address multiplexing
option available)
SRAM-type interface
Programmable READ latency (RL), row cycle time,
and burst sequence length
Balanced READ and WRITE latencies in order to optimize data bus utilization
Data mask for WRITE commands
Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On-die DLL generates CK edge-aligned data and
output data clock signals
Data valid signal (QVLD)
32ms refresh (8K refresh for each bank; 64K refresh
command must be issued in total each 32ms)
HSTL I/O (1.5V or 1.8V nominal)
–Ω matched impedance outputs
2.5V V EXT, 1.8V V DD, 1.5V or 1.8V V DDQ I/O
On-die termination (ODT) RTT
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1
Note:
1
Marking
-18
-25E
-25
-33
16M18
None
IT
FM
BM
TR
SJ
:B
1. Not all options listed can be combined to
define an offered product. Use the part catalog search on micron.com for available offerings.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
288Mb: x18 SIO RLDRAM 2
Features
BGA Part Marking Decoder
Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s BGA Part Marking Decoder is available on Micron’s Web site at micron.com.
Figure 1: 288Mb RLDRAM 2 SIO Part Numbers
Example Part Number:
MT49H16M18CSJ-25 :B
-
Configuration I/O Package
MT49H
:
Speed Temp
Revision
I/O
Rev. A None
Common None
Separate
Rev. B
C
Commercial
16M18
Industrial
Package
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:B
Temperature
Configuration
16 Meg x 18
Rev.
144-ball μBGA
FM
Speed Grade
tCK = 1.8ns
-18
144-ball μBGA (Pb-free)
BM
-25
tCK = 2.5ns
144-ball FBGA
TR
-25E
tCK = 2.5ns
144-ball FBGA (Pb-free)
SJ
-33
tCK = 3.3ns
2
None
IT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
288Mb: x18 SIO RLDRAM 2
Features
Contents
General Description ......................................................................................................................................... 7
Functional Block Diagrams .............................................................................................................................. 8
Ball Assignments and Descriptions ................................................................................................................... 9
Package Dimensions ....................................................................................................................................... 11
Electrical Specifications – IDD .......................................................................................................................... 13
Absolute Maximum Ratings ............................................................................................................................ 16
AC and DC Operating Conditions .................................................................................................................... 16
Input Slew Rate Derating ................................................................................................................................ 19
Temperature and Thermal Impedance ............................................................................................................ 26
Commands .................................................................................................................................................... 28
MODE REGISTER SET (MRS) Command ......................................................................................................... 29
Configuration Tables .................................................................................................................................. 31
Burst Length (BL) ....................................................................................................................................... 31
Address Multiplexing .................................................................................................................................. 33
DLL RESET ................................................................................................................................................. 33
Drive Impedance Matching ........................................................................................................................ 33
On-Die Termination (ODT) ......................................................................................................................... 34
READ Command ............................................................................................................................................ 35
WRITE Command .......................................................................................................................................... 36
AUTO REFRESH (AREF) Command ................................................................................................................. 37
INITIALIZATION Operation ............................................................................................................................ 38
WRITE Operations .......................................................................................................................................... 41
READ Operations ........................................................................................................................................... 45
AUTO REFRESH Operation ............................................................................................................................. 50
Operations with On-Die Termination .............................................................................................................. 51
Multiplexed Address Mode .............................................................................................................................. 54
Command Description ............................................................................................................................... 54
Power-Up/Initialization Sequence .............................................................................................................. 55
Mode Register ............................................................................................................................................ 56
Address Mapping ....................................................................................................................................... 57
Configuration Tables .................................................................................................................................. 57
REFRESH Command in Multiplexed Address Mode ..................................................................................... 58
IEEE 1149.1 Serial Boundary Scan Test Access Port ........................................................................................... 62
Disabling the Serial Boundary Scan Test Access Port .................................................................................... 62
Test Access Port (TAP) ..................................................................................................................................... 62
Test Clock (TCK) ......................................................................................................................................... 62
Test Mode Select (TMS) .............................................................................................................................. 62
Test Data-In (TDI) ...................................................................................................................................... 63
Test Data-Out (TDO) .................................................................................................................................. 63
TAP Controller ................................................................................................................................................ 63
Test-Logic-Reset ......................................................................................................................................... 63
Run-Test/Idle ............................................................................................................................................. 63
Select-DR-Scan .......................................................................................................................................... 63
Capture-DR ................................................................................................................................................ 63
Shift-DR ..................................................................................................................................................... 63
Exit1-DR, Pause-DR, and Exit2-DR .............................................................................................................. 64
Update-DR ................................................................................................................................................. 64
Instruction Register States .......................................................................................................................... 64
TAP Reset ....................................................................................................................................................... 65
TAP Registers ................................................................................................................................................. 65
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288Mb: x18 SIO RLDRAM 2
Features
Instruction Register ....................................................................................................................................
Bypass Register ..........................................................................................................................................
Boundary Scan Register ..............................................................................................................................
Identification (ID) Register ..........................................................................................................................
TAP Instruction Set .........................................................................................................................................
EXTEST ......................................................................................................................................................
IDCODE .....................................................................................................................................................
SAMPLE/PRELOAD ....................................................................................................................................
CLAMP ......................................................................................................................................................
High-Z .......................................................................................................................................................
BYPASS ......................................................................................................................................................
Reserved for Future Use ..............................................................................................................................
Revision History .............................................................................................................................................
Rev. I – 06/01/15 .........................................................................................................................................
Rev. H – 4/11 ..............................................................................................................................................
Rev. G – 04/11 .............................................................................................................................................
Rev. F – 06/09 .............................................................................................................................................
Rev. E – 05/09 .............................................................................................................................................
Rev. D – 06/08 .............................................................................................................................................
Rev. C – 06/08 .............................................................................................................................................
Rev. B – 07/07 .............................................................................................................................................
Rev. A – 05/07 .............................................................................................................................................
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65
65
66
66
67
67
67
67
68
68
68
68
73
73
73
73
73
73
73
73
73
74
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288Mb: x18 SIO RLDRAM 2
Features
List of Figures
Figure 1: 288Mb RLDRAM 2 SIO Part Numbers ................................................................................................. 2
Figure 2: State Diagram ................................................................................................................................... 7
Figure 3: 16 Meg x 18 Functional Block Diagram ............................................................................................... 8
Figure 4: 144-Ball μBGA ................................................................................................................................. 11
Figure 5: 144-Ball FBGA ................................................................................................................................. 12
Figure 6: Clock Input ..................................................................................................................................... 18
Figure 7: Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate ........................................................................... 22
Figure 8: Example Temperature Test Point Location ........................................................................................ 27
Figure 9: Mode Register Set ............................................................................................................................ 29
Figure 10: Mode Register Definition in Nonmultiplexed Address Mode ............................................................ 30
Figure 11: Read Burst Lengths ........................................................................................................................ 32
Figure 12: On-Die Termination-Equivalent Circuit .......................................................................................... 34
Figure 13: READ Command ........................................................................................................................... 35
Figure 14: WRITE Command ......................................................................................................................... 36
Figure 15: AUTO REFRESH Command ........................................................................................................... 37
Figure 16: Power-Up/Initialization Sequence ................................................................................................. 39
Figure 17: Power-Up/Initialization Flow Chart ................................................................................................ 40
Figure 18: WRITE Burst ................................................................................................................................. 41
Figure 19: Consecutive WRITE-to-WRITE ....................................................................................................... 42
Figure 20: WRITE-to-READ ............................................................................................................................ 43
Figure 21: WRITE – DM Operation ................................................................................................................. 44
Figure 22: Basic READ Burst Timing ............................................................................................................... 45
Figure 23: Consecutive READ Bursts (BL = 2) .................................................................................................. 46
Figure 24: Consecutive READ Bursts (BL = 4) .................................................................................................. 46
Figure 25: READ-to-WRITE ............................................................................................................................ 47
Figure 26: READ/WRITE Interleave ................................................................................................................ 48
Figure 27: Read Data Valid Window for x18 Device .......................................................................................... 49
Figure 28: AUTO REFRESH Cycle ................................................................................................................... 50
Figure 29: READ Burst with ODT .................................................................................................................... 51
Figure 30: READ-NOP-READ with ODT .......................................................................................................... 52
Figure 31: READ-to-WRITE with ODT ............................................................................................................ 53
Figure 32: Command Description in Multiplexed Address Mode ..................................................................... 54
Figure 33: Power-Up/Initialization Sequence in Multiplexed Address Mode ..................................................... 55
Figure 34: Mode Register Definition in Multiplexed Address Mode .................................................................. 56
Figure 35: Burst REFRESH Operation with Multiplexed Addressing ................................................................. 58
Figure 36: Consecutive WRITE Bursts with Multiplexed Addressing ................................................................. 58
Figure 37: WRITE-to-READ with Multiplexed Addressing ................................................................................ 59
Figure 38: Consecutive READ Bursts with Multiplexed Addressing ................................................................... 60
Figure 39: READ-to-WRITE with Multiplexed Addressing ................................................................................ 61
Figure 40: TAP Controller State Diagram ......................................................................................................... 64
Figure 41: TAP Controller Block Diagram ........................................................................................................ 64
Figure 42: JTAG Operation – Loading Instruction Code and Shifting Out Data .................................................. 69
Figure 43: TAP Timing ................................................................................................................................... 69
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288Mb: x18 SIO RLDRAM 2
Features
List of Tables
Table 1: 16 Meg x 18 Ball Assignments (Top View) 144-Ball BGA ........................................................................ 9
Table 2: Ball Descriptions ................................................................................................................................ 9
Table 3: IDD Operating Conditions and Maximum Limits – Rev. A .................................................................... 13
Table 4: IDD Operating Conditions and Maximum Limits – Rev. B .................................................................... 14
Table 5: Absolute Maximum Ratings .............................................................................................................. 16
Table 6: DC Electrical Characteristics and Operating Conditions ..................................................................... 16
Table 7: Input AC Logic Levels ........................................................................................................................ 17
Table 8: Differential Input Clock Operating Conditions ................................................................................... 18
Table 9: Address and Command Setup and Hold Derating Values .................................................................... 19
Table 10: Data Setup and Hold Derating Values .............................................................................................. 21
Table 11: Capacitance – μBGA ........................................................................................................................ 22
Table 12: Capacitance – FBGA ........................................................................................................................ 22
Table 13: AC Electrical Characteristics ............................................................................................................ 23
Table 14: Temperature Limits ......................................................................................................................... 26
Table 15: Thermal Impedance ........................................................................................................................ 27
Table 16: Description of Commands .............................................................................................................. 28
Table 17: Command Table ............................................................................................................................. 28
Table 18: Cycle Time and READ/WRITE Latency Configuration Table .............................................................. 31
Table 19: Address Widths at Different Burst Lengths ....................................................................................... 32
Table 20: On-Die Termination DC Parameters ................................................................................................ 34
Table 21: Address Mapping in Multiplexed Address Mode ............................................................................... 57
Table 22: Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode .............................. 57
Table 23: Instruction Codes ........................................................................................................................... 67
Table 24: TAP Input AC Logic Levels ............................................................................................................... 70
Table 25: TAP AC Electrical Characteristics ..................................................................................................... 70
Table 26: TAP DC Electrical Characteristics and Operating Conditions ............................................................. 71
Table 27: Identification Register Definitions ................................................................................................... 71
Table 28: Scan Register Sizes .......................................................................................................................... 71
Table 29: Boundary Scan (Exit) Order ............................................................................................................. 71
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288Mb: x18 SIO RLDRAM 2
General Description
General Description
The Micron® reduced latency DRAM (RLDRAM®) 2 is a high-speed memory device designed for high bandwidth data storage—telecommunications, networking, and cache
applications, etc. The chip’s 8-bank architecture is optimized for sustainable highspeed operation.
The DDR separate I/O interface transfers two data words per clock cycle at the I/O balls.
The read port has dedicated data outputs to support READ operations, while the write
port has dedicated input balls to support WRITE operations. Output data is referenced
to the free-running output data clock. This architecture eliminates the need for highspeed bus turnaround.
Commands, addresses, and control signals are registered at every positive edge of the
differential input clock, while input data is registered at both positive and negative
edges of the input data clock(s).
Read and write accesses to the device are burst-oriented. The burst length (BL) is programmable from 2, 4, or 8 by setting the mode register.
The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output
drivers.
Bank-scheduled refresh is supported with the row address generated internally.
The μBGA 144-ball package is used to enable ultra high-speed data transfer rates and a
simple upgrade path from early generation devices.
Figure 2: State Diagram
Initialization
sequence
DSEL/NOP
WRITE
READ
MRS
AREF
Automatic sequence
Command sequence
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288Mb: x18 SIO RLDRAM 2
Functional Block Diagrams
Functional Block Diagrams
Figure 3: 16 Meg x 18 Functional Block Diagram
ZQ
ZQ CAL
Output drivers
ODT control
CK
CK#
Command
decode
CS#
REF#
WE#
Control
logic
VTT
Refresh
counter
Mode register
18
13
Rowaddress
MUX
13
13
Bank 0
row
address
latch
8,192
and
decoder
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
RTT
ODT control
CK/CK#
Bank 0
memory
array
(8192 x 32 x 8 x 18)2
DLL
ZQ CAL
144
SENSEamplifiers
AMPLIFIERS
Sense
n
READ
logic n
18
18
(0 ....17)
18
Drivers
Q
latch
Q[17:0]
QVLD
QK[1:0]/QK#[1:0]
4
QK/QK#
generator
8192
144
A[19:0]1
BA[2:0]
23
Address
register
Bank
control
logic
3
1
2
I/O gating
DQM mask logic
8
8
8
1
7
Columnaddress
counter/
latch
Column
decoder
WRITE
FIFO
and
drivers
18
n
n
18
18
Input
logic
144
5
DK/DK#
2
32
D[17:0]
VTT
CLK
in
1
7
RCVRS
RTT
1
2
ODT control
DM
Notes:
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1. Examples for BL = 2; column address will be reduced with an increase in burst length.
2. The “8” = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ
logic).
8
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288Mb: x18 SIO RLDRAM 2
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Table 1: 16 Meg x 18 Ball Assignments (Top View) 144-Ball BGA
1
2
3
4
A
VREF
VSS
VEXT
VSS
5
6
7
8
9
10
11
12
VSS
VEXT
TMS
TCK
B
VDD
D4
Q4
VSSQ
VSSQ
Q0
D0
VDD
C
VTT
D5
Q5
VDDQ
VDDQ
Q1
D1
VTT
D
A221
D6
Q6
VSSQ
VSSQ
QK0#
QK0
VSS
E
A212
D7
Q7
VDDQ
VDDQ
Q2
D2
A202
F
A5
D8
Q8
VSSQ
VSSQ
Q3
D3
QVLD
G
A8
A6
A7
VDD
VDD
A2
A1
A0
H
BA2
A9
VSS
VSS
VSS
VSS
A4
A3
J
NF3
NF3
VDD
VDD
VDD
VDD
BA0
CK
K
DK
DK#
VDD
VDD
VDD
VDD
BA1
CK#
L
REF#
CS#
VSS
VSS
VSS
VSS
A14
A13
M
WE#
A16
A17
VDD
VDD
A12
A11
A10
N
A18
D14
Q14
VSSQ
VSSQ
Q9
D9
A19
P
A15
D15
Q15
VDDQ
VDDQ
Q10
D10
DM
R
VSS
QK1
QK1#
VSSQ
VSSQ
Q11
D11
VSS
T
VTT
D16
Q16
VDDQ
VDDQ
Q12
D12
VTT
U
VDD
D17
Q17
VSSQ
VSSQ
Q13
D13
VDD
V
VREF
ZQ
VEXT
VSS
VSS
VEXT
TDO
TDI
Notes:
1. Reserved for future use. This may be optionally connected to GND.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may be optionally connected to GND.
3. No function. This signal is internally connected and has parasitic characteristics of a clock
input signal. This may be optionally connected to GND.
Table 2: Ball Descriptions
Symbol
Type
Description
A0–A19
Input
Address inputs: A0–A19 define the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are
sampled at the rising edge of CK.
BA0–BA2
Input
Bank address inputs: Select to which internal bank a command is being applied.
CK, CK#
Input
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on
the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
CS#
Input
Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When
the command decoder is disabled, new commands are ignored, but internal operations continue.
D0–D17
Input
Data input: The D signals form the 18-bit input data bus. During WRITE commands, the data is
sampled at both edges of DK.
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288Mb: x18 SIO RLDRAM 2
Ball Assignments and Descriptions
Table 2: Ball Descriptions (Continued)
Symbol
Type
Description
DK, DK#
Input
Input data clock: DK and DK# are the differential input data clocks. All input data is referenced to both edges of DK. DK# is ideally 180 degrees out of phase with DK. D0–D17 are referenced to DK and DK#.
DM
Input
Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked
when DM is sampled HIGH. DM is sampled on both edges of DK. Tie signal to ground if not
used.
TCK
Input
IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used.
TMS, TDI
Input
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not
used.
WE#, REF#
Input
Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with
CS#) the command to be executed.
Q0–Q17
Output
Data output: The Q signals form the 18-bit output data bus. During READ commands, the data is referenced to both edges of QK.
QKx, QKx#
Output
Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are freerunning, and during READs are edge-aligned with data output from the device. QKx# is ideally
180 degrees out of phase with QKx. QK0 and QK0# are aligned with Q0–Q8 and QK1 and QK1#
are aligned with Q9–Q17.
QVLD
Output
Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and
QKx#.
TDO
Output
IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function is not used.
ZQ
Reference External impedance (25–60Ω
ΩThis signal is used to tune the device outputs to the system data bus impedance. Q output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to ground. Connecting ZQ to GND invokes the minimum impedance mode. Connecting ZQ
to VDD invokes the maximum impedance mode. Refer to figure: Mode Register Definition in
Nonmultiplexed Address Mode to activate this function.
VDD
Supply
Power supply: Nominally 1.8V. For range, see table: DC Electrical Characteristics and Operating Conditions.
VDDQ
Supply
DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity. For range, see table: DC Electrical Characteristics and Operating Conditions.
VEXT
Supply
Power supply: Nominally, 2.5V. For range, see table: DC Electrical Characteristics and Operating Conditions.
VREF
Supply
Input reference voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
VSS
Supply
Ground.
VSSQQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
VTT
Supply
Power supply: Isolated termination supply. Nominally, VDDQ/2. For range, see table: DC Electrical Characteristics and Operating Conditions.
A20–A21
–
Reserved for future use: These signals are internally connected and can be treated as address
inputs.
A22
–
Reserved for future use: This signal is not connected and can be connected to ground.
NF
–
No function: These balls can be connected to ground.
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Package Dimensions
Package Dimensions
Figure 4: 144-Ball μBGA
10.6 CTR
10º TYP
Seating
plane
A
0.12 A
144X Ø0.51
Solder ball material:
Eutectic (62% Sn,
36% Pb, 2% Ag) or
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls post-reflow
on Ø0.39 SMD
ball pads.
0.73 ±0.1
0.49 ±0.05
12 11 10 9
Ball A1 ID
4 3 2 1
Ball A1 ID
A
B
C
D
E
F
G
H
J
17 CTR
K
18.5 ±0.1
18.1 CTR
L
M
N
P
R
T
U
1 TYP
V
0.8 TYP
1.2 MAX
0.34 MIN
8.8 CTR
11 ±0.1
Note:
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1. All dimensions are in millimeters.
11
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288Mb: x18 SIO RLDRAM 2
Package Dimensions
Figure 5: 144-Ball FBGA
Seating plane
A
144X Ø0.55
Dimensions apply
to solder balls postreflow on Ø0.40
NSMD ball pads.
0.12 A
Ball A1 ID
(covered by SR)
12 11 10
9
4
3
2
Ball A1 ID
1
A
B
C
D
E
F
G
H
18.5 ±0.1
J
K
17.0
CTR
L
M
N
P
R
T
U
1.0 TYP
V
1.1 ±0.1
0.8 TYP
8.8 CTR
0.3 MIN
11 ±0.1
Notes:
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1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
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288Mb: x18 SIO RLDRAM 2
Electrical Specifications – IDD
Electrical Specifications – IDD
Table 3: IDD Operating Conditions and Maximum Limits – Rev. A
Description
Conditions
Symbol
-25
-33
-5
Unit
Standby current
tCK
ISB1 (VDD)
48
48
48
mA
Active standby
current
tCK
= MIN, CS# = 1; No commands; Bank
address incremented and half address/
data change once every 4 clock cycles
Operational current
BL = 2; tCK = MIN; tRC = MIN; 1 bank active; Half address changes once per tRC;
Read followed by write sequence
Operational current
BL = 4; tCK = MIN; tRC = MIN; 1 bank active; Half address changes once per tRC;
Read followed by write sequence
Operational current
BL = 8; tCK = MIN; tRC = MIN; 1 bank active; Half address changes once per tRC;
Read followed by write sequence
Burst refresh current
tCK
Distributed refresh current
tCK
= MIN;
= MIN; Single bank refresh; Half address/data toggle
Operating burst
write current example
BL = 2; tCK = MIN; tRC = MIN; Cyclic
bank access; Half of address bits change
every clock cycle; Continuous data
Operating burst
write current example
BL = 4; tCK = MIN; tRC = MIN; Cyclic
bank access; Half of address bits change
every 2 clock cycles; Continuous data
Operating burst
write current example
BL = 8; tCK = MIN; tRC = MIN; Cyclic
bank access; Half of address bits change
every 4 clock cycles; Continuous data
Operating burst
read current example
= Idle; All banks idle; No inputs toggling
= MIN; tRC = MIN; Cyclic bank refresh; Data inputs are switching
tRC
ISB1 (VEXT)
26
26
26
ISB2 (VDD)
288
233
189
ISB2 (VEXT)
26
26
26
IDD1 (VDD)
348
305
255
IDD1 (VEXT)
41
36
36
IDD2 (VDD)
362
319
269
IDD2 (VEXT)
48
42
42
IDD3 (VDD)
408
368
286
IDD3 (VEXT)
55
48
48
IREF1 (VDD)
785
615
430
IREF1 (VEXT)
133
111
105
IREF2 (VDD)
325
267
221
IREF2 (VEXT)
48
42
42
IDD2W (VDD)
970
819
597
IDD2W (VEXT)
100
90
69
IDD4W (VDD)
779
609
439
IDD4W (VEXT)
88
77
63
IDD8W (VDD)
668
525
364
IDD8W (VEXT)
60
51
40
BL = 2; Cyclic bank access; Half of address bits change every clock cycle;
Measurement is taken during continuous READ
IDD2R (VDD) x18
860
735
525
IDD2R (VEXT)
100
90
69
Operating burst
read current example
BL = 4; Cyclic bank access; Half of address bits change every 2 clocks; Measurement is taken during continuous
READ
IDD4R (VDD) x18
680
525
380
IDD4R (VEXT)
88
77
63
Operating burst
read current example
BL = 8; Cyclic bank access; Half of address bits change every 4 clock cycles;
Measurement is taken during continuous READ
IDD8R (VDD) x18
570
450
310
IDD8R (VEXT)
60
51
40
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13
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Electrical Specifications – IDD
Table 4: IDD Operating Conditions and Maximum Limits – Rev. B
Description
Conditions
Symbol
-18
-25E
-25
-33
Unit
Standby current
tCK
ISB1 (VDD)
55
55
55
55
mA
ISB1 (VEXT)
5
5
5
5
Active standby
current
tCK
= Idle; All banks idle; No inputs toggling
= MIN, CS# = 1; No commands; Bank
address incremented and half address/
data change once every 4 clock cycles
ISB2 (VDD)
250
215
215
190
ISB2 (VEXT)
5
5
5
5
Operational cur- BL = 2; tCK = MIN; tRC = MIN; 1 bank active; Half address changes once per tRC;
rent
Read followed by write sequence
IDD1 (VDD)
310
285
260
225
IDD1 (VEXT)
10
10
10
10
IDD2 (VDD)
315
290
260
220
IDD2 (VEXT)
10
10
10
10
IDD3 (VDD)
330
305
275
230
IDD3 (VEXT)
15
15
15
15
IREF1 (VDD)
660
540
530
430
Operational cur- BL = 4; tCK = MIN; tRC = MIN; 1 bank active; Half address changes once per tRC;
rent
Read followed by write sequence
Operational cur- BL = 8; tCK = MIN; tRC = MIN; 1 bank active; Half address changes once per tRC;
rent
Read followed by write sequence
Burst refresh
current
tCK
= MIN; tRC = MIN; Cyclic bank refresh; Data inputs are switching
Distributed refresh current
tCK
= MIN; tRC = MIN; Single bank refresh; Half address/data toggle
tCK
tRC
IREF1 (VEXT)
45
30
30
25
IREF2 (VDD)
295
265
250
215
IREF2 (VEXT)
10
10
10
10
= MIN;
= MIN; Cyclic bank
Operating burst BL = 2;
write current ex- access; Half of address bits change every
clock cycle; Continuous data
ample
IDD2W (VDD)
830
655
655
530
IDD2W (VEXT)
40
35
35
30
Operating burst BL = 4; tCK = MIN; tRC = MIN; Cyclic bank
write current ex- access; Half of address bits change every
2 clock cycles; Continuous data
ample
IDD4W (VDD)
580
465
465
385
IDD4W (VEXT)
25
20
20
20
IDD8W (VDD)
445
370
370
305
IDD8W (VEXT)
25
20
20
20
Operating burst BL = 2; Cyclic bank access; Half of address IDD2R (VDD) x18
read current ex- bits change every clock cycle; MeasureIDD2R (VEXT)
ment is taken during continuous READ
ample
805
640
640
515
40
35
35
30
Operating burst BL = 4; Cyclic bank access; Half of address IDD4R (VDD) x18
read current ex- bits change every 2 clocks; Measurement
IDD4R (VEXT)
is taken during continuous READ
ample
545
440
440
365
25
20
20
20
Operating burst BL = 8; Cyclic bank access; Half of address IDD8R (VDD) x18
read current ex- bits change every 4 clock cycles; MeasIDD8R (VEXT)
urement is taken during continuous
ample
READ
410
335
335
280
25
20
20
20
Operating burst BL = 8; tCK = MIN; tRC = MIN; Cyclic bank
write current ex- access; Half of address bits change every
4 clock cycles; Continuous data
ample
Notes:
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1. IDD specifications are tested after the device is properly initialized. +0°C ≤ Tc ≤ +95°C;
+1.7V ≤ VDD ≤ +1.9V, +2.38V ≤ VEXT ≤ +2.63V, +1.4V ≤ VDDQ ≤ VDD, VREF = VDDQ/2.
2. tCK = tDK = MIN; tRC = MIN.
3. Input slew rate is specified in the Input AC Logic Levels table.
4. Definitions for IDD conditions:
4a. LOW is defined as VIN ≤ VIL(AC) MAX.
14
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Electrical Specifications – IDD
5.
6.
7.
8.
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4b. HIGH is defined as VIN ≥ VIH(AC) MAX.
4c. Stable is defined as inputs remaining at a HIGH or LOW level.
4d. Floating is defined as inputs at VREF = VDDQ/2.
4e. Continuous is defined as half the D or Q signals changing between HIGH and LOW
every half clock cycle (twice per clock).
4f. Continuous address is defined as half the address signals changing between HIGH
and LOW every clock cycle (once per clock).
4g. Sequential bank access is defined as the bank address incrementing by one every
tRC.
4h. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2, this is every clock; for BL = 4, this is every other clock; and for BL
= 8, this is every fourth clock.
CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions more than once per clock cycle.
IDD parameters are specified with ODT disabled.
Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at
nominal reference/supply voltage levels, but the related specifications and device operations are tested for the full voltage range specified.
IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input
timing is still referenced to VREF (or to the crossing point for CK/CK#). Parameter specifications are tested for the specified AC input levels under normal use conditions. The
minimum slew rate for the input signals used to test the device is 2 V/ns in the range
between VIL(AC) and VIH(AC).
15
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Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 5: Absolute Maximum Ratings
Parameter
Min
Max
Units
I/O voltage
–0.3
VDDQ + 0.3
V
Voltage on VEXT supply relative to VSS
–0.3
+2.8
V
Voltage on VDD supply relative to VSS
–0.3
+2.1
V
Voltage on VDDQ supply relative to VSS
–0.3
+2.1
V
AC and DC Operating Conditions
Table 6: DC Electrical Characteristics and Operating Conditions
Description
Conditions
Symbol
Min
Max
Units
Supply voltage
–
VEXT
2.38
2.63
V
Supply voltage
–
VDD
1.7
1.9
V
Notes
2
Isolated output buffer supply
–
VDDQ
1.4
VDD
V
2, 3
Reference voltage
–
VREF
0.49 × VDDQ
0.51 × VDDQ
V
4, 5, 6
Termination voltage
–
VTT
0.95 × VREF
1.05 × VREF
V
7, 8
Input high (logic 1) voltage
–
VIH
VREF + 0.1
VDDQ + 0.3
V
2
VSSQ - 0.3
VREF - 0.1
–
VIL
V
2
Output high current
VOH = VDDQ/2
IOH
(VDDQ/2)/
(VDDQ/2)/
(1.15 × RQ/5) (0.85 × RQ/5)
A
9, 10, 11
Output low current
VOL = VDDQ/2
IOL
(VDDQ/2)/
(VDDQ/2)/
(1.15 × RQ/5) (0.85 × RQ/5)
A
9, 10, 11
0V ≤ VIN ≤ VDD
ILC
Input low (logic 0) voltage
Clock input leakage current
–5
5
μA
Input leakage current
0V ≤ VIN ≤ VDD
ILI
–5
5
μA
Output leakage current
0V ≤ VIN ≤ VDDQ
ILO
–5
5
μA
–
IREF
–5
5
μA
Reference voltage current
Notes:
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1. Applies to the entire table: Unless otherwise noted: +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤
+1.9V
2. All voltages referenced to VSS (GND).
3. Overshoot: VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2. Undershoot: VIL(AC) ≥ –0.5V for t ≤ tCK/2.
During normal operation, VDDQ must not exceed VDD. Control input signals may not
have pulse widths less than tCK/2 or operate at frequencies exceeding tCK (MAX).
4. VDDQ can be set to a nominal 1.5V ± 0.1V or 1.8V ± 0.1V supply.
5. Typically the value of VREF is expected to be 0.5 x VDDQ of the transmitting device. VREF is
expected to track variations in VDDQ.
6. Peak-to-peak AC noise on VREF must not exceed ±2% VREF(DC).
16
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AC and DC Operating Conditions
7. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the
DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed
±2% of the DC value. Thus, from VDDQ/2, VREF is allowed ±2% VDDQ/2 for DC error and
an additional ±2% VDDQ/2 for AC noise. This measurement is to be taken at the nearest
VREF bypass capacitor.
8. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
9. On-die termination may be selected using mode register bit 9 (see figure: Mode Register
Definition in Nonmultiplexed Address Mode). A resistance RTT from each data input signal to the nearest VTT can be enabled. RTT –Ω at 95°C TC.
10. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from
the device, IOL flows into the device.
11. If MRS bit A8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external impedance matched resistor.
12. For VOL and VOH, refer to the RLDRAM 2, HSPICE, or IBIS driver models.
Table 7: Input AC Logic Levels
Description
Symbol
Min
Max
Input high (logic 1) voltage
VIH
VREF + 0.2
–
V
Input low (logic 0) voltage
VIL
–
VREF - 0.2
V
Notes:
Units
1. Unless otherwise noted: +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V
2. All voltages referenced to VSS (GND).
3. The AC and DC input level specifications are as defined in the HSTL standard (that is, the
receiver will effectively switch as a result of the signal crossing the AC input level, and
will remain in that state as long as the signal does not ring back above [below] the DC
input LOW [HIGH] level).
4. The minimum slew rate for the input signals used to test the device is 2 V/ns in the
range between Vil(AC) and VIH(AC) (see figure below).
VDDQ
VIH(AC) MIN
VSWING
VIL(AC) MAX
GND
Rise time:
2 V/ns
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Fall time:
2 V/ns
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AC and DC Operating Conditions
Table 8: Differential Input Clock Operating Conditions
Notes 1–5 apply to the entire table.
Parameter/Condition
Symbol
Min
Max
Units
Notes
Clock input voltage level: CK and CK#
VIN(DC)
–0.3
VDDQ + 0.3
V
Clock input differential voltage: CK and CK#
VID(DC)
0.2
VDDQ + 0.6
V
5
Clock input differential voltage: CK and CK#
VID(AC)
0.4
VDDQ + 0.6
V
5
Clock input crossing point voltage: CK and CK#
VIX(AC)
VDDQ/2 - 0.15
VDDQ/2 + 0.15
V
6
Notes:
Unless otherwise noted: +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V
DKx and DKx# have the same requirements as CK and CK#.
All voltages referenced to VSS (GND).
The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which
CK and CK# cross. The input reference level for signals other than CK/CK# is VREF.
5. CK and CK# input slew rate must be ≥2 V/ns (≥4 V/ns if measured differentially).
6. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
7. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track
variations in the DC level of the same.
1.
2.
3.
4.
Figure 6: Clock Input
VIN(DC) MAX
Maximum clock level
CK#
VDDQ/2 + 0.15
X
VIX(AC) MAX
VDDQ/2
1
VDDQ/2 - 0.15
X
VID(DC)2
VID(AC)3
VIX(AC) MIN
CK
Minimum clock level
VIN(DC) MIN
Notes:
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1.
2.
3.
4.
CK and CK# must cross within this region.
CK and CK# must meet at least VID(DC) MIN when static and centered around VDDQ/2.
Minimum peak-to-peak swing.
It is a violation to tri-state CK and CK# after the part is initialized.
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Input Slew Rate Derating
Input Slew Rate Derating
The following two tables define the address, command, and data setup and hold derating values. These values are added to the default tAS/tCS/tDS and tAH/tCH/tDH specifications when the slew rate of any of these input signals is less than the 2 V/ns the nominal setup and hold specifications are based upon.
To determine the setup and hold time needed for a given slew rate, add the tAS/tCS default specification to the “tAS/tCS V REF to CK/CK# Crossing” and the tAH/tCH default
specification to the “tAH/tCH CK/CK# Crossing to V REF” derated values on the Address
and Command Setup and Hold Derating Values table. The derated data setup and hold
values can be determined in a like manner using the “tDS V REF to CK/CK# Crossing”
and “tDH to CK/CK# Crossing to V REF” values on the Data Setup and Hold Derating Values table. The derating values on the Address and Command Setup and Hold Derating
Values table and the Data Setup and Hold Derating Values table apply to all speed
grades.
The setup times on the Address and Command Setup and Hold Derating Values table
and the Data Setup and Hold Derating Values table represent a rising signal. In this case,
the time from which the rising signal crosses V IH(AC) min to the CK/CK# cross point is
static and must be maintained across all slew rates. The derated setup timing represents
the point at which the rising signal crosses V REF(DC) to the CK/CK# cross point. This derated value is calculated by determining the time needed to maintain the given slew
rate and the delta between V IH(AC) MIN and the CK/CK# cross point. The setup values in
the Address and Command Setup and Hold Derating Values table and the Data Setup
and Hold Derating Values table are also valid for falling signals (with respect to V IH(AC)
max and the CK/CK# cross point).
The hold times in the Address and Command Setup and Hold Derating Values table and
the Data Setup and Hold Derating Values table represent falling signals. In this case, the
time from which the falling signal crosses the CK/CK# cross point to when the signal
crosses V IH(DC) MIN is static and must be maintained across all slew rates. The derated
hold timing represents the delta between the CK/CK# cross point to when the falling
signal crosses V REF(DC). This derated value is calculated by determining the time needed
to maintain the given slew rate and the delta between the CK/CK# cross point and
VIH(DC). The hold values in the Address and Command Setup and Hold Derating Values
table and the Data Setup and Hold Derating Values table are also valid for rising signals
(with respect to V IL(DC) max and the CK and CK# cross point).
Table 9: Address and Command Setup and Hold Derating Values
Command/
Address Slew
Rate (V/ns)
tAS/tCS
tAS/tCS
VREF to
CK/CK# Crossing
VIH(AC) Min
to CK/CK# Crossing
tAH/tCH
CK/CK#
Crossing to VREF
CK/CK#
Crossing to VIH(DC)
Min
Units
tAH/tCH
CK, CK# Differential Slew Rate: 2.0 V/ns
2.0
0
–100
0
–50
ps
1.9
5
–100
3
–50
ps
1.8
11
–100
6
–50
ps
1.7
18
–100
9
–50
ps
1.6
25
–100
13
–50
ps
1.5
33
–100
17
–50
ps
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Input Slew Rate Derating
Table 9: Address and Command Setup and Hold Derating Values (Continued)
Command/
Address Slew
Rate (V/ns)
tAS/tCS
tAH/tCH
VREF to
CK/CK# Crossing
VIH(AC) Min
to CK/CK# Crossing
CK/CK#
Crossing to VREF
CK/CK#
Crossing to VIH(DC)
Min
Units
1.4
43
–100
22
–50
ps
1.3
54
–100
27
–50
ps
1.2
67
–100
34
–50
ps
1.1
82
–100
41
–50
ps
1.0
100
–100
50
–50
ps
tAS/tCS
tAH/tCH
CK, CK# Differential Slew Rate: 1.5 V/ns
2.0
30
–70
30
–20
ps
1.9
35
–70
33
–20
ps
1.8
41
–70
36
–20
ps
1.7
48
–70
39
–20
ps
1.6
55
–70
43
–20
ps
1.5
63
–70
47
–20
ps
1.4
73
–70
52
–20
ps
1.3
84
–70
57
–20
ps
1.2
97
–70
64
–20
ps
1.1
112
–70
71
–20
ps
1.0
130
–70
80
–20
ps
CK, CK# Differential Slew Rate: 1.0 V/ns
2.0
60
–40
60
10
ps
1.9
65
–40
63
10
ps
1.8
71
–40
66
10
ps
1.7
78
–40
69
10
ps
1.6
85
–40
73
10
ps
1.5
93
–40
77
10
ps
1.4
103
–40
82
10
ps
1.3
114
–40
87
10
ps
1.2
127
–40
94
10
ps
1.1
142
–40
101
10
ps
1.0
160
–40
110
10
ps
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Input Slew Rate Derating
Table 10: Data Setup and Hold Derating Values
Data Slew Rate
(V/ns)
tDS
VREF to
CK/CK# Crossing
tDS
VIH(AC) Min to
CK/CK# Crossing
tDH
CK/CK# Cross- tDH CK/CK# Crossing to VREF
ing to VIH(DC) Min
Units
DK, DK# Differential Slew Rate: 2.0 V/ns
2.0
0
–100
0
–50
ps
1.9
5
–100
3
–50
ps
1.8
11
–100
6
–50
ps
1.7
18
–100
9
–50
ps
1.6
25
–100
13
–50
ps
1.5
33
–100
17
–50
ps
1.4
43
–100
22
–50
ps
1.3
54
–100
27
–50
ps
1.2
67
–100
34
–50
ps
1.1
82
–100
41
–50
ps
1.0
100
–100
50
–50
ps
DK, DK# Differential Slew Rate: 1.5 V/ns
2.0
30
–70
30
–20
ps
1.9
35
–70
33
–20
ps
1.8
41
–70
36
–20
ps
1.7
48
–70
39
–20
ps
1.6
55
–70
43
–20
ps
1.5
63
–70
47
–20
ps
1.4
73
–70
52
–20
ps
1.3
84
–70
57
–20
ps
1.2
97
–70
64
–20
ps
1.1
112
–70
71
–20
ps
1.0
130
–70
80
–20
ps
DK, DK# Differential Slew Rate: 1.0 V/ns
2.0
60
–40
60
10
ps
1.9
65
–40
63
10
ps
1.8
71
–40
66
10
ps
1.7
78
–40
69
10
ps
1.6
85
–40
73
10
ps
1.5
93
–40
77
10
ps
1.4
103
–40
82
10
ps
1.3
114
–40
87
10
ps
1.2
127
–40
94
10
ps
1.1
142
–40
101
10
ps
1.0
160
–40
110
10
ps
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Input Slew Rate Derating
Figure 7: Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate
VIH(AC) MIN
VREF to DC VREF to DC
region
region
VSWING (MAX)
VREF to AC
region
VREF to AC
region
VDDQ
VIH(DC) MIN
VREF(DC)
VIL(DC) MAX
VIL(AC) MAX
VSSQ
Table 11: Capacitance – μBGA
Description
Symbol
Conditions
Min
Address/control input capacitance
CI
2.0
pF
CO
TA = 25°C; f = 100 MHz
VDD = VDDQ = 1.8V
1.0
Input/output capacitance (D, Q, DM, and QK/QK#)
3.0
4.5
pF
Clock capacitance (CK/CK#, and DK/DK#)
CCK
1.5
2.5
pF
CJTAG
1.5
4.5
pF
JTAG pins
Notes:
Max
Units
1. Capacitance is not tested on ZQ pin.
2. JTAG pins are tested at 50 MHz.
Table 12: Capacitance – FBGA
Description
Address/control input capacitance
Symbol
Conditions
Min
Max
Units
CI
TA = 25°C; f = 100 MHz
VDD = VDDQ = 1.8V
1.5
2.5
pF
Input/output capacitance (D, Q, DM, and QK/QK#)
CO
3.5
5.0
pF
Clock capacitance (CK/CK#, and DK/DK#)
CCK
2.0
3.0
pF
CJTAG
2.0
5.0
pF
JTAG pins
Notes:
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1. Capacitance is not tested on ZQ pin.
2. JTAG pins are tested at 50 MHz.
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Input Slew Rate Derating
Table 13: AC Electrical Characteristics
Notes 1-4 apply to the entire table.
-18
Description
-25E
-25
-33
-5
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Input clock cycle
time
tCK
1.875
5.7
2.5
5.7
2.5
5.7
3.3
5.7
5.0
Input data clock
cycle time
tDK
Clock jitter: period
tJITper
Clock jitter: cycleto-cycle
tJITcc
Clock HIGH time
tCKH,
Max Units Notes
Clock
tCK
–100
tCK
100
–150
200
tCK
150
–150
300
tCK
150
–200
300
5.7
tCK
200
–250
400
ns
ns
250
ps
500
ps
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
5, 6
tDKH
Clock LOW time
tCKL,
tDKL
Clock to input data clock
tCKDK
–0.3
0.3
–0.45
0.5
–0.3
0.5
–0.3
1.0
–0.3
1.5
ns
Mode register set
cycle time to any
command
tMRSC
6
–
6
–
6
–
6
–
6
–
tCK
Address/
command and input setup time
tAS/tCS
0.3
–
0.4
–
0.4
–
0.5
–
0.8
–
ns
Data-in and data
mask to DK setup
time
tDS
0.17
–
0.25
–
0.25
–
0.3
–
0.4
–
ns
Address/
command and input hold time
tAH/tCH
0.3
–
0.4
–
0.4
–
0.5
–
0.8
–
ns
Data-in and data
mask to DK hold
time
tDH
0.17
–
0.25
–
0.25
–
0.3
–
0.4
–
ns
Setup Times
Hold Times
Data and Data Strobe
Output data clock
HIGH time
tQKH
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCKH
Output data clock
LOW time
tQKL
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCKL
Half-clock period
tQHP
MIN
(tQKH,
tQKL)
–
MIN
(tQKH,
tQKL)
–
MIN
(tQKH,
tQKL)
–
MIN
(tQKH,
tQKL)
–
MIN
(tQKH,
tQKL)
–
–
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Input Slew Rate Derating
Table 13: AC Electrical Characteristics (Continued)
Notes 1-4 apply to the entire table.
-18
Description
-25E
-25
-33
-5
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
QK edge to clock
edge skew
tCKQK
–0.2
0.2
–0.25
0.25
–0.25
0.25
–0.3
0.3
–0.5
0.5
ns
QK edge to output data edge
tQKQ0,
–0.12
0.12
–0.2
0.2
–0.2
0.2
–0.25
0.25
–0.3
0.3
ns
7
–0.22
0.22
–0.3
0.3
–0.3
0.3
–0.35
0.35
–0.4
0.4
ns
8
–0.22
0.22
–0.3
0.3
–0.3
0.3
–0.35
0.35
–0.4
0.4
ns
tQKQ1
QK edge to any
output data edge
tQKQ
QK edge to QVLD
tQKVLD
Data valid window
Max Units Notes
tDVW
tQHP
tQHP
tQHP
tQHP
tQHP
(tQKQx
[MAX]
+|
tQKQx
[MIN]|)
–
(tQKQx
[MAX]
+|
tQKQx
[MIN]|)
–
(tQKQx[
MAX] +
|tQKQx
[MIN]|)
–
(tQKQx[
MAX] +
|tQKQx
[MIN]|)
–
(tQKQx[
MAX] +
|tQKQx
[MIN]|)
–
–
tREFI
–
0.49
–
0.49
–
0.49
–
0.49
–
0.49
μs
Refresh
Average periodic
refresh interval
Notes:
9
1. All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK#
and to the crossing point with VREF of the command, address, and data signals.
2. Outputs measured with equivalent load:
VTT
50Ω
Q
Test point
10pF
3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at
nominal reference/supply voltage levels, but the related specifications and device operations are tested for the full voltage range specified.
4. AC timing may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input
timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter
specifications are tested for the specified AC input levels under normal use conditions.
The minimum slew rate for the input signals used to test the device is 2 V/ns in the
range between VIL(AC) and VIH(AC).
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising
edge.
6. Frequency drift is not allowed.
7. tQKQ0 is referenced to Q0–Q8 and tQKQ1 is referenced to Q9–Q17 for a x18 device. For
a x9 device, Q0–Q8 are referenced to tQKQ0 (x9 is only available in the 576Mb design).
8. tQKQ takes into account the skew between any QKx and any Q.
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Input Slew Rate Derating
9. To improve efficiency, eight AREF commands (one for each bank) can be posted to the
device on consecutive cycles at periodic intervals of 3.90μs.
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Temperature and Thermal Impedance
Temperature and Thermal Impedance
It is imperative that the device’s temperature specifications, shown in the Temperature
Limits table, are maintained in order to ensure that the junction temperature is in the
proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’s thermal impedances correctly. The thermal impedances are listed for the available packages.
Using thermal impedances incorrectly can produce significant errors. Read Micron
technical note TN-00-88, Thermal Applications, prior to using the thermal impedances
listed in the Temperature Limits table. For designs that are expected to last several years
and require the flexibility to use several DRAM die shrinks, consider using final target
theta values (rather than existing values) to account for increased thermal impedances
from the die size reduction.
The device’s safe junction temperature range can be maintained when the T C specification is not exceeded. In applications where the device’s ambient temperature is too
high, use of forced air and/or heat sinks may be required in order to satisfy the case
temperature specifications.
Table 14: Temperature Limits
Parameter
Storage temperature
Reliability junction temperature
Commercial
Symbol
Min
Max
Units
Notes
TSTG
–55
+150
°C
1
TJ
–
+110
°C
2
–
+110
°C
2
Industrial
Operating junction temperature
Commercial
TJ
Industrial
Operating case temperature
Commercial
TC
Industrial
Notes:
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0
+100
°C
3
–40
+100
°C
3
0
+95
°C
4,5
–40
+95
°C
4,5,6
1. MAX storage case temperature; TSTG is measured in the center of the package, as shown
in Example Temperature Test Point Location. This case temperature limit can be exceeded briefly during package reflow, as noted in Micron technical note TN-00-15.
2. Temperatures greater than 110°C may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at or above this is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect the
reliability of the part.
3. Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow.
4. MAX operating case temperature; TC is measured in the center of the package, as shown
in Example Temperature Test Point Location.
5. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
6. Both temperature specifications must be satisfied.
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Temperature and Thermal Impedance
Table 15: Thermal Impedance
Package
Substrate
θ JA (°C/W)
Airflow = 0m/s
θ JA (°C/W)
Airflow = 1m/s
θ JA (°C/W)
Airflow = 2m/s
θ JB (°C/W)
θ JC (°C/W)
Rev. A die
2-layer
41.2
29.1
25.3
14.3
2.27
4-layer
28.2
21.9
19.9
13.6
2-layer
53.7
42.0
37.7
28.9
4-layer
34.1
28.9
27.1
21.9
Rev. B die
Note:
3.9
1. Thermal impedance data is based on a number of samples from multiple lots and should
be viewed as a typical number.
Figure 8: Example Temperature Test Point Location
Test point
18.50
9.25
5.50
11.00
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Commands
Commands
All input states or sequences not shown are illegal or reserved. All command and address inputs must meet setup and hold times around the rising edge of CK.
Table 16: Description of Commands
Command
Description
Notes
DSEL/NOP The NOP command is used to perform a no operation to the RLDRAM, which essentially deselects the
chip. Use the NOP command to prevent unwanted commands from being registered during idle or
wait states. Operations already in progress are not affected. Output values depend on command history.
1
MRS
The mode register is set via the address inputs A0–A17. See the Mode Register Definition in Nonmultiplexed Address Mode figure for further information. The MRS command can only be issued when
all banks are idle and no other operation is in progress.
READ
The READ command is used to initiate a burst read access to a bank. The value on the BA0–BA2 inputs selects the bank, and the address provided on inputs A0–An selects the data location within the
bank.
2
WRITE
The WRITE command is used to initiate a burst write access to a bank. The value on the BA0–BA2 inputs selects the bank, and the address provided on inputs A0–An selects the data location within the
bank. Input data appearing on the D is written to the memory array subject to the DM input logic
level appearing coincident with the data. If the DM signal is registered LOW, the corresponding data
will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be
ignored (that is, this part of the data word will not be written).
2
AREF
The AREF command is used during normal operation of the RLDRAM to refresh the memory content
of a bank. The command is nonpersistent, so it must be issued each time a refresh is required. The
value on the BA0–BA2 inputs selects the bank. The refresh address is generated by an internal refresh
controller, effectively making each address bit a “Don’t Care” during the AREF command. See the AUTO REFRESH (AREF) section for more details.
Notes:
1. When the chip is deselected, internal NOP commands are generated and no commands
are accepted.
2. For 288Mb, n = 19.
Table 17: Command Table
Operation
Device DESELECT/no operation
Code
CS#
WE#
REF#
A0–An2
BA0–BA2
DSEL/NOP
H
X
X
X
X
Notes
MRS
MRS
L
L
L
OPCODE
X
2
READ
READ
L
H
H
A
BA
3
WRITE
WRITE
L
L
H
A
BA
3
AREF
L
H
L
X
BA
AUTO REFRESH
Notes:
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1. Applies to entire table: X = “Don’t Care;” H = logic HIGH; L = logic LOW; A = valid address; BA = valid bank address.
2. Only A0–A17 are used for the MRS command.
3. Address width varies with burst length; see the Address Widths at Different Burst
Lengths table for details.
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MODE REGISTER SET (MRS) Command
MODE REGISTER SET (MRS) Command
The mode register set stores the data for controlling the operating modes of the memory. It programs the device configuration, burst length, test mode, and I/O options. During an MRS command, the address inputs A0–A17 are sampled and stored in the mode
register. After issuing a valid MRS command, tMRSC must be met before any command
can be issued to the device. This statement does not apply to the consecutive MRS commands needed for internal logic reset during the initialization routine. The MRS command can only be issued when all banks are idle and no other operation is in progress.
Note: The data written by the prior burst length is not guaranteed to be accurate when
the burst length of the device is changed.
Figure 9: Mode Register Set
CK#
CK
CS#
WE#
REF#
ADDRESS
OPCODE
BANK
ADDRESS
Don’t Care
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MODE REGISTER SET (MRS) Command
Figure 10: Mode Register Definition in Nonmultiplexed Address Mode
A17
...
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
17–10
9 8 7 6 5
Reserved1 ODT IM DLL NA2 AM
4 3
BL
1
On
M7
0
Drive Impedance
Internal 50Ω5 (default)
0
DLL Reset
DLL reset4 (default)
1
External (ZQ)
1
DLL enabled
M8
Notes:
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Off (default)
1.
2.
3.
4.
5.
2 1 0
Config
Mode Register (Mx)
M2 M1 M0 Configuration
0 0 0 13 (default)
M9 On-Die Termination
0
Address Bus
0
0
1
13
0
1
0
2
0
1
1
3
1
0
0
43
1
0
1
5
1
1
0
Reserved
1
1
1
Reserved
M4 M3
Burst Length
M5
Address MUX
0
Nonmultiplexed (default)
0
0
2 (default)
1
Multiplexed
0
1
4
1
0
8
1
1
Reserved
A10–A17 must be set to zero; A18–An = “Don’t Care.”
A6 not used in MRS.
BL = 8 is not available.
DLL RESET turns the DLL off.
±30% temperature variation.
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MODE REGISTER SET (MRS) Command
Configuration Tables
The table below shows the different configurations that can be programmed into the
mode register. The WRITE latency is equal to the READ latency plus one in each configuration in order to maximize data bus utilization. Bits M0, M1, and M2 are used to select the configuration during the MRS command.
Table 18: Cycle Time and READ/WRITE Latency Configuration Table
Notes 1 and 2 apply to entire table
Configuration
Parameter
tRC
13
2
3
43,4
5
4
6
8
3
5
tCK
Units
tRL
4
6
8
3
5
tCK
tWL
5
7
9
4
6
tCK
266–175
400–175
533–175
200–175
333–175
MHz
Valid frequency range
Notes:
1. Minimum operating frequency for the Die Rev. A -18 is 370 MHz.
2. BL = 8 is not available.
3. The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ
to the same bank. In this instance the minimum tRC is 4 cycles.
Burst Length (BL)
Burst length is defined by M3 and M4 of the mode register. Read and write accesses to
the device are burst-oriented, with the burst length being programmable to 2, 4, or 8.
Changes in the burst length affect the width of the address bus (see the Address Widths
at Different Burst Lengths table for details).
Note: The data written by the prior burst length is not guaranteed to be accurate when
the burst length of the device is changed.
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MODE REGISTER SET (MRS) Command
Figure 11: Read Burst Lengths
CK#
T0
T1
T2
T3
T4
T4n
READ
NOP
NOP
NOP
NOP
T5
T5n
T6
T6n
T7
T7n
CK
COMMAND
ADDRESS
NOP
NOP
NOP
NOP
Bank a,
Col n
RL = 4
QK#
BL = 2
QK
QVLD
DO
an
Q
QK#
BL = 4
QK
QVLD
DO
an
Q
QK#
BL = 8
QK
QVLD
DO
an
Q
Transitioning Data
Notes:
Don’t Care
1. DO an = data-out from bank a and address an.
2. Subsequent elements of data-out appear after DO n.
3. Shown with nominal tCKQK.
Table 19: Address Widths at Different Burst Lengths
Configuration
Burst Length
x18
2
A0–A19
4
A0–A18
8
A0–A17
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MODE REGISTER SET (MRS) Command
Address Multiplexing
The multiplexed address option is available by setting mode register bit M5 to 1. Once
this bit is set, the READ, WRITE, and MRS commands follow the format described in the
Command Description in Multiplexed Address Mode figure. Further information on operation with multiplexed addresses can be seen in Multiplexed Address Mode.
Although the device has the ability to operate with an SRAM interface by accepting the
entire address in one clock, an option in the mode register can be set so that it functions
with multiplexed addresses, similar to a traditional DRAM.
In multiplexed address mode, the address can be provided to the device in two parts
that are latched into the memory with two consecutive rising clock edges. This provides
the advantage of only needing a maximum of 11 address balls to control the device, reducing the number of signals on the controller side. The data bus efficiency in continuous burst mode is only affected when using the BL = 2 setting because the device requires two clocks to read and write the data.
The bank addresses are delivered to the device at the same time as the WRITE and
READ command and the first address part, Ax. The Address Mapping in Multiplexed
Address Mode table shows the addresses needed for both the first and second rising
clock edges (Ax and Ay, respectively).
The AREF command does not require an address on the second rising clock edge, as only the bank address is needed during this command. Because of this, AREF commands
may be issued on consecutive clocks.
DLL RESET
DLL reset is selected with bit M7 of the mode register. The default setting for this option
is LOW, whereby the DLL is disabled.
Once M7 is set HIGH, 1024 cycles (5μs at 200 MHz) are needed before a READ command can be issued. This time enables the internal clock to be synchronized with the
external clock.
Failing to wait for synchronization to occur may result in a violation of the tCKQK parameter.
A reset of the DLL is necessary if tCK or V DD is changed after the DLL has already been
enabled. To reset the DLL, an MRS command must be issued where M7 is set LOW. After
waiting tMRSC, a subsequent MRS command should be issued whereby M7 goes HIGH,
and 1024 clock cycles are then needed before a READ command is issued.
Drive Impedance Matching
The device is equipped with programmable impedance output buffers. This option is
selected by setting bit M8 HIGH during the MRS command. The purpose of the programmable impedance output buffers is to enable the user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is
connected between the ZQ ball and V SS. The value of the resistor must be five times the
desired impedance. For example, a 300Ω resistor is required for an output impedance of
60Ω. The range of RQ is 125–300Ω, which guarantees output impedance in the range of
25–60Ω (within 15%).
Output impedance updates may be required because over time variations may occur in
supply voltage and temperature. When the external drive impedance is enabled in the
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MODE REGISTER SET (MRS) Command
MRS, the device will periodically sample the value of RQ. An impedance update is transparent to the system and does not affect device operation. All data sheet timing and
current specifications are met during an update.
When bit M8 is set LOW during the MRS command, the device provides an internal impedance at the output buffer of 50Ω (±30% with temperature variation). This impedance is also periodically sampled and adjusted to compensate for variation in supply
voltage and temperature.
On-Die Termination (ODT)
ODT is enabled by setting M9 to a value of 1 during an MRS command. With ODT on,
the D, Q, and DM are terminated to V TT with a resistance RTT. The command, address,
QVLD, and clock signals are not terminated. The following figure shows the equivalent
circuit of a D receiver with ODT.
The ODT function is dynamically switched off when a Q begins to drive after a READ
command is issued. Similarly, ODT is designed to switch on at the Q after the device has
issued the last piece of data. The D and DM pins will always be terminated.
Table 20: On-Die Termination DC Parameters
Description
Symbol
Min
Max
Units
Notes
Termination voltage
VTT
0.95 × VREF
1.05 × VREF
V
1, 2
On-die termination
RTT
125
185
Ω
3
Notes:
1. All voltages referenced to VSS (GND).
2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. The RTT value is measured at 95°C TC.
Figure 12: On-Die Termination-Equivalent Circuit
VTT
SW
RTT
Receiver
D
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READ Command
READ Command
A READ command with an address initiates read access. During READ bursts, the device drives the read data to be edge-aligned with the QKx signals. After a programmable
READ latency, data is available at the outputs. One half clock cycle prior to valid data on
the read bus, QVLD, transitions from LOW to HIGH. QVLD is also edge-aligned with the
QKx signals.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the
skew between QK0 and the last valid data edge generated at the DQ signals associated
with QK0 (tQKQ0 is referenced to DQ0–DQ17 for a x36 configuration and DQ0–DQ8 for
a x18 configuration). tQKQ1 is the skew between QK1 and the last valid data edge generated at the DQ signals associated with QK1 (tQKQ1 is referenced to DQ18–DQ35 for a
x36 and DQ9–DQ17 for a x18 configuration). tQKQx is derived at each QKx clock edge
and is not cumulative over time. tQKQ is defined as the skew between either QK differential pair and any output data edge.
After completion of a burst, assuming no other command has been initiated, output data (DQ) goes High-Z. The QVLD signal transitions LOW on the last bit of the READ burst.
Note that if CK/CK# violates the V ID(DC) specification while a READ burst is occurring,
QVLD will remain HIGH until a dummy READ command is issued. The QK clocks are
free-running and will continue to cycle after READ burst is complete. Back-to-back
READ commands are possible, producing a continuous flow of output data. The data
valid window is derived from each QK transition and is defined as:
tQHP
- (tQKQ [MAX] + |tQKQ [MIN]|). See the Read Data Valid Window for x9 Device figure, the Read Data Valid Window for x18 Device figure, and the Read Data Valid Window
for x36 Device figure for illustration.
Any READ burst may be followed by a subsequent WRITE command. The READ-toWRITE figure illustrates the timing requirements for a READ followed by a WRITE. Some
systems having long line lengths or severe skews may need additional idle cycles inserted between READ and WRITE commands to prevent data bus contention.
Figure 13: READ Command
CK#
CK
CS#
WE#
REF#
ADDRESS
A
BANK
ADDRESS
BA
DON’T CARE
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WRITE Command
WRITE Command
Write accesses are initiated with a WRITE command. The address needs to be provided
during the WRITE command.
During WRITE commands, data will be registered at both edges of DK according to the
programmed burst length (BL). The device operates with a WRITE latency (WL) that is
one cycle longer than the programmed READ latency (RL + 1), with the first valid data
registered at the first rising DK edge WL cycles after the WRITE command.
Because the input and output data buses are separate, any WRITE burst may be followed by a subsequent READ command without encountering external data bus contention.
Setup and hold times for incoming DQ relative to the DK edges are specified as tDS and
tDH. The input data is masked if the corresponding DM signal is HIGH. The setup and
hold times for the DM signal are also tDS and tDH.
Figure 14: WRITE Command
CK#
CK
CS#
WE#
REF#
ADDRESS
A
BANK
ADDRESS
BA
DON’T CARE
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AUTO REFRESH (AREF) Command
AUTO REFRESH (AREF) Command
AREF is used to perform a REFRESH cycle on one row in a specific bank. Because the
row addresses are generated by an internal refresh counter for each bank, the external
address balls are “Don’t Care.” The bank addresses must be provided during the AREF
command. The bank address is needed during the AREF command so refreshing of the
part can effectively be hidden behind commands to other banks. The delay between the
AREF command and a subsequent command to the same bank must be at least tRC.
Within a period of 32ms (tREF), the entire device must be refreshed. The 288Mb device
requires 64K cycles at an average periodic interval of 0.49μs MAX (actual periodic refresh interval is 32ms/8K rows/8 banks = 0.488μs). To improve efficiency, eight AREF
commands (one for each bank) can be posted to the device at periodic intervals of 3.9μs
(32ms/8K rows = 3.90μs).
Figure 15: AUTO REFRESH Command
CK#
CK
CS#
WE#
REF#
ADDRESS
BANK
ADDRESS
BA
DON’T CARE
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INITIALIZATION Operation
INITIALIZATION Operation
The device must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operations or permanent damage to the device.
The following sequence is used for power-up:
1. Apply power (VEXT, V DD, V DDQ, V REF, V TT) and start clock as soon as the supply voltages are stable. Apply V DD and V EXT before or at the same time as V DDQ.1 Apply
VDDQ before or at the same time as V REF and V TT. Although there is no timing relation between V EXT and V DD, the chip starts the power-up sequence only after both
voltages approach their nominal levels. CK/CK# must meet V ID(DC) prior to being
applied.2 Apply NOP conditions to command pins. Ensuring CK/CK# meet V ID(DC)
while applying NOP conditions to the command pins guarantees that the device
will not receive unwanted commands during initialization.
2. Maintain stable conditions for 200μs (MIN).
3. Issue at least three consecutive MRS commands: two dummies or more plus one
valid MRS. The purpose of these consecutive MRS commands is to internally reset
the logic of the device. Note that tMRSC does not need to be met between these
consecutive commands. It is recommended that all address pins are held LOW
during the dummy MRS commands.
4. tMRSC after the valid MRS, an AUTO REFRESH command to all 8 banks (along
with 1024 NOP commands) must be issued prior to normal operation. The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP
commands) does not matter. As is required for any operation, tRC must be met between an AUTO REFRESH command and a subsequent valid command to the
same bank. Note that previous versions of the data sheet required each of these
AUTO REFRESH commands be separated by 2048 NOP commands. This properly
initializes the device but is no longer required.
Notes:
1. It is possible to apply V DDQ before V DD. However, when doing this, the D, DM, Q,
and all other pins with an output driver, will go HIGH instead of tri-stating. These
pins will remain high until V DD is at the same level as V DDQ. Care should be taken
to avoid bus conflicts during this period.
2. If V ID(DC) on CK/CK# can not be met prior to being applied to the device, placing a
large external resistor from CS# to V DD is a viable option for ensuring the command bus does not receive unwanted commands during this unspecified state.
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INITIALIZATION Operation
Figure 16: Power-Up/Initialization Sequence
VEXT
VDD
VDDQ
VREF
VTT
T0
T1
tCK
CK
tCKH
T3
T2
CK#
tCKL
T4
T5
T6
T8
T7
T9
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tDK
DK#
DK
tDKH
COMMAND
NOP
tDKL
NOP
NOP
((
))
((
))
NOP
MRS
MRS
MRS
((
))
((
))
REF
((
))
((
))
REF
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
VALID
((
))
((
))
VALID
DM
((
))
((
))
ADDRESS
((
))
((
))
BANK ADDRESS
((
))
((
))
((
))
((
))
High-Z
((
))
((
))
((
))
((
))
High-Z
((
))
((
))
((
))
((
))
High-Z
((
))
((
))
((
))
((
))
tMRSC
Refresh
all banks5
1024 NOP
commands
D
Q
RTT
1,2
CODE
T = 200μs (MIN)
Power-up:
VDD and stable
clock (CK, CK#)
Notes:
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1,2
CODE
2
CODE
VALID
Bank 0
((
))
((
))
Bank 7
DON’T CARE
1.
2.
3.
4.
Recommend all address pins held LOW during dummy MRS commands.
A10–A17 must be LOW.
DLL must be reset if tCK or VDD are changed.
CK and CK# must be separated at all times to prevent bogus commands from being issued.
5. The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP
commands) does not matter. As is required for any operation, tRC must be met between
an AUTO REFRESH command and a subsequent valid command to the same bank.
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INITIALIZATION Operation
Figure 17: Power-Up/Initialization Flow Chart
Step
Note:
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1
VDD, and VEXT ramp
2
VDDQ ramp
3
Apply VREF and VTT
4
Apply stable CK/CK# and DK/DK#
5
Wait at least 200μs
6
Issue MRS command—A[17:10] must be low
7
Issue MRS command—A[17:10] must be low
8
Desired load mode register with A[17:10] low
9
Assert NOP for tMRSC
10
Issue AUTO REFRESH to bank 0
11
Issue AUTO REFRESH to bank 1
12
Issue AUTO REFRESH to bank 2
13
Issue AUTO REFRESH to bank 3
14
Issue AUTO REFRESH to bank 4
15
Issue AUTO REFRESH to bank 5
16
Issue AUTO REFRESH to bank 6
17
Issue AUTO REFRESH to bank 7
18
Wait 1024 NOP commands1
19
Valid command
Voltage rails
can be applied
simultaneously
MRS commands
must be on
consecutive clock
cycles
1. The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP
commands) does not matter. As is required for any operation, tRC must be met between
an AUTO REFRESH command and a subsequent valid command to the same bank.
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WRITE Operations
WRITE Operations
Figure 18: WRITE Burst
T0
T1
T2
T3
T4
T5
T5n
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
ADDRESS
Bank a,
Add n
T6
T6n
T7
CK#
CK
t CKDK (NOM)
NOP
NOP
WL = 5
DK#
DK
DI
an
D
DM
t CKDK (MIN)
WL - tCKDK
DK#
DK
DI
an
D
DM
t CKDK (MAX)
WL + tCKDK
DK#
DK
DI
an
D
DM
TRANSITIONING DATA
Notes:
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DON’T CARE
1. DI an = data-in for address n; subsequent elements of burst are applied following DI an.
2. BL = 4.
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WRITE Operations
Figure 19: Consecutive WRITE-to-WRITE
T0
T1
T2
T3
WRITE
NOP
WRITE
NOP
T4
T5
T5n
T6
T6n
T7
T7n
T8
T8n
T9
CK#
CK
COMMAND
ADDRESS
Bank a,
Add n
Bank b,
Add n
WRITE
NOP
NOP
NOP
NOP
NOP
Bank a,
Add n
DK#
DK
t
RC = 4
WL = 5
WL = 5
DI
an
D
DI
bn
DI
an
DM
TRANSITIONING DATA
Notes:
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DON’T CARE
1.
2.
3.
4.
DI an (or bn) = data-in for bank a (or bank b) and address n.
Three subsequent elements of the burst are applied following DI for each bank.
BL = 4.
Each WRITE command may be to any bank; if the second WRITE is to the same bank,
tRC must be met.
5. Nominal conditions are assumed for specifications not defined.
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WRITE Operations
Figure 20: WRITE-to-READ
T0
T1
T2
T3
T4
T5
T5n
WRITE
READ
NOP
NOP
NOP
NOP
Bank a,
Add n
Bank b,
Add n
T6
T6n
T7
CK#
CK
COMMAND
ADDRESS
NOP
NOP
WL = 5
RL = 4
QK#
QK
DK#
DK
QVLD
DI
an
D
DO
bn
Q
DM
TRANSITIONING DATA
Notes:
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1.
2.
3.
4.
5.
DON’T CARE
DI an = data-in for bank a and address n.
DO bn = data-out from bank b and address n.
Three subsequent elements of each burst follow DI an and DO bn.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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WRITE Operations
Figure 21: WRITE – DM Operation
CK#
T1
T0
CK
COMMAND
T2
tCK
WRITE
NOP
tCH
NOP
T3
T4
NOP
NOP
T5
T6
NOP
NOP
T6n
T7
T7n
T8
tCL
NOP
NOP
Bank a,
Add n
ADDRESS
DK#
DK
tDKL
WL = 5
tDKH
DI
n
D
DM
tDS
tDH
TRANSITIONING DATA
Notes:
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1.
2.
3.
4.
DON’T CARE
DI n = data-in from address n.
Subsequent elements of burst are provided on following clock edges.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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READ Operations
READ Operations
Figure 22: Basic READ Burst Timing
CK#
T1
T0
T2
T3
T4
T5
T5n
NOP
NOP
READ
T6
T6n
T7
CK
tCK
COMMAND
NOP
READ
tCH
tCL
NOP
Bank a
Add n
ADDRESS
NOP
NOP
Bank a
Add n
RL = 4
tRC = 4
DM
tCKQK (MIN)
t CKQK (MIN)
QK#
QK
tQK
tQKH
tQKVLD
tQKL
tQKVLD
QVLD
DO
n
Q
tCKQK (MAX)
t CKQK (MAX)
QK#
QK
tQK
tQKH
tQKL
QVLD
DO
n
Q
TRANSITIONING DATA
Notes:
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1.
2.
3.
4.
DON’T CARE
DO n = data-out from address n.
Three subsequent elements of the burst are applied following DO n.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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READ Operations
Figure 23: Consecutive READ Bursts (BL = 2)
T5n
T6n
T0
T1
T2
T3
T4
COMMAND
READ
READ
READ
READ
READ
READ
READ
ADDRESS
Bank a
Add n
Bank b
Add n
Bank c
Add n
Bank d
Add n
Bank e
Add n
Bank f
Add n
Bank g
Add n
CK#
T4n
T5
T6
CK
RL = 4
QVLD
QK#
QK
DO
an
Q
DO
bn
DO
cn
TRANSITIONING DATA
Notes:
DON’T CARE
1.
2.
3.
4.
5.
DO an (or bn or cn) = data-out from bank a (or bank b or bank c) and address n.
One subsequent element of the burst from each bank appears after each DO x.
Nominal conditions are assumed for specifications not defined.
Example applies only when READ commands are issued to same device.
Bank address can be to any bank, but the subsequent READ can only be to the same
bank if tRC has been met.
6. Data from the READ commands to bank d through bank g will appear on subsequent
clock cycles that are not shown.
Figure 24: Consecutive READ Bursts (BL = 4)
T0
T1
T2
T3
T4
COMMAND
READ
NOP
READ
NOP
READ
ADDRESS
Bank a
Add n
CK#
T4n
T5
T5n
T6n
T6
CK
Bank b
Add n
NOP
Bank c
Add n
READ
Bank d
Add n
RL = 4
QVLD
QK#
QK
DO
an
Q
TRANSITIONING DATA
Notes:
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DO
bn
DON’T CARE
1.
2.
3.
4.
5.
DO an (or bn) = data-out from bank a (or bank b) and address n.
Three subsequent elements of the burst from each bank appears after each DO x.
Nominal conditions are assumed for specifications not defined.
Example applies only when READ commands are issued to same device.
Bank address can be to any bank, but the subsequent READ can only be to the same
bank if tRC has been met.
6. Data from the READ commands to banks c and d will appear on subsequent clock cycles
that are not shown.
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READ Operations
Figure 25: READ-to-WRITE
T0
T1
T2
T3
T4
COMMAND
READ
WRITE
NOP
NOP
READ
ADDRESS
Bank a,
Add n
Bank b,
Add n
CK#
T4n
T5
T5n
T6
T6n
T7
T7n
T8
T8n
CK
NOP
NOP
NOP
NOP
NOP
Bank a,
Add n
DM
QK#
QK
DK#
DK
t
RC = RL = 4
WL = RL + 1 = 5
QVLD
DI
bn
D
DO
an
Q
DO
an
TRANSITIONING DATA
Notes:
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1.
2.
3.
4.
5.
DON’T CARE
DO an = data-out from bank a and address n.
DI bn = data-in for bank b and address n.
Three subsequent elements of each burst follow DI bn and each DO an.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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READ Operations
Figure 26: READ/WRITE Interleave
T0
T1
T2
T3
T4
COMMAND
READ
WRITE
READ
WRITE
READ
WRITE
READ
WRITE
READ
ADDRESS
Bank a,
Add n
Bank b,
Add n
Bank c,
Add n
Bank d,
Add n
Bank a,
Add n
Bank b,
Add n
Bank c,
Add n
Bank d,
Add n
Bank a,
Add n
CK#
T4n
T5
T5n
T6
T6n
T7
T7n
T8
T8n
CK
DM
QK#
QK
DK#
DK
t
RC = RL = 4
WL = RL + 1 = 5
QVLD
DI
bn
D
DO
an
Q
DI
dn
DO
cn
DO
an
TRANSITIONING DATA
Notes:
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1.
2.
3.
4.
5.
DON’T CARE
DO xn = data-out from bank x and address n.
DI xn = data-in for bank x and address n.
Three subsequent elements of each burst follow each DI xn and DO xn.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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READ Operations
Figure 27: Read Data Valid Window for x18 Device
QK0#
QK0
tQKQ0 (MAX)3
tQHP1
tQKQ0 (MAX)3
tQKQ0 (MIN)3
tQHP1
tQKQ0 (MAX)3
tQKQ0 (MIN)3
tQHP1
tQKQ0 (MAX)3
tQKQ0 (MIN)3
tQHP1
tQKQ0 (MIN)3
Q0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Q8
Q (last valid data)
Q (first valid data)
All Qs and QKs collectively
tDVW2
tDVW2
tDVW2
tDVW2
QK1#
QK1
tQKQ1 (MAX)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MIN)4
Q9
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Q17
Q (last valid data)
Q (first valid data)
All Qs and QKs collectively
tDVW2
Notes:
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tDVW2
tDVW2
tDVW2
1. tQHP is defined as the lesser of tQKH or tQKL.
2. Minimum data valid window (tDVW) can be expressed as tQHP - (tQKQx [MAX] + |
tQKQx [MIN]|).
t
3. QKQ0 is referenced to Q0–Q8.
4. tQKQ1 is referenced to Q9–Q17.
5. tQKQ takes into account the skew between any QKx and any Q.
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AUTO REFRESH Operation
AUTO REFRESH Operation
Figure 28: AUTO REFRESH Cycle
T0
T1
T2
((
))
CK#
CK
tCK
COMMAND
AREFx
AREFy
ADDRESS
BANK
BAx
BAy
((
))
T3
tCH
ACx
D
Q
DM
tRC
((
))
((
))
((
))
((
))
Indicates a break in
time scale
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ACy
((
))
((
))
DK, DK#
Notes:
tCL
DON’T CARE
1. AREFx = auto refresh command to bank x.
2. ACx = any command to bank x; ACy = any command to bank y.
3. BAx = bank address to bank x; BAy = bank address to bank y.
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Operations with On-Die Termination
Operations with On-Die Termination
Figure 29: READ Burst with ODT
CK#
T0
T1
T2
T3
T4
T4n
READ
NOP
NOP
NOP
NOP
T5
T5n
T6
T6n
T7
T7n
CK
COMMAND
ADDRESS
NOP
NOP
NOP
NOP
Bank a,
Col n
RL = 4
QK#
BL = 2
QK
QVLD
DO
n
Q
Q ODT
Q ODT on
Q ODT on
Q ODT off
QK#
BL = 4
QK
QVLD
DO
n
Q
Q ODT
Q ODT on
Q ODT off
Q ODT on
QK#
BL = 8
QK
QVLD
DO
n
Q
Q ODT off
Q ODT on
Q ODT
TRANSITIONING DATA
Notes:
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on
DON’T CARE
1. DO n = data out.
2. DO n is followed by the remaining bits of the burst.
3. Nominal conditions are assumed for specifications not defined.
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Operations with On-Die Termination
Figure 30: READ-NOP-READ with ODT
CK#
T0
T1
T2
T3
T4
T4n
READ
NOP
READ
NOP
NOP
T5
T6
T6n
NOP
NOP
T7
CK
COMMAND
ADDRESS
Bank a,
Col n
NOP
NOP
Bank b,
Col n
RL = 4
QK#
QK
QVLD
DO
an
Q
Q ODT off
Q ODT on
Q ODT
DO
bn
Q ODT on
Q ODT off
TRANSITIONING DATA
Notes:
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1.
2.
3.
4.
Q ODT on
DON’T CARE
DO an (or bn) = data-out from bank a (or bank b) and address n.
BL = 2.
One subsequent element of the burst appears after DO an and DO bn.
Nominal conditions are assumed for specifications not defined.
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Operations with On-Die Termination
Figure 31: READ-to-WRITE with ODT
T0
T1
T2
T3
T4
COMMAND
READ
WRITE
NOP
NOP
READ
ADDRESS
Bank a,
Add n
Bank b,
Add n
CK#
T4n
T5
T5n
T6
T6n
T7
T7n
T8
T8n
CK
NOP
NOP
NOP
NOP
NOP
Bank a,
Add n
DM
QK#
QK
DK#
DK
t
RC = RL = 4
WL = RL + 1 = 5
QVLD
DI
bn
D
DO
an
Q
D and DM ODT
DO
an
D and DM ODT on
Q ODT
Q ODT off
Q ODT on
Q ODT on
TRANSITIONING DATA
Notes:
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1.
2.
3.
4.
Q ODT off
DON’T CARE
DO an = data-out from bank a and address n; DI bn = data-in for bank b and address n.
BL = 4.
Three subsequent elements of each burst appear after each DO an and DI bn.
Nominal conditions are assumed for specifications not defined.
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Multiplexed Address Mode
Multiplexed Address Mode
Command Description
Figure 32: Command Description in Multiplexed Address Mode
READ
WRITE
MRS
REF
CK#
CK
CS#
WE#
REF#
ADDRESS
Ax
BANK
ADDRESS
BA
Ay
Ax
Ay
Ax
BA
BA
Ay
BA
DON’T CARE
Note:
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1. The minimum setup and hold times of the two address parts are defined tAS and tAH.
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Multiplexed Address Mode
Power-Up/Initialization Sequence
Figure 33: Power-Up/Initialization Sequence in Multiplexed Address Mode
VEXT
VDD
VDDQ
VREF
VTT
T0
T1
tCK
CK
tCKH
T3
T2
CK#
tCKL
T4
T5
T6
T7
T8
T9
T10
T11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tDK
DK#
DK
tDKH
COMMAND
NOP
tDKL
NOP
NOP
((
))
((
))
NOP
MRS
MRS
((
))
((
))
MRS
MRS
NOP
((
))
((
))
((
))
((
))
REF
((
))
((
))
REF
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
VALID
((
))
((
))
VALID
DM
((
))
((
))
ADDRESS
((
))
((
))
BANK
ADDRESS
((
))
((
))
((
))
((
))
((
))
((
))
High-Z
((
))
((
))
((
))
((
))
((
))
High-Z
((
))
((
))
((
))
((
))
((
))
High-Z
((
))
((
))
((
))
((
))
((
))
tMRSC
tMRSC
Refresh
all banks9
1024 NOP
commands
D
Q
RTT
CODE
1,2
1,2
CODE
T = 200μs (MIN)
Power-up:
VDD and stable
clock (CK, CK#)
Notes:
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CODE
2,3
((
))
((
))
Ax
2,4
Ay
VALID
Bank 0
((
))
((
))
Bank 7
Indicates a break in
time scale
5
5
5
DON’T CARE
1. Recommended that all address pins held low during dummy MRS commands.
2. A10–A18 must be LOW.
3. Set address A5 HIGH. This enables the part to enter multiplexed address mode when in
non-multiplexed mode operation. Multiplexed address mode can also be entered at
some later time by issuing an MRS command with A5 HIGH. Once address bit A5 is set
HIGH, tMRSC must be satisfied before the two-cycle multiplexed mode MRS command is
issued.
4. Address A5 must be set HIGH. This and the following step set the desired mode register
once the device is in multiplexed address mode.
5. Any command or address.
6. The above sequence must be followed in order to power up the device in the multiplexed address mode.
7. DLL must be reset if tCK or VDD are changed.
8. CK and CK# must separated at all times to prevent bogus commands from being issued.
9. The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP
commands) does not matter. As is required for any operation, tRC must be met between
an AUTO REFRESH command and a subsequent VALID command to the same bank.
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Multiplexed Address Mode
Mode Register
Figure 34: Mode Register Definition in Multiplexed Address Mode
A5 A4 A3
A0
Ax A18 . . . A10 A9 A8
Ay A18 . . . A10
A9 A8
A4 A3
18–10
9 8 7 6 5
Reserved1 ODT IM DLL NA5 AM
4
0
1
Notes:
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1
0
Mode Register (Mx)
Config
M2
M1
M0
Off (default)
0
0
0
Configuration
12 (default)
1
On
0
0
1
12
0
1
0
2
0
1
1
3
DLL Reset
DLL reset4 (default)
1
0
0
42
1
0
1
5
DLL enabled
1
1
0
Reserved
1
1
1
Reserved
M4 M3
Burst Length
Drive Impedance
Internal 50Ω3 (default)
External (ZQ)
1.
2.
3.
4.
5.
6.
7.
2
0
M9 On-Die Termination
M8
3
BL
M7
0
1
M5
Address MUX
0
Nonmultiplexed (default)
0
0
2 (default)
1
Multiplexed
0
1
4
1
0
8
1
1
Reserved
Bits A10–A18 must be set to zero.
BL = 8 is not available.
±30% temperature variation.
DLL RESET turns the DLL off.
Ay8 not used in MRS.
BA0–BA2 are “Don’t Care.”
Addresses A0, A3, A4, A5, A8, and A9 must be set as shown in order to activate the
mode register in the multiplexed address mode.
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Multiplexed Address Mode
Address Mapping
Table 21: Address Mapping in Multiplexed Address Mode
Address
Data
Width
Burst
Length
Ball
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
x18
2
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
4
8
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
X
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
1. X = “Don’t Care.”
2. Ay address is reserved for A20 expansion in multiplexed mode.
3. Ay address is reserved for A21 expansion in multiplexed mode.
Notes:
Configuration Tables
In multiplexed address mode, the READ and WRITE latencies are increased by one
clock cycle. However, the device cycle time remains the same as when in non-multiplexed address mode.
Table 22: Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode
Note 1 applies to entire table
Configuration
13
2
3
43, 4
5
Units
tRC
4
6
8
3
5
tCK
tRL
5
7
9
4
6
tCK
tWL
6
8
10
5
7
tCK
266–175
400–175
533–175
200–175
333–175
MHz
Parameter
Valid frequency range
Notes:
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1.
2.
3.
4.
tRC <20ns in any configuration is only available with -25E and -18 speed grades.
Minimum operating frequency for -18 is 370 MHz.
BL = 8 is not available.
The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ
to the same bank. In this instance the minimum tRC is 4 cycles.
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Multiplexed Address Mode
REFRESH Command in Multiplexed Address Mode
Similar to other commands when in multiplexed address mode, AREF is executed on
the rising clock edge following the one on which the command is issued. However, because only the bank address is required for AREF, the next command can be applied on
the following clock. The operation of the AREF command and any other command is
represented in the following figure.
Figure 35: Burst REFRESH Operation with Multiplexed Addressing
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
AREF
AREF
AREF
AREF
AREF
AREF
AREF
AREF
T10
T11
CK#
CK
1
COMMAND
AC
NOP
ADDRESS
Ax
Ay
Ax
Bank n
BANK
1
AC
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Ay
Bank n
DON’T CARE
1. Any command.
2. Bank n is chosen so that tRC is met.
Notes:
Figure 36: Consecutive WRITE Bursts with Multiplexed Addressing
T0
T1
T2
T3
WRITE
NOP
WRITE
NOP
Ax
Ay
Ax
Ay
T4
T5
T6
WRITE
NOP
NOP
Ax
Ay
T6n
T7
T7n
T8
T8n
T9
CK#
CK
COMMAND
ADDRESS
BANK
Bank a
NOP
NOP
NOP
Bank a1
Bank b
DK#
DK
t
RC = 4
WL = 6
DI
a
D
DI
b
DM
TRANSITIONING DATA
Notes:
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DON’T CARE
1. Data from the second WRITE command to bank a will appear on subsequent clock cycles
that are not shown.
2. DI a = data-in for bank a; DI b = data-in for bank b.
3. Three subsequent elements of the burst are applied following DI for each bank.
4. Each WRITE command may be to any bank; if the second WRITE is to the same bank, tRC
must be met.
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Multiplexed Address Mode
Figure 37: WRITE-to-READ with Multiplexed Addressing
T0
T1
T2
T3
T4
T5
T6
WRITE
NOP
READ
NOP
NOP
NOP
NOP
Ax
Ay
Ax
Ay
T6n
T7
T7n
CK#
CK
COMMAND
ADDRESS
NOP
WL = 6
BANK
Bank a
Bank b
RL = 5
QK#
QK
DK#
DK
QVLD
DI
a
D
DO
b
Q
DM
TRANSITIONING DATA
Notes:
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1.
2.
3.
4.
5.
6.
DON’T CARE
DI a = data-in for bank a.
DO b = data-out from bank b.
One subsequent element of each burst follows DI a and DO b.
BL = 2.
Nominal conditions are assumed for specifications not defined.
Bank address can be to any bank, but the subsequent READ can only be to the same
bank if tRC has been met.
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Multiplexed Address Mode
Figure 38: Consecutive READ Bursts with Multiplexed Addressing
T0
T1
T2
T3
T4
COMMAND
READ
NOP
READ
NOP
READ
ADDRESS
Bank a
Add n
CK#
T4n
T5
T5n
T6n
T6
CK
Bank b
Add n
NOP
Bank c
Add n
READ
Bank d
Add n
RL = 4
QVLD
QK#
QK
DO
an
Q
TRANSITIONING DATA
Notes:
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DO
bn
DON’T CARE
1.
2.
3.
4.
5.
6.
DO a = data-out from bank a.
Nominal conditions are assumed for specifications not defined.
BL = 4.
Three subsequent elements of the burst appear following DO a.
Example applies only when READ commands are issued to same device.
Bank address can be to any bank, but the subsequent READ can only be to the same
bank if tRC has been met.
7. Data from the READ commands to banks b through bank d will appear on subsequent
clock cycles (not shown).
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Multiplexed Address Mode
Figure 39: READ-to-WRITE with Multiplexed Addressing
T0
T1
T2
T3
T4
T5
READ
NOP
WRITE
NOP
NOP
NOP
Ax
Ay
Ax
Ay
T5n
T6
T6n
T7
T8
NOP
NOP
NOP
T8n
CK#
CK
COMMAND
ADDRESS
BANK
NOP
Bank b
Bank a
DM
QK#
QK
DK#
DK
RL = 5
WL = RL + 1 = 6
QVLD
DI
bn
D
DO
an
Q
TRANSITIONING DATA
Notes:
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DON’T CARE
1.
2.
3.
4.
5.
6.
DO an = data-out from bank a.
DI bn = data-in for bank b.
Nominal conditions are assumed for specifications not defined.
BL = 4.
Three subsequent elements of the burst are applied following DO an.
Three subsequent elements of the burst which appear following DI bn are not all
shown.
7. Bank address can be to any bank, but the WRITE command can only be to the same
bank if tRC has been met.
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IEEE 1149.1 Serial Boundary Scan Test Access Port
IEEE 1149.1 Serial Boundary Scan Test Access Port
RLDRAM incorporates a serial boundary-scan test access port (TAP) for testing connectivity once it has been mounted on a printed circuit board (PCB). As the complexity of
PCB high-density surface mounting techniques increase, the boundary-scan architecture is a valuable resource for interconnectivity debug. This port operates in accordance
with IEEE Standard 1149.1-2001 (JTAG) with the exception of the ZQ pin. To ensure
proper boundary-scan testing of the ZQ pin, MRS bit M8 needs to be set to 0 until the
JTAG testing of the pin is complete.
Note: Upon power up, the default state of MRS bit M8 is low.
If the device boundary scan register is to be used upon power up and prior to device
initialization, it is imperative that the CK and CK# pins meet V ID(DC) or CS# be held
HIGH from power up until testing. Not doing so could result in inadvertent MRS commands being loaded and subsequently causing unexpected results from address pins
that are dependent upon the state of the mode register. If these measures cannot be taken, the part must be initialized prior to boundary scan testing. If a full initialization is
not practical or feasible prior to boundary scan testing, a single MRS command with desired settings may be issued instead. After the single MRS command is issued, the
tMRSC parameter must be satisfied prior to boundary scan testing.
The input signals of the test access port (TDI, TMS, and TCK) use V DD as a supply, while
the output signal of the TAP (TDO) uses V DDQ.
The JTAG test access port utilizes the device TAP controller, from which the instruction
register, boundary scan register, bypass register, and ID register can be selected.
Disabling the Serial Boundary Scan Test Access Port
It is possible to operate the device without using the JTAG feature. To disable the TAP
controller, TCK must be tied LOW (V SS) to prevent clocking of the device. TDI and TMS
are internally pulled up and may be unconnected. They may alternately be connected
to V DD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the
device will come up in a reset state, which will not interfere with the operation of the
device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising
edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the
rising edge of TCK.
All of the states in the TAP Controller State Diagram are entered through the serial input
of the TMS pin. A 0 in the diagram represents a LOW on the TMS pin during the rising
edge of TCK while a 1 represents a HIGH on TMS.
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TAP Controller
Test Data-In (TDI)
The TDI ball is used to serially input test instructions and data into the registers and can
be connected to the input of any of the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram. TDI is connected to the most significant bit (MSB) of any register (see TAP Controller Block Diagram).
Test Data-Out (TDO)
The TDO output ball is used to serially clock test instructions and data out from the registers. The TDO output driver is only active during the Shift-IR and Shift-DR TAP controller states. In all other states, the TDO pin is in a High-Z state. The output changes on
the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register (see the TAP Controller Block Diagram).
TAP Controller
The TAP controller is a finite state machine that uses the state of the TMS pin at the rising edge of TCK to navigate through its various modes of operation. See the TAP Controller State Diagram.
Test-Logic-Reset
The test-logic-reset controller state is entered when TMS is held HIGH for at least five
consecutive rising edges of TCK. As long as TMS remains HIGH, the TAP controller will
remain in the test-logic-reset state. The test logic is inactive during this state.
Run-Test/Idle
The run-test/idle is a controller state in-between scan operations. This state can be
maintained by holding TMS LOW. From here either the data register scan, or subsequently, the instruction register scan, can be selected.
Select-DR-Scan
Select-DR-scan is a temporary controller state. All test data registers retain their previous state while here.
Capture-DR
The capture-DR state is where the data is parallel-loaded into the test data registers. If
the boundary scan register is the currently selected register, then the data currently on
the pins is latched into the test data registers.
Shift-DR
Data is shifted serially through the data register while in this state. As new data is input
through the TDI pin, data is shifted out of the TDO pin.
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TAP Controller
Exit1-DR, Pause-DR, and Exit2-DR
The purpose of exit1-DR is used to provide a path to return back to the run-test/idle
state (through the update-DR state). The pause-DR state is entered when the shifting of
data through the test registers needs to be suspended. When shifting is to reconvene,
the controller enters the exit2-DR state and then can re-enter the shift-DR state.
Update-DR
When the EXTEST instruction is selected, there are latched parallel outputs of the boundary-scan shift register that only change state during the update-DR controller state.
Instruction Register States
The instruction register states of the TAP controller are similar to the data register
states. The desired instruction is serially shifted into the instruction register during the
shift-IR state and is loaded during the update-IR state.
Figure 40: TAP Controller State Diagram
1
Test-logic
reset
0
Run-test/
Idle
0
1
Select
DR-scan
1
Select
IR-scan
0
1
0
1
Capture-DR
Capture-IR
0
0
Shift-DR
Shift-IR
0
1
1
Exit1-IR
0
1
0
Pause-DR
Pause-IR
0
1
0
1
Exit2-DR
0
Exit2-IR
1
1
Update-DR
1
0
1
Exit1-DR
0
1
0
Update-IR
1
0
Figure 41: TAP Controller Block Diagram
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TAP Reset
0
Bypass register
7 6 5 4 3 2 1 0
TDI
Selection
circuitry
Instruction register
31 30 29 .
.
Selection
circuitry
. 2 1 0
TDO
Identification register
x1 . . . . . 2 1 0
Boundry scan register
TCK
TMS
TAP controller
1. x = 112 for all configurations.
Note:
TAP Reset
A reset is performed by forcing TMS HIGH (V DDQ) for five rising edges of TCK. The reset
does not affect the operation of the RLDRAM and may be performed while the RLDRAM
is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a
High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and allow data to be scanned
into and out of the device test circuitry. Only one register can be selected at a time
through the instruction register. Data is serially loaded into the TDI ball on the rising
edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is
loaded during the update-IR state of the TAP controller. Upon power-up, the instruction
register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the capture-IR state, the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board-level serial test data
path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous
to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the device with
minimal delay. The bypass register is set LOW (V SS) when the BYPASS instruction is executed.
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TAP Registers
Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the
device. Several balls are also included in the scan register to reserved balls. The device
has a 113-bit register.
The boundary scan register is loaded with the contents of the RAM I/O ring when the
TAP controller is in the capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the shift-DR state.
The Boundary Scan (Exit) Order table shows the order in which the bits are connected.
Each bit corresponds to one of the balls on the device package. The most significant bit
of the register is connected to TDI, and the least significant bit is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR
state when the IDCODE command is loaded in the instruction register. The IDCODE is
hardwired into the device and can be shifted out when the TAP controller is in the shiftDR state. The ID register has a vendor code and other information described in the
Identification Register Definitions table.
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TAP Instruction Set
TAP Instruction Set
Many different TAP instructions (2 8) are possible with the 8-bit instruction register. All
combinations used are listed in the table here, followed by detailed descriptions. Remaining instructions are reserved and should not be used. The TAP controller used in
this device is fully compliant to the 1149.1 convention.
Instructions are loaded into the TAP controller during the shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are
shifted through the instruction register through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller needs to be moved into the updateIR state.
Table 23: Instruction Codes
Instruction
Code
Description
Extest
0000 0000 Captures I/O ring contents; Places the boundary scan register between TDI and TDO; This operation does not affect device operations
ID code
0010 0001 Loads the ID register with the vendor ID code and places the register between TDI and TDO;
This operation does not affect device operations
Sample/preload
0000 0101 Captures I/O ring contents; Places the boundary scan register between TDI and TDO
Clamp
0000 0111 Selects the bypass register to be connected between TDI and TDO; Data driven by output
balls are determined from values held in the boundary scan register
High-Z
0000 0011 Selects the bypass register to be connected between TDI and TDO; All outputs are forced into High-Z
Bypass
1111 1111 Places the bypass register between TDI and TDO; This operation does not affect device operations
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register cells at output balls are used to apply a test vector, while
those at input balls capture test results. Typically, the first test vector to be applied using
the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output driver is
turned on, and the PRELOAD data is driven onto the output balls.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls
and allows the IDCODE to be shifted out of the device when the TAP controller enters
the shift-DR state. The IDCODE instruction is loaded into the instruction register upon
power-up or whenever the TAP controller is given a test logic reset state.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the
TAP controller is in the capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.
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TAP Instruction Set
The user must be aware that the TAP controller clock can only operate at a frequency up
to 50 MHz, while the RLDRAM clock operates significantly faster. Because there is a
large difference between the clock frequencies, it is possible that during the capture-DR
state, an input or output will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm the device, but there is
no guarantee as to the value that will be captured. Repeatable results may not be possible.
To ensure that the boundary scan register will capture the correct value of a signal, the
signal must be stabilized long enough to meet the TAP controller’s capture setup plus
hold time (tCS plus tCH). The RLDRAM clock input might not be captured correctly if
there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the
shift-DR state. This places the boundary scan register between the TDI and TDO balls.
CLAMP
When the CLAMP instruction is loaded into the instruction register, the data driven by
the output balls are determined from the values held in the boundary scan register.
High-Z
The High-Z instruction causes the boundary scan register to be connected between the
TDI and TDO. This places all outputs into a High-Z state.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed
in a shift-DR state, the bypass register is placed between TDI and TDO. The advantage
of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
Reserved for Future Use
The remaining instructions are not implemented but are reserved for future use. Do not
use these instructions.
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TAP Instruction Set
Figure 42: JTAG Operation – Loading Instruction Code and Shifting Out Data
T0
T1
T2
T3
T4
T5
T6
T7
TCK
TMS
((
))
((
))
TDI
((
))
((
))
TAP
CONTROLLER
STATE
T8
T9
((
))
((
))
Test-LogicReset
Run-Test
Idle
Select-DRSCAN
Select-IRSCAN
Capture-IR
Shift-IR
Shift-IR
((
))
((
))
Exit 1-IR
Pause-IR
Pause-IR
((
))
((
))
TDO
8-bit instruction code
T10
T11
T12
T13
T14
T15
T16
TCK
T18
T19
Update-DR
Run-Test
Idle
Run-Test
Idle
((
))
((
))
TMS
((
))
((
))
TDI
TAP
CONTROLLER
STATE
T17
((
))
((
))
Exit 2-IR
Update-IR
Select-DRScan
Capture-DR
Shift-DR
Shift-DR
((
))
((
))
Exit1-DR
((
))
((
))
TDO
n-bit register between
TDI and TDO
TRANSITIONING DATA
DON’T CARE
Figure 43: TAP Timing
T1
T2
T3
Test clock
(TCK)
tTHTL
tMVTH
tTHMX
tDVTH
tTHDX
t
TLTH
T4
T5
T6
tTHTH
Test mode select
(TMS)
Test data-in
(TDI)
tTLOV
tTLOX
Test data-out
(TDO)
UNDEFINED
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TAP Instruction Set
Table 24: TAP Input AC Logic Levels
+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted
Description
Symbol
Min
Max
Units
Input high (logic 1) voltage
VIH
Input low (logic 0) voltage
VIL
VREF + 0.3
–
V
–
VREF - 0.3
V
Table 25: TAP AC Electrical Characteristics
Note:
All voltages referenced to VSS (GND); +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V
Description
Symbol
Min
Max
Units
Clock
Clock cycle time
tTHTH
Clock frequency
fTF
Clock HIGH time
tTHTL
10
ns
Clock LOW time
tTLTH
10
ns
TCK LOW to TDO unknown
tTLOX
0
ns
20
ns
50
MHz
TDI/TDO times
TCK LOW to TDO valid
tTLOV
TDI valid to TCK HIGH
tDVTH
5
ns
TCK HIGH to TDI invalid
tTHDX
5
ns
tMVTH
5
ns
tCS
5
ns
tTHMX
5
ns
tCH
5
ns
10
ns
Setup times
TMS setup
Capture setup
Hold times
TMS hold
Capture hold
Note:
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2. tCS and tCH refer to the setup and hold time requirements of latching data from the
boundary scan register.
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TAP Instruction Set
Table 26: TAP DC Electrical Characteristics and Operating Conditions
+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted; All voltages referenced to VSS (GND)
Description
Condition
Symbol
Min
Max
Units Notes
Input high (logic 1) voltage
–
VIH
VREF + 0.15
VDD + 0.3
V
1, 2
Input low (logic 0) voltage
–
VIL
VSSQ - 0.3
VREF - 0.15
V
1, 2
0V ≤ VIN ≤ VDD
ILI
–5.0
5.0
μA
Output disabled, 0V ≤ VIN ≤ VDDQ
IIO
–5.0
5.0
μA
Output low voltage
IOLc = 100μA
VOL1
0.2
V
1
Output low voltage
IOLt = 2mA
VOL2
0.4
V
1
Output high voltage
|IOHc| = 100μA
VOH1
VDDQ - 0.2
V
1
Output high voltage
|IOHt| = 2mA
VOH2
VDDQ - 0.4
V
1
Input leakage current
Output leakage current
Note:
1. Overshoot = VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2; undershoot = VIL(AC) ≥ –0.5V for t ≤ tCK/2;
during normal operation, VDDQ must not exceed VDD.
Table 27: Identification Register Definitions
Instruction Field
All Devices
Description
Revision number
(31:28)
abcd
ab = 00 for Die Rev. A, 01 for Die Rev. B
cd = 00 for x9, 01 for x18, 10 for x36
Device ID (27:12)
00jkidef10100111
def = 000 for 288Mb, 001 for 576Mb
i = 0 for common I/O, 1 for separate I/O
jk = 01 for RLDRAM 2, 00 for RLDRAM
Micron JEDEC ID code
(11:1)
00000101100
ID register presence indicator (0)
1
Allows unique identification of RLDRAM vendor
Indicates the presence of an ID register
Table 28: Scan Register Sizes
Register Name
Bit Size
Instruction
8
Bypass
1
ID
32
Boundary scan
113
Table 29: Boundary Scan (Exit) Order
Bit#
Ball
Bit#
Ball
Bit#
Ball
1
K1
39
R11
77
C11
2
K2
40
R11
78
C11
3
L2
41
P11
79
C10
4
L1
42
P11
80
C10
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TAP Instruction Set
Table 29: Boundary Scan (Exit) Order (Continued)
Bit#
Ball
Bit#
Ball
Bit#
Ball
5
M1
43
P10
81
B11
6
M3
44
P10
82
B11
7
M2
45
N11
83
B10
8
N1
46
N11
84
B10
9
P1
47
N10
85
B3
10
N3
48
N10
86
B3
11
N3
49
P12
87
B2
12
N2
50
N12
88
B2
13
N2
51
M11
89
C3
14
P3
52
M10
90
C3
15
P3
53
M12
91
C2
16
P2
54
L12
92
C2
17
P2
55
L11
93
D3
18
R2
56
K11
94
D3
19
R3
57
K12
95
D2
20
T2
58
J12
96
D2
21
T2
59
J11
97
E2
22
T3
60
H11
98
E2
23
T3
61
H12
99
E3
24
U2
62
G12
100
E3
25
U2
63
G10
101
F2
26
U3
64
G11
102
F2
27
U3
65
E12
103
F3
28
V2
66
F12
104
F3
29
U10
67
F10
105
E1
30
U10
68
F10
106
F1
31
U11
69
F11
107
G2
32
U11
70
F11
108
G3
33
T10
71
E10
109
G1
34
T10
72
E10
110
H1
35
T11
73
E11
111
H2
36
T11
74
E11
112
J2
37
R10
75
D11
113
J1
38
R10
76
D10
–
–
Note:
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1. Any unused balls in the order will read as a logic “0.”
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Revision History
Revision History
Rev. I – 06/01/15
• Updated date code for actual release starting with Cisco. Updated copyright drr
• Added FBGA package codes to features and part numbering figure. tq
• Added in FBGA pin capacitance table. tq
Rev. H – 4/11
• Added revision :B information
• Updated functional block diagrams and notes
• Deleted FBGA package option
Rev. G – 04/11
• Added in Rev. B - Thermal Impedance numbers into Table
Rev. F – 06/09
• Updated package drawings
• Added μBGA capacitance table
Rev. E – 05/09
• Added μBGA package
Rev. D – 06/08
• Corrected Max bandwidth on page 1 to be 38.4 Gb/s
• Added ‘:A’ to part number on first page and in ‘576Mb RLDRAM CIO Part Numbers’
figure
• Remove the superscript ‘1’ from the ‘HU’ package on the first page
• Added IDD values for -18 speed grade
• Added the words ‘continuous data’ to IDD2R, IDD4R, and IDD8R
Rev. C – 06/08
• Updated JTAG verbiage
Rev. B – 07/07
• Added “288Mb Only” to -5 header on Table 12 on page 24.
• Updated DLL RESET reference and Note 4 on the Mode Register Definition in Nonmultiplexed Address Mode figure to align with the DLL RESET reference and Note 5
on the Mode Register Definition in Multiplexed Address Mode figure.
• Modified Notes 1 and 3, updated Note 4, and removed Step 5 in the INITIALIZATION
section.
• Added Note 5 on the Power-Up/Initialization Sequence figure.
• Updated Note value from 400 MHz to 370 MHz.
• Removed tCKQK from Basic READ Burst Timing figure.
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Revision History
• Added Note 3, updated Note 4, added Note 9 on the Power-Up/Initialization Sequence in Multiplexed Address Mode figure.
• Updated Mode Register Definition in Multiplexed Address Mode figure and reorganized its notes.
• Updated Note on page value from 400 MHz to 370 MHz and updated Note on page on on
page .
• Updated device ID description in the Identification Register Definitions table.
Rev. A – 05/07
• Added Simplified State Diagram.
• Changed Note 3 under the DC Electrical Characteristics and Operating Conditions table to be 1.5V±0.1V and 1.8V±0.1V from 1.5V + 0.1V and 1.8V + 0.1V.
• Replaced Note 4 in the INITIALIZATION section.
• Removed Vih (max) and Vil (min) from the Input AC Logic Levels table.
• Changed the internal impedance range to ±30% from ±15% to align with where testing has occurred (i.e., when MRS bit 8 is low).
• Included more description of all of the Mode Registers.
• Added additional examples of operations occurring during multiplexed operations.
• Changed the ODT resistance to be 125–185Ω from 135–165Ω to align with where we
have always tested.
• Changed Capacitance conditions in Table 11 on page 24 from 1 MHz to 100 MHz and
included V DD = V DDQ = 1.8V. Included DK/DK# in the “Clock Capacitance” description; Changed capacitance testing frequency from 1 MHz to 100 MHz. Added signal
descriptions for each pin type in the description row. Added JTAG column and values;
Added Notes 1 and 2.
• Removed timing portion of the Cycle Time and READ/WRITE Latency Configuration
Table and replaced with valid operation in given frequency ranges. Also added the
MODE REGISTER SET (MRS) section that includes configurations 4 and 5. Changed
format of both tables.
• Moved a few notes from under the Differential Input Clock Operating Conditions table to either under the Electrical Specifications - I DD section or the AC Electrical
Characteristics table.
• Added the Input Slew Rate Derating section, including the Address and Command
Setup and Hold Derating Values table, the Data Setup and Hold Derating Values table,
and the Nominal t AS/t CS/tDS andtAH/tCH/tDH Slew Rate figure.
• Combined 288Mb and 576Mb AC parameters into the AC Electrical Characteristics table.
• Updated -18 tCK MAX value from 2.5 to 2.7 in the AC Electrical Characteristics table.
• In the Mode Register Set (MRS) section, added a note in the AC Electrical Characteristics table.
– Changed jitter specs to be tJITper and tJITcc instead of tCKvar
– Added tQHP and tQDVW
– Added tREFI
• Changed 576Mb tCKDK values based on silicon results.
• Removed Storage Temperature and Junction Temperature from the Absolute Maximum Ratings table and added them to newly added Temperature Limits table.
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Revision History
• Added the Temperature and Thermal Impedance section that includes the Temperature Limits table, and the Thermal Impedance table, along with the Example Temperature Test Point Location figure.
• Modified Step 4 in the INITIALIZATION section.
• Updated the Power-Up/Initialization Sequence figure.
• Added Note 2 and removed Step 5 in the INITIALIZATION section.
• Added the Power-Up/Initialization Flow Chart.
• Added the WRITE Burst figure.
• Added the Read Data Valid Window for x18 Device figure and the Read Data Valid
Window for x9 Device figure.
• Changed Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed
Mode to align with Cycle Time and READ/WRITE Latency Configuration Table and
added the Multiplexed Address Mode section.
• Clarified MRS commands during initialization routine must be consecutive and added Note 6.
• Updated Notes on page and on page on on page .
• Updated the IEEE 1149.1 Serial Boundary Scan (JTAG) section, including the TAP
Controller section and JTAG Operation - Loading Instruction Code and Shifting Out
Data figure.
• Reordered structure of entire document.
• Created new format with core and density specific sections...includes removing density specific addresses where applicable.
• Redrew most timing diagrams to common standard.
• Initial RLDRAM II SIO core data sheet.
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www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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