TN-47-02 DDR2 Offers New Features/Functionality Introduction Technical Note DDR2 Offers New Features and Functionality Introduction DDR2 SDRAM introduces features and functions that go beyond the DDR SDRAM specification and enable DDR2 to operate at data rates of 800MHz and above. The advancements of DDR2 are largely the result of changes in DRAM architecture and signaling, as well as additions to the mode register for lower power and improved command/data bandwidth. This article discusses the various the changes and new features and benefits of DDR2 technology. DRAM Architecture Changes DDR2 Array Definition Changes to the DRAM architecture include shortened page size for reduced activation power, burst lengths of four and eight for improved data bandwidth capability, and the addition of eight banks in 1Gb densities and above. DDR2 Page Size Page size is important to the power consumption of a DRAM device. Page size is defined as the minimum number of column locations that are accessed with a single ACTIVATE command. This is calculated as the number of column locations times the number of DQs on the DRAM. For example, the 512Mb, x8 DDR2 SDRAM has 1,024 column locations, so the page size is 1,024 columns times 8 DQs, which equals 8,192 bits. Dividing the 8,192 bits by a word length of 8 equals 1,024 bytes or 1KB. Each time an ACTIVATE command is given, all bits in the page are read by the sense amplifiers and restored to the correct value. Because this process is a major contributor to the active power, a device with a shorter page size has a significantly lower operating current. The page size of the 512Mb DDR2 device is half that of DDR SDRAM. Therefore, the current consumed by the ACTIVATE commands is greatly reduced, resulting in improved IDD0, IDD1, and IDD7 specifications. (See Table 1 for a comparison of DDR2 and DDR page sizes and banks.) 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All information discussed herein is provided on an “as is” basis, without warranties of any kind. TN-47-02 DDR2 Offers New Features/Functionality DRAM Architecture Changes Table 1: DRAM Architectures Density 256Mb Page Size Banks Page Size Banks Page Size Banks Page Size Banks 512Mb 1Gb 2Gb DDR DDR2 1KB 4 2KB 4 2KB 4 – – 1KB 4 1KB (x4, x8), 2KB (x16) 4 1KB (x4, x8), 2KB (x16) 8 1KB (x4, x8), 2KB (x16) 8 With the higher-density DDR2 SDRAM (512Mb, 1Gb, and 2Gb), the page size increases on the x16 device. The x4 and x8 devices continue to operate at lower activate currents with a 1KB page size, similar to the 256Mb DDR2 SDRAM. However, the x16 DDR2 page size increases to 2KB. While power consumption increases on the x16 DDR2 SDRAM, system power is typically no higher than that of the x8 device. A 64-bit bus requires eight x8 DRAM devices to support the bus width, while only four x16 DRAM devices are required. Thus, the activate current of a x16 component may be somewhat higher, but the overall system power consumption is still lower. DDR2 Bank Accesses Another change from DDR to DDR2 (as shown in Table 1) is the number of banks on the larger-density DDR2 devices. A typical four-bank access, which is applicable to the 256Mb and 512Mb DDR2 SDRAM, is shown in Figure 1. Bank accesses for DDR2 devices are similar to DDR, except ACTIVATE command spacing is 7.5ns for 1KB and 10ns for 2KB page sizes, due to the increased power consumption of the larger page size. When a bank is precharged, it may be activated again after tRC is met, following the original ACTIVATE command. The larger-density 1Gb and 2Gb DDR2 devices use eight banks, which increases flexibility in DRAM accesses. However, it also increases the power that must be delivered to the DRAM. To keep the power delivery from adversely affecting the functionality of the DRAM and the memory subsystem, an additional restriction (tFAW) is applied to bank ACTIVATE commands, as shown in Figure 2. ACTIVATE-to-ACTIVATE spacing remains t RRD, as in the four-bank case; however, there is an additional restriction within any t FAW window where no more than four banks may be activated. This requires a short amount of extra time prior to activating the fifth bank. Figure 1: ACTIVATE for Four-Bank DDR or DDR2 Devices Clock tRP tRAS tRRD CMD/ ADD ACT B0,Rx ACT B1,Rx ACT B2,Rx ACT B3,Rx PRE B0 PRE B1,Rx ACT B0,Rx tRC 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality Signaling Features Figure 2: ACTIVATE for Eight-Bank DDR or DDR2 Devices Clock tRRD CMD/ ADD ACT B0,Rx ACT B1,Rx ACT B2,Rx ACT B3,Rx ACT B4,Rx PRE B0 ACT B5,Rx PRE B1 ACT B6,Rx PRE B2 tFAW Note: tRRD is 7.5ns on 1KB page size and 10ns on 2KB page size (two clock minimum). tFAW is 37.5ns on 1KB page size and 50ns on 2KB page size. Signaling Features On-Die Termination On-die termination (ODT) has been added to the DDR2 data signals to improve signal integrity in the system. Figure 3 shows a functional diagram of the on-die termination. The termination value of RTT is the Thevinen equivalent of the resistors that terminate the DQ inputs to VSSQ and VDDQ. An ODT pin is added to the DRAM so the system can turn the termination on and off as needed. In a simple system with one DRAM load per DQ signal, the termination is turned on for WRITEs and disabled for READs. Figure 3: Functional Diagram for On-Die Termination Output Driver DQ Pins VDDQ 2RTT RCVR 2RTT VSSQ ODT Pin Control Figure 4 shows the ODT trace routing on a typical PC system with two memory slots. Each slot contains two ranks of memory (front and back). A separate ODT signal is routed to each rank of memory to provide flexibility in power management and the best system performance. The routing of ODT signals is similar to the routing of CS# signals. 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality ODT WRITEs ODT1 (back) ODT2 (front) ODT3 (back) Register ODT0 (front) Register Typical 2-Slot ODT Routing Controller Figure 4: ODT WRITEs Figure 5 shows a typical termination scheme for write data in a 533 Mbit/s, two-module system. If only one module is loaded in the system, a 150 ohm equivalent termination (300 ohm pull-up/300 ohm pull-down) must be enabled on the module during the WRITE. If two modules are loaded into the system, the termination on the module not receiving the write data should be enabled at 75 ohm equivalent termination resistance (150 ohm pull-up/150 ohm pull-down). This termination scheme provides optimal trade-offs between signal integrity and voltage swing. The equivalent comparison for write data at 533 Mbit/s is shown in Figure 6. Neither bus has significant overshoot. However, the voltage margin on the SSTL bus is not sufficiently outside the DRAM input voltage requirements. Thus, when the input slew rate slows down in the two-slot system, the data eye that the DRAM must capture is significantly reduced. The ODT system shows increased voltage margin, and the data eye remains significantly larger, even under heavily loaded conditions. 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality ODT WRITEs Figure 5: Typical ODT Configuration for DRAM WRITEs Active Module VDDQ One Module Populated 300Ω RCVR 300Ω System Controller VSSQ Active Module Standby Module VDDQ Two Modules Populated 150Ω RCVR 150Ω System Controller VSSQ Figure 6: ODT vs. SSTL Termination Comparison for WRITEs ODT Termination Input Voltage (V) One Single-Rank Module Input Voltage (V) SSTL Termination 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 0.1 0 0.75 1.5 2.25 3 3.75 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 - 0.1 0 Input Voltage (V) Input Voltage (V) Two Dual-Rank Modules (Second Module) 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 - 0.1 0 0.75 1.5 2.25 3 Time (nanoseconds) 0.75 1.5 2.25 3 3.75 Time (nanoseconds) Time (nanoseconds) 3.75 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 - 0.1 0 0.75 1.5 2.25 3 3.75 Time (nanoseconds) ODT READs Figure 7 shows a typical termination scheme for read data in a 533 Mbit/s, two-module system. For READs, on-die termination must be included on the controller. If only one module is loaded in the system, a 75 ohm termination should be enabled on the system controller. If two modules are loaded, the controller termination should be increased to 150 ohms and the unused module should terminate at 75 ohms. This configuration provides good voltage margin at the controller. Figure 8 shows a comparison of a DDR2 DQ bus for a typical SSTL-terminated, twomodule system using ODT termination versus a non-ODT system reading data at 533 MT/s. The most obvious difference between the two buses is the reduction in the overshoot on the data bus. The overshoot reduction significantly improves the voltage margin and reduces inter-symbol interference (ISI). The second major improvement using DDR2 ODT is the increase in the slew rate in the two-module case. The SSTL bus 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality ODT WRITEs starts “laying over” when more loads are added, which detracts from the timing margin in the system. Both of these improvements dramatically increase the size of the data eye that the system controller must capture to read data from the DRAM. Overall, ODT implementation provides improved signal integrity, data eyes, and voltage margin for DDR2 to enable systems to attain higher data rates. At the same time, it is an option and can be disabled for systems that require a more traditional SSTL-type of bus. Figure 7: Typical ODT Configuration for DRAM READs Active Module One Module Populated System Controller VDDQ 150Ω RCVR 150Ω VSSQ Active Module Standby Module Two Modules Populated VDDQ 150Ω System Controller 150Ω VDDQ VSSQ 300Ω RCVR 300Ω VSSQ Figure 8: ODT vs. SSTL Termination Comparison for READs ODT Termination 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 - 0.1 Input Voltage (V) One Single-Rank Module Input Voltage (V) SSTL Termination 1.9 0 0.75 1.5 2.25 3 3.75 0.3 0.1 - 0.1 0 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 - 0.1 1.5 2.25 3 3.75 1.9 0 0.75 1.5 2.25 3 Time (nanoseconds) 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 0.75 Time (nanoseconds) Input Voltage (V) Two Dual-Rank Modules (Second Module) Input Voltage (V) Time (nanoseconds) 6 3.75 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 - 0.1 0 0.75 1.5 2.25 3 3.75 Time (nanoseconds) Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality ODT WRITEs Termination Values As illustrated in Figures 5 and 7, on-die termination can have different values, depending on the system configuration. This is controlled via the extended mode register (EMR). (See Figure 9.) If extended mode bits 2 and 6 are both “0,” the on-die termination is disabled on the DRAM. Three additional options include selecting either an RTT equivalent value of 50 ohms (100 ohms pull-up and 100 ohms pull-down), or 75 ohms (150 ohms pull-up and 150 ohms pull-down) or an RTT equivalent of 150 ohms (300 ohms pull-up and 300 ohms pull-down). The proper termination value is selected to optimize signal integrity at minimum power, as shown in Figures 6 and 8. Figure 9: Extended Mode Register Control for On-Die Termination BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EMR 0* out RDQS DQS# OCD Program RTT Posted CAS RTT ODS DLL Address Bus Extended Mode Register *E13 (A13) is reserved for future use and must be programmed to “0”. Figure 10: E6 E2 RTT (nominal) 0 0 RTT disabled 0 1 75 ohms 1 0 150 ohms 1 1 50 ohms E15 E14 0 0 Mode Register Mode Register (MR) 0 1 Extended Mode Register (EMR) 1 0 Extended Mode Register (EMR2) 1 1 Extended Mode Register (EMR3) Rank-to-Rank ODT Control – READs Clock Module in First Slot CMD READ 2 tCK 2.5 tCK ODT DQ Termination On CL = 3 Data-Out CL = 3 Module in Second Slot READ CMD ODT 2 tCK 2.5 tCK DQ Termination On Data-Out RTT eff 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN RTT 7 RTT/2 RTT Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality ODT WRITEs On-Die Termination Control in Active Mode After the proper value of termination is selected, the system controller must switch the termination on and off at the proper times. While the DRAM is in active or fast exit power-down mode, the termination turns on two clock cycles after the ODT signal is registered HIGH, as shown in Figure 10. For module 2, the ODT signal is latched HIGH on the same clock cycle as the READ command to module 1. Two clock cycles later, the on-die termination on the module 2 DRAM turns on. To schedule on-die termination, ODT should be transitioned HIGH three clocks before the data is on the bus to ensure it is on prior to the preamble. To disable on-die termination, the ODT signal must be registered LOW by the clock. Then, two and a half cycles later, the termination turns off, as shown in Figure 10. The extra half cycle allows the termination to remain enabled until after the data has stopped driving on the bus. Thus, the ODT pin can be registered LOW two clock cycles prior to the end of the data burst on the bus. On-Die Termination Control in Power-Down Asynchronous operations are also associated with the ODT pin when the DRAM is in slow exit active power-down or precharge power-down mode. During this operation, the turn on and off time is an analog delay off the registration of the ODT signal. The timing isn’t as critical since data can’t be read from or written to a rank that is in power-down mode. Thus, the system only has to enable the termination to form a window around the data from the other ranks. See the DDR2 data sheet for additional information on specific ODT timings and restrictions. On-Die Termination Control in Self Refresh During self refresh, the DRAM disables on-die termination and ignores the ODT pin, regardless of the values programmed into the EMR. A memory subsystem that is in self refresh mode cannot read or write data, so disabling on-die termination does not affect signal quality, and it allows the DRAM to minimize power consumption. Off-Chip Driver (OCD) The Off-Chip Driver (OCD) function is no longer required on DDR2 devices and is not supported on Micron devices. During initialization, the OCD mode register should be enabled to its default setting. Please reference specific data sheets for the initialization sequence instructions. 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality Additional Mode Register Changes Additional Mode Register Changes Mode Register (MR) Some of the additional features and functionality that have been added to DDR2 require changes in the MR and the EMR. Figure 11 highlights the changes made in the MR for DDR2. These include support for burst lengths of 4 and 8 only, a modification of the sequential interleave mode, and extension of the CAS latencies supported. In addition, a low-power definition for active power-down mode and a write recovery parameter have been added. Figure 11: Mode Register Changes for DDR2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR 0* PD WR DLL TM CAS Latency BT Burst Length M15 M14 M7 Mode Register Mode Mode Register M2 M1 M0 Burst Length 0 0 Mode Register (MR) 0 Normal 0 0 0 Reserved 0 1 Extended Mode Register (EMR) 1 Test 0 0 1 Reserved 1 0 Extended Mode Register (EMR2) 0 1 0 4 1 1 Extended Mode Register (EMR3) DLL Reset 0 1 1 8 0 No 1 0 0 Reserved 1 Yes 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M12 Power-Down Mode 0 Fast Exit (Normal) 1 Slow Exit (Low Power) M6 M5 M4 M3 Burst Type 0 0 0 Reserved 0 0 0 Reserved 0 Sequential 0 0 1 2 0 0 1 Reserved 1 Interleaved 0 1 0 3 0 1 0 2 0 1 1 4 0 1 1 3 1 0 0 5 1 0 0 4 1 0 1 6 1 0 1 5 1 1 0 Reserved 1 1 0 6 1 1 1 Reserved 1 1 1 Reserved M11 M10 M9 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN Address Bus Write Recovery 9 CAS Latency *M13 (A13) is reserved for future use and must be programmed to “0”. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality Additional Mode Register Changes CAS Latency DDR2 operates at higher clock frequencies than DDR SDRAM. Figure 13 illustrates the difference between a DDR READ at a 266 MHz data rate and a DDR2 READ at a 533 MHz data rate. The latency of each device is the same, approximately 15ns. For the DDR SDRAM, this is equivalent to two clocks; for DDR2, four clocks. As clock rates increase, the number of latencies possible must also increase. Figure 12 shows the latencies supported for various clock rates and CAS latencies. The DRAM latency is calculated as tCK × CAS latency supported. DDR2 is targeted at latencies of 12ns–20ns. If the DRAM latency is beyond this range, it is unlikely that a system will utilize that latency due to lost system performance. Likewise, it is unlikely the DRAM will meet latencies below 12ns due to DRAM core performance. To support DDR2’s higher clock rates, the CAS latency programmability has been set at three to six clocks. Half clock latencies are not supported. Figure 12: DDR2 READ Latencies READ Latency (clocks) RL tCK DDR2-400 DDR2-533 5ns 3 4 5 6 15ns 20ns 25ns 30ns 15ns 18.75ns 22.5ns 3.75ns 11.25ns DDR2-667 3ns 9ns 12ns 15ns 18ns DDR2-800 2.5ns 7.5ns 10ns 12.5ns 15ns Unlikely operation Note: Refer to individual datasheets to determine which latencies are supported for each speed grade and part number combination. WRITE Latency DDR2 also includes a modification to the WRITE latency specification. Figure 14 illustrates the differences between DDR and DDR2 SDRAM. DDR SDRAM has a WRITE latency of one clock, which means that approximately one clock after a WRITE command, the DRAM starts clocking in data. However, given the increase in clock rates, this time is very short, making it difficult for the DRAM to prepare to capture data. DDR2 enables the WRITE latency to track the CAS latency minus one clock. Figure 14 shows a 533 MHz DDR2 device with CAS latency set to four clocks. The WRITE latency is set to CAS latency – 1 clock, which is three clocks. The modification in WRITE latency allows more time for DRAM input buffers to support higher clock frequencies. Additionally, tracking WRITE latency with CAS latency simplifies system read-to-write timings. 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality Additional Mode Register Changes Figure 13: DDR2 vs. DDR READ DDR READ at 266 MHz READ CL = 2 @ tCK = 7.5ns is 15ns Data-Out DDR2 READ at 533 MHz READ CL = 4 @ tCK = 3.75ns is 15ns Data-Out Figure 14: DDR2 vs. DDR WRITE DDR WRITE at 266 MHz WRITE Equivalent WL = 1 @ tCK = 7.5ns is 7.5ns Data-In DDR2 WRITE at 533 MHz WRITE WL = 3 @ tCK = 3.75ns is 11.25ns (assuming CL = 4 and AL = 0) Data-In Sequential Interleave To support the high data rates of DDR2, the DRAM must have the flexibility to prefetch four bits of data from the core instead of only two. Consequently, support for a burst length of two has been dropped. Prefetching four bits, however, makes it difficult to support the traditional sequential interleave mode for DRAM burst lengths of eight. The sequential burst orders for DDR2 are shown in Figure 15. For burst lengths of four, there is no change from the DDR specification. However, for burst lengths of eight, a new burst type called sequential nibble is implemented. During sequential nibble operation, the DRAM breaks the eight-bit burst into two separate four-bit nibbles. The sequential 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality Additional Mode Register Changes interleave is executed on the nibble with the starting column location, followed by a similar sequential interleave on the other nibble using the starting location that is equal to the lower bits of the starting column. Using the nibble sequential burst, a system requiring sequential interleave can take advantage of the eight-bit burst and still use any starting column within the burst. The interleave burst ordering for DDR2 is the same as DDR. Figure 15: Sequential Burst Ordering Burst Length 4 8 Starting Column (A2, A1, A0) 000 001 010 011 000 001 010 011 100 101 110 111 Order of Accesses Within a Burst Burst Type = Sequential DDR DDR2 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 0,1,2,3,4,5,6,7 1,2,3,4,5,6,7,0 2,3,4,5,6,7,0,1 3,4,5,6,7,0,1,2 4,5,6,7,0,1,2,3 5,6,7,0,1,2,3,4 6,7,0,1,2,3,4,5 7,0,1,2,3,4,5,6 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 0,1,2,3,4,5,6,7 1,2,3,0,5,6,7,4 2,3,0,1,6,7,4,5 3,0,1,2,7,4,5,6 4,5,6,7,0,1,2,3 5,6,7,4,1,2,3,0 6,7,4,5,2,3,0,1 7,4,5,6,3,0,1,2 Different 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality Extended Mode Register (EMR) Active Power-Down Mode Active power-down mode enables a system designer to optimize power and performance. In this mode, the transition timing between power-down exit and the next command is dependent upon the power-down mode bit. If the power-down mode is set to fast exit mode, there is a two-clock delay from active power-down exit to any command (including READ). Alternatively, the power-down mode bit may be set to slow exit mode, which extends the power-down exit delay to six clocks, minus the additive latency to a READ command. Active power-down slow exit is the same as the precharge power-down time during all operations of the DRAM. The power-down mode bit is ignored in precharge power-down. (See Table 2.) Write Recovery Write recovery (WR) must be correctly entered into the MR to ensure proper DRAM operation. Write recovery is measured from the end of write data to the time when the internal auto precharge operation starts (see Figure 16). To correctly set the MR, WR is calculated as tWR/tCK, rounded up to the next integer. Extended Mode Register (EMR) Additional enhancements have been made to the EMR, as shown in Figure 17. ODT was discussed previously, but other enhancements include additive latency, output disable, and DQ strobe configurability. Table 2: DDR2 Active Power-Down Mode Options MR (bit 12) PD Mode Delay from CKE HIGH to Command 0 Fast Exit DDR2-400, tXARD = 6-AL in clocks DDR2-533, tXARD = 6-AL in clocks DDR2-667, tXARD = 7-AL in clocks DDR2-800, tXARD = 8-AL in clocks 1 Slow Exit Ignored Active PowerDown Precharge Power-Down 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 13 tXARD = 2 clocks for all speeds 2 clocks to any non-READ command Additive latency – 6 clocks to READ need to add 667 and 800 specs Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality Extended Mode Register (EMR) Figure 16: DDR2 Write-to-Precharge Timing CK# T0 T1 T2 T3 T4 T5 NOP ACT NOP WRITE1 NOP NOP T5n T6 T6n T7 T8 T9 NOP NOP NOP CK CKE COMMAND RA ADDRESS NOP Col n Note 2 A10 RA BA0, BA1 Bank x Bank x tRCD WR3 WL = 2 tRP tRAS tDQSS (NOM) DQS,DQS# DI b DQ DM TRANSITIONING DATA DON’T CARE NOTE: 1. Burst length = 4, additive latency = 0, and WRITE latency = 2. 2. Enable auto precharge. t t 3. WR is programmed via EMR [11,10,9] and is calculated by dividing WR (ns) by CK and rounding up to the next integer value. Figure 17: Extended Mode Register BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EMR 0* out RDQS DQS# OCD Program RTT Posted CAS RTT ODS DLL E12 Output Enable E11 RDQS Enable RTT (nominal) E0 DLL Enable 0 0 RTT disabled 0 Enable (Normal) 0 1 75 ohms 1 Disable (Test/Debug) E1 Output Drive Strength 0 Full: Target 18 ohms 1 Weak: Target 40 ohms No 0 No 0 Enable 1 0 150 ohms 1 Yes 1 Yes 1 Disable 1 1 50 ohms E15 E14 Mode Register E9 E8 E7 OCD Operation 0 0 Mode Register (MR) 0 0 0 OCD calibration mode exit 0 1 Extended Mode Register (EMR) 0 0 1 Drive (1) pull-up 1 0 Extended Mode Register (EMR2) 0 1 0 Drive (0) pull-down 1 1 Extended Mode Register (EMR3) 1 0 0 OCD enter adjust mode 1 1 1 OCD calibration default 14 Extended Mode Register E6 E2 0 *E13 (A13) is reserved for future use and must be programmed to “0”. 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN E10 DQS# Enable Address Bus E5 E4 E3 Posted CAS Additive Latency (AL) 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality Extended Mode Register (EMR) Additive Latency Figure 18 shows an example of DDR2 bank interleave READs. During these accesses, a bank is opened with an ACTIVATE command. After tRCD is met, a READ with auto precharge command is issued and data is read out of the DRAM. As seen in Figure 18, there are times when a command cannot be issued at the optimal location because there is a command slot conflict. For example, ACT (to bank 2) must be delayed by one clock because the RD_AP (to bank 0) is already in that spot. The result is a gap in the output data. To improve system scheduling, DDR2 includes a mode register for additive latency. Using additive latency, the DRAM captures READ or WRITE commands but waits to execute them until the additive latency time expires. Figure 18: DDR2 READs With no Additive Latency DDR2 with Additive Latency = 0, CAS Latency = 4 Clock tRRD CMD/ ADD Data ACT B0,Rx ACT B1,Rx tRCD RD AP ACT RD AP B0,Cx B2,Rx B1,Cx CAS Latency RD AP B2,Cx Data-Out Data-Out Data-Out Gap in Data Figure 19 illustrates DRAM operation with two different additive latencies. The top figure shows an operation similar to DDR SDRAM using AL = 0 clocks. The bottom figure shows AL = tRCD - 1 clock. In this configuration, the ACTIVATE and READ commands can be issued back-to-back. The DRAM holds the READ command for the additive latency time and then executes it on the same clock as the top diagram. With additive latency set to tRCD – 1 clock, a simplified read system timing can be attained. Figure 20 assumes tRCD = 4 clocks. Thus, additive latency is set to three clocks. This allows the READ command to directly follow the ACTIVATE command. With a burst length of four, which requires two clocks to burst data, the two clocks for the back-toback ACT and RD_AP commands match perfectly, enabling data to be continuously output from the DRAM without gaps. The simplicity of system bus scheduling is expected to be particularly popular in applications that have high page misses. 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality Extended Mode Register (EMR) Figure 19: DDR2 With Additive Latency DDR2 with Additive Latency = 0 Clock CMD/ ADD ACT B0,Rx RD B0,Cx tRCD Data CAS Latency Data-Out DDR2 with Additive Latency = (tRCD - 1) Clock CMD/ ADD ACT B0,Rx Data RD B0,Cx Additive Latency CAS Latency Data-Out tRCD READ Latency Figure 20: DDR2 READs Using Additive Latency Clock tRRD CMD/ ADD Data ACT RD AP ACT RD AP ACT RD AP B0,Rx B0,Cx B1,Rx B1,Cx B2,Rx B2,Cx Additive Latency CAS Latency Data-Out Data-Out Data-Out No Gap in Data READ Latency 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality Extended Mode Register (EMR) Figure 21: Extended Mode Register for DQS Configuration BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EMR 0* out RDQS DQS# OCD Program RTT Posted CAS RTT ODS DLL E11 RDQS Enable E10 Address Bus Extended Mode Register DQS Enable 0 No 0 Enable 1 Yes 1 Disable Mode Register E15 E14 0 0 Mode Register (MR) 0 1 Extended Mode Register (EMR) 1 0 Extended Mode Register (EMR2) 1 1 Extended Mode Register (EMR3) DQS Configuration The EMR also allows configuration of the DQ strobes for multiple system configurations. Figure 21 highlights the areas of the extended mode register that configure the strobes. Bit 10 switches the strobes between differential and single-ended mode, and bit 11 can be used to enable the redundant strobe on the x8 device. Single/Differential Data Strobe DDR2 supports single-ended strobes in the same manner as DDR SDRAM, as shown in Figure 22. DDR2 SDRAM also supports differential strobes. If differential strobes are enabled, DQS operates the same as in single-ended mode with the addition of DQS# operating as the complement in differential signals. For READs the DRAM will output both signals, as shown in Figure 23. For WRITEs, the system must provide both input signals. The use of differential strobes is system-dependent and may enable improved system timings due to reduced crosstalk and less simultaneous switching noise on the strobe output drivers. Figure 22: Single-Ended Strobe Clock DQS Read Data 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality Extended Mode Register (EMR) Figure 23: Differential Strobe Clock DQS#, DQS Read Data Redundant DQS (RDQS) The RDQS option is only available on the x8 DRAM and is required when mixing x4 and x8 DRAM devices in the same system. An example of this is shown in Figure 24. Because the x8 DRAM has only one DQS input for the eight-bit byte and the x4 has a DQS for each four-bit nibble, the loading of the DQS lines is different when the devices are mixed in the same system. RDQS reduces this effect. If devices are mixed in the system, the signal routing from the second x4 DRAM is routed to the RDQS pin on the x8 DRAM. During WRITEs, the loading and termination on the RDQS is the same as the DQS signals, so all signaling is matched for the x4 DRAMs. For READs, the x8 DRAM drives the RDQS output the same way it does the DQS. Thus, the controller can use RDQS to capture read data on a nibble device and the x8 DRAM emulates the functionality of the x4. Systems mixing x4 and x8 devices can utilize RDQS signals to improve timing. RDQS functionality is only an option on the x8 DRAM. Additionally, if RDQS is enabled, the data mask functionality of the x8 DRAM is disabled. Figure 24: x4 and x8 Devices in Same System x4 DRAM Controller 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN DQ0 DQ1 DQ2 DQ3 DQS DQ0 DQ1 DQ2 DQ3 DQS DQ4 DQ5 DQ6 DQ7 DQS DQ0 DQ1 DQ2 DQ3 DQS DQ8 DQ9 DQ10 DQ11 DQS DQ0 DQ1 DQ2 DQ3 DQS DQ12 DQ13 DQ14 DQ15 DQS DQ0 DQ1 DQ2 DQ3 DQS x8 DRAM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS RDQS/DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS RDQS/DM 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality Conclusion Output Disable For DDR SDRAM, it can be difficult to measure IDD values in system environments. All IDD values are specified with IOUT = 0mA, which is challenging to accomplish in the system. Thus, DDR2 has an option to disable the output drivers from the EMR. If the output disable option is set, the last stage of the output driver is disabled. WRITEs are completed normally and READs execute except for the final output stage. Thus, IDD measurements within a system environment can be made. Conclusion DRAM architecture changes enable twice the bandwidth without increasing the demand on the DRAM core and while keeping power low. The evolutionary changes enable DDR2 to operate between 400 MHz, 533 MHz ,667 MHz, and 800 MHz. A summary of the functionality changes is shown in Table 3 on page 20. Modifications to the DRAM architecture include shortened row lengths for reduced activation power, burst lengths of four and eight for improved data bandwidth capability, and the addition of eight banks in 1Gb densities and above. New signaling features include ODT and OCD. ODT provides improved signal quality due to better system termination on the data signals. Modifications were also made to the mode register and extended mode register, including CAS latency, additive latency, and programmable data strobes. 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. TN-47-02 DDR2 Offers New Features/Functionality Conclusion Table 3: Feature Overview Feature/Option Data Transfer Rate DDR DDR2 266, 333, 400 MHz 400, 533, 667, 800 MHz TSOP and FBGA FBGA only Operating Voltage 2.5V 1.8V I/O Voltage 2.5V 1.8V I/O Type SSTL_2 SSTL_18 Densities 64Mb–1Gb 256Mb–2Gb Internal Banks 4 4 and 8 Prefetch (MIN Write Burst) 2 4 CAS Latency (CL) 2, 2.5, 3 clocks 3, 4, 5, 6 clocks no 0, 1, 2, 3, 4 clocks Package Additive Latency (AL) READ Latency CL AL + CL WRITE Latency fixed READ latency - 1 clock x4/ x8/ x16 x4/ x8/ x16 none none bidirectional strobe (single ended) bidirectional strobe (single ended or differential) with RDQS On-Die Termination none selectable Burst Lengths 2, 4, 8 4, 8 I/O Width Output Calibration Data Strobes ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 [email protected] www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef80debf27 TN4702.fm - Rev. A 6/06 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved.