16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM SYNCHRONOUS DRAM MODULE MT2LSDT432U – 16MB MT4LSDT832UD – 32MB MT4LSDT1632UD – 64MB MT4LSDT3232UD – 128MB For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/modules Features Figure 1: 100-Pin DIMM (MO–161) • 100-pin, dual in-line memory module (DIMM) • PC 100- and PC133-compliant • 16MB (4 Meg x 32) , 32MB (8 Meg x 32), 64MB (16 Meg x 32), and 128MB (32 Meg x 32) • Utilizes 125 MHz and 133 MHz SDRAM components • Single +3.3V power supply • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge and Auto Refresh Modes 16MB, 32MB, and 64MB modules; 64ms, 4,096-cycle refresh (15.625µs refresh interval); 128MB modules; 64ms, 8,192-cycle refresh (7.81µs refresh interval) • LVTTL-compatible inputs and outputs • Serial Presence-Detect (SPD) • Gold edge contacts Table 1: Standard 1.00in. (25.40mm) Options Marking • Package 100-pin DIMM (standard) 100-pin DIMM (lead-free) • Timing (Cycle Timing) 7.5ns (133 MHz) 8ns (125 MHz) 10ns (100 MHz) • PCB Standard 1.00in. (25.40mm) Timing Parameters G Y -75 -8 -10 CL = CAS (READ) Latency ACCESS TIME SPEED CLOCK SETUP GRADE FREQUENCY CL = 2 CL = 3 TIME -75 -8 -10 Table 2: 133 MHz 125 MHz 100 MHz 5.4ns 6ns 9ns 5.4ns 6ns 7.5ns HOLD TIME 1.5ns 2ns 2ns 0.8ns 1ns 1ns Address Table MODULE DENSITY Refresh Count Device Banks Device Configuration Device Row Addressing Device Column Addressing Module Ranks 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 16MB 32MB 64MB 128MB 4K 4K 4K 8K 4 (BA0–BA1) 4 (BA0–BA1) 4 (BA0–BA1) 4 (BA0–BA1) 64Mb (4 Meg x 16) 64Mb (4 Meg x 16) 128Mb (8 Meg x 16) 4K (A0–A11) 4K (A0–A11) 4K (A0–A11) 256 (A0–A7) 256 (A0–A7) 2 (S0#, S2#, S1#, S3#) 512 (A0–A8) 2 (S0#, S2#, S1#, S3#) 256Mb (16 Meg x 16) 8K (A0–A12) 512 (A0–A8) 2 (S0#, S2#, S1#, S3#) 1 (S0#, S2#) 1 ©2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 3: Part Numbers PART NUMBER1 MT2LSDT432UG-75__ MT2LSDT432UY-75__ MT2LSDT432UG-8__ MT2LSDT432UY-8__ MT2LSDT432UG-10__ MT2LSDT432UY-10__ MT4LSDT832UDG-75__ MT4LSDT832UDY-75__ MT4LSDT832UDG-8__ MT4LSDT832UDY-8__ MT4LSDT832UDG-10__ MT4LSDT832UDY-10__ MT4LSDT1632UDG-75__ MT4LSDT1632UDY-75__ MT4LSDT1632UDG-8__ MT4LSDT1632UDY-8__ MT4LSDT1632UDG-10__ MT4LSDT1632UDY-10__ MT4LSDT3232UDG-75__ MT4LSDT3232UDY-75__ MT4LSDT3232UDG-8__ MT4LSDT3232UDY-8__ MT4LSDT3232UDG-10__ MT4LSDT3232UDY-10__ DENSITY CONFIGURATION SYSTEM BUS SPEED 16MB 16MB 16MB 16MB 16MB 16MB 32MB 32MB 32MB 32MB 32MB 32MB 64MB 64MB 64MB 64MB 64MB 64MB 128MB 128MB 128MB 128MB 128MB 128MB 4 Meg x 32 4 Meg x 32 4 Meg x 32 4 Meg x 32 4 Meg x 32 4 Meg x 32 8 Meg x 32 8 Meg x 32 8 Meg x 32 8 Meg x 32 8 Meg x 32 8 Meg x 32 16 Meg x 32 16 Meg x 32 16 Meg x 32 16 Meg x 32 16 Meg x 32 16 Meg x 32 32 Meg x 32 32 Meg x 32 32 Meg x 32 32 Meg x 32 32 Meg x 32 32 Meg x 32 133 MHz 133 MHz 125 MHz 125 MHz 100 MHz 100 MHz 133 MHz 133 MHz 125 MHz 125 MHz 100 MHz 100 MHz 133 MHz 133 MHz 125 MHz 125 MHz 100 MHz 100 MHz 133 MHz 133 MHz 125 MHz 125 MHz 100 MHz 100 MHz NOTE: 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT2LSDT432UG-8B1. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 4: Pin Assignment (100-Pin DIMM Front) Table 5: Pin Assignment (100-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 2 3 4 5 6 7 8 9 10 11 12 51 52 53 54 55 56 57 58 59 60 61 62 Vss DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQMB0 Vss 13 14 15 16 17 18 19 20 21 22 23 24 25 A0 A2 A4 A6 A8 A10 BA1 A12 VDD DNU RFU RFU CK0 26 27 28 29 30 31 32 33 34 35 36 37 Vss CKE0 WE# S0# S2# VDD NC NC NC NC Vss DQMB2 38 39 40 41 42 43 44 45 46 47 48 49 50 DQ16 DQ17 DQ18 DQ19 VDD DQ20 DQ21 DQ22 DQ23 Vss SDA SCL VDD Vss DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 DQ14 DQ15 DQMB1 Vss 63 64 65 66 67 68 69 70 71 72 73 74 75 A1 A3 A5 A7 A9 BA0 A11 NC VDD RAS# CAS# RFU CK1 76 77 78 79 80 81 82 83 84 85 86 87 Vss CKE1 DNU S1# S3# VDD NC NC NC NC Vss DQMB3 88 89 90 91 92 93 94 95 96 97 98 99 100 DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 Vss SA0 SA1 SA2 Figure 2: Module Layout Front View Back View U1 (Not populated for the 16MB module) U4 U2 U3 U5 PIN 1 PIN 23 PIN 50 PIN100 Indicates a VDD pin 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 3 PIN 73 PIN 51 Indicates a VSS pin Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 6: Pin Descriptions Pin numbers may not correlate with symbols; for more information refer to the Pin Assignment tables on page 3 PIN NUMBERS SYMBOL TYPE DESCRIPTION 28, 72, 73 RAS#, CAS#, WE# Input 25, 75 CK0, CK1 Input 27, 77 CKE0, CKE1 Input 29, 30, 79, 80 S0#–S3# Input 11, 37, 61, 87 DQMB0–DQMB3 Input 19, 68 BA0, BA1 Input 13-18, 63-67, 69–70 A0–A12 Input 2–5, 7–10, 38–41, 43–46, 52–55, 57–60, 88–91, 93–96 6, 21, 31, 42, 50, 56, 71, 81, 92 1, 12, 26, 36, 47, 51, 62, 76, 86, 97 48 DQ0–DQ31 Input/ Output Command Inputs: RAS#, CAS# and WE# (along with S#) define the command being entered. Clock: CK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. Deactivating the clock provides POWER-DOWN and SELF REFRESH operation (all banks idle), or CLOCK SUSPEND operation (burst access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CK is disabled during power-down and self refresh modes, providing low standby power. Chip Select: S# enables (registered LOW) and disablse (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Input/Output Mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (after a two-clock latency) when DQMB is sampled HIGH during a READ cycle. Bank Address: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs: A0-A12 are sampled during the ACTIVE command (row-address A0-A12) and READ/WRITE command (column-address A0-A8, with A10 defining AUTO PRECHARGE) to select one location out of the memory array in the respective bank. A10 is sampled during a PRE-CHARGE command to determine if both banks are to be precharged (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data I/Os: Data bus. VDD Supply Power Supply: +3.3V ±0.3V. VSS Supply Ground. SDA Input/ Output 49 SCL Input 98-100 SA0–SA2 Input 23, 24, 74 22, 78 RFU DNU – – 32–35, 70, 82–85 NC – Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and data out of the presencedetect portion of the module. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Reserved for Future Use: These pins should be left unconnected. Do Not Use: These pins are not connected on this module but are assigned pins on the compatible DRAM version. Not connected. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Figure 3: Functional Block Diagram – 16MB S0# DQMB0 DQML CS# DQ DQ DQ DQ DQ DQ DQ U1 DQ DQMH DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 S2# DQMB2 DQML CS# DQ DQ DQ DQ DQ DQ DQ U2 DQ DQMH DQ DQ DQ DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 RAS# RAS#: SDRAMs CAS# CAS#: SDRAMs CKE0 CKE: SDRAMs WE# WE#: SDRAMs A0-A11 CK0 6.8pF CK1 A0-A11: SDRAMs BA0 BA0: SDRAMs BA1 BA1: SDRAMs U1 U2 10pF SPD SCL VDD SDRAMs VSS SDRAMs WP A0 A1 A2 SDA SA0 SA1 SA2 Standard modules use the following SDRAM devices: MT48LC8M16A2TG NOTE: 1. All resistor values are 10Ω. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/ numberguide. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN U5 Lead-free modules use the following SDRAM devices: MT48LC8M16A2P 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Figure 4: Functional Block Diagram – 32MB, 64MB, 128MB S1# S0# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQML CS# DQ DQ DQ DQ DQ DQ DQ U1 DQ DQMH DQ DQ DQ DQ DQ DQ DQ DQ DQML CS# DQ DQ DQ DQ DQ DQ DQ U3 DQ DQMH DQ DQ DQ DQ DQ DQ DQ DQ DQML CS# DQ DQ DQ DQ DQ DQ DQ U2 DQ DQMH DQ DQ DQ DQ DQ DQ DQ DQ DQML CS# DQ DQ DQ DQ DQ DQ DQ U4 DQ DQMH DQ DQ DQ DQ DQ DQ DQ DQ S3# S2# DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 RAS# RAS#: SDRAMs CAS# CAS#: SDRAMs CKE0 CKE: SDRAMs U1-U2 CKE1 CKE: SDRAMs U3-U4 WE# WE#: SDRAMs A0-A11 (32MB, 64MB) A0-A11: SDRAMs A0-A12 (128MB) A0-A12: SDRAMs BA0 BA0: SDRAMs BA1 BA1: SDRAMs CK0 6.8pF SDRAMs VSS SDRAMs 6.8pF SPD SCL U5 A0 A1 A2 SDA SA0 SA1 SA2 Standard modules use the following SDRAM devices: MT48LC8M16A2TG (32MB); MT48LC16M16A2TG (64MB); MT48LC32M16A2TG (128MB) NOTE: 1. All resistor values are 10Ω. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/ numberguide. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN U3 U4 CK1 WP VDD U1 U2 Lead-free modules use the following SDRAM devices: MT48LC8M16A2P (32MB); MT48LC16M16A2TG (64MB); MT48LC32M16A2TG (128MB) 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM General Description Serial Presence-Detect Operation The MT2LSDT432U, MT4LSDT832UD, MT4LSDT1632UD, and MT4LSDT3232UD are high-speed CMOS, dynamic random-access, 16MB, 32MB, 64MB, and 128MB memory modules organized in a x32 configuration. These modules use SDRAM devices which are internally configured as quad-bank DRAMs with a synchronous interface (all signals are registered on the positive edge of the clock signal CK). Read and write accesses to the SDRAM module are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed. BA0, BA1 select the device bank; A0–A11 (16MB, 32MB, and 64MB) or A0–A12 (128MB). The address bits registered coincident with the READ or WRITE command (A0–A7 for 16MB and 32MB; A0–A8 for 64MB and 128MB) are used to select the starting device column location for the burst access. These modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. These modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one device bank while accessing one of the other three device banks will hide the PRECHARGE cycles and provide seamless, high-speed, random access operation. These modules are designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs, outputs, and clocks are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal device banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 64Mb, 128Mb, or 256Mb SDRAM component data sheets. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN These modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All device banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. Mode Register Definition The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 5, Mode Register Definition Diagram, on page 8. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Figure 5: Mode Register Definition Diagram Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. For the 128MB module, address A12 (M12) is undefined but should be driven LOW during loading of the mode register. The mode register must be loaded when all device banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. 16MB, 32MB, and 64MB Modules A11 A10 A9 A6 A7 A5 A4 A3 A1 A2 A0 Address Bus 11 9 10 8 6 7 Reserved* WB Op Mode 5 4 3 CAS Latency 1 2 BT 0 Mode Register (Mx) Burst Length *Should program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices. 128MB Module A12 12 Burst Length A11 A10 A9 A8 11 8 10 9 A6 A7 7 Reserved* Reserved* WB Op Mode Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 5, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in Table 7, Burst Definition, on page 9. The block is uniquely selected by A1–Ai when the burst length is set to two; by A2–Ai when the burst length is set to four; and by A3–Ai when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block See note 7 of Table 7, Burst Definition, on page 9 for values of Ai. Full-page bursts wrap within the page if the boundary is reached, as shown in Table 7, Burst Definition, on page 9. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN A8 6 A5 A4 5 A3 4 CAS Latency 3 BT 1 2 A0 0 Address Bus Mode Register (Mx) Burst Length Burst Length *Should program M11, M10 = “0, 0” to ensure compatibility with future devices. M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Burst Type M3 0 Sequential 1 Interleaved M6 M5 M4 8 A1 A2 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - All other states reserved M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 7: BURST LENGTH Figure 6: CAS Latency Diagram Burst Definition ORDER OF ACCESSES WITHIN A BURST STARTING COLUMN ADDRESS A0 2 0 1 A1 A0 0 0 4 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 8 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Full Page n = A0–A8 (512) (location 0–y) TYPE = SEQUENTIAL TYPE = INTERLEAVED 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 T0 T1 T2 T3 READ NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CAS Latency = 2 T0 T1 T2 T3 COMMAND READ NOP NOP NOP tLZ 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2, Cn+3, Cn+4..., ...Cn-1, Cn... 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported tOH DOUT DQ tAC CAS Latency = 3 DON’T CARE UNDEFINED CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ will start driving after T1 and the data will be valid by T2, as shown in Figure 6, CAS Latency Diagram. Table 8, CAS Latency Table, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. NOTE: 1. For a burst length of two, A1–Ai select the block-oftwo burst; A0 selects the starting column within the block. 2. For a burst length of four, A2–Ai select the block-offour burst; A0-A1 select the starting column within the block. 3. For a burst length of eight, A3–Ai select the block-ofeight burst; A0-A2 select the starting column within the block. 4. For a full-page burst, the full row is selected, and A0–Ai select the starting column. 5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. For a burst length of one, A0–Ai select the unique column to be accessed, and Mode Register bit M3 is ignored. 7. Ai = A7 for 16MB and 32MB; Ai = A8 for 64MB and 128MB 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN T4 CLK 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Operating Mode Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Table 8: ALLOWABLE OPERATING CLOCK FREQUENCY (MHz) Write Burst Mode When M9 = 0, the burst length programmed via M0– M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN CAS Latency Table 10 SPEED CAS LATENCY = 2 CAS LATENCY = 3 -75 -8 -10 ≤ 100 ≤ 100 ≤ 100 ≤ 133 ≤ 133 ≤ 100 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Commands Table 9, Commands and DQMB Operation Truth Table provides a general reference of available commands. For a more detailed description of commands Table 9: and operations, refer to the 64Mb, 128Mb, or 256Mb SDRAM component data sheet. Commands and DQMB Operation Truth Table CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) S# RAS# CAS# WE# DQMB COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) H L L L X H L H X H H L X H H H X X X WRITE (Select bank and column, and start WRITE burst) L H L L BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z L L L H L L H H L L L H L/H7 X X X L – – L – – L – – L – – X L H L/H7 ADDR DQS NOTES X X Bank/Row Bank/Col X X X X 1 2 Bank/Col Valid 4 X Code X Active X X 3 4, 5 Op-Code X – Active – High-Z 6 7 7 NOTE: 1. A0–A11(32MB) or A0–A12 (64MB, 128MB, and 128MB) provide row address and BA0 and BA1 determine which bank is made active. 2. A0–A8 (16MB and 32MB) or A0–A8 (64MB and 128MB) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0 and BA1 determine which bank is being read from or written to. 3. A10 LOW: BA0 and BA1 determine which bank is being precharged. A10 HIGH: both banks are precharged and BA0 and BA1 are “Don’t Care.” 4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 6. A0–A11 (32MB) or A0–A12 (64MB, 128MB, and 128MB) define the op-code written to the Mode Register. 7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +4.6V Operating Temperature TOPR (Commercial - ambient) . . . . . . 0°C to +65°C Storage Temperature (plastic) . . . . . . -55°C to +150°C Table 10: DC Electrical Characteristics and Operating Conditions – 16MB Notes: 1, 6; VDD = +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) Command and Address CK, DQMB S# DQ OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V ≤ VOUT ≤ VDD OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) SYM MIN MAX UNITS VDD VIH VIL II 1 II 2 II 3 IOZ 3 2 -0.3 -10 -10 -5 -5 3.6 VDD + 0.3 0.4 10 10 5 5 V V V µA µA µA µA VOH VOL 2.4 – – 0.4 V V NOTES 22 22 33 33 Table 11: DC Electrical Characteristics and Operating Conditions – 32MB, 64MB, 128MB Notes: 1, 6; notes appear on page 18; VDD = +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) Command and Address CK, DQMB S# DQ OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V ≤ VOUT ≤ VDD OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 12 SYM MIN MAX UNITS VDD VIH VIL II1 II2 II3 IOZ 3 2 -0.3 -20 -10 -5 -10 3.6 VDD + 0.3 0.8 20 10 5 10 V V V µA µA µA µA VOH VOL 2.4 – – 0.4 V V NOTES 22 22 33 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 12: IDD Specifications and Conditions – 16MB Notes: 1, 6, 11, 13; notes appear on page 18; VDD = +3.3V ±0.3V MAX PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; RC = RC (MIN); CAS latency = 3 STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle STANDBY CURRENT: Active Mode; CKE = HIGH; S3# = HIGH; All banks active after tRCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All banks active; CAS latency = 3 t AUTO REFRESH CURRENT: RC = tRC (MIN); CL = 3 t CKE = HIGH; S# = HIGH RC = 15.625µs; CL = 3 SELF REFRESH CURRENT: CKE ≤ 0.2V SYM -75 -8 -10 UNITS NOTES IDD1 230 190 180 mA IDD2 IDD3 4 90 4 70 6 60 mA mA IDD4 280 240 210 mA IDD5 IDD6 IDD7 420 6 2 380 80 2 340 70 4 mA mA mA 3, 18, 19, 29 29 3, 12, 19, 29 3, 18, 19, 29 3, 12, 18, 19, 29, 30 -10 UNITS t 4 Table 13: IDD Specifications and Conditions – 32MB Notes: 1, 6, 11, 13; notes appear on page 18; VDD = +3.3V ±0.3V MAX PARAMETER/CONDITION SYM -75 -8 IDD1a 234 260 240 mA OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; RC = tRC (MIN); CAS latency = 3 8 8 12 mA IDD2b STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle a IDD3 104 140 120 mA STANDBY CURRENT: Active Mode; CKE = HIGH; S# = HIGH; All banks active after tRCD met; No accesses in progress 304 310 270 mA OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; IDD4a All banks active; CAS latency = 3 tRC = tRC (MIN); CL = 3 IDD5b 1,240 760 680 mA AUTO REFRESH CURRENT: t CKE = HIGH; S# = HIGH IDD6b 12 160 140 mA RC = 15.625µs; CL = 3 IDD7b 8 4 8 mA SELF REFRESH CURRENT: CKE ≤ 0.2V a - Value calculated as one module rank in this operating condition, and all other ranks in Power-Down Mode. b - Value calculated reflects all module ranks in this operating condition. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 13 NOTES 3, 18, 19, 29 29 3, 12, 19, 29 3, 18, 19, 29 3, 12, 18, 19, 29, 30 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 14: IDD Specifications and Conditions – 64MB Notes: 1, 6, 11, 13; notes appear on page 18; VDD = +3.3V ±0.3V MAX PARAMETER/CONDITION SYM -75 -8 -10 UNITS a IDD1 304 360 360 mA OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; RC = RC (MIN); CAS latency = 3 8 8 8 mA IDD2b STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle IDD3a 104 160 160 mA STANDBY CURRENT: Active Mode; CKE = HIGH; S# = HIGH; All banks active after tRCD met; No accesses in progress 304 360 360 mA OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; IDD4a All banks active; CAS latency = 3 t IDD5b 1,240 800 800 mA AUTO REFRESH CURRENT: RC = tRC (MIN); CL = 3 t CKE = HIGH; S# = HIGH IDD6b 12 180 180 mA RC = 15.625µs; CL = 3 b IDD7 8 6 6 mA SELF REFRESH CURRENT: CKE ≤ 0.2V a - Value calculated as one module rank in this operating condition, and all other ranks in Power-Down Mode. b - Value calculated reflects all module ranks in this operating condition. t NOTES 3, 18, 19, 29 29 3, 12, 19, 29 3, 18, 19, 29 3, 12, 18, 19, 29, 30 4 Table 15: IDD Specifications and Conditions – 128MB Notes: 1, 6, 11, 13; notes appear on page 18; VDD = +3.3V ±0.3V MAX PARAMETER/CONDITION SYM -75 -8 -10 UNITS 254 254 254 mA IDD1 OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; RC = tRC (MIN); CAS latency = 3 IDD2 8 8 8 mA STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle IDD3 84 84 84 mA STANDBY CURRENT: Active Mode; CKE = HIGH; S# = HIGH; All banks active after tRCD met; No accesses in progress 274 274 274 mA IDD4 OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All banks active; CAS latency = 3 tRC = tRC (MIN); CL = 3 1,080 1,080 1,080 mA IDD5 AUTO REFRESH CURRENT: CKE = HIGH; S# = HIGH t 14 14 14 mA IDD6 RC = 7.8125µs; CL = 3 IDD7 10 10 10 mA SELF REFRESH CURRENT: CKE ≤ 0.2V a - Value calculated as one module rank in this operating condition, and all other ranks in Power-Down Mode. b - Value calculated reflects all module ranks in this operating condition. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 14 NOTES 3, 18, 19, 29 29 3, 12, 19, 29 3, 18, 19, 29 3, 12, 18, 19, 29, 30 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 16: Capacitance – 16MB Note: 2; notes appear on page 18 PARAMETER SYMBOL MIN MAX UNITS CI 1 CI 2 CI 3 CI 4 CI 5 CIO 5 5 11.8 5 5 4 7.6 7.6 13.8 7.6 7.6 6 pF pF pF pF pF pF Input Capacitance: Address and Command Input Capacitance: CKE Input Capacitance: CK Input Capacitance: S# Input Capacitance: DQMB Input/Output Capacitance: DQ Table 17: Capacitance – 32MB, 64MB, and 128MB Note: 2; notes appear on page 18 PARAMETER Input Capacitance: Address and Command Input Capacitance: CKE Input Capacitance: CK Input Capacitance: S# Input Capacitance: DQMB Input/Output Capacitance: DQ 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 15 SYMBOL MIN MAX UNITS CI1 CI2 CI3 CI4 CI5 CIO 10 5 11.8 5 10 8 15.2 7.6 13.8 7.6 15.2 12 pF pF pF pF pF pF Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 18: SDRAM Component AC Electrical Characteristics Notes: 5, 6, 8, 9, 11, 31; notes appear on page 18 AC CHARACTERISTICS PARAMETER Access time from CLK (positive edge) -75 SYMBOL CL = 3 CL = 2 MIN -8 MAX MIN -10 MAX MIN MAX UNITS NOTES t 5.4 6 7.5 ns t 6 6 9 ns AC AC 0.8 1 1 27 ns Address hold time t Address setup time t AS 1.5 2 2 ns CLK high-level width t CH 2.5 3 3 ns CLK low-level width t CL 2.5 3 3 ns tCK 7.5 8 10 ns 22 t 22 Clock cycle time AH CL = 3 CK 10 10 15 ns CKE hold time tCKH 0.8 1 1 ns CKE setup time tCKS 1.5 2 2 ns CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 1 1 ns CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 2 2 ns Data-in hold time tDH 0.8 1 1 ns Data-in setup time tDS 1.5 2 2 ns CL = 2 Data-out high-impedance time CL=3 tHZ 5.4 5.4 6 ns 10 CL = 2 tHZ 5.4 6 6 ns 10 Data-out low-impedance time tLZ 1 1 2 ns Data-out hold time (load) tOH 3 3 3 ns 1.8 1.8 n/a ns 28 ns 32 Data-out hold time (no load) tOH ACTIVE to PRECHARGE command period tRAS 44 tRC 66 70 90 ns tRCAR 66 70 90 ns ACTIVE to READ or WRITE delay tRCD 20 20 30 ns Refresh period (8,192 cycles) t ACTIVEto ACTIVE command period AUTO REFRESH period N 120,000 50 64 REF 120,000 60 64 120,000 64 ms tRP 20 20 30 ns ACTIVE bank A to ACTIVE bank B command period Transition time tRRD 15 20 20 ns T 0.3 1 1 WRITE recovery time t WR Exit SELF REFRESH to ACTIVE command tXSR 1 CLK + 7ns 15 75 1 CLK + 7ns 15 90 1 CLK + 7ns 15 90 PRECHARGE command period 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN t 16 1.2 ns 7 – 23 ns ns 24 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM . Table 19: AC Functional Characteristics Notes: 5, 6, 8, 9, 11, 31; notes appear on page 18 PARAMETER SYMBOL -75 -8 -10 UNITS NOTES CCD 1 1 1 t CK 17 tCKED 1 1 1 tCK 14 CKE to clock enable or power-down exit setup mode tPED 1 1 1 tCK 14 DQM to input data delay tDQD 0 0 0 tCK 17 DQM to data mask during WRITEs t DQM 0 0 0 t 17 DQM to data high-impedance during READs t DQZ 2 2 2 t 17 WRITE command to input data delay t t READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CK CK DWD 0 0 0 t CK 17 Data-in to ACTIVATE command tDAL 5 4 4 tCK 15, 21 Data-in to precharge tDPL 2 2 2 tCK 16, 21 Last data-in to BURST STOP command tBDL 1 1 1 tCK 17 Last data-in to new READ/WRITE command tCDL 1 1 1 tCK 17 Lastdata-intoPRECHARGEcommand tRDL 2 2 2 tCK 16, 21 LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE CL = 3 command CL = 2 tMRD 2 2 2 tCK 25 tROH 3 3 3 tCK 17 tROH 2 2 2 tCK 17 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Notes 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will decrease or decrease in a proportional amount by the amount the frequency is altered for th etest condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 133 MHz for -75, tCK = 125 MHz for -8, andtCK = 100 MHz for -10. 22. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns after the first clock delay, after the last WRITE is executed. 25. Precharge mode only. 26. JEDEC specifies three clocks. 27. tAC for -75 at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. tCK = 7.5ns for -75, tCK = 8ns for -8, and tCK = 15ns for -10. 30. CKE is HIGH during refresh command period t RFC(MIN), else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 31. Refer to device data sheet for timing waveforms. 32. The value of tRAS used in -13E speed grade modules is calculated from tRC - tRP. 33. Leakage number reflects the worst-case leakage possible through the module pin, not what each memory device contributes. 1. All voltages referenced to VSS. 2. This parameter is sampled. VDD = VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ TA ≤ 70°C) is ensured. 6. An initial pause of 100µs is required after powerup, followed by two Auto Refresh commands, before proper device operation is ensured. The two Auto Refresh command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: Q 50pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet t OH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7, Data Validity, and Figure 8, Definition of Start and Stop). Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure 9, Acknowledge Response from Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 7: Data Validity Figure 8: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 9: Acknowledge Response from Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 20: EEPROM Device Select Code Most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW Table 21: EEPROM Operating Modes MODE Current Address Read RandomAddressRead Sequential Read Byte Write Page Write RW BIT WC BYTES 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 INITIAL SEQUENCE Start, Device Select, RW = 1 Start, Device Select, RW= 0, Address RESTART, Device Select, RW= 1 Similar to Current or Random Address Read START, Device Select, RW = 0 START, Device Select, RW = 0 1 ≥1 1 ≤ 16 Figure 10: SPD EEPROM tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 22: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS VDD VIH VIL VOL ILI ILO ISB IDD 3 VDD x 0.7 -1 – – – – – 3.6 VDD + 0.5 VDD x 0.3 0.4 10 10 30 2 V V V V µA µA µA mA SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz Table 23: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL MIN MAX UNITS NOTES tAA 0.2 1.3 200 0.9 µs µs ns ns µs µs µs ns µs µs KHz ns µs µs ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH 300 0 0.6 0.6 tI tLOW 50 1.3 tR 0.3 400 fSCL tSU:DAT tSU:STA t SU:STO tWRC 100 0.6 0.6 10 2 2 3 4 NOTE: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 24: Serial Presence-Detect Matrix – 16MB, 32MB “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW” BYTE 0 1 2 3 4 5 6 7 8 9 Number of Bytes Used by Micron Total Number of SPD Memory Bytes Memory Type Number of Row Addresses Number of Column Addresses Number of Module Ranks Module Data Width Module Data Width (continued) Module Voltage Interface Levels 10 SDRAM Access From Clock, tAC (CAS Latency = 3) 11 12 13 14 15 Module Configuration Type Refresh Rate/Type SDRAM Width (Primary SDRAM) Error-Checking SDRAM Data Width 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ENTRY (VERSION) DESCRIPTION 128 256 SDRAM 12 8 1 or 2 32 0 LVTTL 7.5ns (-75) 8ns (-8) 10ns (-10) 5.4ns (-75) 6ns (-8) 7.5ns (-10) None 15.625µs/Self 8 0 SDRAM Cycle Time, tCK (CAS Latency = 3) 1 tCK 1, 2, 4, 8, Page 4 2, 3 0 0 Unbuffered Attributes tCK (CAS Latency = 2) 10ns (-75/-8) SDRAM Cycle Time, 15ns (-10) 6ns (-75/-8) SDRAM Access From Clock, tAC, (CAS Latency = 2) 9ns (-10) Not SDRAM Cycle Time, tCK (CAS Latency = 1) Supported Not SDRAM Access From Clock, tAC, (CAS Latency = 1) Supported 20ns (-75/-8) Minimum Row Precharge Time, tRP 30ns (-10) 15ns (-75) Minimum Row Active to Row Active, tRRD 20ns (-8/-10) 20ns (-75/-8) Minimum RAS# to CAS# Delay, tRCD 30ns (-10) tRAS 44ns (-75) Minimum RAS# Pulse Width, 50ns (-8) 60ns (-10) 16MB Module Rank Density 1.5ns (-75) Command Address Setup, tAS 2ns (-8/-10) 0.8ns (-75) Command Address Hold, tAH 1ns (-8/-10) Minimum Clock Delay, tCCD Burst Lengths Supported Number of Banks on SDRAM Device CAS Latencies Supported CS Latency WE Latency SDRAM Module Attributes SDRAM Device Attributes: General 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 22 MT2LSDT432U MT4LSDT832UD 80 08 04 0C 08 01 20 00 01 75 80 A0 54 60 75 00 80 10 00 01 80 08 04 0C 08 02 20 00 01 75 80 A0 54 60 75 00 80 10 00 01 8F 04 06 01 01 00 0E A0 F0 60 90 00 8F 04 06 01 01 00 0E A0 F0 60 90 00 00 00 14 1E 0F 14 14 1E 2C 32 3C 04 15 20 08 10 14 1E 0F 14 14 1E 2C 32 3C 04 15 20 08 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 24: Serial Presence-Detect Matrix – 16MB, 32MB (Continued) “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW” BYTE ENTRY (VERSION) DESCRIPTION 34 Data Signal Input Setup, tDS 35 Data Signal Input Hold, tDH 36-40 41 Reserved Bytes Device Minimum Active/Auto-Refresh Time, tRC 42–61 62 63 Reserved Bytes SPD Revision Checksum for Bytes 0-62 64 65-71 72 73-90 91 92 93 94 95-98 99-127 Manufacturer's JEDEC ID Code Manufacturer's JEDEC Code (Cont.) Manufacturing Location Module Part Number (ASCII) PCB Identification Code Identification Code (Continuted) Year of Manufacture in BCD Week of Manufacture in BCD Module Serial Number Manufacturer-Specific Data (RSVD) 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 1.5ns (-75) 2ns (-8/-10) 0.8ns (-75) 1ns (-8/-10) – 66ns (-75) 71ns (-8) 66ns (-10) – REV. 2.0 (-75) (-8) (-10) MICRON 1-12 1-9 0 23 MT2LSDT432U MT4LSDT832UD 15 20 08 10 00 42 46 5A 00 02 A5 F6 DD 2C FF 01-0C Variable Data 01-09 00 Variable Data Variable Data Variable Data – 15 20 08 10 00 42 46 5A 00 02 A6 F7 DE 2C FF 01-0C Variable Data 01-09 00 Variable Data Variable Data Variable Data – Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 25: Serial Presence-Detect Matrix – 64MB, 128MB “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW” BYTE ENTRY (VERSION) DESCRIPTION 0 1 2 3 4 5 6 7 8 9 Number of Bytes Used by Micron Total Number of SPD Memory Bytes Memory Type Number of Row Addresses Number of Column Addresses Number of Module Ranks Module Data Width Module Data Width (continued) Module Voltage Interface Levels 10 SDRAM Access From Clock, tAC (CAS Latency = 3) 11 12 Module Configuration Type Refresh Rate/Type 13 14 15 SDRAM Width (Primary SDRAM) Error-Checking SDRAM Data Width SDRAM Cycle Time, tCK (CAS Latency = 3) 128 256 SDRAM 12 or 13 9 2 32 0 LVTTL 7.5ns(-75) 8ns (-8) 10ns(-10) 5.4(-75) 6ns (-8) 7.5ns (-10) None 15.625µs, 7.81µs/ Self 8 0 MT4LSDT1632UD MT4LSDT3232UD 80 08 04 0C 09 02 20 00 01 75 80 A0 54 60 75 00 80 80 08 04 0D 09 02 20 00 01 75 80 A0 54 60 75 00 82 10 00 01 10 00 01 8F 04 06 01 01 00 0E A0 F0 60 90 00 8F 04 06 01 01 00 0E A0 F0 60 90 00 24 SDRAM Access From Clock, tAC, (CAS Latency = 2) 25 SDRAM Cycle Time, tCK (CAS Latency = 1) 1 tCK 1, 2, 4, 8, Page 4 2, 3 0 0 Unbuffered Attributes 10ns (-75/-8) 15ns (-10) 6ns (-75/-8) 9ns (-10) Not Supported 26 SDRAM Access From Clock, tAC, (CAS Latency = 1) Not Supported 00 00 20ns (-75/-8) 30ns (-10) 15ns (-75) 20ns (-10/-8) 20ns (-75/-8) 30ns (-10) 44ns (-75) 50ns (-8) 60ns (-10) 32MB or 64MB 1.5ns (-75) 2ns (-8/-10) 0.8ns (-75) 1ns (-8/-10) 14 1E 0F 14 14 1E 2C 32 3C 08 15 20 08 10 14 1E 0F 14 14 1E 2C 32 3C 10 15 20 08 10 16 17 18 19 20 21 22 23 Minimum Clock Delay, tCCD Burst Lengths Supported Number of Banks on SDRAM Device CAS Latencies Supported CS Latency WE Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, tCK (CAS Latency = 2) 27 Minimum Row Precharge Time, RP 28 Minimum Row Active to Row Active, tRRD 29 Minimum RAS# to CAS# Delay, tRCD 30 Minimum RAS# Pulse Width, tRAS 31 32 Module Rank Density 33 Command Address Hold, tAH t Command Address Setup, tAS 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Table 25: Serial Presence-Detect Matrix – 64MB, 128MB (Continued) “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW” BYTE ENTRY (VERSION) DESCRIPTION 34 Data Signal Input Setup, tDS 35 Data Signal Input Hold, tDH 36-40 41 Reserved Bytes Device Minimum Active/Auto-Refresh Time, tRC 42–61 62 63 Reserved Bytes SPD Revision Checksum For Bytes 0-62 64 65-71 72 73-90 91 92 93 94 95-98 99-127 Manufacturer's JEDEC ID Code Manufacturer's JEDEC Code (Cont.) Manufacturing Location Module Part Number (ASCII) PCB Identification Code Identification Code (Continuted) Year of Manufacture in BCD Week of Manufacture in BCD Module Serial Number Manufacturer-Specific Data (Rsvd) 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 1.5ns (-75) 2ns (-8/-10) 0.8ns (-75) 1ns (-8/-10) – 66ns (-75) 71ns (-8) 66ns (-10) – REV. 2 or 2 (-75) (-8) (-10) MICRON 1-12 1-9 0 25 MT4LSDT1632UD MT4LSDT3232UD 15 20 08 10 00 42 46 5A 00 02 AB FC E3 2C FF 01-0C Variable Data 01-09 00 Variable Data Variable Data Variable Data – 15 20 08 10 00 42 46 5A 00 02 B6 02 EE 2C FF 01-0C Variable Data 01-09 00 Variable Data Variable Data Variable Data – Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Figure 11: 100-Pin DIMM Dimensions – 16MB Front View 0.125 (3.18) MAX 3.557 (90.34) 3.545 (90.04) 0.079 (2.00) R (2X) U1 U2 U5 1.005 (25.53) 0.995 (25.27) 0.118 (3.00) (2X) 0.700 (17.78) TYP 0.118 (3.00) TYP 0.118 (3.00) TYP 0.250 (6.35) TYP 0.039 (1.00) R(2X) PIN 1 0.128 (3.25) (2X) 0.118 (3.00) 0.039 (1.00) 0.050 (1.27) TYP TYP 0.054 (1.37) 0.046 (1.17) PIN 50 2.850 (72.39) Back View No Components This Side of Module PIN 100 PIN 51 NOTE: All dimensions in inches (millimeters); MAX or typical where noted. MIN 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) 100-PIN SDRAM UDIMM Figure 12: 100-Pin DIMM Dimensions – 32MB, 64MB, and 128MB Front View 0.157 (4.00) MAX 3.557 (90.34) 3.545 (90.04) 0.079 (2.00) R (2X) U1 U2 U5 1.005 (25.53) 0.995 (25.27) 0.118 (3.00) (2X) 0.700 (17.78) TYP 0.118 (3.00) TYP 0.118 (3.00) TYP 0.250 (6.35) TYP 0.039 (1.00) R(2X) PIN 1 0.128 (3.25) (2X) 0.118 (3.00) 0.039 (1.00) 0.050 (1.27) TYP TYP 0.054 (1.37) 0.046 (1.17) PIN 50 2.850 (72.39) Back View U4 U3 PIN 100 PIN 51 NOTE: All dimensions in inches (millimeters); MAX or typical where noted. MIN Data Sheet Designation Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved.