512MB (x64, SR) 204-Pin DDR3 SODIMM

512MB (x64, SR) 204-Pin DDR3 SODIMM
Features
DDR3 SDRAM SODIMM
MT4JSF6464H – 512MB
Features
Figure 1: 204-Pin SODIMM (MO-268 R/C C)
PCB height: 30.0mm (1.18in)
• DDR3 functionality and operations supported as
defined in the component data sheet
• 204-pin, small-outline dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC3-12800, PC3-10600,
PC3-8500, or PC3-6400
• 512MB (64 Meg x 64)
• VDD = 1.5V ±0.075V
• VDDSPD = 3.0–3.6V
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Single rank
• On-board I2C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
• 8 internal device banks
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Lead-free
• Fly-by topology
• Terminated control, command, and address bus
Options
Marking
• Operating temperature1
– Commercial (0°C ≤ T A ≤ +70°C)
– Industrial (–40°C ≤ T A ≤ +85°C)
• Package
– 204-pin DIMM (lead-free)
• Frequency/CAS latency
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
Notes:
None
I
Y
-1G6
-1G4
-1G1
1. Contact Micron for industrial temperature
module offerings.
2. Not recommended for new designs.
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed
Grade
Industry
Nomenclature
-1G6
PC3-12800
1600
-1G4
PC3-10600
-1G1
PC3-8500
-1G0
-80B
tRP
tRC
CL = 9
CL = 8
CL = 7
CL = 6
CL = 5
(ns)
(ns)
(ns)
1333
1333
1066
1066
800
667
13.125
13.125
48.125
–
1333
1333
1066
1066
800
667
13.125
13.125
49.125
–
–
–
1066
1066
800
667
13.125
13.125
50.625
PC3-8500
–
–
–
1066
–
800
667
15
15
52.5
PC3-6400
–
–
–
–
–
800
667
15
15
52.5
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2007 Micron Technology, Inc. All rights reserved.
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CL = 11 CL = 10
tRCD
Products and specifications discussed herein are subject to change by Micron without notice.
512MB (x64, SR) 204-Pin DDR3 SODIMM
Features
Table 2: Addressing
Parameter
512MB
Refresh count
8K
Row address
8K A[12:0]
Device bank address
8 BA[2:0]
Device configuration
1Gb (64 Meg x 16)
Column address
1K A[9:0]
Module rank address
1 S0#
Table 3: Part Numbers and Timing Parameters – 512MB Modules
Base device: MT41J64M16,1 1Gb DDR3 SDRAM
Module
Part Number2
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-t RP)
MT4JSF6464H(I)Y-1G6__
512MB
64 Meg x 64
12.8 GB/s
1.25ns/1600 MT/s
11-11-11
MT4JSF6464H(I)Y-1G4__
512MB
64 Meg x 64
10.6 GB/s
1.5ns/1333 MT/s
9-9-9
MT4JSF6464H(I)Y-1G1__
512MB
64 Meg x 64
8.5 GB/s
1.87ns/1066 MT/s
7-7-7
Notes:
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT4JSF6464HY-1G1B1.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2007 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 204-Pin DDR3 SODIMM
Features
Contents
Pin Assignments ............................................................................................................................................... 4
Pin Descriptions ............................................................................................................................................... 5
DQ Map ........................................................................................................................................................... 7
Functional Block Diagram ................................................................................................................................ 8
General Description ......................................................................................................................................... 9
Fly-By Topology ............................................................................................................................................ 9
Temperature Sensor with Serial Presence-Detect EEPROM ................................................................................. 9
Thermal Sensor Operations .......................................................................................................................... 9
Serial Presence-Detect EEPROM Operation ................................................................................................... 9
Electrical Specifications .................................................................................................................................. 10
DRAM Operating Conditions .......................................................................................................................... 11
Design Considerations ................................................................................................................................ 11
IDD Specifications ........................................................................................................................................... 12
Temperature Sensor with Serial Presence-Detect EEPROM ............................................................................... 13
Serial Presence-Detect ................................................................................................................................ 13
EVENT# Pin ............................................................................................................................................... 14
Module Dimensions ....................................................................................................................................... 15
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2007 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 204-Pin DDR3 SODIMM
Pin Assignments
Pin Assignments
Table 4: Pin Assignments
204-Pin DDR3 SODIMM Front
204-Pin DDR3 SODIMM Back
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
1
VREFDQ
53
DQ19
105
VDD
157
DQ42
2
VSS
54
VSS
106
VDD
158
DQ46
3
VSS
55
VSS
107
A10
159
DQ43
4
DQ4
56
DQ28
108
BA1
160
DQ47
5
DQ0
57
DQ24
109
BA0
161
VSS
6
DQ5
58
DQ29
110
RAS#
162
VSS
7
DQ1
59
DQ25
111
VDD
163
DQ48
8
VSS
60
VSS
112
VDD
164
DQ52
9
VSS
61
VSS
113
WE#
165
DQ49
10
DQS0#
62
DQ3#
114
S0#
166
DQ53
11
DM0
63
DM3
115
CAS#
167
VSS
12
DQS0
64
DQ3
116
ODT0
168
VSS
13
VSS
65
VSS
117
VDD
169
DQS6#
14
VSS
66
VSS
118
VDD
170
DM6
15
DQ2
67
DQ26
119
NF
171
DQS6
16
DQ6
68
DQ30
120
NC
172
VSS
17
DQ3
69
DQ27
121
NC
173
VSS
18
DQ7
70
DQ31
122
NC
174
DQ54
19
VSS
71
VSS
123
VDD
175
DQ50
20
VSS
72
VSS
124
VDD
176
DQ55
21
DQ8
73
CKE0
125
NC
177
DQ51
22
DQ12
74
NC
126
VREFCA
178
VSS
23
DQ9
75
VDD
127
VSS
179
VSS
24
DQ13
76
VDD
128
VSS
180
DQ60
25
VSS
77
NC
129
DQ32
181
DQ56
26
VSS
78
NC
130
DQ36
182
DQ61
27
DQS1#
79
BA2
131
DQ33
183
DQ57
28
DM1
80
NF
132
DQ37
184
VSS
29
DQS1
81
VDD
133
VSS
185
VSS
30
RESET#
82
VDD
134
VSS
186
DQS7#
31
VSS
83
A12
135
DQS4#
187
DM7
32
VSS
84
A11
136
DM4
188
DQS7
33
DQ10
85
A9
137
DQS4
189
VSS
34
DQ14
86
A7
138
VSS
190
VSS
35
DQ11
87
VDD
139
VSS
191
DQ58
36
DQ15
88
VDD
140
DQ38
192
DQ62
37
VSS
89
A8
141
DQ34
193
DQ59
38
VSS
90
A6
142
DQ39
194
DQ63
39
DQ16
91
A5
143
DQ35
195
VSS
40
DQ20
92
A4
144
VSS
196
VSS
41
DQ17
93
VDD
145
VSS
197
SA0
42
DQ21
94
VDD
146
DQ44
198
EVENT#
43
VSS
95
A3
147
DQ40
199
VDDSPD
44
VSS
96
A2
148
DQ45
200
SDA
45
DQS2#
97
A1
149
DQ41
201
SA1
46
DM2
98
A0
150
VSS
202
SCL
47
DQS2
99
VDD
151
VSS
203
VTT
48
VSS
100
VDD
152
DQS5#
204
VTT
49
VSS
101
CK0
153
DM5
–
–
50
DQ22
102
CK1
154
DQS5
–
–
51
DQ18
103
CK0#
155
VSS
–
–
52
DQ23
104
CK1#
156
VSS
–
–
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2007 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 204-Pin DDR3 SODIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR3
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 5: Pin Descriptions
Symbol
Type
Description
Ax
Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
BAx
Input
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.
CKx,
CKx#
Input
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx
Input
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM.
DMx
Input
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx
Input
On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In
Input
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
Input
(LVCMOS)
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM
and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed.
Sx#
Input
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
SAx
Input
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range on the I2C bus.
SCL
Input
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to and from the temperature sensor/SPD EEPROM on the I2C bus.
CBx
I/O
Check bits: Used for system error detection and correction.
DQx
I/O
Data input/output: Bidirectional data bus.
DQSx,
DQSx#
I/O
Data strobe: Differential data strobes. Output with read data; edge-aligned with
read data; input with write data; center-aligned with write data.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2007 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 204-Pin DDR3 SODIMM
Pin Descriptions
Table 5: Pin Descriptions (Continued)
Symbol
Type
SDA
I/O
Description
Serial data: Used to transfer addresses and data into and out of the temperature sensor/SPD EEPROM on the I2C bus.
TDQSx,
TDQSx#
Output
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When TDQS is enabled, DM is
disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are
no function.
Err_Out#
Output
Parity error output: Parity error found on the command and address bus.
(open drain)
EVENT#
Output
Temperature event:The EVENT# pin is asserted by the temperature sensor when criti(open drain) cal temperature thresholds have been exceeded.
VDD
Supply
Power supply: 1.5V ±0.075V. The component VDD and VDDQ are connected to the
module VDD.
VDDSPD
Supply
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.
VREFCA
Supply
Reference voltage: Control, command, and address VDD/2.
VREFDQ
Supply
Reference voltage: DQ, DM VDD/2.
VSS
Supply
Ground.
VTT
Supply
Termination voltage: Used for control, command, and address VDD/2.
NC
–
No connect: These pins are not connected on the module.
NF
–
No function: These pins are connected within the module, but provide no functionality.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2007 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 204-Pin DDR3 SODIMM
DQ Map
DQ Map
Table 6: Component-to-Module DQ Map
Component
Reference
Number
Component
DQ
U1
U3
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Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
10
33
U2
0
26
67
1
13
24
1
29
58
10
0
5
10
20
40
11
6
16
11
23
52
12
1
7
12
21
42
13
3
17
13
18
51
14
5
6
14
17
41
15
7
18
15
19
53
2
11
35
2
27
69
3
12
22
3
24
57
4
14
34
4
30
68
5
8
21
5
28
56
6
15
36
6
31
70
7
9
23
7
25
59
8
4
4
8
16
39
9
2
15
9
22
50
0
38
140
0
50
175
U4
1
37
132
1
53
166
10
44
146
10
56
181
11
43
159
11
59
193
12
45
148
12
61
182
13
42
157
13
58
191
14
40
147
14
60
180
15
46
158
15
63
194
2
39
142
2
55
176
3
33
131
3
49
165
4
34
141
4
54
174
5
32
129
5
48
163
6
35
143
6
51
177
7
36
130
7
52
164
8
41
149
8
57
183
9
47
160
9
62
192
7
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© 2007 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 204-Pin DDR3 SODIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
S0#
UDQS#
UDQS
UDM
DQS0#
DQS0
DM0
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQS#
LDQS
LDM
DQS1#
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2#
DQS2
DM2
UDQS#
UDQS
UDM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
VSS
CS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
VSS
VSS
BA[2:0]
BA[2:0]: DDR3 SDRAM
A[12:0]
A[12:0]: DDR3 SDRAM
RAS#: DDR3 SDRAM
CAS#: DDR3 SDRAM
RAS#
CAS#
WE#
CKE0
ODT0
U5
SCL
WE#: DDR3 SDRAM
CKE0: DDR3 SDRAM
ODT0: DDR3 SDRAM
RESET#: DDR3 SDRAM
RESET#
Temperature sensor/
SPD EEPROM
EVT A0
A1
VDDSPD
VTT
DDR3
SDRAM
CK
CK#
Note:
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DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DDR3 SDRAM x 4
CK1
CK1#
Temperature sensor/SPD EEPROM
VDD
DDR3 SDRAM
VTT
Control, command, and address termination
DDR3
SDRAM
ODT0, BA[2:0], S0#
U4
SA0 SA1 VSS
EVENT#
Clock, control, command, and address line terminations:
CKE0, A[12:0],
RAS#, CAS#, WE#,
A2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK0
CK0#
SDA
U3
CS#
UDQS#
UDQS
UDM
DQS7#
DQS7
DM7
CS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
LDQS#
LDQS
LDM
DQS6#
DQS6
DM6
U2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
UDQS#
UDQS
UDM
DQS5#
DQS5
DM5
LDQS#
LDQS
LDM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDQS#
LDQS
LDM
DQS4#
DQS4
DM4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
VSS
DQS3#
DQS3
DM3
CS#
VREFCA
DDR3 SDRAM
VREFDQ
DDR3 SDRAM
VSS
DDR3 SDRAM
VDD
1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
8
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© 2007 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 204-Pin DDR3 SODIMM
General Description
General Description
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words
per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
Fly-By Topology
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write-leveling feature of DDR3.
Temperature Sensor with Serial Presence-Detect EEPROM
Thermal Sensor Operations
The temperature from the integrated thermal sensor is monitored and converts into a
digital word via the I2C bus. System designers can use the user-programmable registers
to create a custom temperature-sensing solution based on system requirements. Programming and configuration details comply with JEDEC standard No. 21-C page 4.7-1,
"Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor."
Serial Presence-Detect EEPROM Operation
DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Modules." These bytes identify module-specific timing parameters, configuration information, and physical attributes. The remaining 128 bytes of storage are available for use by
the customer. System READ/WRITE operations between the master (system logic) and
the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock)
SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, permanently
disabling hardware write protection. For further information refer to Micron technical
note TN-04-42, "Memory Module Serial Presence-Detect."
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2007 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 204-Pin DDR3 SODIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 7: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.975
V
Table 8: Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
VDD
VDD supply voltage
1.425
1.5
1.575
V
IVTT
Termination reference current from VTT
–600
–
600
mA
VTT
Termination reference voltage (DC) – command/address bus
0.49 × VDD 20mV
0.5 × VDD
0.51 × VDD +
20mV
V
Address inputs, RAS#,
CAS#, WE#,
S#, CKE,
ODT, BA, CK,
CK#
–8
0
8
µA
DM
–2
0
2
Output leakage current; 0V ≤ DQ, DQS,
VOUT ≤ VDDQ; DQ and ODT are DQS#
disabled; ODT is HIGH
–5
0
5
µA
VREF supply leakage current; VREFDQ = VDD/2
or VREFCA = VDD/2 (All other pins not under
test = 0V)
–4
0
4
µA
Module ambient operating
temperature
Commercial
0
–
70
°C
–40
–
85
°C
DDR3 SDRAM component
case operating temperature
Commercial
0
–
95
°C
–40
–
95
°C
II
IOZ
IVREF
TA
TC
Input leakage current; Any input 0V ≤ VIN ≤ VDD; VREF input
0V ≤ VIN ≤ 0.95V (All other
pins not under test = 0V)
Notes:
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Industrial
Industrial
Notes
1
2, 3
2, 3, 4
1. VTT termination voltage in excess of the stated limit will adversely affect the command
and address signals’ voltage margin and will reduce timing margins.
2. TA and TC are simultaneous requirements.
3. For further information, refer to technical note TN-00-08: “Thermal Applications,” available on Micron’s Web site.
4. The refresh rate is required to double when 85°C < TC ≤ 95°C.
10
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512MB (x64, SR) 204-Pin DDR3 SODIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR3 component data sheets.
Component specifications are available on Micron’s web site. Module speed grades correlate with component speed grades, as shown below.
Table 9: Module and Component Speed Grades
DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-2G1
-093
-1G9
-107
-1G6
-125
-1G4
-15E
-1G1
-187E
-1G0
-187
-80C
-25E
-80B
-25
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system's
memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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512MB (x64, SR) 204-Pin DDR3 SODIMM
IDD Specifications
IDD Specifications
Table 10: DDR3 IDD Specifications and Conditions – 512MB
Values are for the MT41J64M16 DDR3 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) component data sheet
Parameter
Symbol
1600
1333
1066
Units
Operating current 0: One bank ACTIVATE-to-PRECHARGE
IDD0
480
440
400
mA
Operating current 1: One bank ACTIVATE-to-READto-PRECHARGE
IDD1
680
600
520
mA
Precharge power-down current: Slow exit
IDD2P0
48
48
48
mA
Precharge power-down current: Fast exit
IDD2P1
180
160
140
mA
Precharge quiet standby current
IDD2Q
268
240
212
mA
Precharge standby current
IDD2N
280
260
220
mA
Precharge standby ODT current
IDD2NT
460
420
380
mA
Active power-down current
IDD3P
180
160
140
mA
Active standby current
IDD3N
260
240
220
mA
Burst read operating current
IDD4R
1280
1160
1040
mA
Burst write operating current
IDD4W
1720
1420
1180
mA
Refresh current
IDD5B
1040
960
880
mA
Self refresh temperature current: MAX TC = 85°C
IDD6
24
24
24
mA
Self refresh temperature current (SRT-enabled):
MAX TC = 95°C
IDD6ET
36
36
36
mA
All banks interleaved read current
IDD7
1840
1680
1520
mA
Reset current
IDD8
56
56
56
mA
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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512MB (x64, SR) 204-Pin DDR3 SODIMM
Temperature Sensor with Serial Presence-Detect EEPROM
Temperature Sensor with Serial Presence-Detect EEPROM
The temperature sensor continuously monitors the module's temperature and can be
read back at any time over the I2C bus shared with the SPD EEPROM. Refer to JEDEC
standard No. 21-C page 4.7-1, "Definition of the TSE2002av, Serial Presence Detect with
Temperature Sensor."
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 11: Temperature Sensor with SPD EEPROM Operating Conditions
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
3.0
3.6
V
Supply current: VDD = 3.3V
IDD
–
2.0
mA
Input high voltage: Logic 1; SCL, SDA
VIH
VDDSPD x 0.7
VDDSPD + 1
V
Input low voltage: Logic 0; SCL, SDA
VIL
–0.5
VDDSPD x 0.3
V
Output low voltage: IOUT = 2.1mA
VOL
–
0.4
V
Input current
IIN
–5.0
5.0
µA
Temperature sensing range
–
–40
125
°C
Temperature sensor accuracy (class B)
–
–1.0
1.0
°C
Supply voltage
Table 12: Temperature Sensor and SPD EEPROM Serial Interface Timing
Parameter/Condition
Symbol
Min
Max
Units
tBUF
4.7
–
µs
SDA fall time
tF
20
300
ns
SDA rise time
tR
–
1000
ns
tHD:DAT
200
900
ns
Time bus must be free before a new transition can
start
Data hold time
Start condition hold time
tH:STA
4.0
–
µs
Clock HIGH period
tHIGH
4.0
50
µs
Clock LOW period
tLOW
4.7
–
µs
tSCL
10
100
kHz
Data setup time
tSU:DAT
250
–
ns
Start condition setup time
tSU:STA
4.7
–
µs
Stop condition setup time
tSU:STO
4.0
–
µs
SCL clock frequency
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512MB (x64, SR) 204-Pin DDR3 SODIMM
Temperature Sensor with Serial Presence-Detect EEPROM
EVENT# Pin
The temperature sensor also adds the EVENT# pin (open-drain). Not used by the SPD
EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be
set up in the sensor’s configuration register.
EVENT# has three defined modes of operation: interrupt mode, compare mode, and
critical temperature mode. Event thresholds are programmed in the 0x01 register using
a hysteresis. The alarm window provides a comparison window, with upper and lower
limits set in the alarm upper boundary register and the alarm lower boundary register,
respectively. When the alarm window is enabled, EVENT# will trigger whenever the
temperature is outside the MIN or MAX values set by the user.
The interrupt mode enables software to reset EVENT# after a critical temperature
threshold has been detected. Threshold points are set in the configuration register by
the user. This mode triggers the critical temperature limit and both the MIN and MAX of
the temperature window.
The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by
the user and returns to the logic HIGH state only when the temperature falls below the
programmed thresholds.
Critical temperature mode triggers EVENT# only when the temperature has exceeded
the programmed critical trip point. When the critical trip point has been reached, the
temperature sensor goes into comparator mode, and the critical EVENT# cannot be
cleared through software.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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512MB (x64, SR) 204-Pin DDR3 SODIMM
Module Dimensions
Module Dimensions
Figure 3: 204-Pin DDR3 SODIMM
2.45 (0.096)
MAX
Front view
67.75 (2.667)
67.45 (2.656)
2.0 (0.079) R
(2X)
U1
1.8 (0.071)
(2X)
U3
U2
30.15 (1.187)
29.85 (1.175)
U4
20.0 (0.787)
TYP
U5
6.0 (0.236)
TYP
2.0 (0.079)
TYP
Pin 1
1.0 (0.039)
TYP
0.45 (0.018)
TYP
0.60 (0.024)
TYP
Pin 203
1.1 (0.043)
0.9 (0.035)
63.60 (2.504)
TYP
Back view
No components this side of module
4.0 (0.157)
TYP
2.55 (0.10)
TYP
3.0 (0.12)
TYP
Pin 204
39.0 (1.535)
TYP
Pin 2
21.0 (0.827)
TYP
24.8 (0.976)
TYP
Notes:
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2007 Micron Technology, Inc. All rights reserved.