2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM Features DDR3 SDRAM VLP RDIMM MT18JDF25672PDZ – 2GB MT18JDF51272PDZ – 4GB Features Figure 1: 240-Pin VLP RDIMM (MO-269 R/C L) Module height: 18.75mm (0.738in) Options Marking • Operating temperature – Commercial (0°C ≤ T A ≤ +70°C) • Package – 240-pin DIMM (halogen-free) • Frequency/CAS latency – 1.25ns @ CL = 11 (DDR3-1600) – 1.5ns @ CL = 9 (DDR3-1333) – 1.87ns @ CL = 7 (DDR3-1066) None Z -1G6 -1G4 -1G1 Table 1: Key Timing Parameters Data Rate (MT/s) tRCD tRP tRC Speed Grade Industry Nomenclature CL = 9 CL = 8 CL = 7 CL = 6 CL = 5 (ns) (ns) (ns) -1G6 PC3-12800 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125 -1G4 PC3-10600 – 1333 1333 1066 1066 800 667 13.125 13.125 49.125 -1G1 PC3-8500 – – – 1066 1066 800 667 13.125 13.125 50.625 -1G0 PC3-8500 – – – 1066 – 800 667 15 15 52.5 -80B PC3-6400 – – – – – 800 667 15 15 52.5 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN CL = 11 CL = 10 Products and specifications discussed herein are subject to change by Micron without notice. DRAFT: 12/19/2011 • DDR3 functionality and operations supported as defined in the component data sheet • 240-pin, very low profile registered dual in-line memory module (VLP RDIMM) • Fast data transfer rates: PC3-12800, PC3-10600, PC3-8500, or PC3-6400 • 2GB (256 Meg x 72), 4GB (512 Meg x 72) • VDD = 1.5V ±0.075V • VDDSPD = +3.0V to +3.6V • Supports ECC error detection and correction • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals • Dual rank • On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM • 8 internal device banks • Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) • Selectable BC4 or BL8 on-the-fly (OTF) • Gold edge contacts • Halogen-free • Fly-by topology • Terminated control, command, and address bus 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM Features Table 2: Addressing Parameter 2GB 4GB 8K 8K 16K A[13:0] 32K A[14:0] Device bank address 8 BA[2:0] 8 BA[2:0] Device configuration Refresh count Row address 1Gb (128 Meg x 8) 2Gb (256 Meg x 8) Column address 1K A[9:0] 1K A[9:0] Module rank address 2 S#[1:0] 2 S#[1:0] Base device: MT41J128M8,1 1Gb DDR3 SDRAM Module Part Number2 Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 1.25ns/1600 MT/s 11-11-11 MT18JDF25672PDZ-1G6__ 2GB 256 Meg x 72 12.8 GB/s MT18JDF25672PDZ-1G4__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 9-9-9 MT18JDF25672PDZ-1G1__ 2GB 256 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 7-7-7 Notes: 1. The data sheet for the base device can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT18JDF25672PDZ-1G1D1. Table 4: Part Numbers and Timing Parameters – 4GB Modules Base device: MT41J256M8,1 2Gb DDR3 SDRAM Module Part Number2 Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT18JDF51272PDZ-1G6__ 4GB 512 Meg x 72 12.8 GB/s 1.25ns/1600 MT/s 11-11-11 MT18JDF51272PDZ-1G4__ 4GB 512 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 9-9-9 MT18JDF51272PDZ-1G1__ 4GB 512 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 7-7-7 Notes: 1. The data sheet for the base device can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT18JDF51272PDZ-1G1D1. PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Table 3: Part Numbers and Timing Parameters – 2GB Modules 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM Pin Assignments Pin Assignments Table 5: Pin Assignments 240-Pin DDR3 VLP RDIMM Back Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin 1 VREFDQ 31 DQ25 61 A2 91 DQ41 121 VSS 151 VSS 181 A1 211 VSS 2 VSS 32 VSS 62 VDD 92 VSS 122 DQ4 152 DM3/ TDQS12 182 VDD 212 DM5/ TDQS14 3 DQ0 33 DQS3# 63 NC 93 DQS5# 123 DQ5 153 NF/ TDQS12# 183 VDD 213 NF/ TDQS14# 4 DQ1 34 DQS3 64 NC 94 DQS5 124 VSS 154 VSS 184 CK0 214 VSS 5 VSS 35 VSS 65 VDD 95 VSS 125 DM0/ TDQS9 155 DQ30 185 CK0# 215 DQ46 6 DQS0# 36 DQ26 66 VDD 96 DQ42 126 NF/ TDQS9# 156 DQ31 186 VDD 216 DQ47 7 DQS0 37 DQ27 67 VREFCA 97 DQ43 127 VSS 157 VSS 187 EVENT# 217 VSS 8 VSS 38 VSS 68 Par_In 98 VSS 128 DQ6 158 CB4 188 A0 218 DQ52 9 DQ2 39 CB0 69 VDD 99 DQ48 129 DQ7 159 CB5 189 VDD 219 DQ53 10 DQ3 40 CB1 70 A10 100 DQ49 130 VSS 160 VSS 190 BA1 220 VSS 11 VSS 41 VSS 71 BA0 101 VSS 131 DQ12 161 DM8/ TDQS17 191 VDD 221 DM6/ TDQS15 12 DQ8 42 DQS8# 72 VDD 102 DQS6# 132 DQ13 162 NF/ TDQS17# 192 RAS# 222 NF/ TDQS15# 13 DQ9 43 DQS8 73 WE# 103 DQS6 133 VSS 163 VSS 193 S0# 223 VSS 14 VSS 44 VSS 74 CAS# 104 VSS 134 DM1/ TDQS10 164 CB6 194 VDD 224 DQ54 15 DQS1# 45 CB2 75 VDD 105 DQ50 135 NF/ TDQS10# 165 CB7 195 ODT0 225 DQ55 16 DQS1 46 CB3 76 S1# 106 DQ51 136 VSS 166 VSS 196 A13 226 VSS 17 VSS 47 VSS 77 ODT1 107 VSS 137 DQ14 167 NC 197 VDD 227 DQ60 18 DQ10 48 VTT 78 VDD 108 DQ56 138 DQ15 168 RESET# 198 NC 228 DQ61 19 DQ11 49 VTT 79 NC 109 DQ57 139 VSS 169 CKE1 199 VSS 229 VSS 20 VSS 50 CKE0 80 VSS 110 VSS 140 DQ20 170 VDD 200 DQ36 230 DM7/ TDQS16 21 DQ16 51 VDD 81 DQ32 111 DQS7# 141 DQ21 171 A15 201 DQ37 231 NF/ TDQS16# 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 VSS 172 A14 202 VSS 232 VSS 23 VSS 53 Err_Out# 83 VSS 113 VSS 143 DM2/ TDQS11 173 VDD 203 DM4/ TDQS13 233 DQ62 24 DQS2# 54 VDD 84 DQS4# 114 DQ58 144 NF/ TDQS11# 174 A12 204 NF/ TDQS13# 234 DQ63 25 DQS2 55 A11 85 DQS4 115 DQ59 145 VSS 175 A9 205 VSS 235 VSS 26 VSS 56 A7 86 VSS 116 VSS 146 DQ22 176 VDD 206 DQ38 236 VDDSPD 27 DQ18 57 VDD 87 DQ34 117 SA0 147 DQ23 177 A8 207 DQ39 237 SA1 28 DQ19 58 A5 88 DQ35 118 SCL 148 VSS 178 A6 208 VSS 238 SDA 29 VSS 59 A4 89 VSS 119 SA2 149 DQ28 179 VDD 209 DQ44 239 VSS 30 DQ24 60 VDD 90 DQ40 120 VTT 150 DQ29 180 A3 210 DQ45 240 VTT PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 3 Symbol Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 240-Pin DDR3 VLP RDIMM Front Pin 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM Pin Descriptions Pin Descriptions The pin description table below is a comprehensive list of all possible pins for all DDR3 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Symbol Type Description Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information. BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. CKx, CKx# Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins. ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input (LVCMOS) Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed. Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. SAx Input Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range on the I2C bus. SCL Input Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to and from the temperature sensor/SPD EEPROM on the I2C bus. CBx I/O Check bits: Used for system error detection and correction. DQx I/O Data input/output: Bidirectional data bus. DQSx, DQSx# I/O Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; input with write data; center-aligned with write data. PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Table 6: Pin Descriptions 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM Pin Descriptions Table 6: Pin Descriptions (Continued) Type SDA I/O Description Serial data: Used to transfer addresses and data into and out of the temperature sensor/SPD EEPROM on the I2C bus. TDQSx, TDQSx# Output Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When TDQS is enabled, DM is disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are no function. Err_Out# Output Parity error output: Parity error found on the command and address bus. (open drain) EVENT# Output Temperature event:The EVENT# pin is asserted by the temperature sensor when criti(open drain) cal temperature thresholds have been exceeded. VDD Supply Power supply: 1.5V ±0.075V. The component VDD and VDDQ are connected to the module VDD. VDDSPD Supply Temperature sensor/SPD EEPROM power supply: 3.0–3.6V. VREFCA Supply Reference voltage: Control, command, and address VDD/2. VREFDQ Supply Reference voltage: DQ, DM VDD/2. VSS Supply Ground. VTT Supply Termination voltage: Used for control, command, and address VDD/2. NC – No connect: These pins are not connected on the module. NF – No function: These pins are connected within the module, but provide no functionality. PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Symbol 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM DQ Map DQ Map Component Reference Number Component DQ U1 U3 U5 U8 Module DQ Module Pin Number Component Reference Number Component DQ Module DQ Module Pin Number 0 2 9 U2 0 10 18 1 1 4 1 9 13 2 3 10 2 11 19 3 0 3 3 8 12 4 6 128 4 14 137 5 4 122 5 12 131 6 7 129 6 15 138 7 5 123 7 13 132 0 18 27 0 26 36 1 17 22 1 25 31 2 19 28 2 27 37 3 16 21 3 24 30 4 22 146 4 30 155 5 20 140 5 28 149 6 23 147 6 31 156 7 21 141 7 29 150 0 CB2 45 0 34 87 1 CB1 40 1 33 82 2 CB3 46 2 35 88 3 CB0 39 3 32 81 4 CB6 164 4 38 206 5 CB4 158 5 36 200 6 CB7 165 6 39 207 7 CB5 159 7 37 201 0 42 96 0 50 105 1 41 91 1 49 100 2 43 97 2 51 106 3 40 90 3 48 99 4 46 215 4 54 224 5 44 209 5 52 218 6 47 216 6 55 225 7 45 210 7 53 219 PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN U4 U7 U9 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Table 7: Component-to-Module DQ Map 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM DQ Map Component Reference Number Component DQ U10 U12 U14 U17 Module DQ Module Pin Number Component Reference Number Component DQ Module DQ Module Pin Number 0 58 114 U11 0 57 109 1 57 109 1 58 114 2 59 115 2 56 108 3 56 108 3 59 115 4 62 233 4 61 228 5 60 227 5 63 234 6 63 234 6 60 227 7 61 228 7 62 233 0 49 100 0 41 91 1 50 105 1 42 96 2 48 99 2 40 90 3 51 106 3 43 97 4 53 219 4 45 210 5 55 225 5 47 216 6 52 218 6 44 209 7 54 224 7 46 215 0 33 82 0 CB1 40 1 34 87 1 CB2 45 2 32 81 2 CB0 39 3 35 88 3 CB3 46 4 37 201 4 CB5 159 5 39 207 5 CB7 165 6 36 200 6 CB4 158 7 38 206 7 CB6 164 0 25 31 0 17 22 1 26 36 1 18 27 2 24 30 2 16 21 3 27 37 3 19 28 4 29 150 4 21 141 5 31 156 5 23 147 6 28 149 6 20 140 7 30 155 7 22 146 PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN U13 U16 U18 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Table 7: Component-to-Module DQ Map (Continued) 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM DQ Map Table 7: Component-to-Module DQ Map (Continued) Component DQ Module DQ Module Pin Number Component Reference Number Component DQ Module DQ Module Pin Number U19 0 9 13 U20 0 1 4 1 10 18 1 2 9 2 8 12 2 0 3 3 11 19 3 3 10 4 13 132 4 5 123 5 15 138 5 7 129 6 12 131 6 4 122 7 14 137 7 6 128 DRAFT: 12/19/2011 Component Reference Number PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram RS1# RS0# DQS4 DQS4# DM4/DQS13 NF/TDQS13# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VSS DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ ZQ NF/ CS# DQS DQS# TDQS# U1 DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ NF/ CS# DQS DQS# TDQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U20 VSS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VSS DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ ZQ NF/ CS# DQS DQS# TDQS# U2 DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 VSS DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ ZQ U19 U3 DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VSS DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ ZQ U18 U4 DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ NF/ CS# DQS DQS# TDQS# DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ NF/ CS# DQS DQS# TDQS# CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 VSS DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ ZQ NF/ CS# DQS DQS# TDQS# U5 DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ NF/ CS# DQS DQS# TDQS# U9 DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ U16 ZQ VSS SCL U12 EVT A0 SDA A1 A2 SA0 SA1 SA2 EVENT# VSS DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ ZQ NF/ CS# DQS DQS# TDQS# U10 DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ NF/ CS# DQS DQS# TDQS# U11 ZQ VSS Temperature sensor/SPD EEPROM VDD DDR3 SDRAM VTT DDR3 SDRAM VREFCA DDR3 SDRAM VREFDQ DDR3 SDRAM VSS DDR3 SDRAM Clock, control, command, and address line terminations: DDR3 SDRAM VTT DDR3 SDRAM VDD CK CK# PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN U15 Temperature sensor/ SPD EEPROM ZQ RS#[1:0], RCKE[1:0], RA[14/13:0], RRAS#, RCAS#, RWE#, RODT[1:0], RBA[2:0] Note: DDR3 SDRAM CK# Rank 0: U1–U5, U7–U10 Rank 1: U11–U14, U16–U20 NF/ CS# DQS DQS# TDQS# DQS7 DQS7# DM7/DQS16 NF/TDQS16# VDDSPD NF/ CS# DQS DQS# TDQS# RESET# CK P L L DDR3 SDRAM VSS DQS8 DQS8# DM8/DQS17 NF/TDQS17# a n d CK0 CK0# U13 RS0#: Rank 0 RS1#: Rank 1 RBA[2:0]: DDR3 SDRAM RA[14/13:0]: DDR3 SDRAM RRAS#: DDR3 SDRAM RCAS#: DDR3 SDRAM RWE#: DDR3 SDRAM RCKE0: Rank 0 RCKE1: Rank 1 RODT0: Rank 0 RODT1: Rank 1 Err_Out ZQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ VSS ZQ U8 DM/ TDQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U17 NF CS# DQS DQS# TDQS# R e g i s t e r S0# S1# BA[2:0] A[15:0] RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 Par_In VSS VSS ZQ NF/ CS# DQS DQS# TDQS# DQ DQ DQ DQ DQ DQ DQ DQ ZQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 VSS U14 DQS6 DQS6# DM6/DQS15 NF/TDQS15# NF/ CS# DQS DQS# TDQS# DQS3 DQS3# DM3/DQS12 NF/TDQS12# DQ DQ DQ DQ DQ DQ DQ DQ NF/ CS# DQS DQS# TDQS# ZQ DM/ TDQS VSS ZQ NF/ CS# DQS DQS# TDQS# U7 DM/ TDQS VSS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 VSS NF/ CS# DQS DQS# TDQS# DQS5 DQS5# DM5/DQS14 NF/TDQS14# NF/ CS# DQS DQS# TDQS# DQS2 DQS2# DM2/DQS11 NF/TDQS11# DQ DQ DQ DQ DQ DQ DQ DQ ZQ VSS ZQ DQS1 DQS1# DM1/DQS10 NF/TDQS10# U6 DM/ TDQS 1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor that is tied to ground. It is used for the calibration of the component’s ODT and output driver. 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 DQS0 DQS0# DM0/DQS9 NF/TDQS9# 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM General Description General Description DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially a 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. DDR3 modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write-leveling feature of DDR3. Registering Clock Driver Operation Registered DDR3 SDRAM modules use a registering clock driver device consisting of a register and a phase-lock loop (PLL). The device complies with the JEDEC standard "Definition of the SSTE32882 Registering Clock Driver with Parity and Quad Chip Selects for DDR3 RDIMM Applications." The register section of the registering clock driver latches command and address input signals on the rising clock edge. The PLL section of the registering clock driver receives and redrives the differential clock signals (CK, CK#) to the DDR3 SDRAM devices. The register(s) and PLL reduce clock, control, command, and address signals loading by isolating DRAM from the system controller. Parity Operations The registering clock driver includes an even parity function for checking parity. The memory controller accepts a parity bit at the Par_In input and compares it with the data received on A[15:0], BA[2:0], RAS#, CAS#, and WE#. Valid parity is defined as an even number of ones (1s) across the address and command inputs (A[15:0], BA[2:0], RAS#, CAS#, and WE#) combined with Par_In. Parity errors are flagged on Err_Out#. Address and command parity is checked during all DRAM operations and during control word WRITE operations to the registering clock driver. For SDRAM operations, the address is still propagated to the SDRAM even when there is a parity error. When writing to the internal control words of the registering clock driver, the write will be ignored if parity is not valid. For this reason, systems must connect the Par_In pins on the DIMM and provide correct parity when writing to the registering clock driver control word configuration registers. PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Fly-By Topology 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM Temperature Sensor with Serial Presence-Detect EEPROM Temperature Sensor with Serial Presence-Detect EEPROM Thermal Sensor Operations The temperature from the integrated thermal sensor is monitored and converts into a digital word via the I2C bus. System designers can use the user-programmable registers to create a custom temperature-sensing solution based on system requirements. Programming and configuration details comply with JEDEC standard No. 21-C page 4.7-1, "Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor." DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Modules." These bytes identify module-specific timing parameters, configuration information, and physical attributes. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, permanently disabling hardware write protection. For further information refer to Micron technical note TN-04-42, "Memory Module Serial Presence-Detect." PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Serial Presence-Detect EEPROM Operation 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 8: Absolute Maximum Ratings Symbol Parameter Min Max Units VDD VDD supply voltage relative to VSS –0.4 1.975 V VIN, VOUT Voltage on any pin relative to VSS –0.4 1.975 V Symbol Parameter Min Nom Max Units VDD VDD supply voltage 1.425 1.5 1.575 V IVTT Termination reference current from VTT –600 – +600 mA VTT Termination reference voltage (DC) – command/address bus 0.49 × VDD - 20mV 0.5 × VDD 0.51 × VDD + 20mV V TBD TBD TBD µA –4 0 +4 II Input leakage current; Any input 0V ≤ VIN ≤ VDD; VREF input 0V ≤ VIN ≤ 0.95V (All other pins not under test = 0V) Address inputs, RAS#, CAS#, WE#, S#, CKE, ODT, BA, CK, CK# DM IOZ Output leakage current; DQ, DQS, 0V ≤ VOUT ≤ VDD; DQ DQS# and ODT are disabled; ODT is HIGH –10 0 +10 µA IVREF VREF supply leakage current; VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) –18 0 +18 µA Notes 1 TA Module ambient operating temperature Commercial 0 – +70 °C 2, 3 TC DDR3 SDRAM component case operating temperature Commercial 0 – +95 °C 2, 3, 4 Notes: PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 1. VTT termination voltage in excess of the stated limit will adversely affect the command and address signals’ voltage margin and will reduce timing margins. 2. TA and TC are simultaneous requirements. 3. For further information, refer to technical note TN-00-08: “Thermal Applications,” available on Micron’s Web site. 4. The refresh rate is required to double when 85°C < TC ≤ 95°C. 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Table 9: Operating Conditions 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR3 component data sheets. Component specifications are available on Micron’s Web site. Module speed grades correlate with component speed grades, as shown below. Table 10: Module and Component Speed Grades -1G9 -107 -1G6 -125 -1G4 -15E -1G1 -187E -1G0 -187 -80C -25E -80B -25 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Component Speed Grade 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM IDD Specifications IDD Specifications Table 11: DDR3 IDD Specifications and Conditions – 2GB (Die Revision G) Operating current 0: One bank ACTIVATE-to-PRECHARGE Operating current 1: One bank ACTIVATE-to-READ-toPRECHARGE IDD01 768 693 648 mA 1 918 873 828 mA 216 216 216 mA IDD1 IDD2P02 Precharge power-down current: Slow exit Precharge power-down current: Fast exit IDD2P1 2 540 540 450 mA Precharge quiet standby current IDD2Q2 720 630 630 mA 2 810 720 630 mA IDD2NT 1 603 558 513 mA Active power-down current IDD3P 2 630 540 540 mA Active standby current IDD3N2 810 720 720 mA Burst read operating current IDD4R1 1368 1233 1098 mA 1 1413 1233 1098 mA 1 Precharge standby current IDD2N Precharge standby ODT current Burst write operating current IDD4W Refresh current IDD5B 1638 1593 1548 mA Self refresh temperature current: MAX TC = 85°C IDD62 144 144 144 mA IDD6ET2 180 180 180 mA IDD71 2313 2223 1863 mA 252 252 252 mA Self refresh temperature current (SRT-enabled): MAX TC = 95°C All banks interleaved read current RESET low current IDD8 Notes: PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 2 1. One module rank in the active IDD, the other rank in IDD2P0 (slow exit). 2. All ranks in this IDD condition. 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Values are for the MT41J128M8 DDR3 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet Parameter Symbol 1600 1333 1066 Units 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM IDD Specifications Table 12: DDR3 IDD Specifications and Conditions – 4GB (Die Revision D) IDD01 Operating current 0: One bank ACTIVATE-to-PRECHARGE 1 Operating current 1: One bank ACTIVATE-to-READ-toPRECHARGE IDD1 IDD2P02 Precharge power-down current: Slow exit 963 873 783 mA 1053 1008 963 mA 216 216 216 mA Precharge power-down current: Fast exit IDD2P1 2 630 540 450 mA Precharge quiet standby current IDD2Q2 720 630 540 mA 2 720 630 540 mA 1 558 513 468 mA Precharge standby current IDD2N Precharge standby ODT current IDD2NT Active power-down current IDD3P 2 720 630 540 mA Active standby current IDD3N2 810 720 630 mA 1 1728 1548 1368 mA Burst write operating current IDD4W 1 1773 1593 1413 mA Refresh current IDD5B1 2043 1908 1818 mA Self refresh temperature current: MAX TC = 85°C IDD62 216 216 216 mA IDD6ET 270 270 270 mA IDD71 4023 3573 3123 mA 252 252 252 mA Burst read operating current IDD4R 2 Self refresh temperature current (SRT-enabled): MAX TC = 95°C All banks interleaved read current RESET low current IDD8 Notes: PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 2 1. One module rank in the active IDD, the other rank in IDD2P0 (slow exit). 2. All ranks in this IDD condition. 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Values are for the MT41J256M8 DDR3 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) component data sheet Parameter Symbol 1600 1333 1066 Units 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM IDD Specifications Table 13: DDR3 IDD Specifications and Conditions – 4GB (Die Revision M) Operating current 0: One bank ACTIVATE-to-PRECHARGE Operating current 1: One bank ACTIVATE-to-READ-toPRECHARGE IDD01 738 693 648 mA 1 828 783 738 mA IDD1 IDD2P02 Precharge power-down current: Slow exit 216 216 216 mA Precharge power-down current: Fast exit IDD2P1 2 666 576 486 mA Precharge quiet standby current IDD2Q2 720 630 540 mA 2 774 684 594 mA 1 513 468 423 mA Precharge standby current IDD2N Precharge standby ODT current IDD2NT Active power-down current IDD3P 2 900 810 720 mA Active standby current IDD3N2 990 900 810 mA 1 1512 1377 1278 mA Burst write operating current IDD4W 1 1413 1278 1143 mA Refresh current IDD5B1 1863 1818 1773 mA Self refresh temperature current: MAX TC = 85°C IDD62 216 216 216 mA IDD6ET 243 243 243 mA IDD71 2268 2133 1998 mA 234 234 234 mA Burst read operating current IDD4R 2 Self refresh temperature current (SRT-enabled): MAX TC = 95°C All banks interleaved read current RESET low current IDD8 Notes: PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 2 1. One module rank in the active IDD, the other rank in IDD2P0 (slow exit). 2. All ranks in this IDD condition. 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Values are for the MT41J256M8 DDR3 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) component data sheet Parameter Symbol 1600 1333 1066 Units 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM Registering Clock Driver Specifications Registering Clock Driver Specifications SSTE32882 devices or equivalent Parameter Symbol Pins Min Nom Max Units DC supply voltage VDD – 1.425 1.5 1.575 V DC reference voltage VREF – 0.49 × VDD - 20mV 0.5 × VDD 0.51 × VDD + 20mV V DC termination voltage VTT – 0.49 × VDD - 20mV 0.5 × VDD 0.51 × VDD + 20mV V AC high-level input voltage VIH(AC) Control, command, address VREF + 175mV – VDD + 400mV V AC low-level input voltage VIL(AC) Control, command, address –0.4 – VREF - 175mV V DC high-level input voltage VIH(DC) Control, command, address VREF + 100mV – VDD + 0.4 V DC low-level input voltage VIL(DC) Control, command, address –0.4 – VREF - 100mV V High-level input voltage VIH(CMOS) RESET#, MIRROR 0.65 × VDD – VDD V Low-level input voltage VIL(CMOS) RESET#, MIRROR 0 – 0.35 × VDD V Differential input crosspoint voltage range VIX(AC) CK, CK#, FBIN, FBIN# 0.5 × VDD - 175mV 0.5 × VDD 0.5 × VDD + 175mV V Differential input voltage VID(AC) CK, CK# 350 – VDD + TBD mV High-level output current IOH Err_Out# – – TBD mA Low-level output current IOL Err_Out# TBD – TBD mA Note: PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 1. Timing and switching specifications for the register listed are critical for proper operation of the DDR3 SDRAM RDIMMs. These are meant to be a subset of the parameters for the specific device used on the module. 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Table 14: Registering Clock Driver Electrical Characteristics 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM Temperature Sensor with Serial Presence-Detect EEPROM Temperature Sensor with Serial Presence-Detect EEPROM The temperature sensor continuously monitors the module's temperature and can be read back at any time over the I2C bus shared with the SPD EEPROM. Refer to JEDEC standard No. 21-C page 4.7-1, "Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor." Serial Presence-Detect For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD. Parameter/Condition Symbol Min Max Units VDDSPD 3.0 3.6 V Supply current: VDD = 3.3V IDD – 2.0 mA Input high voltage: Logic 1; SCL, SDA VIH 1.45 VDDSPD + 1 V Supply voltage Input low voltage: Logic 0; SCL, SDA VIL – 0.55 V Output low voltage: IOUT = 2.1mA VOL – 0.4 V Input current IIN –5.0 5.0 µA Temperature sensing range – –40 125 °C Temperature sensor accuracy (class B) – –1.0 1.0 °C Table 16: Temperature Sensor and EEPROM Serial Interface Timing Parameter/Condition Symbol Min Max Units tBUF 4.7 – µs SDA fall time tF 20 300 ns SDA rise time tR – 1000 ns tHD:DAT 200 900 ns Time bus must be free before a new transition can start Data hold time Start condition hold time tH:STA 4.0 – µs Clock HIGH period tHIGH 4.0 50 µs Clock LOW period tLOW 4.7 – µs tSCL 10 100 kHz Data setup time tSU:DAT 250 – ns Start condition setup time tSU:STA 4.7 – µs Stop condition setup time tSU:STO 4.0 – µs SCL clock frequency PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Table 15: Temperature Sensor with SPD EEPROM Operating Conditions 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM Temperature Sensor with Serial Presence-Detect EEPROM EVENT# Pin The temperature sensor also adds the EVENT# pin (open-drain). Not used by the SPD EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be set up in the sensor’s configuration register. EVENT# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. Event thresholds are programmed in the 0x01 register using a hysteresis. The alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. When the alarm window is enabled, EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by the user. The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by the user and returns to the logic HIGH state only when the temperature falls below the programmed thresholds. Critical temperature mode triggers EVENT# only when the temperature has exceeded the programmed critical trip point. When the critical trip point has been reached, the temperature sensor goes into comparator mode, and the critical EVENT# cannot be cleared through software. PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 The interrupt mode enables software to reset EVENT# after a critical temperature threshold has been detected. Threshold points are set in the configuration register by the user. This mode triggers the critical temperature limit and both the MIN and MAX of the temperature window. 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM Module Dimensions Module Dimensions Figure 3: 240-Pin DDR3 VLP RDIMM 4.0 (0.157) MAX Front view 133.50 (5.256) 133.20 (5.244) 0.75 (0.03) R (6X) U1 U2 U3 U4 U5 2.5 (0.098) D (2X) U7 U6 U8 U9 U10 18.9 (0.744) 18.6 (0.732) 9.5 (0.374) TYP 2.3 (0.091) TYP 0.76 (0.03) R Pin 1 2.2 (0.087) TYP Pin 120 1.0 (0.039) TYP 1.45 (0.057) TYP 0.8 (0.031) TYP 1.37 (0.054) 1.17 (0.046) 123.0 (4.84) TYP Back view U15 U11 U12 U13 U14 U16 U17 U18 U19 U20 3.0 (0.118) 4X TYP 3.05 (0.12) TYP Pin 240 47.0 (1.85) TYP 71.0 (2.79) TYP Notes: PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN Pin 121 5.0 (0.197) TYP 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 54.68 (2.15) TYP 2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM VLP RDIMM Revision History Revision History Rev. D – 12/11 • Updated 2GB IDDs with die revision 'G' (V68A:G) values • Added 4GB die revision 'M' (V79D:M) IDD table Rev. C – 8/10 • Updated with new, approved common topics. • Updated TBD values for I DDs. • • • • • • • • • • • • • Updated document format. Updated parameters with subscripts throughout document. Document name in header: Changed QR to DR. 240-Pin VLP RDIMM (MO-269 R/C L) figure: Changed PCB height to Module height. Options/Marking table: Deleted industrial temperature and marking; deleted 1G0, 80C, and 80B; deleted notes 1 and 2. Part Numbers and Timing Parameters – 2GB table: Deleted industrial temperature (I) option; deleted 1G3, 1G0, 80C, 80B. Part Numbers and Timing Parameters – 4GB table: Deleted industrial temperature (I) option; deleted 1G3, 1G0, 80C, 80B. Pin Assignments table: Changed the following pin assignments: 167 to NC. Pin Descriptions table: Address inputs: Added “A[14:0] address the 2Gb DDR3 devices;” Serial data: Deleted “on the module;” NU: Deleted. Component-to-Module DQ Map table: Added U14 and U16; changed U12 module pin number 06 to 106. Functional Block Diagram figure: Updated with TDQS and NF/TDQS#. Operating Conditions table: Deleted industrial temperatures; changed IVREF Max to +18. DDR3 IDD Specifications and Conditions – 2GB table: Deleted 800 column; changed slow exit symbol to IDD2P0; changed fast exit symbol to IDD2P1. • • DDR3 IDD Specifications and Conditions – 4GB table: Deleted 800 column; changed slow exit symbol to IDD2P0; changed fast exit symbol to IDD2P1; updated IDD values in 333 and 1066 columns. Rev. A – 4/09 • Initial release; PCB 0779 referenced. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef837c3c22 jdf18c256_512x72pdz.pdf – Rev. D 12/11 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. DRAFT: 12/19/2011 Rev. B – 11/09