256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Features DDR SDRAM UDIMM MT9VDDT3272A – 256MB MT9VDDT6472A – 512MB For component data sheets, refer to Micron’s Web site: www.micron.com Features Figure 1: • 184-pin, unbuffered dual in-line memory module (UDIMM) • Fast data transfer rates: PC2100, PC2700, or PC3200 • 256MB (32 Meg x 72) and 512MB (64 Meg x 72) • Supports ECC error detection and correction • Vdd = Vddq = +2.5V (-40B: Vdd = Vddq) • Vddspd = +2.3V to +3.6V • 2.5V I/O (SSTL_2-compatible) • Internal, pipelined double data rate (DDR) architecture; 2n-prefetch architecture • Bidirectional data strobe (DQS) transmitted/ received with data—that is, source-synchronous data capture • Differential clock inputs (CK and CK#) • Multiple internal device banks for concurrent operation • Single rank • Selectable burst lengths (BL): 2, 4, or 8 • Auto precharge option • Auto refresh and self refresh modes: 7.8125µs maximum average periodic refresh interval • Serial presence-detect (SPD) with EEPROM • Selectable CAS latency (CL) for maximum compatibility • Gold edge contacts Table 1: 184-Pin UDIMM (MO-206) PCB height: 31.75mm (1.25in) Options Marking • Operating temperature1 – Commercial (0°C ≤ TA ≤ +70°C) – Industrial (–40°C ≤ TA ≤ +85°C) • Package – 184-pin DIMM (standard) – 184-pin DIMM (Pb-free) • Memory clock, speed, CAS latency – 5.0ns (200 MHz), 400 MT/s, CL = 3 – 6.0ns (167 MHz), 333 MT/s, CL = 2.5 – 7.5ns (133 MHz), 266 MT/s, CL = 22 – 7.5ns (133 MHz), 266 MT/s, CL = 22 – 7.5ns (133 MHz), 266 MT/s, CL = 2.52 None I G Y -40B -335 -262 -26A -265 1. Contact Micron for industrial temperature module offerings. 2. Not recommended for new designs. Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 3 CL = 2.5 CL = 2 (ns) tRP (ns) tRC (ns) -40B -335 -262 -26A -265 PC3200 PC2700 PC2100 PC2100 PC2100 400 – – – – 333 333 266 266 266 266 266 266 266 200 15 18 15 20 20 15 18 15 20 20 55 60 60 65 65 Notes: PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN tRCD Notes 1 1. The values of tRCD and tRP for -335 modules show 18ns to align with industry specifications; actual DDR SDRAM device specifications are 15ns. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Features Table 2: Addressing Parameter Refresh count Row address Device bank address Device configuration Column address Module rank address Table 3: 256MB 512MB 8K 8K (A0–A12) 4 (BA0, BA1) 256Mb (32 Meg x 8) 1K (A0–A9) 1 (S0#) 8K 8K (A0–A12) 4 (BA0, BA1) 512Mb (64 Meg x 8) 2K (A0–A9, A11) 1 (S0#) Part Numbers and Timing Parameters – 256MB Base device: MT46V32M8,1 256Mb DDR SDRAM Part Number2 MT9VDDT3272AG-40B__ MT9VDDT3272AY-40B__ MT9VDDT3272AG-335__ MT9VDDT3272AY-335__ MT9VDDT3272AG-262__ MT9VDDT3272AG-26A__ MT9VDDT3272AG-265__ MT9VDDT3272AY-265__ Table 4: Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 3.2 GB/s 3.2 GB/s 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 5.0ns/400 MT/s 5.0ns/400 MT/s 6.0ns/333 MT/s 6.0ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 3-3-3 3-3-3 2.5-3-3 2.5-3-3 2-2-2 2-3-3 2.5-3-3 2.5-3-3 Part Numbers and Timing Parameters – 512MB Base device: MT46V64M8,1 512Mb DDR SDRAM Part Number2 MT9VDDT6472AG-40B__ MT9VDDT6472AY-40B__ MT9VDDT6472AG-335__ MT9VDDT6472AY-335__ MT9VDDT6472AG-262__ MT9VDDT6472AG-265__ MT9VDDT6472AY-265__ Notes: PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 512MB 512MB 512MB 512MB 512MB 512MB 512MB 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 3.2 GB/s 3.2 GB/s 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 5.0ns/400 MT/s 5.0ns/400 MT/s 6.0ns/333 MT/s 6.0ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 3-3-3 3-3-3 2.5-3-3 2.5-3-3 2-2-2 2.5-3-3 2.5-3-3 1. Data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT9VDDT6472AY-40BF1. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 5: Pin Assignments 184-Pin DDR UDIMM Front 184-Pin DDR UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 Vref DQ0 Vss DQ1 DQS0 DQ2 Vdd DQ3 NC NC Vss DQ8 DQ9 DQS1 Vddq CK1 CK1# Vss DQ10 DQ11 CKE0 Vddq DQ16 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 DQ17 DQS2 Vss A9 DQ18 A7 Vddq DQ19 A5 DQ24 Vss DQ25 DQS3 A4 Vdd DQ26 DQ27 A2 Vss A1 CB0 CB1 Vdd PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 DQS8 A0 CB2 Vss CB3 BA1 DQ32 Vddq DQ33 DQS4 DQ34 Vss BA0 DQ35 DQ40 Vddq WE# DQ41 CAS# Vss DQS5 DQ42 DQ43 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Vdd NC DQ48 DQ49 Vss CK2# CK2 Vddq DQS6 DQ50 DQ51 Vss NC DQ56 DQ57 Vdd DQS7 DQ58 DQ59 Vss NC SDA SCL 3 Symbol Pin Symbol Pin Symbol Pin Symbol Vss DQ4 DQ5 Vddq DM0 DQ6 DQ7 Vss NC NC NC Vddq DQ12 DQ13 DM1 Vdd DQ14 DQ15 NC Vddq NC DQ20 A12 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Vss DQ21 A11 DM2 Vdd DQ22 A8 DQ23 Vss A6 DQ28 DQ29 Vddq DM3 A3 DQ30 Vss DQ31 CB4 CB5 Vddq CK0 CK0# 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 Vss DM8 A10 CB6 Vddq CB7 Vss DQ36 DQ37 Vdd DM4 DQ38 DQ39 Vss DQ44 RAS# DQ45 Vddq S0# NC DM5 Vss DQ46 162 DQ47 163 NC 164 Vddq 165 DQ52 166 DQ53 167 NC 168 Vdd 169 DM6 170 DQ54 171 DQ55 172 Vddq 173 NC 174 DQ60 175 DQ61 176 Vss 177 DM7 178 DQ62 179 DQ63 180 Vddq 181 SA0 182 SA1 183 SA2 184 Vddspd Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions Symbol Type Description A0–A12 Input BA0, BA1 Input CK0, CK0#, CK1, CK1#, CK2, CK2# CKE0 Input Input DM0–DM8 Input RAS#, CAS#, WE# S0# Input SA0–SA2 Input SCL Input CB0–CB7 DQ0–DQ63 DQS0–DQS8 I/O I/O I/O SDA I/O Vdd/Vddq Vddspd Vref Vss NC Supply Supply Supply Supply – Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0 and BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Bank address: BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. Clock enable: CKE enables (registered HIGH) and CKE disables (registered LOW) the internal clock, input buffers, and output drivers. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Chip selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. Presence-detect address inputs: These pins are used to configure the SPD EEPROM address range on the I2C bus. Serial clock for SPD EEPROM: SCL is used to synchronize the presence-detect data transfer to and from the module. Check bits. Data input/output: Data bus. Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned with write data. Used to capture data. Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V) SPD EEPROM power supply: +2.3V to +3.6V. SSTL_2 reference voltage (Vdd/2). Ground. No connect: These pins are not connected on the module. Input PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S0# DQS0 DQS4 DM9 DM13 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ DQ DQ U1 DQ DQ DQ DQ DQ DQS1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ DQ DQ U6 DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ U7 DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ DQ DQ U8 DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ DQ DQ U9 DQ DQ DQ DQ DQ DQS5 DM10 DM14 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ U2 DQ DQ DQ DQ DQ DQS2 DQS6 DM11 DM15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ DQ DQ U3 DQ DQ DQ DQ DQ DQS3 DQS7 DM12 DM16 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ DQ DQ DQ U4 DQ DQ DQ DQ CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM CS# DQS DQ DQ DQ U5 DQ DQ DQ DQ DQ DQS8 DM17 BA0, BA1 A0–A12 RAS# CAS# WE# CKE0 PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN SCL U10 SPD EEPROM WP A0 A1 A2 VSS SA0 SA1 SA2 BA0, BA1: DDR SDRAM A0–A12: DDR SDRAM RAS#: DDR SDRAM CAS#: DDR SDRAM WE#: DDR SDRAM CKE0: DDR SDRAM 5 SDA CK0 CK0# U4–U6 CK1 CK1# U1–U3 CK2 CK2# U7–U9 Vddspd SPD EEPROM Vdd/Vddq DDR SDRAM Vref DDR SDRAM Vss DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM General Description General Description The MT9VDDT3272A and MT9VDDT6472A are high-speed, CMOS dynamic random access 256MB and 512MB memory modules organized in a x72 configuration. These modules use DDR SDRAM devices with 4 internal banks. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer 2 data words per clock cycle at the I/O pins. A single read or write access for DDR SDRAM modules effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and 2 corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various DDR SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0], which provide 8 unique DIMM/EEPROM addresses. Write protect (WP) is connected to Vss, permanently disabling hardware write protect. PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device’s data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 7: Symbol Vdd/Vddq Vin, Vout Ii Ioz TA Absolute Maximum Ratings Parameter Min Max Units Vdd/Vddq supply voltage relative to Vss Voltage on any pin relative to Vss Input leakage current; Any input 0V ≤ Vin ≤ Vdd; Address inputs, Vref input 0V ≤ Vin ≤ 1.35V (All other pins not under RAS#, CAS#, WE#, BA, test = 0V) S#, CKE CK, CK# DM Output leakage current; 0V ≤ Vout ≤ Vddq; DQ are DQ, DQS disabled DRAM ambient operating temperature1 Commercial Industrial –1.0 –0.5 –18 +3.6 +3.2 +18 V V µA –6 –2 –5 +6 +2 +5 µA 0 –40 +70 +85 °C °C Notes: PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN 1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available on Micron’s Web site. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Electrical Specifications DRAM Operating Conditions Recommended AC operating conditions are given in the DDR component data sheets. Component specifications are available on Micron’s Web site. Module speed grades correlate with component speed grades, as shown in Table 8. Table 8: Module and Component Speed Grades DDR components may exceed the listed module speed grades Module Speed Grade Component Speed Grade -40B -335 -262 -26A -265 -5B -6 -75E -75Z -75 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system’s memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Idd Specifications Table 9: Idd Specifications and Conditions – 256MB (Die Revision K) Values are for the MT46V32M8 DDR SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet Parameter/Condition t t Operating one bank active-precharge current: RC = RC (MIN); CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every 2 clock cycles Operating one bank active-read-precharge current: BL = 2; tRC = tRC (MIN); t CK = tCK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ, DM, and DQS Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); Iout = 0mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tRFC = tRFC (MIN) Auto refresh current tRFC = 7.8125µs Self refresh current: CKE ≤ 0.2V Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands Symbol -40B -335 Units Idd0 900 810 mA Idd1 1080 1035 mA Idd2P 36 36 mA Idd2F 450 450 mA Idd3P 315 270 mA Idd3N 540 495 mA Idd4R 1620 1440 mA Idd4W 1620 1440 mA Idd5 Idd5A Idd6 Idd7 1440 54 36 2610 1440 54 36 2430 mA mA mA mA t PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Table 10: Idd Specifications and Conditions – 256MB (All other Die Revisions) Values are for the MT46V32M8 DDR SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet Parameter/Condition Operating one bank active-precharge current: t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every 2 clock cycles Operating one bank active-read-precharge current: BL = 4; t RC = tRC (MIN); tCK = tCK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ, DM, and DQS Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); Iout = 0mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tRFC = tRFC (MIN) Auto refresh current tRFC = 7.8125µs Self refresh current: CKE ≤ 0.2V Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN 10 Symbol -40B -335 -262 -26A/ -265 Units Idd0 1215 1125 1125 1080 mA Idd1 1530 1530 1440 1305 mA Idd2P 36 36 36 36 mA Idd2F 540 450 405 405 mA Idd3P 360 270 225 mA Idd3N 630 540 450 225/ 270 450 Idd4R 1800 1575 1350 1350 mA Idd4W 1755 1575 1350 1350 mA Idd5 2340 2295 2115 mA Idd5A Idd6 Idd7 54 36 4230 54 36 3690 54 36 3150 2115/ 2205 54 36 3150/ 3285 mA mA mA mA Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Table 11: Idd Specifications and Conditions – 512MB Values are for the MT46V64M8 DDR SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) component data sheet Parameter/Condition t t Operating one bank active-precharge current: RC = RC (MIN); CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every 2 clock cycles Operating one bank active-read-precharge current: BL = 4; t RC = tRC (MIN); tCK = tCK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ, DM, and DQS Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); Iout = 0mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tRFC = tRFC (MIN) Auto refresh current tRFC = 7.8125µs Self refresh current: CKE ≤ 0.2V Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands Symbol -40B -335 -262 -26A/ -265 Units Idd0 1395 1170 1170 1035 mA Idd1 1665 1440 1440 1305 mA Idd2P 45 45 45 45 mA Idd2F 495 405 405 360 mA Idd3P 405 315 315 270 mA Idd3N 540 450 450 405 mA Idd4R 1710 1485 1485 1305 mA Idd4W 1755 1575 1395 1215 mA Idd5 Idd5A Idd6 Idd7 3105 99 45 4050 2610 90 45 3645 2610 90 45 3600 2520 90 45 3150 mA mA mA mA t PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Serial Presence-Detect Serial Presence-Detect Table 12: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Symbol Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: Iout = 3mA Input leakage current: Vin = GND to Vdd Output leakage current: Vout = GND to Vdd Standby current: SCL = SDA = Vdd - 0.3V; All other inputs = Vss or Vdd Power supply current: SCL clock frequency = 100 kHz Vddspd Vih Vil Vol Ili Ilo Isb Icc Table 13: Min Max 2.3 3.6 Vddspd × 0.7 Vddspd + 0.5 –1.0 Vddspd × 0.3 – 0.4 – 10 – 10 – 30 – 2.0 Units V V V V µA µA µA mA Serial Presence-Detect EEPROM AC Operating Conditions Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA fall time SDA rise time Data-in hold time Start condition hold time Clock HIGH period Clock LOW period SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: Symbol Min Max Units Notes tAA 0.2 1.3 200 – – 0 0.6 0.6 1.3 – 100 0.6 0.6 – 0.9 – – 300 300 – – – – 400 – – – 5 µs µs ns ns ns µs µs µs µs kHz ns µs µs ms 1 tBUF tHD:DAT tF tR tHD:DI tHD:STA tHIGH tLOW fSCL tSU:DAT tSU:STA tSU:STO tWRC 2 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. Serial Presence-Detect Data For the latest serial presence-detect data, refer to Micron’s SPD page: www.micron.com/SPD. PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Module Dimensions Module Dimensions Figure 3: 184-pin DDR UDIMM 3.18 (0.125) MAX Front view 133.50 (5.256) 133.20 (5.244) U10 2.0 (0.079) R (4X) U1 U2 U3 U4 U5 U6 U7 U8 U9 31.88 (1.255) 31.62 (1.245) 17.78 (0.7) TYP 2.5 (0.098) D (2X) 2.3 (0.091) TYP 0.9 (0.035) R 2.21 (0.087) TYP Pin 1 1.27 (0.05) TYP 1.0 (0.039) TYP 1.02 (0.04) TYP Pin 92 6.35 (0.25) TYP 1.37 (0.054) 1.17 (0.046) 120.65 (4.75) TYP Back view No components this side of module 2.92 (0.115) TYP Pin 93 Pin 184 49.53 (1.95) TYP 64.77 (2.55) TYP 10.0 (0.394) TYP 73.41 (2.89) TYP Notes: PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Module Dimensions 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C32_64x72A.fm - Rev. F 10/08 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved.