BH3856S / BH3856FS Audio ICs 2-wire serial sound control IC BH3856S / BH3856FS The BH3856S and BH3856FS are signal processing ICs designed for volume and tone control in televisions, mini component stereo systems, and other audio products. Their two-line serial control (I2C BUS) enables them to control volume and tone on the basis of signals from a microcomputer, etc. !Applications Televisions, [Video equipped television], personal computer televisions, mini component stereo systems, car stereos. !Features 1) I2C BUS facilitates direct serial control from a microcomputer of volume (main volume), balance (left / right), and tone (bass, treble). DC control is also possible. 2) Volume is produced by a low-distortion, low-noise VCA. Designed to minimize step noise. 3) Stable standard voltage supply and built-in I/O buffer mean that few attachments are needed. SSOP-A32 package designed to save space. 4) Matrix surround yields powerful sound. !Absolute maximum ratings (Ta = 25°C) Parameter Symbol Limits Unit Vcc 10.0 V Pd 1200 ∗1 850 ∗2 Power supply voltage Power dissipation BH3856S BH3856FS mW Operating temperature Topr −40~+85 °C Storage temperature Tstg −55~+150 °C ∗1 Reduced by 12mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 6.8mW for each increase in Ta of 1°C over 25°C. !Recommended operating conditions (Ta = 25°C) Parameter Power supply voltage Symbol Min. Typ. Max. Unit VCC 6.0 9 9.5 V Note : I2C BUS is a registered trademark of Philips. BH3856S / BH3856FS Audio ICs !Block diagram BH3856S A_GND 30k 30k 1 VCC 30 FILTER 29 IN2 28 BVN2 27 BIN2 26 BVO2 − − 2 BVN1 3 BIN1 4 BVO1 5 47k 7 47k + + − Volume Volume 5.1k Tone 6 TIN1 Tone TVN1 (Bass) 5.1k − (Bass) IN1 25 TVN2 24 TIN2 23 TVO2 22 OUT2 21 VC1 20 VC2 19 TC Matrix surround − − 10 SC 11 Volume Volume 30k Control VCC 2.1k + 9 + 8 (Treble) TVO1 OUT1 (Treble) 2.1k VCC 30k 200k 30k N.C. 12 SDA 13 18 BC SCL 14 17 Vref 30k Reference Voltage D_GND SLAVE ADDRESS 16 SELECT SW 15 BH3856FS A_GND 30k 1 30k VCC BVN1 3 BIN1 4 N.C. 5 BVO1 6 47k (Bass) 5.1k − FILTER 31 IN2 30 BVN2 47k + + − Tone Volume Volume Matrix surround TIN1 8 TVO1 9 OUT1 10 VCC 11 (Treble) (Treble) 7 29 N.C. 28 BIN2 27 BVO2 26 TVN2 5.1k Tone 2 (Bass) IN1 TVN1 32 − − 2.1k 25 TIN2 24 TVO2 23 OUT2 22 VC1 21 VC2 20 TC 19 BC 2.1k − Volume + + Volume Control − 30k VCC SC 12 SDA 13 N.C. 14 SCL 15 D_GND 16 30k 200k 30k 30k Reference Voltage 18 Vref SLAVE ADDRESS 17 SELECT SW BH3856S / BH3856FS Audio ICs !Pin descriptions Pin No. Function Pin name BH3856S BH3856FS Analog ground 1 1 A_GND 2 2 IN1 3 3 BVN1 Channel 1 bass filter 4 4 BIN1 Channel 1 bass filter 5 6 BVO1 Channel 1 bass filter 6 7 TVN1 Channel 1 treble filter 7 8 TIN1 Channel 1 treble filter 8 9 TVO1 Channel 1 treble filter Channel 1 volume output Channel 1 volume input 9 10 OUT1 10 11 VCC Power supply 11 12 SC Time constant pin for prevention of switching shock 13 13 SDA SDA data input pin 14 15 SCL SCL data input pin 15 16 D_GND 16 17 SASS 17 18 Vref Reference voltage output 18 19 BC Time constant pin for prevention of switching shock 19 20 TC Time constant pin for prevention of switching shock 20 21 VC2 Time constant pin for prevention of switching shock 21 22 VC1 Time constant pin for prevention of switching shock 22 23 OUT2 Channel 2 volume output 23 24 TVO2 Channel 2 treble filter 24 25 TIN2 Channel 2 treble filter 25 26 TVN2 Channel 2 treble filter 26 27 BVO2 Channel 2 bass filter 27 28 BIN2 Channel 2 bass filter 28 30 BVN2 Channel 2 bass filter 29 31 IN2 30 32 FILTER 12 5, 14, 29 N.C. Digital ground Slave address selection pin Channel 2 volulme input Filter Not connected internally. BH3856S / BH3856FS Audio ICs !Input / output circuits Symbol Pin voltage Equivalent circuit Description VCC IN1 IN2 4.5V 4.5V Main volume input pin. Designed for input impedance of 47kΩTyp.). 2pin 31pin 47kΩ A_GND 2/1VCC VCC BVN1 BVN2 4.5V 4.5V 50kΩ A_GND Pin for low band filter connection. 3pin 30pin VCC BIN1 BIN2 4.5V 4.5V 4pin 28pin Pin for low band filter connection. 5.1kΩ 2/1VCC A_GND VCC BVO1 BVO1 4.5V 4.5V 6pin 27pin 50kΩ Pin for low band filter connection. A_GND VCC 30kΩ FILTER 5.2V 32pin A_GND Filter input pin. Please install a capacitor of about 10µF to the filter pin. Has built-in precharge and discharge circuits. 30kΩ VCC TVN1 TVN2 4.5V 4.5V 25kΩ A_GND Pin for high band filter connection. 7pin 26pin VCC TIN1 TIN2 4.5V 4.5V 8pin 25pin Pin for high band filter connection. 2.1kΩ 2/1VCC A_GND ∗The pin numbers are for the BH3856S. BH3856S / BH3856FS Audio ICs Symbol Pin voltage Equivalent Circuit Description VCC TVO1 TVO2 4.5V 4.5V 25kΩ Pin for high band filter connection. 9pin 24pin A_GND VCC OUT1 OUT2 4.5V 4.5V Main volume output pin. OUT1 is the volume output for Channel 1. OUT2 is the volume output for Channel 2. 10pin 24pin A_GND VCC Digital SC BC TC VC1 VC2 VREF − 12pin 19pin 20pin 22pin 21pin A_GND For prevention of shock noise during step switching. SC : Surround pin BC : Bass pin TC : Treble pin VC1 : Volume pin (Channel 1) VC2 : Volume pin (Channel 2) VCC Vref 3.8V 3.8V regulator output pin. Output requires capacitor for stopping oscillation. Output pin has built-in precharge and discharge circuits, so there is no problem with start-up or shut-down even with a large capacitor. This pin is for connection to the high-band filter. 18pin A_GND VCC SDA SCL SASS − 2kΩ 13pin 15pin 17pin A_GND VCC − A_GND − Analog GND pin. Connected to IC board. D_GND − Digital GND pin. Separate from Analog GND pin. · I2C bass input pin SDA : serial data line SCL : serial clock line · Slave address selection pin SASS: slave address selection switch Power supply voltage pin. ∗The pin numbers are for the BH3856S. BH3856S / BH3856FS Audio ICs !Electrical characteristics (unless otherwise noted, Ta = 25°C, VCC = 9V, f = 1kHz, BW = 20 ~ 20kHz, VOL = Max., TONE = ALL FLAT, Rg = 600Ω, RL = 10kΩ) Parameter Quiescent current Symbol Min. Typ. Max. Unit IQ − 20 27 mA Conditions No signal Maximum input Vim 2.3 2.5 − Vrms Maximum output Vom 2.3 2.5 − Vrms Gv −1.5 0 +1.5 dB VIN=1Vrms Maximum attenuation ATT 90 110 − dB Vo=1Vrms Crosstalk VCT 70 80 − dB Vo=1Vrms VB Max. +12 +15 +18 dB 100Hz, VIN=100mVrms VB Min. −18 −15 −12 dB 100Hz, VIN=100mVrms Voltage gain Low range control width THD=1%, VOL=−20dB (ATT) THD=1% VT Max. +12 +15 +18 dB 100kHz, VIN=100mVrms VT Min. −18 −15 −12 dB 100kHz, VIN=100mVrms Matrix surround single-channel gain GSR 4 6 8 dB Vo=1Vrms Total Harmonic distortion THD − 0.01 0.1 % Vo=0.5Vrms, BPF=400Hz~30kHz Output noise voltage VNO1 − 45 65 µVrms No signal, VOL=Max., Rg=0 Residual output noise voltage VMNO − 2 10 µVrms No signal, VOL=−∞, Rg=0 Reference power supply output voltage Vref 3.5 3.8 4.1 V Reference power supply output current capacity Iref 3.0 10 − mA Vref > 3.7V GCB −1.5 0 +1.5 dB channel 1 taken as the standard for measurements. RIN kΩ f=1kHz f=1kHz High range control width Channel balance 33 47 61 − − 10 Ω Ripple rejection ratio RR 40 − − dB f=100Hz, VRR=1Vrms Input high level voltage VIH 4 − − V SCL, SDA Input low level voltage VIL − − 1 V SCL, SDA Output impedance ∗ ∗ Iref=3mA ROUT Input impedance ∗ ∗ Measurement performed using Matsushita Communication Industrial VP-9690A DIN AUDIO filter (average value wave detection, effective value display). Not designed for radiation resistance. Signal input occurs in equiphase. BH3856S / BH3856FS Audio ICs !Measurement circuit 30k + − 2 S4 − + 0.1µF + − 27 5.1k 5 2.1k 2200pF (Treble) 2200pF 7 C4 4.7k 10µF 25 Matrix surround (Treble) C3 Tone 6 Volume Volume 2.1k 2200pF 23 10µF 11 200k T1 VVC1 30k 21 VVC2 30k 20 S6 1 1 10µF T2 13 18 14 17 S7 10µF Reference voltage VCC VCC 15 BH3856S Fig.1 1 1.2k 16 Units : R [Ω] C [F] Note : Diagram depicts the BH3856S. THD VBC 30k 2 V 19 12 S5 10k V VTC 30k I VCC A 2 Volume VAOUT2 VCC V Volume VOUT2 10 22 − Control + VOUT1 10k VAOUT1 − + 9 10µF V 2200pF 10µF V V 24 8 THD 1 2 3 2 0.1µF 26 V S2 1 VAIN2 10µF VAIN1 5.1k 0.1µF 47k VAIN22 0.1µF 4 C2 VAIN11 47k (Bass) C1 4.7k V 28 3 2 (Bass) S3 1 0.47µF 29 Tone S1 30 VCC 0.47µF 3 2 1 1000µF 30k 1 2 V1 V BH3856S / BH3856FS Audio ICs !Performing data settings (1) I2C BUS timing Symbol Min. Typ. Max. Unit SCL clock frequency Parameter fSCL 0 − 100 kHz SCL clock hold time, HIGH state tHIGH 4 − − µs SCL clock hold time, LOW state tLOW 4.7 − − µs SDA and SDL signal start-up time tr − − 1 µs SDA and SDL signal shut-down time tf − − 0.3 µs Set-up time for re-send [start] conditions tSU;STA 4.7 − − µs Hold time (re-send) [start] conditions (After hold time ends, initial clock pulse is generated.) tHD;STA 4 − − µs Set time for [stop] conditions. tSU;STO 4.7 − − µs tBUF 4.7 − − µs tSU;DAT 250 − − ns Bus free time between [stop] condition and [start] condition Data set-up time tr tf SLC tLOW tHIGH SDA start condition tSU ; STA tHD ; STA tSU ; STO tBUF SDA stop condition SDA tSU ; DAT tHD ; DAT tSU ; STA = start code set-up time. tBUF = bus free time. tHD ; STA = start code hold time. tSU ; DAT = data set-up time. tSU ; STO = stop code set-up time. tHD ; DAT = data hold time. I2C BUS timing rules BH3856S / BH3856FS Audio ICs (2) I2C BUS data format MSB LSB MSB LSB MSB LSB S Slave address A Select address A Data A P 1bit 8bit 1bit 8bit 1bit 8bit 1bit 1bit •S • Slave address •A • Select address • Data •P = start condition (start bit recognition) = IC recognition. Upper 7 bits are random. Bottom bit is “L” for the sake of overwrite. = acknowledge bit (recognition of acknowledgment) = selection between volume, bass, treble and matrix surround. = volume and tone data = stop condition (stop bit recognition) (3) BH3856S / BH3856FS slave address MSB LSB A6 A5 A4 A3 A2 A1 A0 R/W 1 0 0 0 0 0 A 0 • Slave address selection 1) A = 1 (10000010) [SASS pin HIGH] 2) A = 0 (10000000) [SASS pin LOW] (4) Interface protocol 1) Basic protocol S A Slave address MSB LSB A Select address MSB LSB A Data P MSB LSB 2) Auto increment (Select address increases (+1) by the value of the data.) S A Slave address MSB LSB A Select address MSB LSB Data 1, data 2,...data N MSB A P A P LSB (Example 1) The address data specified by select address is taken as data 1. (Example 2) The address data specified by select address +1 is taken as data 2. (Example 3) The address data specified by select address +N−1 is taken as data N. 3) Structure with which transmission is not possible (In this case, only select address 1 is set.) S Slave address MSB A LSB Select address 1 MSB LSB A Data MSB LSB A Select address 2 MSB Note : Following transmission of data, data transmitted as select address 2 will not be recognized as select address 2, but as data. LSB A Data MSB LSB BH3856S / BH3856FS Audio ICs (5) Specification of select address and data Function LSB D7 D6 D5 Data D4 D3 D2 D1 D0 MSB Select address MSB LSB 0 Volume ch1 (L) 0 0 0 0 0 0 0 0 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 1 Volume ch2 (R) 0 0 0 0 0 0 0 1 VR7 VR6 VR5 VR4 VR3 VR2 VR1 VR0 2 Bass 0 0 0 0 0 0 1 0 0 0 BA5 BA4 BA3 BA2 BA1 BA0 3 Treble 0 0 0 0 0 0 1 1 0 0 TR5 TR4 TR3 TR2 TR1 TR0 4 Surround 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 SR0 ∗The auto increment function cycles the select address in the manner shown in Figure A. (Fig. A) 0 → 1 → 2 ↑ ↓ 4 ← ← ←3 ∗The cycle commences from the initially specified select address. (6) Surround data Function MSB Matrix surround OFF Matrix surround ON Data D4 D3 D6 D5 0 0 0 0 0 0 0 0 D7 (7) Matrix surround + + + L→ + Input R→ Output (2L−R) + ×1 + ×1 Input + Output (2R−L) LSB D2 D1 D0 0 0 0 0 0 0 0 1 BH3856S / BH3856FS Audio ICs (8) Volume attenuation (reference values) ATT (dB) DATA (HEX) ATT (dB) DATA (HEX) ATT (dB) DATA (HEX) 0 FF −19 85 −56 42 −1 E4 −20 82 −58 3F −2 D8 −22 7C −60 3C −3 CF −24 78 −62 39 −4 C8 −26 74 −64 36 −5 C2 −28 70 −66 34 −6 BD −30 6D −68 32 −7 B8 −32 6A −70 2F −8 B2 −34 68 −72 2D −9 AD −36 65 −74 2A −10 A9 −38 61 −76 28 −11 A5 −40 5C −78 26 −12 A0 −42 59 −80 24 −13 9C −44 55 −82 22 −14 98 −46 52 −84 20 −15 94 −48 4E −86 1E −16 90 −50 4B −90 1A −17 8C −52 48 −100 13 −18 89 −54 45 −112 00 Note : All figures in this table are reference values. When using this IC, check this table carefully and perform the appropriate setting. (9) Bass / Treble gain settings (reference values) ATT (dB) DATA (HEX) ATT (dB) DATA (HEX) 15 3F 0 1F 14 38 −1 1C 13 35 −2 1B 12 33 −3 19 11 31 −4 18 10 2F −5 17 9 2E −6 16 8 2D −7 15 7 2C −8 13 6 2B −9 12 5 2A −10 11 4 29 −11 0F 3 27 −12 0D 2 26 −13 0B 1 25 −14 08 0 1F −15 05 Notes : (1) The gain values in the treble and bass data setting tables above are based on the assumption that the filter constants have been set so that maximum and minimum gain are equal to the peak and bottom values listed in the frequency characteristics drawings. (2) All figures in this table are reference values. When using this IC, check this table carefully and perform the appropriate setting. BH3856S / BH3856FS Audio ICs !Application example 10µF 30k 30k VCC 1 30 + − 0.47µF AGND 3 C1 28 47k 47k 0.1µF + − (Bass) 5.1k 0.1µF − + (Bass) 4 C2 5.1k C2 0.1µF C3 2200pF C4 2200pF 25 surround (Treble) (Treble) 2.1k 8 Tone Tone 7 Volume Volume Matrix 2200pF 2200pF 0.1µF 26 6 C4 C1 27 5 C3 0.47µF 29 2 24 2.1k 23 10µF 10µF + − VCC 33µF Volume Control 10 VCC 22 − Volume 11 0.22µF + 9 30k 21 0.22µF 30k 20 200k DGND 0.033µF 30k 12 19 3.3µF 30k MICRO COMPUTER 13 18 14 17 10µF Reference voltage AGND 16 15 BH3856S Fig.2 Note : Diagram depicts the BH3856S. DGND BH3856S / BH3856FS Audio ICs !Operation notes (1) Operating power supply voltage range As long as the operating power supply voltage and ambient temperature are kept within the specified range, the basic circuits are guaranteed to function, but be sure to check the constants as well as the element settings, voltage settings, and temperature settings. (2) Bass filter C1 BVO −3dB 0.1µF R2 50kΩ C2 BIN BVN − + 0.1µF R1 5.1kΩ IC internal BIAS IC internal BIAS ( 12 Vcc ) ( 12 Vcc ) f0 ∆f ∗B.P.F. composed of multiple feedback active f0 can be varied according to the value of C.BIN (theoretical equation) f0 = 1 × 2π G= R2 C1 × 1+ 5kΩ C2 1 R1R2C1C2 1 2 Q 1 R2C1C2 1.0 × 10−5 C Q × (C1 + C2) −1 Note : Filter gain is calculated using the equation on the left. Total output gain is the sum of the gain for each of the internal circuits. −1 (When R1 = 5.1kΩ, R2 = 50kΩ, C1 = C2 = C) f0 = 1 2 1.57 G = 5.0 Frequency f: (Hz) BH3856S / BH3856FS Audio ICs (3) About the treble filter C3 TVO −3dB 2200pF R2 25kΩ C4 TIN TVN − R1 2.1kΩ + 2200pF IC internal BIAS IC internal BIAS ( 12 Vcc ) ( 12 Vcc ) f0 Frequency f: (Hz) ∆f ∗The band-pass filter is constructed using a multiple-feedback active filter. f0 can be varied by changing the value of the capacitors. (Theoretical formulas) f0 = 1 × 2π G= R2 C3 × 1+ 5kΩ C4 1 R1R2C3C4 1 2 1 Q R1 R2C3C4 2 × (C3 + C4) −1 Note : The filter gain is given by the formula on the left, but the total output gain is determined by the this in combination with the internal circuit. −1 (When R1 = 2.1kΩ, R2 = 25kΩ, C3 = C4 = C) f0 = 2.2 × 10−5 C Q 1.73 G = 2.5 (4) I2C BUS control High-frequency digital signals are input on the SCL and SDA terminals, so ensure that the wiring and PCB pattern is designed in such a way as to ensure that these signals do not interfere with the analog signal system. If you are not using I2C BUS control (i.e. you are using DC control), connect the SCL, SDA and SASS terminals to GND (do not leave them disconnected). (5) Step switching noise The VC1, VC2, TC, BC and SC terminals have components connected to them the application example. The values of these components may need to be changed depending on the signal level setting and PCB pattern. Investigate carefully before deciding on the values of the various circuit constants. The equivalent circuit for these terminals is given below (an integrator circuit is set at the first stage to slow the variation). Each Pin R C + − R value (kΩ) VC1, VC2, BC, TC 30 SC 200 (6) Volume and tone level settings This specification sheet gives reference values for the amount of attenuation and gain with respect to the serial control data. The internal D / A convertor is an R-2R circuit, and data exists for the places where continuous variation does not occur between data. Use this when fine setting is required. The setting limits are up to 8 bits for volume (256 steps) and 6 bits (64 steps) for tone. BH3856S / BH3856FS Audio ICs (7) Digital / analog separation The digital and analog power supplies and grounds for this IC (BH3856) are completely separate. The digital circuits are supplied from a stable reference source that is on the chip (Vref (3.8V)). For this reason, there is no need to worry about timing shifts, on interference due to digital noise. (8) Matrix surround + + + L→ + Input R→ Output (2L-R) + ×1 + ×1 Input + Output (2R-L) ∗The matrix surround circuit construction is as shown in the diagram above. The gain is obtained from the formulas in the diagram. Phase Gain 0dB Negative Phase Gain 6dB (However, reverse-phase gain is for input to one channel only) (9) DC control An internal impedance of 30kΩ is seen from the VC1, VC2, TC and BC terminals, are 200kΩ is seen from the SC (pin 11) terminal, so with regard to DC control, we recommend direct control with the voltage source. When using variable volume, take the impedance into consideration when making the setting. Note : The DC control voltage range is 0V to Vref. Do not apply voltages above Vref to the terminals. (10) GND • As shown in the application circuit example, connect the external component GND to the analog GND. • However, the GND for the capacitor connected to the Vref terminal should be connected to the digital GND. • If a capacitor with goof high-frequency characteristics is connected in parallel with the capacitor connected to Vref, the performances of the circuit with respect to static noise will improve (we recommend a ceramic capacitor of between 0.001µF and 0.1µF) • When using long digital and analog ground lines, take care to ensure that there is no potential difference between the two ground lines. BH3856S / BH3856FS Audio ICs !Electrical characteristic curves QUIESCENT CURRENT : IQ (mA) TOTAL HARMONIC DISTORTION : THD (%) RL = 10kΩ 22 20 18 16 14 12 10 8 6 4 2 0 5 7 6 8 9 10 1 25 VCC = 9V f = 1kHz VCC = 9V RL = 10kΩ 20 0.4 VOLTAGE GAIN : GBT (dB) 24 0.1 0.04 15 10 5 0 −5 −10 −15 −20 0.01 −40 POWER SUPPLY VOLTAGE : VCC (V) Fig. 3 Quiescent curve vs. Power supply voltage −30 −20 −10 0 −25 10 10 100 1k 10k FREQUENCY : f (Hz) Fig.4 Total harmonic distortion vs. Input voltage Fig. 5 Output gain vs. Frequency !External dimensions (Units : mm) BH3856FS BH3856S 28.0±0.3 30 16 3.2±0.2 0.3±0.1 17 1 16 0.8 0.36±0.1 0.15±0.1 7.8±0.3 1.8±0.1 10.16 32 5.4±0.2 15 0.11 0.51Min. 4.7±0.3 8.4±0.3 13.6±0.2 1 0.3Min. 0.15 0.5±0.1 1.778 SDIP30 100k INPUT VOLTAGE : VIN (dBV) 0°~15° SSOP-A32