a FEATURES Monolithic 10-Bit/75 MSPS Converter ECL Outputs Bipolar (ⴞ1.75 V) Analog Input 57 dB SNR @ 2.3 MHz Input Low (45 pF) Input Capacitance APPLICATIONS Digital Oscilloscopes Medical Imaging Professional Video Radar Warning/Guidance Systems Infrared Systems 10-Bit 75 MSPS A/D Converter AD9060 FUNCTIONAL BLOCK DIAGRAM MSB LSBs INVERT INVERT 61 59 OVERFLOW AIN +VREF +VSENSE R/2 512 R AD9060 385 R/2 3/4REF R/2 GENERAL DESCRIPTION The AD9060 A/D converter is a 10-bit monolithic converter capable of word rates of 75 MSPS and above. Innovative architecture using 512 input comparators instead of the traditional 1024 required by other flash converters reduces input capacitance and improves linearity. R 1/2REF R/2 The AD9060 is available in a 68-lead ceramic leaded (gull wing) chip carrier package specifically designed for low thermal impedances. Two performance grades for temperatures of both 0°C to +70°C and –55°C to +125°C ranges are offered to allow the user to select the linearity best suited for each application. Dynamic performance is fully characterized and production tested at 25°C. 257 R/2 Inputs and outputs are ECL compatible, which makes the AD9060 the recommended choice for systems with conversion rates >30 MSPS to minimize system noise. An overflow bit is provided to indicate analog input signals greater than +VSENSE. Voltage sense lines are provided to ensure accurate driving of the ± VREF voltages applied to the units. Quarter point taps on the resistor ladder help optimize the integral linearity of the unit. 384 R 256 R R 129 C O M P D A E R C A O OVERFLOW OVERFLOW T D O E R L L O 10 1024 A G T I C C H E S 51 OVERFLOW 50 D9 (MSB) 49 D8 48 D7 L A T C H R/2 46 D5 23 D4 22 D3 21 D2 20 D1 19 D0 (LSB) 1/4REF 63 R/2 47 D6 128 R R R 2 1 R/2 –VSENSE 57 –VREF 56 ENCODE ENCODE –VS +VS GND REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD9060–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (+V = +5 V; –V = –5.2 V; ⴞV S Parameter Temp Test Level RESOLUTION S Min SENSE = ⴞ1.75 V; ENCODE = 60 MSPS, unless otherwise noted.)1 AD9060JZ Typ Max 10 Min AD9060KZ Typ Max 10 Unit Bits 1 DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes ANALOG INPUT Input Bias Current2 Input Resistance Input Capacitance2 Analog Bandwidth REFERENCE INPUT Reference Ladder Resistance Ladder Tempco Reference Ladder Offset Top of Ladder Bottom of Ladder Offset Drift Coefficient SWITCHING PERFORMANCE Conversion Rate Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Delay (tOD)3 Output Rise Time Output Fall Time Output Time Slew3 25°C Full 25°C Full Full I VI I VI VI 1.0 25°C Full 25°C 25°C 25°C I VI I V V 0.4 25°C Full Full I VI V 25°C Full 25°C Full Full I VI I VI V 25°C 25°C 25°C 25°C 25°C 25°C 25°C I V V I I I I DYNAMIC PERFORMANCE Transient Response 25°C Overvoltage Recovery Time 25°C Effective Number of Bits (ENOB) 25°C fIN = 2.3 MHz 25°C fIN = 10.3 MHz fIN = 29.3 MHz 25°C Signal-to-Noise Ratio4 fIN = 2.3 MHz 25°C fIN = 10.3 MHz 25°C fIN = 29.3 MHz 25°C 1.25 1.25 1.5 2.0 2.5 0.75 1.0 1.25 1.5 2.0 LSB LSB LSB LSB 1.0 2.0 mA mA kΩ pF MHz 56 66 Ω Ω Ω/°C 90 90 90 90 50 mV mV mV mV µV/°C 1 5 4 1 1 1.5 MSPS ns ps, rms ns ns ns ns 1.0 Guaranteed 2.0 7.0 45 175 22 14 37 1.0 2.0 56 66 0.4 2.0 7.0 45 175 22 14 37 0.1 45 45 0.1 90 90 90 90 45 45 50 75 2 V V 75 1 5 4 1 1 1.5 9 3 3 3 2 10 10 9 3 3 3 10 10 ns ns I IV IV 8.7 8.0 7.0 9.1 8.6 7.4 8.7 8.0 7.0 9.1 8.6 7.4 Bits Bits Bits I I I 54 51 44 56 54 47 54 51 44 56 54 47 dB dB dB –2– REV. B AD9060 Parameter Temp Test Level Min 25°C 25°C 25°C I I I 54 51 46 56 55 48 54 51 46 58 55 48 dB dB dB 61 55 47 65 58 50 61 55 47 65 58 50 dBc dBc dBc 70 0.5 1 dBc Degrees % DYNAMIC PERFORMANCE (continued) Signal-to-Noise Ratio4 (Without Harmonics) fIN = 2.3 MHz fIN = 10.3 MHz fIN = 29.3 MHz Harmonic Distortion fIN = 2.3 MHz fIN = 10.3 MHz fIN = 29.3 MHz Two-Tone Intermodulation Distortion Rejection5 Differential Phase Differential Gain 25°C 25°C 25°C I I I 25°C 25°C 25°C V V V ENCODE INPUT Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance Pulsewidth (High) Pulsewidth (Low) Full Full Full Full 25°C 25°C 25°C VI VI VI VI V I I DIGITAL OUTPUTS Logic 1 Voltage Logic 0 Voltage Full Full VI VI 25°C Full 25°C Full 25°C Full VI VI VI VI VI VI Full VI POWER SUPPLY +VS Supply Current –VS Supply Current Power Dissipation Power Supply Rejection Ratio (PSRR)6 AD9060JZ Typ Max Min 70 0.5 1 –1.1 AD9060KZ Typ Max –1.1 150 150 5 –1.5 300 300 6 6 150 150 5 –1.5 300 300 6 6 –1.1 –1.1 –1.5 420 150 2.8 6 500 500 180 190 3.3 3.5 10 420 150 2.8 6 Unit V V µA µA pF ns ns –1.5 V V 500 500 180 190 3.3 3.5 mA mA mA mA W W 10 mV/V NOTES 1 3/4REF, 1/2REF, and 1/4REF reference ladder taps are driven from dc sources at +0.875 V, 0 V, and –0.875 V, respectively. Outputs terminated through 100 Ω to –2.0 V; CL < 4 pF. Accuracy of the overflow comparator is not tested and not included in linearity specifications. 2 Measured with A IN = +VSENSE 3 Output delay measured as worst-case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or falling edge of D0–D9. Output skew measured as worst-case difference in output delay among D0–D9. 4 RMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency. 5 Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale. 6 Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change in + VS or –VS. Specifications subject to change without notice. REV. B –3– AD9060 ABSOLUTE MAXIMUM RATINGS 1 MECHANICAL INFORMATION (DIE LAYOUT) +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V AIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +2 V +VREF, –VREF, 3/4REF, 1/2REF, 1/4REF . . . . . . . . . –2 V to +2 V +VREF to –VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V ENCODE, ENCODE . . . . . . . . . . . . . . . . . . . . . . . 0 V to –VS 3/4REF, 1/2REF, 1/4REF Current . . . . . . . . . . . . . . . . . . . ± 10 mA Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature AD9060JZ/AD9060KZ . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature2 . . . . . . . . . . . . . . . . . 150°C Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . . 300°C Die Dimensions . . . . . . . . . 206 mils × 140 mils × 15 (± 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 4 mils × 4 mils Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride GND +VS GND GND +VS –VS –VS +VS –VS GND GND –VS –VS +VS GND GND +VS DIE LAYOUT NC = NO CONNECT +VS GND GND +VS –VS 1/4REF NC MSB INVERT EXPLANATION OF TEST LEVELS Test Level 1/2REF AIN AIN NOTES 1 Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances (part soldered onto board): 68 -lead ceramic chip carrier: θ JC = 1°C/W; θ JA = 17°C/W (no air flow); θ JA = 15°C/W (air flow = 500 LFM). GND D5 D6 D7 D8 D9 OVERFLOW GND GND –VS NC –VREF –VSENSE LSB INVERT 3/4REF +VS GND GND +VS –VS GND D4 D3 D2 D1 (LSB) D0 GND GND –VS +VS ENCODE ENCODE +VREF +VSENSE I. II. 100% production tested. 100% production tested at 25°C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. All devices are 100% production tested at 25°C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices. ORDERING GUIDE Model Temperature Range Package Description Package Options AD9060JZ AD9060KZ AD9060/PCB 0°C to 70°C 0°C to 70°C 0°C to 70°C Leaded Chip Carrier Leaded Chip Carrier Evaluation Board Z-68D Z-68D CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9060 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. B AD9060 AIN AIN 3/4REF +VS GND GND +VS –VS 1/2REF +VS GND GND +VS –VS 1/4REF NC MSB INVERT PIN CONFIGURATION 61 60 9 10 NC +VSENSE +VREF ENCODE ENCODE +VS –VS GND GND (LSB) D0 D1 D2 D3 D4 NC GND NC AD9060 TOP VIEW (Not to Scale) 26 27 GND –VS –VS +VS GND GND +VS +VS –VS GND +VS GND GND +VS –VS –VS GND 44 43 NC LSBs INVERT NC –VSENSE –VREF NC –VS GND GND OVERFLOW D9 (MSB) D8 D7 D6 D5 GND NC NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 1/2REF Midpoint of Internal Reference Ladder. 2, 16, 28, 29, 35, 41, 42, 54, 64 –VS Negative Supply Voltage; Nominally –5.2 V ± 5%. 3, 6, 15, 30, 33, 34, 37, 40, 65, 68 +VS Positive Supply Voltage; Nominally +5 V ± 5%. 4, 5, 17, 18, 25, 27, 31, 32, 36, 38, 39, 43, 45, 52, 53, 66, 67 GND All ground pins should be connected together and to low impedance ground plane. 7 3/4REF Three-Quarter Point of Internal Reference Ladder. 8, 9 AIN Analog Input; Nominally between ± 1.75 V. 11 +VSENSE Voltage Sense Line to Most Positive Point on Internal Resistor Ladder. Normally 1.75 V. 12 +VREF Voltage Force Connection for Top of Internal Reference Ladder. Normally driven to provide 1.75 V at +VSENSE. 13 ENCODE Differential ECL Convert Signal, Starts Digitizing Process. 14 ENCODE ECL Compatible Convert Command, Used to Begin Digitizing Process. 19–23, 46–50 D0–D9 ECL Compatible Digital Output Data. 51 OVERFLOW ECL Compatible Output Indicating AIN > +VSENSE. 56 –VREF Voltage Force Connection for Bottom of Internal Reference Ladder. Normally driven to provide –1.75 V at –VSENSE. 57 –VSENSE Voltage Sense Line to Most Negative Point on Internal Resistor Ladder. Normally –1.75 V. 59 LSBs INVERT Normally Grounded. When connected to +VS, lower order bits (D0–D8) are inverted. Not ECL compatible. 61 MSB INVERT Normally Grounded. When connected to +VS, most significant bit (MSB; D9) is inverted. Not ECL compatible. 63 1/4REF One-Quarter Point of Internal Reference Ladder. REV. B –5– AD9060 Refer to the Functional Block Diagram. As shown, the AD9060 uses a modified “flash,” or parallel, A/D architecture. The analog input range is determined by an external voltage reference (+VREF and –VREF), nominally ± 1.75 V. An internal resistor ladder divides this reference into 512 steps, each representing two quantization levels. Taps along the resistor ladder (1/4REF, 1/2REF, and 3/4REF) are provided to optimize linearity. Rated performance is achieved by driving these points at 1/4, 1/2, and 3/4, respectively, of the voltage reference range. Two-Tone Intermodulation Distortion (IMD) is a frequently cited specification in receiver design. In narrow-band receivers, thirdorder IMD products result in spurious signals in the pass band of the receiver. Like mixers and amplifiers, the ADC is characterized with two, equal amplitude, pure input frequencies. The IMD equals the ratio of the power of either of the two input signals to the power of the strongest third order IMD signal. Unlike mixers and amplifiers, the IMD does not always behave as it does in linear devices (reduced input levels do not result in predictable reductions in IMD). The A/D conversion for the nine most significant bits (MSB) is performed by 512 comparators. The value of the least significant bit (LSB) is determined by a unique interpolation scheme between adjacent comparators. The decoding logic processes the comparator outputs and provides a 10-bit code to the output stage of the converter. Performance graphs provide typical harmonic and SNR data for the AD9060 for increasing analog input frequencies. In choosing an A/D converter, always look at the dynamic range for the analog input frequency of interest. The AD9060 specifications provide guaranteed minimum limits at three analog test frequencies. Flash architecture has an advantage over other A/D architectures because conversion occurs in one step. This means the performance of the converter is limited primarily by the speed and matching of the individual comparators. In the AD9060, an innovative interpolation scheme takes advantage of the flash architecture but minimizes the input capacitance, power, and device count usually associated with that method of conversion. Aperture Delay is the delay between the rising edge of the ENCODE command and the instant at which the analog input is sampled. Many systems require simultaneous sampling of more than one analog input signal with multiple ADCs. In these situations timing is critical, and the absolute value of the aperture delay is not as critical as the matching between devices. THEORY OF OPERATION Aperture Uncertainty, or jitter, is the sample-to-sample variation in aperture delay. This is especially important when sampling high slew rate signals in wide bandwidth systems. Aperture uncertainty is one of the factors that degrades dynamic performance as the analog input frequency is increased. These advantages occur because of using only half the normal number of input comparator cells to accomplish the conversion. In addition, a proprietary decoding scheme minimizes error codes. Input control pins allow the user to select from among binary, inverted binary, twos complement, and inverted twos complement coding (see Table I, the AD9060 Truth Table). Digitizing Oscilloscopes Oscilloscopes provide amplitude information about an observed waveform with respect to time. Digitizing oscilloscopes must accurately sample this signal without distorting the information to be displayed. APPLICATIONS Many of the specifications used to describe A/D converters have evolved from system performance requirements in these applications. Different systems emphasize particular specifications, depending on how the part is used. The following applications highlight some of the specifications and features that make the AD9060 attractive in these systems. One figure of merit for the ADC in these applications is Effective Number of Bits (ENOB). ENOB is calculated with a sine wave curve fit and equals [ ] ENOB = N – log2 Error (measured ) Error (ideal ) Wideband Receivers N is the resolution (number of bits) of the ADC. The measured error is the actual rms error calculated from the converter outputs with a pure sine wave input. Radar and communication receivers (baseband and direct IF digitization), ultrasound medical imaging, signal intelligence, and spectral analysis all place stringent ac performance requirements on analog-to-digital converters (ADCs). Frequency domain characterization of the AD9060 provides signal-to-noise ratio (SNR) and harmonic distortion data to simplify selection of the ADC. The Analog Bandwidth of the converter is the analog input frequency at which the spectral power of the fundamental signal is reduced 3 dB from its low frequency value. The analog bandwidth is a good indicator of a converter’s slewing capabilities. Receiver sensitivity is limited by the Signal-to-Noise Ratio (SNR) of the system. The SNR for an ADC is measured in the frequency domain and calculated with a Fast Fourier Transform (FFT). The SNR equals the ratio of the fundamental component of the signal (rms amplitude) to the rms value of the noise. The noise is the sum of all other spectral components, including harmonic distortion but excluding dc. The Maximum Conversion Rate is defined as the encode rate at which the SNR for the lowest analog signal test frequency tested drops by no more than 3 dB below the guaranteed limit. Imaging Visible and infrared imaging systems each require similar characteristics from ADCs. The signal input (from a CCD camera or multiplexer) is a time division multiplexed signal consisting of a series of pulses whose amplitude varies in direct proportion to the intensity of the radiation detected at the sensor. These varying levels are then digitized by applying ENCODE commands at the correct times, as shown in Figure 1. Good receiver design minimizes the level of spurious signals in the system. Spurious signals developed in the ADC are the result of imperfections in the device transfer function (nonlinearities, delay mismatch, varying input impedance, and so on). In the ADC, these spurious signals appear as Harmonic Distortion. Harmonic Distortion is also measured with an FFT and is specified as the ratio of the fundamental component of the signal (rms amplitude) to the rms value of the worstcase harmonic (usually the second or third). –6– REV. B AD9060 1111111111 +FS (NOT TO SCALE) AIN AD9060 TAPS DRIVEN –FS OUTPUT CODE 1100000000 ENCODE Figure 1. Imaging Application Using AD9060 The actual resolution of the converter is limited by the thermal and quantization noise of the ADC. The low frequency test for SNR or ENOB is a good measure of the noise of the AD9060. At this frequency, the static errors in the ADC determine the useful dynamic range of the ADC. Although the signal being sampled does not have a significant slew rate, this does not imply that dynamic performance is not important. The Transient Response and Overvoltage Recovery Time specifications ensure that the ADC can track full-scale changes in the analog input sufficiently fast to capture a valid sample. Transient Response is the time required for the AD9060 to achieve full accuracy when a step function is applied. Overvoltage Recovery Time is the time required for the AD9060 to recover to full accuracy after an analog input signal 150% of full scale is reduced to the full-scale range of the converter. Professional Video Digital Signal Processing (DSP) is now common in television production. Modern studios rely on digitized video to create stateof-the-art special effects. Video instrumentation also requires high resolution ADCs for studio quality measurement and frame storage. The AD9060 provides sufficient resolution for these demanding applications. Conversion speed, dynamic performance, and analog bandwidth are suitable for digitizing both composite and RGB video sources. USING THE AD9060 Voltage References The AD9060 requires the user to provide two voltage references: +VREF and –VREF. These two voltages are applied across an internal resistor ladder (nominally 37 Ω) and set the analog input voltage range of the converter. The voltage references should be driven from a stable, low impedance source. In addition to these two references, three evenly spaced taps on the resistor ladder (1/4REF, 1/2REF, and 3/4REF) are available. Providing a reference to these quarter points on the resistor ladder will improve the integral linearity of the converter and improve ac performance (ac and dc specifications are tested while driving the quarter points at the indicated levels). The figure below is not intended to show the transfer characteristic of the ADC but illustrates how the linearity of the device is affected by the reference voltages applied to the ladder. REV. B TAPS FLOATING 1000000000 IDEAL LINEARITY 0100000000 0000000000 –VSENSE 1/4REF 1/2REF VIN 3/4REF +VSENSE Figure 2. Effect of Reference Taps on Linearity Resistance between the reference connections and the taps of the first and last comparators causes offset errors. These errors, called “top and bottom of the ladder offsets,” can be nulled by using the voltage sense lines, +VSENSE and –VSENSE, to adjust the reference voltages. Current through the sense lines should be limited to less than 100 µA. Excessive current drawn through the voltage sense lines will affect the accuracy of the sense line voltage. Figure 4 shows a reference circuit that nulls out the offset errors using two op amps and provides appropriate voltage references to the quarter-point taps. Feedback from the sense lines causes the op amps to compensate for the offset errors. The two transistors limit the amount of current drawn directly from the op amps; resistors at the base connections stabilize their operation. The 10 kΩ resistors (R1–R4) between the voltage sense lines form an external resistor ladder; the quarter point voltages are taken off this external ladder and buffered by an op amp. The actual values of resistors R1–R4 are not critical, but they should match well and be large enough (≥10 kΩ) to limit the amount of current drawn from the voltage sense lines. The select resistors (RS) shown in the schematic (each pair can be a potentiometer) are chosen to adjust the quarter-point voltage references but are not necessary if R1–R4 match within 0.05%. An alternative approach for defining the quarter-point references of the resistor ladder is to evaluate the integral linearity error of an individual device and adjust the voltage at the quarter-points to minimize this error. This may improve the low frequency ac performance of the converter. –7– AD9060 +5V 10 9 50 8 44 7 38 6 +VREF * 0.1F +1.75V +VSENSE R/2 R1 10k⍀ R RS +0.875V R/2 1/2 AD708 RS 3/4REF 0.1F R/2 R2 10k⍀ 32 0.4 0.6 0.8 1.0 1.2 1.4 ⴞVSENSE – V 1.6 1.8 R 5 2.0 Figure 3. SNR and ENOB vs. Reference Voltage 2.5V 1.75V 150⍀ R RS AD580 1/2 RS AD708 356⍀ Performance of the AD9060 has been optimized with an analog input voltage of ± 1.75 V (as measured at ± VSENSE). If the analog input range is reduced below these values, relatively larger differential nonlinearity errors may result because of comparator mismatches. As shown in Figure 3, performance of the converter is a function of ± VSENSE. 0V R/2 1/2REF 0.1F R/2 R3 10k⍀ R TO COMPARATORS 56 AD9060 150⍀ 1/2 AD708 EFFECTIVE NUMBER OF BITS – ENOB SIGNAL-TO-NOISE (SNR) – dB 62 R RS RS Applying a voltage greater than 4 V across the internal resistor ladder will cause current densities to exceed rated values and may cause permanent damage to the AD9060. The design of the reference circuit should limit the voltage available to the references. –0.875V 1/2 AD708 R/2 1/4REF 63 0.1F R/2 R4 10k⍀ R R R Analog Input Signal 20k⍀ The signal applied to AIN drives the inputs of 512 parallel comparator cells (see Figure 5). This connection has a typical input resistance of 7 kΩ and input capacitance of 45 pF. The input capacitance is nearly constant over the analog input voltage range as shown in Figure 12, which illustrates that characteristic. R/2 20k⍀ –VSENSE 57 –1.75V 1/2 AD708 –VREF 56 150⍀ * 0.1F –5V * = WIRING RESISTANCE = < 5⍀ Figure 4. Reference Circuit AIN +VSENSE 3/4REF 1/2REF 1/4REF –VSENSE Figure 5. Equivalent Analog Input –8– REV. B AD9060 GND Output data of the AD9060 (D0–D9 and OVERFLOW) are also ECL compatible and should be terminated through 100 Ω to –2 V (or an equivalent load). DIGITAL BITS AND OVERFLOW Figure 6. Equivalent Digital Outputs GND ENCODE ENCODE –VS –VS Figure 7. ENCODE and ENCODE Equivalent Circuits Data Format The format of the output data (D0–D9) is controlled by the MSB INVERT and LSBs INVERT pins. These inputs are dc control inputs and should be connected to GND or +VS. Table I gives information on how to choose from among binary, inverted binary, twos complement, and inverted twos complement coding. The OVERFLOW output is an indication that the analog input signal has exceeded the voltage at +VSENSE. The accuracy of the overflow transition voltage and output delay are not tested or included in the data sheet limits. Performance of the overflow indicator is dependent on the circuit layout and the slew rate of the encode signal. The operation of this function does not affect the other data bits (D0–D9). It is not recommended for applications requiring a critical measure of analog input voltage. Timing Layout and Power Supplies In the AD9060, the rising edge of the ENCODE signal triggers the A/D conversion by latching the comparators (see Figure 8). These ENCODE and ENCODE signals are ECL compatible and should be driven differentially. Jitter on the ENCODE signal will raise the noise floor of the converter. Differential signals, with fast clean edges, will reduce the jitter in the signal and allow optimum ac performance. In applications with a fixed, high frequency encode rate, converter performance is also improved (jitter reduced) by using a crystal oscillator as the system clock. Proper layout of high speed circuits is always critical but is particularly important when both analog and digital signals are involved. The AD9060 units are designed to operate with a 50% duty cycle encode signal; adjustment of the duty cycle may improve the dynamic performance of individual devices. Since the ENCODE and ENCODE signals are differential, the logic levels are not critical. Users should remember, however, that reduced logic levels will reduce the slew rate of the edges and effectively increase the jitter of the signal. ECL terminations for the ENCODE and ENCODE signals should be as close as possible to the AD9060 package to avoid reflections. In systems where only single-ended signals are available, the use of a high speed comparator (such as the AD96685) is recommended to convert to differential signals. An alternative is to connect 1.3 V (ECL midpoint) to ENCODE and drive the ENCODE connection single ended. In such applications, clean, fast edges are necessary to minimize jitter in the signal. N N+1 AIN tA ENCODE N N+1 ENCODE Analog signal paths should be kept as short as possible and be properly terminated to avoid reflections. The analog input voltage and the voltage references should be kept away from digital signal paths; this reduces the amount of digital switching noise that is capacitively coupled into the analog section of the circuit. Digital signal paths should also be kept short, and run lengths should be matched to avoid propagation delay mismatch. Terminations for ECL signals should be as close as possible to the receiving gate. In high speed circuits, layout of the ground circuit is a critical factor. A single, low impedance ground plane on the component side of the board will reduce noise on the circuit ground. Power supplies should be capacitively coupled to the ground plane to reduce noise in the circuit. Multilayer boards allow designers to lay out signal traces without interrupting the ground plane and provide low impedance power planes. It is especially important to maintain the continuity of the ground plane under and around the AD9060. In systems with dedicated digital and analog grounds, all grounds of the AD9060 should be connected to the analog ground plane. The power supplies (+VS and –VS) of the AD9060 should be isolated from the supplies used for external devices; this further reduces the amount of noise coupled into the A/D converter. Sockets limit the dynamic performance and should be used only for prototypes or evaluation—PCK Elastomerics Part No. CCS6855 is recommended for the LCC package. An evaluation board is available to aid designers and provide a suggested layout. tOD DATA OUTPUT DATA FOR N DATA FOR N + 1 tA = APERTURE DELAY tOD = OUTPUT DELAY Figure 8. Timing Diagram REV. B –9– AD9060 62 10 30 9 35 +25ⴗC 44 7 –55ⴗC, +125ⴗC 38 6 32 5 26 4 20 1 2 4 6 8 10 20 40 INPUT FREQUENCY – MHz 60 80 100 40 –55ⴗC 50 55 60 +25ⴗC 65 3 200 70 1 2 4 6 8 10 20 INPUT FREQUENCY – MHz 40 10 ANALOG INPUT = 2.3MHz 50 8 44 7 38 6 32 5 26 4 20 10 20 40 CONVERSION RATE – MSPS 60 80 60 48 INPUT CAPACITANCE – pF 9 56 70 EFFECTIVE NUMBER OF BITS – ENOB 62 60 80 100 Figure 11. Harmonics vs. Input Frequency Figure 9. SNR and ENOB vs. Input Frequency SIGNAL-TO-NOISE (SNR) – dB +125ⴗC 45 50 RESISTANCE 47 40 46 30 CAPACITANCE 45 20 44 10 3 100 –1.8 –1.2 –0.6 0 0.6 ANALOG INPUT (AIN) – V 1.2 INPUT RESISTANCE – k⍀ 8 50 HARMONICS – dBc SIGNAL-TO-NOISE (SNR) – dB 56 EFFECTIVE NUMBER OF BITS – ENOB ENCODE RATE = 60MSPS 1.8 Figure 12. Input Capacitance/Resistance vs. Input Voltage Figure 10. SNR and ENOB vs. Conversion Rate Table I. Truth Table Offset Binary Step 1024 1023 1022 Range 0 = –1.75 V FS = +1.75 V > +1.7500 +1.7466 +1.7432 Twos Complement True MSB INV = 0 LSBs INV = 0 Inverted MSB INV = 1 LSBs INV = 1 True MSB INV = 1 LSBs INV = 0 Inverted MSB INV = 0 LSBs INV = 1 (1)1111111111 1111111111 1111111110 (1)0000000000 0000000000 0000000001 (1)0111111111 0111111111 0111111110 (1)1000000000 1000000000 1000000001 • • • • • • • • • • • • • • • • • 512 511 510 +0.0034 0.000 –0.0034 1000000000 0111111111 0111111110 0111111111 1000000000 1000000001 0000000000 1111111111 1111111110 • 1111111111 0000000000 0000000001 • • • • • • • • • • • • • • • • • 02 01 00 –1.7432 –1.7466 < –1.7466 0000000010 0000000001 0000000000 1111111101 1111111110 1111111111 1000000010 1000000001 1000000000 • 0111111101 0111111110 0111111111 The overflow bit is always 0 except where noted in parentheses ( ). MSB INVERT and LSBs INVERT are considered dc controls. –10– REV. B AD9060 On-board reconstruction of the digital data is provided through the AD9712, a 12-bit monolithic DAC. The analog and reconstructed waveforms can be summed on the board to allow the user to observe the linearity of the AD9060 and the effects of the quarter-point voltages. The digital data and an adjustable data ready signal are available via a 37-pin edge connector. AD9060/PCB EVALUATION BOARD The AD9060/PCB Evaluation Board is available from the factory and is shown here in block diagram form. The board includes a reference circuit that allows the user to adjust both references and the quarter-point voltages. The AD9617 is included as the drive amplifier, and the user can configure the gain from –1 to –15. BUFFERED ANALOG INPUT +5V –VS +VS GND LSBs INVERT J2 200⍀ U5 AD9617 (LSB) D0 D1 24⍀ AIN D2 AD9060 TO ERROR WAVEFORM CIRCUIT DUT D3 D4 D5 D6 D ECL D LATCHES 1/2REF OVERFLOW D 1/4REF DIFFERENTIAL ECL CLOCK –VREF ENCODE Figure 13. PCB Evaluation Board Block Diagram –11– TO ERROR WAVEFORM CIRCUIT OUTPUT DATA CONNECTOR Q DATA READY CLK ENCODE –VSENSE 50⍀ D (MSB) D9 D8 D D D 3/4REF D7 +VSENSE AD9712 DAC IOUT D D D D D +VREF REFERENCE CIRCUIT REV. B DAC OUT +5V MSB INVERT DUT ANALOG INPUT 400⍀ 50⍀ –5V TIMING CIRCUIT AD9060 OUTLINE DIMENSIONS 68-Lead Ceramic Leaded Chip Carrier [CLCC] (Z-68D) Dimensions shown in inches and (millimeters) 0.960 (24.84) 0.950 (24.13) SQ 0.940 (23.88) 0.130 (3.30) 0.040 (1.02) MIN SEATING PLANE 0.025 (0.64) MIN C00564–0–4/03(B) 1.220 (30.99) 1.210 (30.73) SQ 1.200 (30.48) 9 61 60 10 PIN 1 0.058 (1.47) 0.050 (1.27) 0.042 (1.07) 0.705 (17.91) 0.700 (17.78) SQ 0.695 (17.65) TOP VIEW 0.020 (0.51) 0.018 (0.46) 0.016 (0.41) 26 44 27 0.025 (0.625) MIN 0.118 (3.00) 0.105 (2.67) 0.092 (2.34) 43 0.859 (21.82) 0.850 (21.59) 0.841 (21.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location Page 4/03—Data Sheet changed from REV. A to REV. B. Removed AD9060JE/KE/SZ/SE/TZ/TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Removed MIL-STD-833 Compliance Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Renumbered Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 –12– REV. B