High Voltage Latch-Up Proof, Dual SPST Switches ADG5421/ADG5423 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS Latch-up immune under all circumstances Human body model (HBM) ESD rating: 8 kV Low on resistance: 13.5 Ω ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at ±15 V, ±20 V, +12 V, and +36 V VDD to VSS analog signal range ADG5421 S1 IN1 D1 D2 IN2 SWITCHES SHOWN FOR A LOGIC 0 INPUT 11369-001 S2 Figure 1. ADG5421 APPLICATIONS High voltage signal routing Automatic test equipment Analog front-end circuits Precision data acquisition Industrial instrumentation Amplifier gain select Relay replacement ADG5423 S1 IN1 D1 D2 IN2 SWITCHES SHOWN FOR A LOGIC 0 INPUT 11369-002 S2 Figure 2. ADG5423 GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG5421/ADG5423 are monolithic industrial, complementary metal oxide semiconductor (CMOS) analog switches containing two independent latch-up immune singlepole/single-throw (SPST) switches. Each switch conducts equally well in both directions when on, and has an input signal range that extends to the power supplies. In the off condition, signal levels up to the supplies are blocked. Both ADG5421 switches are turned on with a Logic 1 input, whereas the ADG5423 has one switch turned on and one switch turned off for a Logic 1 input. The ADG5423 exhibits break-before-make action for use in multiplexer applications. 1. The ultralow on resistance and on-resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications where low distortion is critical. The latch-up immune construction and high ESD rating make these switches more robust in harsh environments. Rev. A 2. 3. 4. 5. 6. 7. Trench isolation guards against latch-up. A dielectric trench separates the P channel and N channel transistors, thereby preventing latch-up even under severe overvoltage conditions. Low RON of 13.5 Ω. Dual-supply operation. For applications where the analog signal is bipolar, the ADG5421/ADG5423 can operate from dual supplies up to ±22 V. Single-supply operation. For applications where the analog signal is unipolar, the ADG5421/ADG5423 can operate from a single-rail power supply up to 40 V. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. No VL logic power supply required. Available in 10-lead MSOP and 10-lead 3 mm × 3 mm LFCSP packages. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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Technical Support www.analog.com ADG5421/ADG5423 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Continuous Current per Channel, Sx or Dx ..............................7 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................8 Functional Block Diagrams ............................................................. 1 ESD Caution...................................................................................8 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ............................9 Product Highlights ........................................................................... 1 Typical Performance Characteristics ........................................... 10 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 13 Specifications..................................................................................... 3 Terminology .................................................................................... 15 ±15 V Dual Supply ....................................................................... 3 Applications Information .............................................................. 16 ±20 V Dual Supply ....................................................................... 4 Trench Isolation .......................................................................... 16 12 V Single Supply ........................................................................ 5 Outline Dimensions ....................................................................... 17 36 V Single Supply ........................................................................ 6 Ordering Guide .......................................................................... 17 REVISION HISTORY 1/15—Rev. 0 to Rev. A Added 10-Lead LFCSP Package........................................ Universal Changes to Table 5 ............................................................................ 7 Added Figure 3, Renumbered Sequentially; Changes to Table 7..... 9 Changes to Figure 5 ........................................................................ 10 Changes to Figure 30 ...................................................................... 14 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 9/13—Revision 0: Initial Version Rev. A | Page 2 of 17 Data Sheet ADG5421/ADG5423 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C 13.5 15 0.1 0.8 1.8 2.2 ±0.05 ±0.25 ±0.05 ±0.25 ±0.1 ±0.4 −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments VDD to VSS V Ω typ Ω max Ω typ VS = ±10 V, IS = −10 mA; see Figure 25 VDD = +13.5 V, VSS = −13.5 V VS = ±10 V, IS = −10 mA 19 23 1.3 1.4 2.7 3.1 ±1 ±10 ±1 ±10 nA typ nA max nA typ nA max ±4 ±20 nA typ nA max 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON tOFF Break-Before-Make Time Delay, tD (ADG5423 Only) 6 185 220 163 196 73 Ω max Ω typ Ω max 273 313 219 242 21 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V; see Figure 32 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 RL = 1 kΩ, 15 V p-p, f = 20 Hz to 20 kHz; see Figure 27 RL = 50 Ω, CL = 5 pF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Off Isolation −55 dB typ Channel-to-Channel Crosstalk −85 dB typ Total Harmonic Distortion + Noise 0.01 % typ −3 dB Bandwidth Insertion Loss 250 −1 MHz typ dB typ CS (Off) CD (Off) CD (On), CS (On) POWER REQUIREMENTS IDD 12 13 44 pF typ pF typ pF typ VDD/VSS 1 1 ±9/±22 Guaranteed by design; not subject to production test. Rev. A | Page 3 of 17 VS = VD = ±10 V; see Figure 23 ns typ ns max ns typ ns max ns typ ns min pC typ ISS VS = ±10 V, VD = 10 V; see Figure 24 VIN = VGND or VDD 95 70 VDD = +16.5 V, VSS = −16.5 V VS = ±10 V, VD = 10 V; see Figure 24 V min V max µA typ µA max pF typ Charge Injection, QINJ 45 55 0.001 VS = ±10 V, IS = −10 mA µA typ µA max µA typ µA max V min/V max Digital inputs = 0 V or VDD GND = 0 V ADG5421/ADG5423 Data Sheet ±20 V DUAL SUPPLY VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C 12.5 14 0.1 0.8 2.3 2.7 ±0.05 ±0.25 ±0.05 ±0.25 ±0.1 ±0.4 −40°C to +85°C −40°C to +125°C Unit VDD to VSS V Ω typ Ω max Ω typ Ω max Ω typ Ω max 18 22 1.3 1.4 3.3 3.7 ±1 ±10 ±1 ±10 nA typ nA max nA typ nA max ±4 ±20 nA typ nA max 2.0 0.8 6 V min V max µA typ µA max pF typ 168 ns typ 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON Break-Before-Make Time Delay, tD (ADG5423 Only) 199 156 184 65 Charge Injection, QINJ 120 ns max ns typ ns max ns typ ns min pC typ Off Isolation −55 dB typ Channel-to-Channel Crosstalk −85 dB typ Total Harmonic Distortion + Noise 0.01 % typ −3 dB Bandwidth Insertion Loss 250 −0.8 MHz typ dB typ 11 12 44 pF typ pF typ pF typ tOFF 243 276 204 218 38 CS (Off) CD (Off) CD (On), CS (On) POWER REQUIREMENTS IDD ISS VDD/VSS 1 50 70 0.001 110 1 ±9/±22 Guaranteed by design; not subject to production test. Rev. A | Page 4 of 17 µA typ µA max µA typ µA max V min/V max Test Conditions/Comments VS = ±15 V, IS = −10 mA; see Figure 25 VDD = +18 V, VSS = −18 V VS = ±15 V, IS = −10 mA VS = ±15 V, IS = −10 mA VDD = +22 V, VSS = −22 V VS = ±15 V, VD = 15 V; see Figure 24 VS = ±15 V, VD = 15 V; see Figure 24 VS = VD = ±15 V; see Figure 23 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF, VS = 10 V; see Figure 30 VS = 10 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V; see Figure 32 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz; see Figure 27 RL = 50 Ω, CL = 5 pF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +22 V, VSS = −22 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V Data Sheet ADG5421/ADG5423 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to +125°C Unit 0 V to VDD V Ω typ 26 tOFF Break-Before-Make Time Delay, tD (ADG5423 Only) 38 44 Ω max Ω typ 1 5.5 6.8 1.5 1.6 VS = 0 V to 10 V, IS = −10 mA 8.3 12.3 Ω max Ω typ Ω max nA typ VDD = +13.2 V, VSS = 0 V VS = 1 V to 10 V, VD = 10 V to 1 V; see Figure 24 ±0.05 ±0.25 ±0.05 ±1 ±10 ±0.25 ±0.1 ±0.4 ±1 ±10 ±4 ±20 2.0 0.8 0.002 6 295 370 192 235 142 470 540 273 295 78 VS = VD = 1 V to 10 V; see Figure 23 V min V max µA typ µA max pF typ VIN = VGND or VDD ns typ ns max ns typ ns max ns typ RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V; see Figure 32 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 RL = 1 kΩ, 6 V p-p, f = 20 Hz to 20 kHz; see Figure 27 RL = 50 Ω, CL = 5 pF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD ns min pC typ Off Isolation −55 dB typ Channel-to-Channel Crosstalk −85 dB typ Total Harmonic Distortion + Noise 0.03 % typ −3 dB Bandwidth Insertion Loss 290 −1.7 MHz typ dB typ 14 15 38 pF typ pF typ pF typ 40 50 65 9/40 Guaranteed by design; not subject to production test. Rev. A | Page 5 of 17 VS = 1 V to 10 V, VD = 10 V to 1 V; see Figure 24 nA max nA typ nA max 55 VDD 1 nA max nA typ Charge Injection, QINJ CS (Off) CD (Off) CD (On), CS (On) POWER REQUIREMENTS IDD VS = 0 V to 10 V, IS = −10 mA; see Figure 25 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = −10 mA 30 0.1 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON Test Conditions/Comments µA typ µA max V min/V max GND = 0 V, VSS = 0 V ADG5421/ADG5423 Data Sheet 36 V SINGLE SUPPLY VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C 14.5 16 0.1 0.8 3.5 4.3 −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments 0 V to VDD V Ω typ Ω max Ω typ VS = 0 V to 30 V, IS = −10 mA; see Figure 25 VDD = 32.4 V, VSS = 0 V VS = 0 V to 30 V, IS = −10 mA 20 24 1.3 1.4 5.5 6.5 ±0.05 ±0.25 ±0.05 ±1 ±10 ±0.25 ±0.1 ±0.4 ±1 ±10 ±4 ±20 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON tOFF Break-Before-Make Time Delay, tD (ADG5423 Only) 6 181 210 170 192 66 245 280 205 220 37 VS = 0 V to 30 V, IS = −10 mA nA typ VDD = 39.6 V, VSS = 0 V VS = 1 V to 30 V, VD = 30 V to 1 V; see Figure 24 nA max nA typ VS = VD = 1 V to 30 V; see Figure 23 V min V max µA typ µA max pF typ VIN = VGND or VDD ns typ ns max ns typ ns max ns typ RL = 300 Ω, CL = 35 pF VS = 18 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 18 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 18 V; see Figure 32 VS = 18 V, RS = 0 Ω, CL = 1 nF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 RL = 1 kΩ, 18 V p-p, f = 20 Hz to 20 kHz; see Figure 27 RL = 50 Ω, CL = 5 pF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VDD = 39.6 V Digital inputs = 0 V or VDD 110 −55 −85 0.01 ns min pC typ dB typ dB typ % typ −3 dB Bandwidth Insertion Loss 260 −0.9 MHz typ dB typ 13 16 38 pF typ pF typ pF typ 80 100 VDD 130 9/40 Guaranteed by design; not subject to production test. Rev. A | Page 6 of 17 VS = 1 V to 30 V, VD = 30 V to 1 V; see Figure 24 nA max nA typ nA max Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise CS (Off) CD (Off) CD (On), CS (On) POWER REQUIREMENTS IDD 1 Ω max Ω typ Ω max µA typ µA max V min/V max GND = 0 V, VSS = 0 V Data Sheet ADG5421/ADG5423 CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Table 5. Parameter CONTINUOUS CURRENT, Sx OR Dx 10-Lead MSOP VDD = +15 V, VSS = −15 V VDD = +20 V, VSS = −20 V VDD = 12 V, VSS = 0 V VDD = 36 V, VSS = 0 V 10-Lead LFCSP VDD = +15 V, VSS = −15 V VDD = +20 V, VSS = −20 V VDD = 12 V, VSS = 0 V VDD = 36 V, VSS = 0 V 25°C 85°C 125°C Unit Test Conditions/Comments θJA = 133.1°C/W 84 89 67 87 58 60 47 59 39 41 32 40 mA maximum mA maximum mA maximum mA maximum 129 135 103 132 80 83 37 82 48 50 43 49 mA maximum mA maximum mA maximum mA maximum θJA = 48.7°C/W Rev. A | Page 7 of 17 ADG5421/ADG5423 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or Dx Pins Continuous Current, Sx or Dx2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, θJA 10-Lead MSOP (4-Layer Board) 10-Lead LFCSP Reflow Soldering Peak Temperature, Pb Free Human Body Model (HBM) ESD Rating 48 V −0.3 V to +48 V +0.3 V to −48 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 300 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 133.1°C/W 48.7°C/W As per JEDEC J-STD-020 8 kV 1 Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 See Table 5. Rev. A | Page 8 of 17 Data Sheet ADG5421/ADG5423 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D1 9 D2 8 VSS 7 IN1 6 IN2 NC 3 GND 4 VDD 5 ADG5421/ ADG5423 TOP VIEW (Not to Scale) NOTES 1. NC = NO CONNECT. NOT INTERNALLY CONNECTED. S1 1 S2 2 NC 3 GND 4 10 D1 ADG5421/ ADG5423 TOP VIEW (Not to Scale) VDD 5 9 D2 8 VSS 7 IN1 6 IN2 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. EXPOSED PAD TIED TO SUBSTRATE, VSS. Figure 3. MSOP Pin Configuration Figure 4. LFCSP Pin Configuration Table 7. Pin Function Descriptions MSOP Pin No.1 1 2 3 4 5 6 7 8 9 10 N/A 1 LFCSP Pin No. 1 2 3 4 5 6 7 8 9 10 EPAD Mnemonic S1 S2 NC GND VDD IN2 IN1 VSS D2 D1 Description Source Terminal 1. This pin can be an input or output. Source Terminal 2. This pin can be an input or output. No Connect. Not internally connected. Ground (0 V) Reference. Most Positive Power Supply Potential. Logic Control Input. Logic Control Input. Most Negative Power Supply Potential. Drain Terminal 2. This pin can be an input or output. Drain Terminal 1. This pin can be an input or output. Exposed Pad. The exposed pad is tied to substrate, VSS. N/A means not applicable. Table 8. ADG5421 Truth Table INx 0 1 Switch Conditions Off On Table 9. ADG5423 Truth Table INx 0 1 Switch 1 Condition Off On Switch 2 Condition On Off Rev. A | Page 9 of 17 11369-033 10 S2 2 11369-003 S1 1 ADG5421/ADG5423 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 25 16 TA = 25°C TA = 25°C VDD = +10V VSS = –10V VDD = +9V VSS = –9V 14 12 VDD = +11V VSS = –11V ON RESISTANCE (Ω) ON RESISTANCE (Ω) 20 15 10 VDD = +13.5V VSS = –13.5V VDD = +15V VSS = –15V VDD = +16.5V VSS = –16.5V 10 VDD = 32.4V VSS = 0V 8 VDD = 39.6V VSS = 0V VDD = 36V VSS = 0V 6 4 5 –14 –10 –6 –2 2 0 6 10 14 18 VS, VD (V) 0 11369-004 0 –18 0 5 10 15 20 25 30 35 40 11369-007 2 45 VS, VD (V) Figure 5. On Resistance as a Function of VS, VD (Dual Supply: ±10 V, ±15 V) Figure 8. On Resistance as a Function of VS, VD (Single Supply: 36 V) 25 16 TA = 25°C 14 ON RESISTANCE (Ω) ON RESISTANCE (Ω) 20 VDD = +18V VSS = –18V 12 10 8 VDD = +22V VSS = –22V VDD = +20V VSS = –20V 6 TA = +125°C 15 TA = +85°C TA = +25°C 10 TA = –40°C 4 –20 –15 –10 –5 0 5 10 15 20 VDD = +15V VSS = –15V 0 –15 –10 11369-005 0 –25 25 VS, VD (V) VDD = 10V VSS = 0V 30 VDD = 10.8V VSS = 0V 10 15 VDD = +20V VSS = –20V 20 25 ON RESISTANCE (Ω) ON RESISTANCE (Ω) VDD = 9V VSS = 0V 5 Figure 9. On Resistance as a Function of VS (VD) for Different Temperatures, ±15 V Dual Supply 25 TA = 25°C 0 VS, VD (V) Figure 6. On Resistance as a Function of VS, VD (Dual Supply: ±20 V) 35 –5 11369-008 5 2 20 15 VDD = 13.2V VSS = 0V VDD = 12V VSS = 0V VDD = 11V VSS = 0V 10 TA = +125°C 15 TA = +85°C TA = +25°C 10 TA = –40°C 5 0 2 4 6 8 VS, VD (V) 10 12 14 0 –20 11369-006 0 –15 –10 –5 0 VS, VD (V) Figure 7. On Resistance as a Function of VS, VD (Single Supply: 10 V, 12 V) 5 10 15 20 11369-009 5 Figure 10. On Resistance as a Function of VS (VD) for Different Temperatures, ±20 V Dual Supply Rev. A | Page 10 of 17 Data Sheet ADG5421/ADG5423 0.4 40 VDD = +20V VSS = –20V VBIAS = +15V/–15V 35 ID, IS (ON) + + IS (OFF) + – 0.2 ON RESISTANCE (Ω) LEAKAGE CURRENT (nA) TA = +125°C 30 TA = +85°C 25 20 TA = +25°C 15 TA = –40°C 10 ID (OFF) – + 0 ID, IS (ON) – – –0.2 IS (OFF) – + –0.4 0 2 4 6 8 10 12 VS, VD (V) –0.6 11369-010 0 VDD = 12V VSS = 0V 75 50 100 125 Figure 14. Leakage Currents as a Function of Temperature, ±20 V Dual Supply 0.4 25 25 TEMPERATURE (°C) Figure 11. On Resistance as a Function of VS (VD) for Different Temperatures, 12 V Single Supply VDD = 12V VSS = 0V VBIAS = 1V/10V VDD = 36V VSS = 0V 0.3 LEAKAGE CURRENT (nA) 20 ON RESISTANCE (Ω) 0 11369-013 ID (OFF) + – 5 TA = +125°C 15 TA = +85°C TA = +25°C 10 TA = –40°C ID, IS (ON) + + 0.2 ID, IS (ON) – – IS (OFF) + – 0.1 0 ID (OFF) – + 5 –0.1 IS (OFF) – + 5 10 15 20 25 30 35 40 VS, VD (V) 11369-011 –0.2 0 0 50 75 100 Figure 15. Leakage Currents as a Function of Temperature, 12 V Single Supply 0.6 0.4 VDD = 36V VSS = 0V VBIAS = 1V/30V VDD = +15V VSS = –15V VBIAS = +10V/–10V LEAKAGE CURRENT (nA) IS (OFF) + – ID (OFF) – + 0.2 ID, IS (ON) – – 0 IS (OFF) – + –0.2 ID, IS (ON) + + 0.2 ID, IS (ON) + + IS (OFF) + – 0 ID (OFF) – + ID, IS (ON) – – –0.2 IS (OFF) – + –0.4 ID (OFF) + – ID (OFF) + – 25 50 75 TEMPERATURE (°C) 100 125 –0.6 11369-012 0 0 25 50 75 100 125 TEMPERATURE (°C) Figure 13. Leakage Currents as a Function of Temperature, ±15 V Dual Supply Rev. A | Page 11 of 17 Figure 16. Leakage Currents as a Function of Temperature, 36 V Single Supply 11369-015 0.4 –0.4 125 TEMPERATURE (°C) Figure 12. On Resistance as a Function of VS (VD) for Different Temperatures, 36 V Single Supply LEAKAGE CURRENT (nA) 25 11369-014 ID (OFF) + – 0 ADG5421/ADG5423 0 –10 Data Sheet 0.05 TA = 25°C VDD = +15V VSS = –15V TA = 25°C 0.04 –30 THD + N (%) OFF ISOLATION (dB) –20 VDD = 12V, VSS = 0V, VS = 6V p-p VDD = 36V, VSS = 0V, VS = 18V p-p VDD = 15V, VSS = –15V, VS = 15V p-p VDD = 20V, VSS = –20V, VS = 20V p-p –40 –50 –60 0.03 0.02 –70 –80 0.01 100k 1M 10M 100M 1G FREQUENCY (Hz) 0 11369-016 10k 0 5 Figure 17. Off Isolation vs. Frequency 0 TA = 25°C VDD = +15V VSS = –15V 20 TA = 25°C VDD = +15V VSS = –15V –0.5 –1.0 INSERTION LOSS (dB) CROSSTALK (dB) 15 Figure 20. THD + N vs. Frequency 0 –20 10 FREQUENCY (kHz) 11369-019 –90 –100 1k –40 –60 –80 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 –100 100k 1M 10M 100M 1G FREQUENCY (Hz) –5.0 1k 11369-017 –120 10k 10k 100k Figure 18. Crosstalk vs. Frequency 100M 1G 400 VDD VDD VDD VDD = 15V, = 20V, = 12V, = 36V, VSS VSS VSS VSS = –15V = –20V = 0V = 0V 350 300 VDD = 12V, VSS = 0V VDD = 36V, VSS = 0V VDD = 15V, VSS = –15V VDD = 20V, VSS = –20V 200 TIME (ns) 250 150 200 150 100 100 50 0 –20 –10 0 10 20 30 VS (V) 40 0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 22. tTRANSITION Times vs. Temperature Figure 19. Charge Injection vs. Source Voltage (VS) Rev. A | Page 12 of 17 120 11369-021 50 11369-018 CHARGE INJECTION (pC) 10M Figure 21. Bandwidth 300 250 1M FREQUENCY (Hz) 11369-020 –4.5 Data Sheet ADG5421/ADG5423 TEST CIRCUITS VDD VSS 0.1µF 0.1µF VDD NETWORK ANALYZER VSS Sx 50Ω 50Ω INx VS Dx Dx NC = NO CONNECT GND A VD 11369-022 Sx NC RL 50Ω VOUT OFF ISOLATION = 20 log Figure 23. On Leakage VOUT VS 11369-025 VIN ID (ON) Figure 26. Off Isolation VDD VSS 0.1µF 0.1µF AUDIO PRECISION VDD VSS RS Sx VS V p-p INx Dx Dx A VS GND VD VOUT RL 1kΩ 11369-026 Sx Figure 24. Off Leakage Figure 27. THD + Noise VDD VSS 0.1µF 0.1µF VDD NETWORK ANALYZER VSS 50Ω Sx INx VS Dx V VIN Sx RL 50Ω GND Dx RON = V ÷ IDS 11369-024 IDS VS INSERTION LOSS = 20 log VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 28. Bandwidth Figure 25. On Resistance Rev. A | Page 13 of 17 VOUT 11369-027 A VIN ID (OFF) 11369-023 IS (OFF) ADG5421/ADG5423 Data Sheet VDD VSS 0.1µF 0.1µF NETWORK ANALYZER VOUT VDD VSS S1 RL 50Ω Dx R 50Ω S2 VS GND 08487-028 VOUT VS CHANNEL-TO-CHANNEL CROSSTALK = 20 log Figure 29. Channel-to-Channel Crosstalk VDD VSS 0.1µF VDD VSS Sx VS VIN ADG5421 50% 50% VIN ADG5423 50% 50% VOUT Dx CL 35pF RL 300Ω INx VS 0.9VS VOUT 0.1VS 0V GND 11369-029 0.1µF tOFF tON Figure 30. Switching Times, tON and tOFF VSS VDD VSS Sx VS VIN ADG5421 ON VOUT Dx CL 1nF INx VIN OFF ADG5423 VOUT GND QINJ = CL × ΔVOUT ΔVOUT 11369-030 RS VDD Figure 31. Charge Injection VDD VSS S1 D1 S2 D2 RL 300Ω IN1, IN2 CL 35pF VOUT2 RL 300Ω CL 35pF VOUT1 VOUT1 50% 80% 80% 0V 80% VOUT2 80% 0V ADG5423 tD GND Figure 32. Break-Before-Make Time Delay Rev. A | Page 14 of 17 tD 11369-031 VS2 50% 0V VSS VDD VS1 VIN 0.1µF 0.1µF Data Sheet ADG5421/ADG5423 TERMINOLOGY IDD IDD represents the positive supply current. CIN CIN represents digital input capacitance. ISS ISS represents the negative supply current. tON tON represents the delay time between the 50% and 90% points of the digital input and switch on condition. VD, VS VD and VS represent the analog voltage on Terminal D and Terminal S, respectively. tOFF tOFF represents the delay time between the 50% and 90% points of the digital input and switch off condition. RON RON is the ohmic resistance between Terminal D and Terminal S. tD tD represents the off time measured between the 80% point of both switches when switching from one address state to another. ∆RON ∆RON represents the difference between the RON of any two channels. RFLAT (ON) RFLAT (ON) represents the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. Off Isolation Off isolation is a measure of unwanted signal coupling through an off channel. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. IS (Off) IS (Off) is the source leakage current with the switch off. ID (Off) ID (Off) is the drain leakage current with the switch off. ID (On), IS (On) ID (On) and IS (On) represent the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic 0. VINH VINH is the minimum input voltage for Logic 1. Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 dB from its dc level. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by THD + N. IINL, IINH IINL and IINH represent the low and high input currents of the digital inputs. CD (Off) CD (Off) represents the off switch drain capacitance, which is measured with reference to ground. CS (Off) CS (Off) represents the off switch source capacitance, which is measured with reference to ground. CD (On), CS (On) CD (On) and CS (On) represent on switch capacitances, which are measured with reference to ground. Rev. A | Page 15 of 17 ADG5421/ADG5423 Data Sheet APPLICATIONS INFORMATION TRENCH ISOLATION In the ADG5421/ADG5423, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction-isolated switches, are eliminated, and the result is a completely latch-up immune switch. In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. The two transistors form a silicon-controlled rectifier (SCR) type circuit, causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latch-up immune switch. Rev. A | Page 16 of 17 NMOS PMOS P-WELL N-WELL TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 33. Trench Isolation 11369-032 The ADG54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADG5421/ ADG5423 high voltage switches allow single-supply operation from 9 V to 40 V and dual-supply operation from ±9 V to ±22 V. The ADG5421/ADG5423 (as well as other select devices within this family) achieve an 8 kV human body model ESD rating, which provides a robust solution, eliminating the need for separate protection circuitry designs in some applications. Data Sheet ADG5421/ADG5423 OUTLINE DIMENSIONS 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 PIN 1 INDEX AREA 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 BOTTOM VIEW SEATING PLANE 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.30 0.25 0.20 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-05-2013-C 0.80 0.75 0.70 0.20 MIN 1 5 TOP VIEW 0.20 REF Figure 34. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-BA 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 35. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADG5421BCPZ-RL7 ADG5421BRMZ ADG5421BRMZ-RL7 ADG5423BCPZ-RL7 ADG5423BRMZ ADG5423BRMZ-RL7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] Z = RoHS Compliant Part. ©2013–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11369-0-1/15(A) Rev. A | Page 17 of 17 Package Option CP-10-9 RM-10 RM-10 CP-10-9 RM-10 RM-10 Branding BN S47 S47 BM S3D S3D