1 Ω Typical On Resistance, ±5 V, +12 V, +5 V, and +3.3 V, 4:1 Multiplexer ADG1604 FEATURES FUNCTIONAL BLOCK DIAGRAM 1 Ω typical on resistance 0.2 Ω on resistance flatness ±3.3 V to ±8 V dual supply operation 3.3 V to 16 V single supply operation No VL supply required 3 V logic-compatible inputs Rail-to-rail operation Continuous current per channel LFCSP package: 504 mA TSSOP package: 315 mA 14-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP ADG1604 S1 S2 D S3 S4 A0 A1 EN 07982-001 1 OF 4 DECODER Figure 1. APPLICATIONS Communication systems Medical systems Audio signal routing Video signal routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Relay replacements GENERAL DESCRIPTION The ADG1604 is a complementary metal-oxide semiconductor (CMOS) analog multiplexer and switches one of four inputs to a common output, D, as determined by the 3-bit binary address lines, A0, A1, and EN. Logic 0 on the EN pin disables the device. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action. Inherent in the design is low charge injection for minimum transients when switching the digital inputs. The ultralow on resistance of these switches make them ideal solutions for data acquisition and gain switching applications where low on resistance and distortion is critical. The on resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. The CMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 1.6 Ω maximum on resistance over temperature. Minimum distortion: THD + N = 0.007%. 3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. No VL logic power supply required. Ultralow power dissipation: <16 nW. 14-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADG1604 TABLE OF CONTENTS Features .............................................................................................. 1 Continuous Current per Channel, S or D ..................................7 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................8 Functional Block Diagram .............................................................. 1 ESD Caution...................................................................................8 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ............................9 Product Highlights ........................................................................... 1 Typical Performance Characteristics ........................................... 10 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 13 Specifications..................................................................................... 3 Terminology .................................................................................... 16 ±5 V Dual Supply ......................................................................... 3 Outline Dimensions ....................................................................... 17 12 V Single Supply ........................................................................ 4 Ordering Guide .......................................................................... 17 5 V Single Supply .......................................................................... 5 3.3 V Single Supply ....................................................................... 6 REVISION HISTORY 1/09—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADG1604 SPECIFICATIONS ±5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) 25°C −40°C to +85°C VDD to VSS 1 1.2 0.04 0.08 0.2 0.25 1.4 1.6 0.09 0.1 0.29 0.34 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) ±0.1 ±0.2 ±0.1 ±1 Drain Off Leakage, ID (Off ) ±0.2 ±0.2 ±0.4 Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH −40°C to +125°C nA max nA typ VS = ±4.5V, VD = ∓4.5 V; see Figure 23 ±2 ±16 VS = VD = ±4.5 V; see Figure 24 ±2 ±16 nA max nA typ nA max V min V max μA typ μA max pF typ VIN = VGND or VDD 2.0 0.8 0.005 8 Break-Before-Make Time Delay, tD Charge Injection Off Isolation 140 70 Channel-to-Channel Crosstalk 70 dB typ Total Harmonic Distortion + Noise (THD + N) 0.007 % typ 15 63 270 360 MHz typ pF typ pF typ pF typ 336 376 166 177 277 310 28.5 −3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD VDD/VSS VS = ±4.5 V, IS = −10 mA ±8 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ tOFF (EN) VS = ±4.5 V, IS = −10 mA; see Figure 22 VDD = ±4.5 V, VSS = ±4.5 V VS = ±4.5 V, IS = −10 mA VDD = +5.5 V, VSS = −5.5 V VS = ±4.5 V, VD = ∓4.5 V; see Figure 23 150 278 116 146 186 234 50 tON (EN) 1 V Ω typ Ω max Ω typ Ω max Ω typ Ω max Test Conditions/Comments nA typ ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION Unit 0.001 1.0 ±3.3/±8 Guaranteed by design, not subject to production test. Rev. 0 | Page 3 of 20 μA typ μA max V min/max RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 29 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 2.5 V; see Figure 30 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz; see Figure 28 RL = 50 Ω, CL = 5 pF; see Figure 26 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +5.5 V, VSS = −5.5 V Digital inputs = 0 V or VDD ADG1604 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to +125°C 0 V to VDD 0.95 1.1 0.03 0.06 0.2 0.23 ±0.1 ±0.2 ±0.1 ±0.2 ±0.2 ±0.4 1.25 1.45 0.07 0.08 0.27 0.32 ±1 ±8 ±2 ±16 ±2 ±16 2.0 0.8 0.001 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 8 V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ Break-Before-Make Time Delay, tD 100 161 80 95 144 173 25 Charge Injection Off Isolation 125 70 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ Channel-to-Channel Crosstalk 70 dB typ Total Harmonic Distortion + Noise 0.013 % typ 19 60 270 350 MHz typ pF typ pF typ pF typ tON (EN) tOFF (EN) 192 220 104 111 205 234 18 −3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD 0.001 1 IDD VDD 1 Unit 230 360 3.3/16 Guaranteed by design, not subject to production test. Rev. 0 | Page 4 of 20 μA typ μA max μA typ μA max V min/max Test Conditions/Comments VS = 0 V to 10 V, IS = −10 mA; see Figure 22 VDD = 10.8 V, VSS = 0 V VS = 10 V, IS = −10 mA VS = 0 V to 10 V, IS = −10 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23 VS = VD = 1 V or 10 V; see Figure 24 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 29 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V; see Figure 30 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 RL = 110 Ω, 5 Vp-p, f = 20 Hz to 20 kHz; see Figure 28 RL = 50 Ω, CL = 5 pF; see Figure 26 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 12 V Digital inputs = 0 V or VDD Digital inputs = 5 V ADG1604 5 V SINGLE SUPPLY VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to +125°C 0 V to VDD 1.7 2.15 0.05 0.09 0.4 0.53 ±0.05 ±0.2 ±0.05 ±0.2 ±0.1 ±0.4 2.4 2.7 0.12 0.15 0.55 0.6 ±1 ±8 ±2 ±16 ±2 ±16 2.0 0.8 0.001 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 8 V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ Break-Before-Make Time Delay, tD 175 283 135 174 228 288 30 Charge Injection Off Isolation 70 70 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ Channel-to-Channel Crosstalk 70 dB typ Total Harmonic Distortion + Noise 0.09 % typ 16 70 300 400 MHz typ pF typ pF typ pF typ tON (EN) tOFF (EN) 337 380 194 212 342 385 21 −3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD VDD 1 Unit 0.001 1 3.3/16 Guaranteed by design, not subject to production test. Rev. 0 | Page 5 of 20 μA typ μA max V min/max Test Conditions/Comments VS = 0 V to 4.5 V, IS = −10 mA; see Figure 22 VDD = 4.5 V, VSS = 0 V VS = 0 V to 4.5 V, IS = −10 mA VS = 0 V to 4.5 V, IS = −10 mA VDD = 5.5 V, VSS = 0 V VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 23 VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 23 VS = VD = 1 V or 4.5 V; see Figure 24 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 29 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 2.5 V; see Figure 30 VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27 RL = 110 Ω, f = 20 Hz to 20 kHz, VS = 3.5 V p-p; see Figure 28 RL = 50 Ω, CL = 5 pF; see Figure 26 VS = 2.5 V, f = 1 MHz VS = 2.5 V, f = 1 MHz VS = 2.5 V, f = 1 MHz VDD = 5.5 V Digital inputs = 0 V or VDD ADG1604 3.3 V SINGLE SUPPLY VDD = 3.3 V, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to +125°C 0 V to VDD 3.2 3.6 0.06 0.15 1.2 1.6 ±0.02 ±0.25 ±0.02 ±0.25 ±0.05 ±0.6 3.8 4 0.16 0.17 1.7 1.8 ±1 ±8 ±2 ±16 ±2 ±16 2.0 0.8 0.001 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 8 V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ Break-Before-Make Time Delay, tD 280 460 227 308 357 480 25 Charge Injection Off Isolation 60 70 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ Channel-to-Channel Crosstalk 70 dB typ Total Harmonic Distortion + Noise 0.15 % typ 15 76 316 420 MHz typ pF typ pF typ pF typ tON (EN) tOFF (EN) 526 575 332 346 549 601 20 −3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD 0.001 1.0 VDD 1 Unit 1.0 3.3/16 Guaranteed by design, not subject to production test. Rev. 0 | Page 6 of 20 μA typ μA max V min/max Test Conditions/Comments VS = 0 V to VDD, IS = −10 mA; see Figure 22 VDD = 3.3 V, VSS = 0 V VS = 0 V to VDD, IS = −10 mA VS = 0 V to VDD, IS = −10 mA VDD = 3.6 V, VSS = 0 V VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 23 VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 23 VS = VD = 0.6 V or 3 V; see Figure 24 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 29 RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 30 VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27 RL = 110 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p; see Figure 28 RL = 50 Ω, CL = 5 pF; see Figure 26 VS = 1.5 V, f = 1 MHz VS = 1.5 V, f = 1 MHz VS = 1.5 V, f = 1 MHz VDD = 3.6 V Digital inputs = 0 V or VDD ADG1604 CONTINUOUS CURRENT PER CHANNEL, S OR D Table 5. Parameter CONTINUOUS CURRENT, S OR D VDD = +5 V, VSS = −5 V TSSOP (θJA = 150.4°C/W) LFCSP (θJA = 48.7°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 150.4°C/W) LFCSP (θJA = 48.7°C/W) VDD = 5 V, VSS = 0 V TSSOP (θJA = 150.4°C/W) LFCSP (θJA = 48.7°C/W) VDD = 3.3 V, VSS = 0 V TSSOP (θJA = 150.4°C/W) LFCSP (θJA = 48.7°C/W) 25°C 85°C 125°C Unit 315 504 189 259 95 112 mA maximum mA maximum 378 627 221 311 112 126 mA maximum mA maximum 249 403 158 224 91 105 mA maximum mA maximum 256 410 165 235 98 116 mA maximum mA maximum Rev. 0 | Page 7 of 20 ADG1604 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, S or D Continuous Current, S or D 2 Operating Temperature Range Industrial (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, θJA Thermal Impedance (2-Layer Board) 16-Lead LFCSP, θJA Thermal Impedance (4-Layer Board) Reflow Soldering Peak Temperature, Pb free 1 2 Rating 18 V −0.3 V to +18 V +0.3 V to −18 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 1150 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 150.4°C/W 48.7°C/W 260°C Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. See Table 5. Rev. 0 | Page 8 of 20 ADG1604 GND ADG1604 12 VDD S1 4 11 S3 S2 5 TOP VIEW (Not to Scale) 10 S4 D 6 9 NC NC 7 8 NC NC = NO CONNECT S1 3 S2 4 14 A1 13 NC ADG1604 TOP VIEW (Not to Scale) 10 S3 9 S4 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD TIED TO SUBSTRATE, VSS. Figure 2. 14-Lead TSSOP Pin Configuration 07982-003 13 3 12 GND 11 VDD NC 8 2 NC 2 NC 7 EN VSS PIN 1 INDICATOR VSS 1 A1 D 6 14 NC 5 1 07982-002 A0 15 A0 16 EN PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. 16-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions TSSOP 1 2 3 4 5 6 7, 8, 9 10 11 12 13 14 N/A Pin No. LFCSP 15 16 1 3 4 6 2, 5, 7, 8, 13 9 10 11 12 14 17 (EPAD) Mnemonic A0 EN VSS S1 S2 D NC S4 S3 VDD GND A1 EP (EPAD) Description Logic Control Input. Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, the Ax logic inputs determine the on switch. Most Negative Power Supply Potential. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Drain Terminal. This pin can be an input or output. No Connection. Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. Exposed Pad. Tied to substrate, VSS. Table 8. ADG1604 Truth Table EN 0 1 1 1 1 A1 X 0 0 1 1 A0 X 0 1 0 1 S1 Off On Off Off Off Rev. 0 | Page 9 of 20 S2 Off Off On Off Off S3 Off Off Off On Off S4 Off Off Off Off On ADG1604 TYPICAL PERFORMANCE CHARACTERISTICS 1.4 VDD = +3.3V VSS = –3.3V 1.2 ON RESISTANCE (Ω) 1.2 1.0 VDD = +5V VSS = –5V 0.8 VDD = +8V VSS = –8V 0.6 0.4 –8 –6 –4 –2 0 TA = +125°C TA = +85°C TA = +25°C TA = –40°C 1.0 0.8 0.6 2 4 6 8 VS OR VD VOLTAGE (V) 0.4 07982-014 0 2 4 3.5 10 12 2.5 TA = 25°C ON RESISTANCE (Ω) VDD = 3.3V VSS = 0V 2.5 2.0 VDD = 5V VSS = 0V 1.5 VDD = 12V VSS = 0V 4 6 8 10 1.5 12 14 16 VS OR VD VOLTAGE (V) 1.0 Figure 5. On Resistance as a Function of VD (VS) for Single Supply 0 3.5 ON RESISTANCE (Ω) 1.2 1.0 0.8 –4 –2 0 2 VS OR VD VOLTAGE (V) 4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD = 3.3V VSS = 0V 3.0 TA = +125°C TA = +85°C TA = +25°C TA = –40°C 2.5 2.0 TA = +125°C TA = +85°C TA = +25°C TA = –40°C 1.5 6 0 07982-012 0.4 –6 1.5 Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures, 5 V Single Supply 4.0 VDD = +5V VSS = –5V 1.0 VS OR VD VOLTAGE (V) 1.4 0.6 0.5 07982-013 0.5 2 2.0 VDD = 16V VSS = 0V 07982-015 1.0 0 VDD = 5V VSS = 0V TA = +125°C TA = +85°C TA = +25°C TA = –40°C 3.0 ON RESISTANCE (Ω) 8 Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, 12 V Single Supply Figure 4. On Resistance as a Function of VD (VS) for Dual Supply ON RESISTANCE (Ω) 6 VS OR VD VOLTAGE (V) Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures, ±5 V Dual Supply 0.5 1.0 1.5 2.0 VS OR VD VOLTAGE (V) 2.5 3.0 3.5 07982-006 ON RESISTANCE (Ω) VDD = 12V VSS = 0V TA = 25°C 07982-010 1.4 Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures, 3.3 V Single Supply Rev. 0 | Page 10 of 20 ADG1604 18 15 16 ID (OFF) –, + 14 LEAKAGE CURRENT (nA) 5 IS (OFF) +, – 0 IS (OFF) –, + ID, IS (ON) –, – ID (OFF) +, – 10 8 ID, IS (OFF) –, – 6 ID (OFF) –, + 4 IS (OFF) +, – 2 0 –10 IS (OFF) –, + –2 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 10. Leakage Currents as a Function of Temperature, ±5 V Dual Supply 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 13. Leakage Currents as a Function of Temperature, 3.3 V Single Supply 20 600 15 IDD PER CHANNEL TA = 25°C 500 ID, IS (ON) +, + IDD = +12V ISS = 0V 10 400 ID (OFF) –, + 5 IS (OFF) +, – IDD (µA) 300 0 ID, IS (ON) –, – IS (OFF) –, + –5 0 20 40 60 80 100 IDD = +5V ISS = –5V IDD = +5V ISS = 0V ID (OFF) +, – –10 –15 200 100 0 120 TEMPERATURE (°C) IDD = +3.3V ISS = 0V –100 07982-032 LEAKAGE CURRENT (nA) ID (OFF) +, – –4 07982-033 –15 07982-031 –5 ID, IS (OFF) +, + 12 0 2 4 6 8 10 07982-005 LEAKAGE CURRENT (nA) 10 ID, IS (ON) +, + 12 LOGIC (V) Figure 14. IDD vs. Logic Level Figure 11. Leakage Currents as a Function of Temperature, 12 V Single Supply 350 20 300 ID, IS (OFF) +, + 10 ID, IS (OFF) –, – 5 ID (OFF) –, + 250 200 VDD = +5V VSS = –5V 150 100 VDD = +5V VSS = 0V 0 IS (OFF) +, – IS (OFF) –, + ID (OFF) +, – 0 20 40 60 80 TEMPERATURE (°C) 50 100 120 07982-030 –5 Figure 12. Leakage Currents as a Function of Temperature, 5 V Single Supply Rev. 0 | Page 11 of 20 VDD = +12V VSS = 0V 0 –6 VDD = +3.3V VSS = 0V –4 –2 0 2 4 6 8 10 VS (V) Figure 15. Charge Injection vs. Source Voltage 12 14 07982-009 CHARGE INJECTION (pC) LEAKAGE CURRENT (nA) 15 ADG1604 450 0 TA = 25°C VDD = +5V VSS = –5V 400 –1 VDD = +3.3V, VSS = 0V INSERTION LOSS (dB) 350 TIME (ns) 300 VDD = +5V, VSS = 0V 250 200 –2 –3 –4 150 VDD = +5V, VSS = –5V 100 –5 20 40 60 80 100 120 TEMPERATURE (°C) –6 1k 100M –20 NO DECOUPLING CAPACITORS ACPSRR (dB) –30 –40 –50 –60 DECOUPLING CAPACITORS –70 –80 –90 100k 1M 10M 100M 1G –100 1k 07982-007 10k 100k 1M 10M FREQUENCY (Hz) Figure 20. ACPSRR vs. Frequency 0.20 TA = 25°C VDD = +5V VSS = –5V RL = 110Ω TA = 25°C 0.18 –20 VDD = +3.3V VS = 2V p-p 0.16 0.14 THD + N (%) –40 –60 –80 0.12 VDD = +5V VS = 3.5V p-p 0.10 0.08 0.06 VDD = +12V VS = 5V p-p 0.04 –100 VDD = +5V VSS = –5V VS = 5V p-p 10k 100k 1M 10M FREQUENCY (Hz) 100M 1G 07982-018 0.02 –120 1k 0 0 5k 10k 15k FREQUENCY (Hz) Figure 21. THD + N vs. Frequency Figure 18. Crosstalk vs. Frequency Rev. 0 | Page 12 of 20 20k 07982-017 OFF ISOLATION (dB) 10M 0 TA = 25°C –10 VDD = +5V VSS = –5V Figure 17. Off Isolation vs. Frequency CROSSTALK (dB) 1M Figure 19. On Response vs. Frequency FREQUENCY (Hz) 0 100k FREQUENCY (Hz) Figure 16. tON/tOFF Times vs. Temperature –15 –20 TA = 25°C VDD = +5V –25 VSS = –5V –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –95 –100 –105 –110 1k 10k 10k 07982-008 0 07982-019 –20 07982-004 VDD = +12V, VSS = 0V 50 –40 ADG1604 TEST CIRCUITS VDD VSS 0.1µF 0.1µF VDD NETWORK ANALYZER VSS 50Ω Sx 50Ω VS V Sx D RL 50Ω GND D VOUT 07982-020 07982-027 IDS VS VOUT VS OFF ISOLATION = 20 log Figure 25. Off Isolation Figure 22. On Resistance VDD VSS 0.1µF 0.1µF VDD NETWORK ANALYZER VSS 50Ω Sx VS D GND A VS VD VOUT WITH SWITCH VOUT WITHOUT SWITCH INSERTION LOSS = 20 log Figure 23. Off Leakage Figure 26. Bandwidth VDD VSS 0.1µF 0.1µF NETWORK ANALYZER VOUT VDD S1 VSS RL 50Ω D S2 VS NC = NO CONNECT A VD 07982-022 NC D RL 50Ω GND ID (ON) Sx 07982-028 D VOUT CHANNEL-TO-CHANNEL CROSSTALK = 20 log VOUT VS Figure 27. Channel-to-Channel Crosstalk Figure 24. On Leakage Rev. 0 | Page 13 of 20 07982-029 Sx A RL 50Ω ID (OFF) 07982-021 IS (OFF) ADG1604 VDD VSS 0.1µF 0.1µF AUDIO PRECISION VDD VSS RS Sx IN VS V p-p D VIN VOUT RL 110Ω 07982-034 GND Figure 28. THD + Noise VDD VSS 0.1µF ADDRESS DRIVE (VIN) VDD VSS S1 A1 S2 A0 S3 S4 VIN 2.0V EN VS1 VS4 3V 50% 50% 0V 90% VOUT 90% VOUT D GND tTRANSITION CL 35pF RL 300Ω tTRANSITION 07982-023 0.1µF Figure 29. Address to Output Switching Times VIN 300Ω 2.0V VDD VSS 0.1µF VDD VSS S1 A1 S2 A0 S3 S4 EN VOUT D GND ADDRESS DRIVE (VIN) VS1 RL 300Ω CL 35pF 0V VOUT Figure 30. Break-Before-Make Time Delay Rev. 0 | Page 14 of 20 3V 80% 80% tBBM 07982-024 0.1µF ADG1604 VDD VSS 0.1µF VDD VSS S1 A1 S2 A0 S3 S4 EN GND VS 3V 50% VOUT 0.9VOUT OUTPUT D VOUT RL 300Ω 300Ω 50% 0V 0.9VOUT 0V CL 35pF tON (EN) tOFF (EN) Figure 31. Enable-to-Output Switching Delay VDD VSS VDD VSS Sx D VOUT RS VOUT VIN CL 1nF VS ΔVOUT QINJ = CL × ΔVOUT SW OFF SW OFF SW ON DECODER GND VIN A1 A2 SW OFF SW OFF 07982-026 VIN ENABLE DRIVE (VIN) 07982-025 0.1µF EN Figure 32. Charge Injection Rev. 0 | Page 15 of 20 ADG1604 TERMINOLOGY tTRANSITION The delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another. IDD The positive supply current. ISS The negative supply current. tON (EN) The delay between applying the digital control input and the output switching on. See Figure 31. VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between Terminal D and Terminal S. RFLAT(ON) Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. tOFF (EN) The delay between applying the digital control input and the output switching off. See Figure 31. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. ID (Off) The drain leakage current with the switch off. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. ID, IS (On) The channel leakage current with the switch on. Bandwidth The frequency at which the output is attenuated by 3 dB. VINL The maximum input voltage for Logic 0. On Response The frequency response of the on switch. VINH The minimum input voltage for Logic 1. Insertion Loss The loss due to the on resistance of the switch. IINL (IINH) The input current of the digital input. Total Harmonic Distorition + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental. CS (Off) The off switch source capacitance, which is measured with reference to ground. CD (Off) The off switch drain capacitance, which is measured with reference to ground. CD, CS (On) The on switch capacitance, which is measured with reference to ground. AC Power Supply Rejection Ratio (ACPSRR) The ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. CIN The digital input capacitance. Rev. 0 | Page 16 of 20 ADG1604 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.20 0.09 0.30 0.19 0.75 0.60 0.45 8° 0° SEATING PLANE 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 33. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 4.00 BSC SQ 0.60 MAX 12 13 3.75 BSC SQ 1 16 EXPOSED PAD 4 0.65 BSC TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING 0.30 PLANE 0.23 0.18 9 8 PIN 1 INDICATOR 2.65 2.50 SQ 2.35 5 0.25 MIN 1.95 BCS 0.80 MAX 0.65 TYP BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.20 REF 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGC. 031006-A PIN 1 INDICATOR 0.50 0.40 0.30 Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-13) Dimensions shown in millimeters ORDERING GUIDE Model ADG1604BRUZ 1 ADG1604BRUZ-REEL1 ADG1604BRUZ-REEL71 ADG1604BCPZ- REEL1 ADG1604BCPZ-REEL71 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 14-Lead Thin Shrink Small Outline Package [TSSOP] 14-Lead Thin Shrink Small Outline Package [TSSOP] 14-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Z = RoHS Compliant Part. Rev. 0 | Page 17 of 20 Package Option RU-14 RU-14 RU-14 CP-16-13 CP-16-13 ADG1604 NOTES Rev. 0 | Page 18 of 20 ADG1604 NOTES Rev. 0 | Page 19 of 20 ADG1604 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07982-0-1/09(0) Rev. 0 | Page 20 of 20