Technical Data Sheet

Quad-Channel Digital Isolators
ADuM2400/ADuM2401/ADuM2402
Data Sheet
FUNCTIONAL BLOCK DIAGRAMS
ADuM2400
VDD1 1
16 VDD2
15 GND2
VIA 3
ENCODE
DECODE
14 VOA
VIB 4
ENCODE
DECODE
13 VOB
VIC 5
ENCODE
DECODE
12 VOC
VID 6
ENCODE
DECODE
11 VOD
NC 7
10 VE2
9 GND2
GND1 8
05007-001
GND1 2
Figure 1. ADuM2400
ADuM2401
VDD1 1
GND1 2
16
VDD2
15
GND2
VIA 3
ENCODE
DECODE
14
VOA
VIB 4
ENCODE
DECODE
13
VOB
VIC 5
ENCODE
DECODE
12
VOC
VOD 6
DECODE
ENCODE
11
VID
VE1 7
10
VE2
GND1 8
9
GND2
05007-002
Low power operation
5 V operation
1.0 mA per channel maximum @ 0 Mbps to 2 Mbps
3.5 mA per channel maximum @ 10 Mbps
31 mA per channel maximum @ 90 Mbps
3 V operation
0.7 mA per channel maximum @ 0 Mbps to 2 Mbps
2.1 mA per channel maximum @ 10 Mbps
20 mA per channel maximum @ 90 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package version (RW-16)
16-lead SOIC wide body enhanced creepage version (RI-16)
Safety and regulatory approvals (RI-16 package)
UL recognition: 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
IEC 60601-1: 250 V rms (reinforced)
IEC 60950-1: 400 V rms (reinforced)
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 846 V peak
Figure 2. ADuM2401
ADuM2402
VDD1 1
GND1 2
16
VDD2
15
GND2
VIA 3
ENCODE
DECODE
14
VOA
VIB 4
ENCODE
DECODE
13
VOB
VOC 5
DECODE
ENCODE
12
VIC
VOD 6
DECODE
ENCODE
11
VID
VE1 7
10
VE2
GND1 8
9
GND2
05007-003
FEATURES
Figure 3. ADuM2402
APPLICATIONS
General-purpose, high voltage, multichannel isolation
Medical equipment
Motor drives
Power supplies
ture and lifetime effects are eliminated with the simple iCoupler
digital interfaces and stable performance characteristics. Furthermore, iCoupler devices run at one-tenth to one-sixth the power
of optocouplers at comparable signal data rates.
GENERAL DESCRIPTION
The ADuM2400/ADuM2401/ADuM2402 isolators provide four
independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). The ADuM2400/
ADuM2401/ADuM2402 models operate with the supply voltage
of either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage
translation functionality across the isolation barrier. In addition,
the ADuM2400/ADuM2401/ADuM2402 provide low pulse
width distortion (<2 ns for CRWZ grade) and tight channel-tochannel matching (<2 ns for CRWZ grade). The ADuM2400/
ADuM2401/ADuM2402 isolators have a patented refresh feature
that ensures dc correctness in the absence of input logic transitions
and during power-up/power-down conditions.
1
The ADuM2400/ADuM2401/ADuM2402 are 4-channel digital
isolators based on Analog Devices, Inc., iCoupler® technology.
Combining high speed CMOS and monolithic air core transformer
technology, these isolation components provide outstanding
performance characteristics that are superior to alternatives, such
as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain
current transfer ratios, nonlinear transfer functions, and tempera
1
Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
Document Feedback
Rev. F
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ADuM2400/ADuM2401/ADuM2402
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Operating Conditions .................................... 11
Applications ....................................................................................... 1
Absolute Maximum Ratings ......................................................... 12
General Description ......................................................................... 1
ESD Caution................................................................................ 12
Functional Block Diagrams ............................................................. 1
Pin Configurations and Function Descriptions ......................... 13
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 16
Specifications..................................................................................... 3
Application Information ................................................................ 18
Electrical Characteristics—5 V Operation................................ 3
PC Board Layout ........................................................................ 18
Electrical Characteristics—3 V Operation................................ 5
Propagation Delay-Related Parameters................................... 18
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 7
DC Correctness and Magnetic Field Immunity.......................... 18
Package Characteristics ............................................................. 10
Insulation Lifetime ..................................................................... 20
Regulatory Information ............................................................. 10
Outline Dimensions ....................................................................... 21
Insulation and Safety-Related Specifications .......................... 10
Ordering Guide .......................................................................... 22
Power Consumption .................................................................. 19
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 11
REVISION HISTORY
7/15—Rev. E to Rev. F
Changes to Table 5 and Table 6 ..................................................... 10
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
2/12—Rev. D to Rev. E
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Change to PC Board Layout Section ............................................ 18
8/11—Rev. C to Rev. D
Added 16-Lead SOIC_IC .................................................. Universal
Changes to Features Section and General Description
Section ................................................................................................ 1
Changes to Table 5 and Table 6 ..................................................... 10
Changes to Table 8 Endnote .......................................................... 11
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
6/07—Rev. A to Rev. B
Updated VDE Certification Throughout .......................................1
Changes to Features and Note 1 ......................................................1
Changes to Figure 1, Figure 2, and Figure 3 ..................................1
Changes to Regulatory Information ............................................ 10
Changes to Table 7.......................................................................... 11
Changes to Insulation Lifetime Section ...................................... 20
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
1/06—Rev. 0 to Rev. A
Changes to Regulatory Information Section .............................. 13
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
9/05—Revision 0: Initial Version
7/08—Rev. B to Rev. C
Changes to Layout ............................................................................ 1
Changes to Table 6 .......................................................................... 10
Rev. F | Page 2 of 24
Data Sheet
ADuM2400/ADuM2401/ADuM2402
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM2400 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM2401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM2402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 or VDD2 Supply Current
90 Mbps (CRWZ Grade Only)
VDD1 or VDD2 Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM2400ARWZ/ADuM2401ARWZ/
ADuM2402ARWZ
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Propagation Delay Skew6
Channel-to-Channel Matching7
Symbol
Typ
Max Unit
IDDI (Q)
IDDO (Q)
0.50
0.19
0.53 mA
0.21 mA
IDD1 (Q)
IDD2 (Q)
2.2
0.9
2.8
1.4
IDD1 (10)
IDD2 (10)
8.6
2.6
10.6 mA
3.5
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
IDD1 (90)
IDD2 (90)
70
18
100
25
mA
mA
45 MHz logic signal frequency
45 MHz logic signal frequency
IDD1 (Q)
IDD2 (Q)
1.8
1.2
2.4
1.8
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
IDD1 (10)
IDD2 (10)
7.1
4.1
9.0
5.0
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
IDD1 (90)
IDD2 (90)
57
31
82
43
mA
mA
45 MHz logic signal frequency
45 MHz logic signal frequency
IDD1 (Q), IDD2 (Q)
1.5
2.1
mA
DC to 1 MHz logic signal frequency
IDD1 (10), IDD2 (10)
5.6
7.0
mA
5 MHz logic signal frequency
IDD1 (90), IDD2 (90)
44
62
mA
45 MHz logic signal frequency
µA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH,
VOCH, VODH
VOAL, VOBL,
VOCL, VODL
Min
−10
+0.01 +10
2.0
0.8
(VDD1 or VDD2) − 0.1 5.0
(VDD1 or VDD2) − 0.4 4.8
0.0
0.04
0.2
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/tPSKOD
1
50
Rev. F | Page 3 of 24
65
0.1
0.1
0.4
mA
mA
V
V
V
V
V
V
V
1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns
Test Conditions
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
ADuM2400/ADuM2401/ADuM2402
Parameter
ADuM2400BRWZ/ADuM2401BRWZ/
ADuM2402BRWZ
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
Channel-to-Channel Matching,
Opposing-Directional Channels7
ADuM2400CRWZ/ADuM2401CRWZ/
ADuM2402CRWZ
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
Channel-to-Channel Matching,
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at
Logic High Output8
Common-Mode Transient Immunity at
Logic Low Output8
Refresh Rate
Input Dynamic Supply Current per Channel9
Output Dynamic Supply Current per Channel9
Symbol
Data Sheet
Min
Typ
PW
Max Unit
Test Conditions
100
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
15
3
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
tPHL, tPLH
PWD
10
20
32
50
3
5
PW
tPSK
tPSKCD
11.1 ns
Mbps
32
ns
2
ns
ps/°C
10
ns
2
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
90
18
8.3
120
27
0.5
3
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
tR/tF
|CMH|
25
2.5
35
ns
kV/µs
|CML|
25
35
kV/µs
1.2
0.19
0.05
Mbps
mA/Mbps
mA/Mbps
fr
IDDI (D)
IDDO (D)
1
All voltages are relative to their respective ground.
Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The
supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8
through Figure 10 for information on per channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for
total VDD1 and VDD2 supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per channel supply current for a
given data rate.
2
Rev. F | Page 4 of 24
Data Sheet
ADuM2400/ADuM2401/ADuM2402
ELECTRICAL CHARACTERISTICS—3 V OPERATION1
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.
Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM2400 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM2401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM2402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 or VDD2 Supply Current
90 Mbps (CRWZ Grade Only)
VDD1 or VDD2 Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM2400ARWZ/ADuM2401ARWZ/
ADuM2402ARWZ
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Propagation Delay Skew6
Channel-to-Channel Matching7
Symbol
Typ
Max Unit
IDDI (Q)
IDDO (Q)
0.26
0.11
0.31
0.14
mA
mA
IDD1 (Q)
IDD2 (Q)
1.2
0.5
1.9
0.9
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
IDD1 (10)
IDD2 (10)
4.5
1.4
6.5
2.0
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
IDD1 (90)
IDD2 (90)
37
11
65
15
mA
mA
45 MHz logic signal frequency
45 MHz logic signal frequency
IDD1 (Q)
IDD2 (Q)
1.0
0.7
1.6
1.2
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
IDD1 (10)
IDD2 (10)
3.7
2.2
5.4
3.0
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
IDD1 (90)
IDD2 (90)
30
18
52
27
mA
mA
45 MHz logic signal frequency
45 MHz logic signal frequency
IDD1 (Q), IDD2 (Q)
0.9
1.5
mA
DC to 1 MHz logic signal frequency
IDD1 (10), IDD2 (10)
3.0
4.2
mA
5 MHz logic signal frequency
IDD1 (90), IDD2 (90)
24
39
mA
45 MHz logic signal frequency
µA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH,
VOCH, VODH
VOAL, VOBL,
VOCL, VODL
Min
−10
+0.01 +10
1.6
0.4
(VDD1 or VDD2) − 0.1 3.0
(VDD1 or VDD2) − 0.4 2.8
0.0
0.04
0.2
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/tPSKOD
1
50
Rev. F | Page 5 of 24
75
0.1
0.1
0.4
V
V
V
V
V
V
V
1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns
Test Conditions
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
ADuM2400/ADuM2401/ADuM2402
Parameter
ADuM2400BRWZ/ADuM2401BRWZ/
ADuM2402BRWZ
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
Channel-to-Channel Matching,
Opposing-Directional Channels7
ADuM2400CRWZ/ADuM2401CRWZ/
ADuM2402CRWZ
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
Channel-to-Channel Matching,
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at
Logic High Output8
Common-Mode Transient Immunity at
Logic Low Output8
Refresh Rate
Input Dynamic Supply Current per Channel9
Output Dynamic Supply Current per Channel9
Symbol
Data Sheet
Min
Typ
PW
Max Unit
Test Conditions
100
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
22
3
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
11.1
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
10
20
38
50
3
5
PW
tPSK
tPSKCD
16
2
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
90
20
8.3
120
34
0.5
3
45
2
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
tR/tF
|CMH|
25
3
35
ns
kV/µs
|CML|
25
35
kV/µs
1.1
0.10
0.03
Mbps
mA/Mbps
mA/Mbps
fr
IDDI (D)
IDDO (D)
1
All voltages are relative to their respective ground.
Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The
supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8
through Figure 10 for information on per channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for
total VDD1 and VDD2 supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per channel supply current for a
given data rate.
2
Rev. F | Page 6 of 24
Data Sheet
ADuM2400/ADuM2401/ADuM2402
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION1
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications
are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V; or VDD1 = 5 V, VDD2 = 3.0 V.
Table 3.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current per Channel, Quiescent
5 V/3 V Operation
3 V/5 V Operation
ADuM2400 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
ADuM2401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
Symbol
Min
Typ
Max Unit
Test Conditions
0.50
0.26
0.53
0.31
mA
mA
0.11
0.19
0.14
0.21
mA
mA
2.2
1.2
2.8
1.9
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
0.5
0.9
0.9
1.4
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
8.6
4.5
10.6
6.5
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
1.4
2.6
2.0
3.5
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
70
37
100
65
mA
mA
45 MHz logic signal frequency
45 MHz logic signal frequency
11
18
15
25
mA
mA
45 MHz logic signal frequency
45 MHz logic signal frequency
1.8
1.0
2.4
1.6
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
0.7
1.2
1.2
1.8
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
7.1
3.7
9.0
5.4
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
2.2
4.1
3.0
5.0
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
57
30
82
52
mA
mA
45 MHz logic signal frequency
45 MHz logic signal frequency
IDDI (Q)
IDDO (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
IDD1 (90)
IDD2 (90)
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
IDD1 (90)
Rev. F | Page 7 of 24
ADuM2400/ADuM2401/ADuM2402
Parameter
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
ADuM2402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
For All Models
Input Currents
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM2400ARWZ/ADuM2401ARWZ/
ADuM2402ARWZ
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse-Width Distortion, |tPLH − tPHL|5
Propagation Delay Skew6
Channel-to-Channel Matching7
ADuM2400BRWZ/ADuM2401BRWZ/
ADuM2402BRWZ
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Symbol
IDD2 (90)
Data Sheet
Min
Typ
Max Unit
Test Conditions
18
31
27
43
mA
mA
45 MHz logic signal frequency
45 MHz logic signal frequency
1.5
0.9
2.1
1.5
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
0.9
1.5
1.5
2.1
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
5.6
3.0
7.0
4.2
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
3.0
5.6
4.2
7.0
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
44
24
62
39
mA
mA
45 MHz logic signal frequency
45 MHz logic signal frequency
24
44
39
62
mA
mA
45 MHz logic signal frequency
45 MHz logic signal frequency
+0.01
+10
µA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
IDD1 (90)
IDD2 (90)
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
−10
2.0
1.6
V
V
VIL, VEL
0.8
0.4
VOAH, VOBH, (VDD1 or VDD2) −
VOCH, VODH 0.1
(VDD1 or VDD2) −
0.4
VOAL, VOBL,
VOCL, VODL
(VDD1 or VDD2)
(VDD1 or VDD2) −
0.2
0.0
0.1
0.04
0.1
0.2
0.4
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/tPSKOD
1
50
70
PW
tPHL, tPLH
10
15
35
Rev. F | Page 8 of 24
V
V
V
IOx = −20 µA, VIx = VIxH
V
IOx = −4 mA, VIx = VIxH
V
V
V
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
100
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
50
ns
Mbps
ns
Data Sheet
Parameter
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
Channel-to-Channel Matching,
Opposing-Directional Channels7
ADuM2400CRWZ/ADuM2401CRWZ/
ADuM2402CRWZ
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
Channel-to-Channel Matching,
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
Common-Mode Transient Immunity at
Logic High Output8
Common-Mode Transient Immunity at
Logic Low Output8
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
Input Dynamic Supply Current per Channel9
5 V/3 V Operation
3 V/5 V Operation
Output Dynamic Supply Current per Channel9
5 V/3 V Operation
3 V/5 V Operation
ADuM2400/ADuM2401/ADuM2402
Symbol
PWD
Min
Typ
tPSK
tPSKCD
Max Unit
3
ns
ps/°C
22
ns
3
ns
Test Conditions
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
11.1
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
5
PW
tPSK
tPSKCD
14
2
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
90
20
8.3
120
30
0.5
3
40
2
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
tR/tF
CL = 15 pF, CMOS signal levels
|CMH|
25
3.0
2.5
35
ns
ns
kV/µs
|CML|
25
35
kV/µs
1.2
1.1
Mbps
Mbps
0.19
0.10
mA/Mbps
mA/Mbps
0.03
0.05
mA/Mbps
mA/Mbps
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
fr
IDDI (D)
IDDO (D)
1
All voltages are relative to their respective ground.
Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The
supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8
through Figure 10 for information on per channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for
total VDD1 and VDD2 supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per channel supply current for a
given data rate.
2
Rev. F | Page 9 of 24
ADuM2400/ADuM2401/ADuM2402
Data Sheet
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
IC Junction-to-Case Thermal Resistance, Side 1
IC Junction-to-Case Thermal Resistance, Side 2
1
2
Symbol
RI-O
CI-O
CI
θJCI
θJCO
Min
Typ
1012
2.2
4.0
33
28
Max
Unit
Ω
pF
pF
°C/W
°C/W
Test Conditions
f = 1 MHz
Thermocouple located at center
of package underside
Device considered a 2-terminal device: Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and
Pin 16 shorted together.
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM2400/ADuM2401/ADuM2402 are approved by the organizations listed in Table 5. Refer to Table 10 and the Insulation Lifetime
section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 5.
UL
Recognized Under UL 1577
Component Recognition
Program1
Single Protection 5000 V rms
Isolation Voltage
File E214100
CSA
Approved under CSA Component Acceptance
Notice 5A
CQC
Approved under CQC11-471543-2012
Basic insulation per CSA 60950-1-07 and
IEC 60950-1, 600 V rms (848 V peak) maximum
working voltage
Basic insulation per GB4943.1-2011,
600 V rms(848 V peak) maximum
working voltage, tropical climate,
altitude ≤ 5000 m
RW-16 package: reinforced insulation
per GB4943.1-2011, 380 V rms
(537 V peak) maximum working
voltage, tropical climate, altitude ≤
5000 m
RW-16 package: reinforced insulation per
CSA 60950-1-07 and IEC 60950-1, 380 V rms
(537 V peak) maximum working voltage;
reinforced insulation per IEC 60601-1
125 V rms (176 V peak) maximum working
voltage
RI-16 package: reinforced insulation per
CSA 60950-1-07 and IEC 60950-1, 400 V rms
(565 V peak) maximum working voltage;
reinforced insulation per IEC 60601-1 250 V rms
(353 V peak) maximum working voltage
File 205078
VDE
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10): 2006-122
Reinforced insulation,
846 V peak
RI-16 package: reinforced insulation
per 400 V rms (565 V peak) maximum
working voltage, tropical climate,
altitude ≤ 5000 m
File: CQC14001108690
File 2471900-4880-0001
1
In accordance with UL 1577, each ADuM2400/ADuM2401/ADuM2402 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 sec (current leakage
detection limit = 10 µA).
2
In accordance with DIN V VDE V 0884-10, each ADuM2400/ADuM2401/ADuM2402 is proof tested by applying an insulation test voltage ≥1590 V peak for 1 sec (partial
discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap
Symbol Value
5000
L(I01)
8.0 min
Minimum External Tracking (Creepage) RW-16 L(I02)
Package
Minimum External Tracking (Creepage) RI-16 L(I02)
Package
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking CTI
Index)
Isolation Group
Unit Conditions
V rms 1-minute duration
mm Distance measured from input terminals to output terminals, shortest
distance through air along the PCB mounting plane, as an aid to PC
board layout
7.7 min
mm Measured from input terminals to output terminals, shortest distance
path along body
8.3 min
mm Measured from input terminals to output terminals, shortest distance
path along body
0.017 min mm Insulation distance through insulation
>400
V
DIN IEC 112/VDE 0303 Part 1
II
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. F | Page 10 of 24
Data Sheet
ADuM2400/ADuM2401/ADuM2402
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Note that the * marking on packages denotes DIN V VDE V 0884-10 approval for 846 V peak working voltage.
Table 7.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 450 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110, Table 1)
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method b1
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety-Limiting Values
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Symbol
Characteristic
Unit
VIORM
VPR
I to IV
I to II
I to II
40/105/21
2
846
1590
V peak
V peak
1375
1018
V peak
V peak
VTR
6000
V peak
TS
IS1
IS2
RS
150
265
335
>109
°C
mA
mA
Ω
VPR
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 seconds
Maximum value allowed in the event of a failure;
see Figure 4
VIO = 500 V
350
RECOMMENDED OPERATING CONDITIONS
300
Table 8.
Parameter
Operating Temperature (TA)
Supply Voltages1 (VDD1, VDD2)
Input Signal Rise and Fall Times
250
SIDE #2
200
150
SIDE #1
1
50
0
0
50
100
150
CASE TEMPERATURE (°C)
Rating
−40°C to +105°C
2.7 V to 5.5 V
1.0 ms
All voltages are relative to their respective ground.
100
05007-004
SAFETY-LIMITING CURRENT (mA)
Case Temperature
Side 1 Current
Side 2 Current
Insulation Resistance at TS
Conditions
200
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting
Values with Case Temperature per DIN V VDE V 0884-10
Rev. F | Page 11 of 24
ADuM2400/ADuM2401/ADuM2402
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 9.
Parameter
Storage Temperature Range (TST)
Ambient Operating Temperature
Range (TA)
Supply Voltage Range (VDD1, VDD2)1
Input Voltage Range
(VIA, VIB, VIC, VID, VE1, VE2)1, 2
Output Voltage Range
(VOA, VOB, VOC, VOD)1, 2
Average Output Current Per Pin3
Side 1 (IO1)
Side 2 (IO2)
Common-Mode Transients4
Rating
−65°C to +150°C
−40°C to +105°C
−0.5 V to +7.0 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
ESD CAUTION
−18 mA to +18 mA
−22 mA to +22 mA
−100 kV/µs to +100 kV/µs
1
All voltages are relative to their respective ground.
VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PC Board Layout section.
3
See Figure 4 for maximum rated current values for various temperatures.
4
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Rating can cause latchup or permanent damage.
2
Table 10. Maximum Continuous Working Voltage1
Parameter
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Reinforced Insulation
DC Voltage
Reinforced Insulation
1
Max
565
Unit
V peak
Constraint
50-year minimum lifetime
846
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
846
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 11. Truth Table (Positive Logic)
VIx Input1
H
L
X
X
X
X
1
VEx Input
H or NC
H or NC
L
H or NC
L
X
VDDI State1
Powered
Powered
Powered
Unpowered
Unpowered
Powered
VDDO State1
Powered
Powered
Powered
Powered
Powered
Unpowered
VOx Output1 Notes
H
L
Z
H
Outputs return to input state within 1 µs of VDDI power restoration.
Z
Indeterminate Outputs return to input state within 1 µs of VDDO power restoration if
VEx state is H or NC. Outputs return to high impedance state within
8 ns of VDDO power restoration if VEx state is L.
VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and
VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
Rev. F | Page 12 of 24
Data Sheet
ADuM2400/ADuM2401/ADuM2402
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
16 VDD2
*GND1 2
VIB 4
VIC 5
15 GND2*
ADuM2400
TOP VIEW
(Not to Scale)
14 VOA
13 VOB
12 VOC
VID 6
11 VOD
NC 7
10 VE2
*GND1 8
9
GND2*
NC = NO CONNECT
05007-005
VIA 3
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 5. ADuM2400 Pin Configuration
Table 12. ADuM2400 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
VDD1
GND1
VIA
VIB
VIC
VID
NC
GND1
GND2
VE2
11
12
13
14
15
16
VOD
VOC
VOB
VOA
GND2
VDD2
Description
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
No Connect.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected.
VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic
high or low is recommended.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. F | Page 13 of 24
ADuM2400/ADuM2401/ADuM2402
Data Sheet
16 VDD2
VDD1 1
15 GND2*
VIA 3
VIB 4
VIC 5
ADuM2401
TOP VIEW
(Not to Scale)
14 VOA
13 VOB
12 VOC
VOD 6
11 VID
VE1 7
10 VE2
*GND1 8
9
GND2*
05007-006
*GND1 2
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 6. ADuM2401 Pin Configuration
Table 13. ADuM2401 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
VDD1
GND1
VIA
VIB
VIC
VOD
VE1
8
9
10
GND1
GND2
VE2
11
12
13
14
15
16
VID
VOC
VOB
VOA
GND2
VDD2
Description
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Output D.
Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled
when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA,
VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or
low is recommended.
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. F | Page 14 of 24
ADuM2400/ADuM2401/ADuM2402
VDD1 1
16
VDD2
*GND1 2
15
GND2*
VIA 3
14
VOA
13
VOB
12
VIC
VOD 6
11
VID
VE1 7
10
VE2
*GND1 8
9
GND2*
VIB 4
VOC 5
ADuM2402
TOP VIEW
(Not to Scale)
05007-007
Data Sheet
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 7. ADuM2402 Pin Configuration
Table 14. ADuM2402 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
VDD1
GND1
VIA
VIB
VOC
VOD
VE1
8
9
10
GND1
GND2
VE2
11
12
13
14
15
16
VID
VIC
VOB
VOA
GND2
VDD2
Description
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Output C.
Logic Output D.
Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected.
VOC and VOD outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or
low is recommended.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected.
VOA and VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or
low is recommended.
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. F | Page 15 of 24
ADuM2400/ADuM2401/ADuM2402
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
20
80
15
60
CURRENT (mA)
CURRENT/CHANNEL (mA)
70
10
5V
50
40
5V
30
3V
3V
20
5
0
20
40
60
DATA RATE (Mbps)
80
100
0
05007-008
0
0
Figure 8. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
40
60
DATA RATE (Mbps)
80
100
Figure 11. Typical ADuM2400 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
25
6
5
20
4
CURRENT (mA)
3
5V
2
15
10
5V
3V
3V
5
1
0
20
40
60
DATA RATE (Mbps)
80
100
0
05007-009
0
05007-012
CURRENT/CHANNEL (mA)
20
05007-011
10
0
20
40
60
DATA RATE (Mbps)
80
Figure 9. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
Figure 12. Typical ADuM2400 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
10
35
100
30
CURRENT (mA)
25
6
4
5V
20
15
5V
10
3V
2
3V
0
0
20
40
60
DATA RATE (Mbps)
80
100
05007-013
5
05007-010
CURRENT/CHANNEL (mA)
8
0
0
20
40
60
DATA RATE (Mbps)
80
Figure 13. Typical ADuM2401 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Figure 10. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
Rev. F | Page 16 of 24
100
Data Sheet
ADuM2400/ADuM2401/ADuM2402
40
40
35
PROPAGATION DELAY (ns)
CURRENT (mA)
30
25
20
5V
15
3V
10
3V
35
30
5V
0
20
40
60
DATA RATE (Mbps)
80
05007-014
0
100
Figure 14. Typical ADuM2401 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
45
40
30
25
20
5V
15
3V
10
5
0
40
60
DATA RATE (Mbps)
80
05007-015
CURRENT (mA)
35
20
–25
0
25
50
TEMPERATURE (°C)
75
Figure 16. Propagation Delay vs. Temperature, C Grade
50
0
25
–50
100
Figure 15. Typical ADuM2402 VDD1 or VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Rev. F | Page 17 of 24
100
05007-016
5
ADuM2400/ADuM2401/ADuM2402
Data Sheet
APPLICATION INFORMATION
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
The ADuM2400/ADuM2401/ADuM2402 digital isolator
requires no external interface circuitry for the logic interfaces.
Power supply bypassing is strongly recommended at the input
and output supply pins (see Figure 17). Bypass capacitors are
most conveniently connected between Pin 1 and Pin 2 for VDD1
and between Pin 15 and Pin 16 for VDD2. The capacitor value
should be between 0.01 μF and 0.1 μF. The total lead length
between both ends of the capacitor and the input power supply
pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8
and between Pin 9 and Pin 16 should be considered unless the
ground pair on each package side are connected close to the
package.
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent via the transformer to the decoder.
The decoder is bistable and is therefore either set or reset by the
pulses, indicating input logic transitions. In the absence of logic
transitions at the input for more than ~1 μs, a periodic set of
refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses for more than approximately 5 μs, the input side
is assumed to be without power or nonfunctional; in which
case, the isolator output is forced to a default state (see Table 11)
by the watchdog timer circuit.
VDD1
GND1
VIA
VIB
VIC/VOC
VID/VOD
VE1
GND1
VDD2
GND2
VOA
VOB
VOC/VIC
VOD/VID
VE2
GND2
05007-017
PC BOARD LAYOUT
Figure 17. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, the board layout should be designed such that
any coupling that does occur equally affects all pins on a given
component side. Failure to ensure this could cause voltage
differentials between pins exceeding the device’s Absolute
Maximum Ratings, thereby leading to latch-up or permanent
damage.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt)Σ∏rn2; n = 1, 2,…, N
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the length of time
it takes for a logic signal to propagate through a component.
The propagation delay to a logic low output can differ from the
propagation delay to logic high.
50%
50%
Figure 18. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs among channels within a single
ADuM2400/ADuM2401/ADuM2402 component.
Propagation delay skew refers to the maximum amount the
propagation delay differs among multiple ADuM2400/
ADuM2401/ADuM2402 components operated under the same
conditions.
Rev. F | Page 18 of 24
10
1
0.1
0.01
0.001
1k
05007-019
OUTPUT (VOx)
Given the geometry of the receiving coil in the ADuM2400/
ADuM2401/ADuM2402 and an imposed requirement that the
induced voltage be at most 50% of the 0.5 V margin at the
decoder, a maximum allowable magnetic field is calculated as
shown in Figure 19.
100
tPHL
05007-018
tPLH
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
INPUT (VIx)
The limitation on the ADuM2400/ADuM2401/ADuM2402
magnetic field immunity is set by the condition in which induced
voltage in the transformer’s receiving coil is large enough to
either falsely set or reset the decoder. The following analysis
defines the conditions under which this can occur. The 3 V
operating condition of the ADuM2400/ADuM2401/ADuM2402 is
examined because it represents the most susceptible mode of
operation.
1M
10k
10M
100k
MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 19. Maximum Allowable External Magnetic Flux Density
Data Sheet
ADuM2400/ADuM2401/ADuM2402
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM2400/ADuM2401/ADuM2402 transformers. Figure 20
expresses these allowable current magnitudes as a function of
frequency for selected distances. As can be seen, the
ADuM2400/ADuM2401/ADuM2402 is immune and can be
affected only by extremely large currents operated at high
frequency and very close to the component. For the 1 MHz
example noted, place a 0.5 kA current 5 mm away from the
ADuM2400/ADuM2401/ADuM2402 to affect the component’s
operation.
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
05007-020
MAXIMUM ALLOWABLE CURRENT (kA)
1000
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 20. Maximum Allowable Current for Various Current-toADuM2400/ADuM2401/ADuM2402 Spacings
POWER CONSUMPTION
The supply current at a given channel of the ADuM2400/
ADuM2401/ADuM2402 isolator is a function of the supply
voltage, the data rate of the channel, and the output load of the
channel.
For each input channel, the supply current is given by:
IDDI = IDDI (Q)
f ≤ 0.5fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q)
f > 0.5fr
For each output channel, the supply current is given by:
IDDO = IDDO (Q)
f ≤ 0.5fr
-3
IDDO = (IDDO (D) + (0.5 × 10 × CLVDDO) × (2f − fr) + IDDO (Q)
f > 0.5fr
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total IDD1 and IDD2, the supply currents for each
input and output channel corresponding to IDD1 and IDD2 are
calculated and totaled. Figure 8 and Figure 9 provide per channel
supply currents as a function of data rate for an unloaded output
condition. Figure 10 provides per channel supply current as a
function of data rate for a 15 pF output condition. Figure 11
through Figure 15 provide the total IDD1 and IDD2 as a function of
data rate for the ADuM2400/ADuM2401/ADuM2402 channel
configurations.
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce sufficiently large error voltages to trigger the
thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
Rev. F | Page 19 of 24
ADuM2400/ADuM2401/ADuM2402
Data Sheet
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM2400/
ADuM2401/ADuM2402.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. The values shown in Table 10
summarize the peak voltage for 50 years of service life for a
bipolar ac operating condition and the maximum CSA/VDE
approved working voltages. In many cases, the approved
working voltage is higher than the 50-year service life voltage.
Operation at these high working voltages can lead to shortened
insulation life in some cases.
In the case of unipolar ac or dc voltage, the stress on the
insulation is significantly lower. This allows operation at higher
working voltages while still achieving a 50-year service life.
The working voltages listed in Table 10 can be applied while
maintaining the 50-year minimum lifetime, provided the voltage
conforms to either the unipolar ac or dc voltage cases. Any
cross-insulation voltage waveform that does not conform to
Figure 22 or Figure 23 should be treated as a bipolar ac waveform
and its peak voltage should be limited to the 50-year lifetime
voltage value listed in Table 10.
Note that the voltage presented in Figure 22 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
RATED PEAK VOLTAGE
05007-021
INSULATION LIFETIME
0V
Figure 21. Bipolar AC Waveform
RATED PEAK VOLTAGE
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines Analog Devices recommended maximum working
voltage.
RATED PEAK VOLTAGE
Rev. F | Page 20 of 24
05007-022
The insulation lifetime of the ADuM2400/ADuM2401/
ADuM2402 depends on the voltage waveform type imposed
across the isolation barrier. The iCoupler insulation structure
degrades at different rates, depending on whether the waveform
is bipolar ac, unipolar ac, or dc. Figure 21, Figure 22, and Figure 23
illustrate these different isolation voltage waveforms.
0V
05007-023
Figure 22. Unipolar AC Waveform
0V
Figure 23. DC Waveform
Data Sheet
ADuM2400/ADuM2401/ADuM2402
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
1
8
1.27 (0.0500)
BSC
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
03-27-2007-B
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
12.85
12.75
12.65
1.93 REF
16
9
PIN 1
MARK
1
8
2.64
2.54
2.44
2.44
2.24
0.30
0.20
0.10
COPLANARITY
0.1
10.51
10.31
10.11
1.27 BSC
0.46
0.36
0.71
0.50
0.31
0.25 BSC
GAGE
PLANE
SEATING
PLANE
45°
1.01
0.76
0.51
COMPLIANT TO JEDEC STANDARDS MS-013-AC
Figure 25. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-16-2)
Dimensions shown in millimeters
Rev. F | Page 21 of 24
0.32
0.23
8°
0°
11-15-2011-A
7.60
7.50
7.40
ADuM2400/ADuM2401/ADuM2402
Data Sheet
ORDERING GUIDE
Model1, 2
ADuM2400ARWZ
ADuM2400BRWZ
ADuM2400CRWZ
ADuM2400ARIZ
ADuM2400BRIZ
ADuM2400CRIZ
ADuM2401ARWZ
ADuM2401BRWZ
ADuM2401CRWZ
ADuM2401ARIZ
ADuM2401BRIZ
ADuM2401CRIZ
ADuM2402ARWZ
ADuM2402BRWZ
ADuM2402CRWZ
ADuM2402ARIZ
ADuM2402BRIZ
ADuM2402CRIZ
1
2
Number
of Inputs,
VDD1 Side
4
4
4
4
4
4
3
3
3
3
3
3
2
2
2
2
2
2
Number
of Inputs,
VDD2 Side
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
2
2
2
Maximum
Data Rate
(Mbps)
1
10
90
1
10
90
1
10
90
1
10
90
1
10
90
1
10
90
Maximum
Propagation
Delay, 5 V (ns)
100
50
32
100
50
32
100
50
32
100
50
32
100
50
32
100
50
32
Maximum
Pulse Width
Distortion (ns)
40
3
2
40
3
2
40
3
2
40
3
2
40
3
2
40
3
2
Tape and reel is available. The addition of an -RL suffix designates a 13” (1,000 units) tape and reel option.
Z = RoHS Compliant Part.
Rev. F | Page 22 of 24
Temperature
Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_IC
16-Lead SOIC_IC
16-Lead SOIC_IC
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_IC
16-Lead SOIC_IC
16-Lead SOIC_IC
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_IC
16-Lead SOIC_IC
16-Lead SOIC_IC
Package
Option
RW-16
RW-16
RW-16
RI-16-2
RI-16-2
RI-16-2
RW-16
RW-16
RW-16
RI-16-2
RI-16-2
RI-16-2
RW-16
RW-16
RW-16
RI-16-2
RI-16-2
RI-16-2
Data Sheet
ADuM2400/ADuM2401/ADuM2402
NOTES
Rev. F | Page 23 of 24
ADuM2400/ADuM2401/ADuM2402
Data Sheet
NOTES
©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05007-0-7/15(F)
Rev. F | Page 24 of 24