Dual-Channel Digital Isolator ADuM1210 FEATURES GENERAL DESCRIPTION Narrow body, RoHS-compliant, 8-lead SOIC Low power operation 5 V operation 1.1 mA per channel maximum @ 0 Mbps to 2 Mbps 3.7 mA per channel maximum @ 10 Mbps 3 V operation 0.8 mA per channel maximum @ 0 Mbps to 2 Mbps 2.2 mA per channel maximum @ 10 Mbps 3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 10 Mbps (NRZ) Precise timing characteristics 3 ns maximum pulse width distortion 3 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Safety and regulatory approvals UL recognition 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 560 V peak The ADuM1210 1 is a dual-channel, digital isolator based on Analog Devices, Inc. iCoupler® technology. Combining high speed CMOS and monolithic transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives such as optocoupler devices. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The concerns of the typical optocoupler regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuM1210 isolator provides two independent isolation channels operable with the supply voltage on either side, ranging from 2.7 V to 5.5 V. This provides compatibility with lower voltage systems and enables voltage translation functionality across the isolation barrier. In addition, the ADuM1210 provides low pulse width distortion (<3 ns) and tight channel-to-channel matching (<3 ns). Unlike other optocoupler alternatives, the ADuM1210 isolator has a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. Furthermore, as an alternative to the ADuM1200 dual-channel digital isolator that defaults to an output high condition, the ADuM1210 outputs default to a logic low state when input power is off. APPLICATIONS Size-critical multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceiver isolation Digital field bus isolation Gate drive interface 1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329. Other patents pending. VDD1 1 8 VDD2 VIA 2 ENCODE DECODE 7 VOA VIB 3 ENCODE DECODE 6 VOB 5 GND2 GND1 4 05459-001 FUNCTIONAL BLOCK DIAGRAM Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved. ADuM1210 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ......................................................... 11 Applications....................................................................................... 1 ESD Caution................................................................................ 11 General Description ......................................................................... 1 Pin Configuration and Function Descriptions........................... 12 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 13 Revision History ............................................................................... 2 Applications Information .............................................................. 14 Specifications..................................................................................... 3 PC Board Layout ........................................................................ 14 Electrical Characteristics—5 V Operation................................ 3 Propagation Delay-Related Parameters................................... 14 Electrical Characteristics—3 V Operation................................ 5 DC Correctness and Magnetic Field Immunity........................... 14 Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V Operation....................................................................................... 7 Power Consumption .................................................................. 15 Package Characteristics ............................................................... 9 Outline Dimensions ....................................................................... 17 Regulatory Information............................................................... 9 Ordering Guide .......................................................................... 17 Insulation Lifetime ..................................................................... 15 Insulation and Safety-Related Specifications............................ 9 DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Insulation Characteristics.......................................................... 10 Recommended Operating Conditions .................................... 10 REVISION HISTORY 6/07—Rev. B to Rev. C Updated VDE Certification Throughout ...................................... 1 Changes to Features, Applications, and Note 1 ............................ 1 Changes to DC Specifications in Table 1....................................... 3 Changes to DC Specifications in Table 2....................................... 5 Changes to DC Specifications in Table 3....................................... 7 Added Endnote 2 to Table 4 ............................................................ 9 Changes to Regulatory Information Section ................................ 9 Changes to Table 7.......................................................................... 10 Added Table 10 ............................................................................... 11 Added Insulation Lifetime Section .............................................. 15 3/07—Rev. A to Rev. B Changes to Table 1............................................................................ 3 2/06—Rev. 0 to Rev. A Updated Format..................................................................Universal Added Note 1 .................................................................................... 1 Changes to Absolute Maximum Ratings ..................................... 11 Changes to DC Correctness and Magnetic Field Immunity Section ........................................................................... 14 7/05—Revision 0: Initial Version Rev. C | Page 2 of 20 ADuM1210 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. All voltages are relative to their respective ground. Table 1. Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent Output Supply Current, per Channel, Quiescent Total Supply Current, Two Channels 1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps VDD1 Supply Current VDD2 Supply Current Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew 5 Channel-to-Channel Matching, Codirectional Channels 6 Channel-to-Channel Matching, Opposing-Directional Channels6 Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Dynamic Supply Current, per Channel 8 Output Dynamic Supply Current, per Channel8 Symbol Min Typ Max Unit IDDI (Q) 0.50 0.60 mA IDDO (Q) 0.19 0.25 mA IDD1 (Q) IDD2 (Q) 1.1 0.5 1.4 0.8 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency IDD1 (10) IDD2 (10) IIA, IIB VIH VIL VOAH, VOBH 4.3 1.3 +0.01 5.5 2.0 +10 mA mA μA V V V V V V V 5 MHz logic signal frequency 5 MHz logic signal frequency 0 V ≤ VIA, VIB ≤ VDD1 CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels −10 0.7 × VDD1 0.3 × VDD1 VDD2 − 0.1 VDD2 − 0.5 VOAL, VOBL 5.0 4.8 0.0 0.04 0.2 PW 0.1 0.1 0.4 IOx = −20 μA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 400 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL tPSK tPSKCD 15 3 ns Mbps ns ns ps/°C ns ns tPSKOD 15 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V tPHL, tPLH PWD 100 Test Conditions 10 20 50 3 5 tR/tF |CMH| 25 2.5 35 ns kV/μs |CML| 25 35 kV/μs fr IDDI (D) 1.2 0.19 Mbps mA/Mbps IDDO (D) 0.05 mA/Mbps 1 Supply current values are for both channels running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 through Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. Rev. C | Page 3 of 20 ADuM1210 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate. Rev. C | Page 4 of 20 ADuM1210 ELECTRICAL CHARACTERISTICS—3 V OPERATION 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. All voltages are relative to their respective ground. Table 2. Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent Output Supply Current, per Channel, Quiescent Total Supply Current, Two Channels 1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps VDD1 Supply Current VDD2 Supply Current Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew 5 Channel-to-Channel Matching, Codirectional Channels 6 Channel-to-Channel Matching, Opposing-Directional Channels6 Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Dynamic Supply Current, per Channel 8 Output Dynamic Supply Current, per Channel8 Symbol Min Typ Max Unit IDDI (Q) 0.26 0.35 mA IDDO (Q) 0.11 0.20 mA IDD1 (Q) IDD2 (Q) 0.6 0.2 1.0 0.6 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency IDD1 (10) IDD2 (10) IIA, IIB VIH VIL VOAH, VOBH 2.2 0.7 +0.01 3.4 1.1 +10 mA mA μA V V V V V V V 5 MHz logic signal frequency 5 MHz logic signal frequency 0 V ≤ VIA, VIB, ≤ VDD1 CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels −10 0.7 × VDD1 0.3 × VDD1 VDD2 − 0.1 VDD2 − 0.5 VOAL, VOBL 3.0 2.8 0.0 0.04 0.2 PW 0.1 0.1 0.4 IOx = −20 μA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 400 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL tPSK tPSKCD 22 3 ns Mbps ns ns ps/°C ns ns tPSKOD 22 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V tPHL, tPLH PWD 100 Test Conditions 10 20 60 3 5 tR/tF |CMH| 25 3.0 35 ns kV/μs |CML| 25 35 kV/μs fr IDDI (D) 1.1 0.10 Mbps mA/Mbps IDDO (D) 0.03 mA/Mbps 1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. Rev. C | Page 5 of 20 ADuM1210 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate. Rev. C | Page 6 of 20 ADuM1210 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V; or VDD1 = 5.0 V, VDD2 = 3.0 V. All voltages are relative to their respective ground. Table 3. Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation Output Supply Current, per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation Total Supply Current, Two Channels 1 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew 5 Channel-to-Channel Matching, Codirectional Channels 6 Channel-to-Channel Matching, Opposing-Directional Channels6 Output Rise/Fall Time (10% to 90%) 5 V/3 V Operation 3 V/5 V Operation Symbol Min Typ Max Unit Test Conditions mA IDDI (Q) 0.50 0.26 0.6 0.35 mA mA mA 0.11 0.19 0.20 0.25 mA mA 1.1 0.6 1.4 1.0 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 0.2 0.5 0.6 0.8 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 4.3 2.2 5.5 3.4 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency 0.7 1.3 +0.01 1.1 2.0 +10 mA mA μA V V V V V V V 5 MHz logic signal frequency 5 MHz logic signal frequency 0 V ≤ VIA, VIB ≤ VDD1 CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels IDDO (Q) IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10) IIA, IIB VIH VIL VOAH, VOBH −10 0.7 × VDD1 0.3 × VDD1 VDD2 − 0.1 VDD2 − 0.5 VOAL, VOBL VDD2 VDD2 − 0.2 0.0 0.04 0.2 PW 0.1 0.1 0.4 tPSK tPSKCD 22 3 ns Mbps ns ns ps/°C ns ns tPSKOD 22 ns tPHL, tPLH PWD 100 10 15 55 3 5 tR/tF IOx = −20 μA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 400 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL CL = 15 pF, CMOS signal levels 3.0 2.5 Rev. C | Page 7 of 20 ns ns ADuM1210 Parameter Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate 5 V/3 V Operation 3 V/5 V Operation Input Dynamic Supply Current, per Channel 8 5 V/3 V Operation 3 V/5 V Operation Output Dynamic Supply Current, per Channel8 5 V/3 V Operation 3 V/5 V Operation Symbol |CMH| Min 25 Typ 35 Max Unit kV/μs |CML| 25 35 kV/μs 1.2 1.1 Mbps Mbps 0.19 0.10 mA/Mbps mA/Mbps 0.03 0.05 mA/Mbps mA/Mbps Test Conditions VIx = VDD1, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V fr IDDI (D) IDDO (D) 1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate. Rev. C | Page 8 of 20 ADuM1210 PACKAGE CHARACTERISTICS Table 4. Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance 2 IC Junction-to-Case Thermal Resistance Side 1 Side 2 1 2 Symbol RI-O CI-O CI Min θJCI θJCO Typ 1012 1.0 4.0 Max 46 41 Unit Ω pF pF Test Conditions °C/W °C/W Thermocouple located at center of package underside f = 1 MHz The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM1210 is approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 5. UL Recognized Under 1577 Component Recognition Program 1 Single/Basic 2500 V rms Isolation Voltage File E214100 1 2 CSA Approved under CSA Component Acceptance Notice #5A VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 2 Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 peak) maximum working voltage Functional insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage File 205078 Reinforced insulation, 560 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM1210 is proof-tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA). In accordance with DIN V VDE V 0884-10, each ADuM1210 is proof-tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 2500 4.90 min Unit V rms mm Minimum External Tracking (Creepage) L(I02) 4.01 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >175 IIIa mm V Rev. C | Page 9 of 20 Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) ADuM1210 DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS This isolator is suitable for reinforced isolation within the safety limit data only. Maintenance of the safety data is ensured by protective circuits. Note that the asterisk (*) marked on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage. Table 7. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS Conditions VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC Characteristic Unit VIORM VPR I to IV I to III I to II 40/105/21 2 560 1050 V peak V peak 896 672 V peak V peak VTR 4000 V peak TS IS1 IS2 RS 150 160 170 >109 °C mA mA Ω VPR VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 seconds Maximum value allowed in the event of a failure; see Figure 2 VIO = 500 V RECOMMENDED OPERATING CONDITIONS 200 180 SAFETY-LIMITING CURRENT (mA) Symbol Table 8. 160 Parameter Operating Temperature Supply Voltages 1 Input Signal Rise and Fall Times 140 SIDE #2 SIDE #1 120 100 80 1 60 50 100 150 CASE TEMPERATURE (°C) 200 05459-002 20 0 Min −40 2.7 Max +105 5.5 1.0 Unit °C V ms All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. 40 0 Symbol TA VDD1, VDD2 Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN V VDE V 0884-10 Rev. C | Page 10 of 20 ADuM1210 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 9. Parameter Storage Temperature (TST) Range Ambient Operating Temperature (TA) Range Supply Voltages (VDD1, VDD2)1 Input Voltage (VIA, VIB)1 Output Voltage (VOA, VOB)1 Average Output Current, Per Pin (IO)2 Common-Mode Transients (CML, CMH)3 Rating −55°C to +150°C −40°C to +105°C −0.5 V to +7.0 V −0.5 V to VDDI +0.5 V −0.5 V to VDDO +0.5 V −35 mA to +35 mA −100 kV/μs to +100 kV/μs rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1 All voltages are relative to their respective ground. See Figure 2 for maximum rated current values for various temperatures. 3 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum rating may cause latch-up or permanent damage. 2 Table 10. Maximum Continuous Working Voltage 1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Functional Insulation Basic Insulation DC Voltage Functional Insulation Basic Insulation 1 Max 565 Unit V peak Constraint 50-year minimum lifetime 1131 560 V peak V peak Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 1131 560 V peak V peak Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Rev. C | Page 11 of 20 ADuM1210 VDD1 1 VIA 2 VIB 3 GND1 4 ADuM1210 TOP VIEW (Not to Scale) 8 VDD2 7 VOA 6 VOB 5 GND2 05459-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 11. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD1 VIA VIB GND1 GND2 VOB VOA VDD2 Description Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Logic Input A. Logic Input B. Ground 1. Ground reference for Isolator Side 1. Ground 2. Ground reference for Isolator Side 2. Logic Output B. Logic Output A. Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V. Table 12. ADuM1210 Truth Table (Positive Logic) VIA Input H L H L X VIB Input H L L H X VDD1 State Powered Powered Powered Powered Unpowered VDD2 State Powered Powered Powered Powered Powered VOA Output H L H L L VOB Output H L L H L X X Powered Unpowered Indeterminate Indeterminate Rev. C | Page 12 of 20 Description Outputs return to the input state within 1 μs of VDDI power restoration. Outputs return to the input state within 1 μs of VDDO power restoration. ADuM1210 TYPICAL PERFORMANCE CHARACTERISTICS 10 20 15 CURRENT (mA) CURRENT/CHANNEL (mA) 8 6 4 5V 3V 10 5V 5 2 0 10 20 DATA RATE (Mbps) 30 Figure 4. Typical Input Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation 0 4 3 3 CURRENT (mA) 4 2 5V 1 30 2 5V 3V 1 0 10 20 DATA RATE (Mbps) 30 0 Figure 5. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load) 0 3 5V 2 0 10 20 DATA RATE (Mbps) 30 05459-006 3V 0 30 Figure 8. Typical VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation 4 1 10 20 DATA RATE (Mbps) 05459-008 3V 0 CURRENT/CHANNEL (mA) 10 20 DATA RATE (Mbps) Figure 7. Typical VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation 05459-005 CURRENT/CHANNEL (mA) 0 05459-004 0 05459-007 3V Figure 6. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load) Rev. C | Page 13 of 20 ADuM1210 APPLICATIONS INFORMATION PC BOARD LAYOUT The ADuM1210 digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. PROPAGATION DELAY-RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to a logic high output. 50% Given the geometry of the receiving coil in the ADuM1210 and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 10. 100 50% Figure 9. Propagation Delay Parameters Pulse width distortion is the maximum difference between the two propagation delay values and is an indication of how accurately the input signal’s timing is preserved. Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM1210 component. Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM120x components operating under the same conditions. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) OUTPUT (VOx) where: β is the magnetic flux density (gauss). rn is the radius of the nth turn in the receiving coil (cm). N is the number of turns in the receiving coil. tPHL 05459-009 tPLH V = (−dβ / dt) ∑ π rn2; n = 1, 2, … , N 10 1 0.1 0.01 0.001 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 05459-010 INPUT (VIx) The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Figure 10. Maximum Allowable External Magnetic Flux Density Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions of more than ~1 μs at the input, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 12) by the watchdog timer circuit. For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurred during a transmitted pulse (and had the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. The ADuM1210 is extremely immune to external magnetic fields. The limitation on the ADuM1210 magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM1210 is examined because it represents the most susceptible mode of operation. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM1210 transformers. Figure 11 expresses these allowable current magnitudes as a function of frequency for selected distances. As seen in Figure 11, the ADuM1210 is extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example, a 0.5 kA current would have to be placed 5 mm away from the ADuM1210 to affect the component’s operation. Rev. C | Page 14 of 20 ADuM1210 To calculate the total IDD1 and IDD2 supply current, the supply currents for each input and output channel corresponding to IDD1 and IDD2 are calculated and totaled. Figure 4 and Figure 5 show per-channel supply currents as a function of data rate for an unloaded output condition. Figure 6 shows per-channel supply current as a function of data rate for a 15 pF output condition. Figure 7 and Figure 8 show total VDD1 and VDD2 supply current as a function of data rate. DISTANCE = 1m 100 10 DISTANCE = 100mm 1 DISTANCE = 5mm INSULATION LIFETIME 0.1 0.01 1k 10k 100k 1M 10M 100M MAGNETIC FIELD FREQUENCY (Hz) 05459-011 MAXIMUM ALLOWABLE CURRENT (kA) 1000 Figure 11. Maximum Allowable Current for Various Current-to-ADuM1210 Spacings Note that, at combinations of strong magnetic fields and high frequencies, any loops formed by printed circuit board traces can induce sufficiently large error voltages to trigger the threshold of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. POWER CONSUMPTION The supply current at a given channel of the ADuM1210 isolator is a function of the supply voltage, the channel data rate, and the channel output load. For each input channel, the supply current is given by IDDI = IDDI (Q) f ≤ 0.5fr IDDI = IDDI (D) × (2f – fr) + IDDI (Q) f > 0.5fr for each output channel, the supply current is given by IDDO = IDDO (Q) f ≤ 0.5fr −3 IDDO = (IDDO (D) + (0.5 × 10 ) × CLVDDO) × (2f – fr) + IDDO (Q) f > 0.5fr where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz, half the input data rate, NRZ signaling). fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA). All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM1210. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM1210 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 12, Figure 13, and Figure 14 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage. Rev. C | Page 15 of 20 ADuM1210 Note that the voltage presented in Figure 13 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. 05459-014 RATED PEAK VOLTAGE 0V Figure 12. Bipolar AC Waveform 05459-012 RATED PEAK VOLTAGE 0V Figure 13. Unipolar AC Waveform RATED PEAK VOLTAGE 05459-013 In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 10 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage case. Any crossinsulation voltage waveform that does not conform to Figure 13 or Figure 14 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 10. 0V Figure 14. DC Waveform Rev. C | Page 16 of 20 ADuM1210 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 15. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Number of Inputs, VDD1 Side Number of Inputs, VDD2 Side Maximum Data Rate Maximum Propagation Delay, 5 V Maximum Pulse Width Distortion ADuM1210BRZ 1 ADuM1210BRZ-RL71 2 2 0 0 10 Mbps 10 Mbps 50 ns 50 ns 3 ns 3 ns 1 Z = RoHS Compliant Part. Rev. C | Page 17 of 20 Temperature Range −40°C to +105°C −40°C to +105°C Package Description Package Option 8-Lead SOIC_N 8-Lead SOIC_N R-8 R-8 ADuM1210 NOTES Rev. C | Page 18 of 20 ADuM1210 NOTES Rev. C | Page 19 of 20 ADuM1210 NOTES ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05459-0-6/07(C) Rev. C | Page 20 of 20