APPLICATIONS High speed multichannel isolation SPI interface/data converter isolation Instrumentation FUNCTIONAL BLOCK DIAGRAMS ADuM3440 VDD1 1 GND1 2 16 VDD2 15 GND2 VIA 3 ENCODE DECODE 14 VOA VIB 4 ENCODE DECODE 13 VOB VIC 5 ENCODE DECODE 12 VOC VID 6 ENCODE DECODE 11 VOD NC 7 10 VE2 GND1 8 9 GND2 06837-001 Low power operation 5 V operation 1.7 mA per channel maximum @ 0 Mbps to 2 Mbps 68 mA per channel maximum @ 150 Mbps 3.3 V operation 1.0 mA per channel maximum @ 0 Mbps to 2 Mbps 33 mA per channel maximum @ 150 Mbps Bidirectional communication 3.3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 150 Mbps (NRZ) Precise timing characteristics 5 ns maximum pulse width distortion 5 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function 16-lead SOIC wide body package Safety and regulatory approvals UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak Figure 1. ADuM3440 Functional Block Diagram ADuM3441 VDD1 1 GND1 2 16 VDD2 15 GND2 VIA 3 ENCODE DECODE 14 VOA VIB 4 ENCODE DECODE 13 VOB VIC 5 ENCODE DECODE 12 VOC VOD 6 DECODE ENCODE 11 VID VE1 7 10 VE2 GND1 8 9 GND2 06837-002 FEATURES Figure 2. ADuM3441 Functional Block Diagram ADuM3442 VDD1 1 GND1 2 16 VDD2 15 GND2 VIA 3 ENCODE DECODE 14 VOA VIB 4 ENCODE DECODE 13 VOB VOC 5 DECODE ENCODE 12 VIC VOD 6 DECODE ENCODE 11 VID VE1 7 10 VE2 GND1 8 9 GND2 06837-003 Data Sheet Quad Channel, High Speed Digital Isolators ADuM3440/ADuM3441/ADuM3442 Figure 3. ADuM3442 Functional Block Diagram GENERAL DESCRIPTION The ADuM344x1 are four channel, digital isolators based on the Analog Devices, Inc., iCoupler® technology supporting data rates up to 150 Mbps. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. 1 Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuM344x isolators provide four independent isolation channels in a variety of channel configurations (see the Ordering Guide). The ADuM344x operates with the supply voltage on either side ranging from 3.0 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. In addition, the ADuM344x provides low pulse width distortion and tight channel-to-channel matching. Unlike other optocoupler alternatives, the ADuM344x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during the power-up/power-down condition. Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved. ADuM3440/ADuM3441/ADuM3442 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ......................................................... 12 Applications ....................................................................................... 1 ESD Caution................................................................................ 12 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ......................... 13 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 16 Revision History ............................................................................... 2 Applications Information .............................................................. 18 Specifications..................................................................................... 3 PC Board Layout ........................................................................ 18 Electrical Characteristics—5 V Operation................................ 3 Propagation Delay-Related Parameters................................... 18 Electrical Characteristics—3.3 V Operation ............................ 5 System-Level ESD Considerations and Enhancements ........ 18 Electrical Characteristics—Mixed 5 V/3.3 V or 3.3 V/5 V Operation....................................................................................... 7 DC Correctness and Magnetic Field Immunity........................... 18 Package Characteristics ............................................................. 10 Insulation Lifetime ..................................................................... 20 Regulatory Information ............................................................. 10 Outline Dimensions ....................................................................... 21 Insulation and Safety-Related Specifications .......................... 10 Ordering Guide .......................................................................... 21 Power Consumption .................................................................. 19 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ............................................................................ 11 Recommended Operating Conditions .................................... 11 REVISION HISTORY 2/12—Rev. C to Rev. D Created Hyperlink for Safety and Regulatory Approvals Entry in Features Section................................................................. 1 Change to PC Board Layout Section ............................................ 18 Updated Outline Dimensions ....................................................... 21 1/09—Rev. B to Rev. C Change to Propagation Delay Parameter (Table 1) ...................... 3 Change to Propagation Delay Parameter (Table 2) ...................... 5 Change to Propagation Delay Parameter (Table 3) ...................... 8 9/08—Rev. A to Rev. B Changes to Pulse Width Distortion, |tPLH − tPHL| Parameter and Channel-to-Channel Matching, Codirectional Channels Parameter, Table 1 .............................................................................3 Changes to Pulse Width Distortion, |tPLH − tPHL| Parameter and Channel-to-Channel Matching, Codirectional Channels Parameter, Table 2 .............................................................................5 Changes to Pulse Width Distortion, |tPLH − tPHL| Parameter and Channel-to-Channel Matching, Codirectional Channels Parameter, Table 3 .............................................................................8 5/08—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 21 11/07—Rev. 0: Initial Version Rev. D | Page 2 of 24 Data Sheet ADuM3440/ADuM3441/ADuM3442 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Table 1. Parameter DC SPECIFICATIONS Input Supply Current per Channel, Quiescent Output Supply Current per Channel, Quiescent ADuM3440, Total Supply Current, Four Channels 1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 150 Mbps VDD1 Supply Current VDD2 Supply Current ADuM3441, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 150 Mbps VDD1 Supply Current VDD2 Supply Current ADuM3442, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 or VDD2 Supply Current 150 Mbps VDD1 or VDD2 Supply Current For All Models Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH − tPHL| 5 Change vs. Temperature Propagation Delay Skew 6 Channel-to-Channel Matching, Codirectional Channels5 Channel-to-Channel Matching, Opposing Directional Channels5 Symbol Min Typ Max Unit IDDI (Q) IDDO (Q) 0.75 0.5 1.3 1.2 mA mA IDD1 (Q) IDD2 (Q) 3 2 3.9 3 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency IDD1 (150) IDD2 (150) 120 47 220 55 mA mA 75 MHz logic signal frequency 75 MHz logic signal frequency IDD1 (Q) IDD2 (Q) 2.8 2.3 3.6 2.9 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency IDD1 (150) IDD2 (150) 101 65 165 80 mA mA 75 MHz logic signal frequency 75 MHz logic signal frequency IDD1 (Q), IDD2 (Q) 2.5 3.5 mA DC to 1 MHz logic signal frequency IDD1 (150), IDD2 (150) 83 130 mA 75 MHz logic signal frequency +0.01 +10 µA 0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 ≤ VE1, VE2 ≤ VDD1 or VDD2 0.8 5.0 V V V IOx = −20 µA, VIx = VIxH 4.8 V IOx = −4 mA, VIx = VIxH IIA, IIB, IIC, IID, IE1, IE2 VIH, VEH VIL, VEL VOAH, VOBH, VOCH, VODH −10 2.0 (VDD1 or VDD2) − 0.1 (VDD1 or VDD2) − 0.4 VOAL, VOBL, VOCL, VODL 0.0 0.1 V IOx = 20 µA, VIx = VIxL 0.04 0.2 0.1 0.4 V V IOx = 400 µA, VIx = VIxL IOx = 4 mA, VIx = VIxL 6.67 CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels PW tPSK tPSKCD 12 2 ns Mbps ns ns ps/°C ns ns tPSKOD 5 ns tPHL, tPLH PWD 150 20 0.5 3 Rev. D | Page 3 of 24 Test Conditions 32 2 ADuM3440/ADuM3441/ADuM3442 Parameter For All Models Output Disable Propagation Delay (High/Low to High Impedance) Output Enable Propagation Delay (High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Dynamic Supply Current per Channel 8 Output Dynamic Supply Current per Channel8 Symbol Data Sheet Min Typ Max Unit Test Conditions tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V tR/tF |CMH| 25 2.5 35 ns kV/µs |CML| 25 35 kV/µs 1.2 0.196 0.1 Mbps mA/Mbps mA/Mbps fr IDDI (D) IDDO (D) 1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3440/ADuM3441/ADuM3442 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDO. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. D | Page 4 of 24 Data Sheet ADuM3440/ADuM3441/ADuM3442 ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Table 2. Parameter DC SPECIFICATIONS Input Supply Current per Channel, Quiescent Output Supply Current per Channel, Quiescent ADuM3440, Total Supply Current, Four Channels 1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 150 Mbps VDD1 Supply Current VDD2 Supply Current ADuM3441, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 150 Mbps VDD1 Supply Current VDD2 Supply Current ADuM3442, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 or VDD2 Supply Current 150 Mbps VDD1 or VDD2 Supply Current For All Models Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Symbol Typ Max Unit IDDI (Q) IDDO (Q) 0.43 0.3 0.90 0.60 mA mA IDD1 (Q) IDD2 (Q) 1.7 1.2 2.4 1.7 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency IDD1 (150) IDD2 (150) 63 17 110 25 mA mA 75 MHz logic signal frequency 75 MHz logic signal frequency IDD1 (Q) IDD2 (Q) 1.6 1.3 2.2 1.9 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency IDD1 (150) IDD2 (150) 52 29 80 40 mA mA 75 MHz logic signal frequency 75 MHz logic signal frequency IDD1 (Q), IDD2 (Q) 1.5 2.0 mA DC to 1 MHz logic signal frequency IDD1 (150), IDD2 (150) 40 66 mA 75 MHz logic signal frequency +0.01 +10 µA 0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 ≤ VE1, VE2 ≤ VDD1 or VDD2 0.4 V V V IOx = −20 µA, VIx = VIxH V IOx = −4 mA, VIx = VIxH 0.1 V IOx = 20 µA, VIx = VIxL 0.1 0.4 V V IOx = 400 µA, VIx = VIxL IOx = 4 mA, VIx = VIxL 6.67 CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels IIA, IIB, IIC, IID, IE1, IE2 VIH, VEH VIL, VEL VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL Min −10 1.6 (VDD1 or 3.0 VDD2) − 0.1 2.8 (VDD1 or VDD2) − 0.4 0.0 0.04 0.2 SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew 5 Channel-to-Channel Matching, Codirectional Channels 6 Channel-to-Channel Matching, Opposing Directional Channels5 PW tPSK tPSKCD 16 2 ns Mbps ns ns ps/°C ns ns tPSKOD 5 ns tPHL, tPLH PWD 150 20 0.5 3 Rev. D | Page 5 of 24 36 2 Test Conditions ADuM3440/ADuM3441/ADuM3442 Parameter For All Models Output Disable Propagation Delay (High/Low to High Impedance) Output Enable Propagation Delay (High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Dynamic Supply Current per Channel 8 Output Dynamic Supply Current per Channel8 Symbol Data Sheet Min Typ Max Unit Test Conditions tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V tR/tF |CMH| 25 3 35 ns kV/µs |CML| 25 35 kV/µs 1.1 0.076 0.028 Mbps mA/Mbps mA/Mbps fr IDDI (D) IDDO (D) 1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3440/ADuM3441/ADuM3442 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDO. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. D | Page 6 of 24 Data Sheet ADuM3440/ADuM3441/ADuM3442 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OR 3.3 V/5 V OPERATION All voltages are relative to their respective ground. 5 V/3.3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C; VDD1 = 3.3 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.3 V. Table 3. Parameter DC SPECIFICATIONS Input Supply Current per Channel, Quiescent 5 V/3.3 V Operation 3.3 V/5 V Operation Output Supply Current per Channel, Quiescent 5 V/3.3 V Operation 3.3 V/5 V Operation ADuM3440, Total Supply Current, Four Channels 1 DC to 2 Mbps VDD1 Supply Current 5 V/3.3 V Operation 3.3 V/5 V Operation VDD2 Supply Current 5 V/3.3 V Operation 3.3 V/5 V Operation 150 Mbps VDD1 Supply Current 5 V/3.3 V Operation 3.3 V/5 V Operation VDD2 Supply Current 5 V/3.3 V Operation 3.3 V/5 V Operation ADuM3441, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current 5 V/3.3 V Operation 3.3 V/5 V Operation VDD2 Supply Current 5 V/3.3 V Operation 3.3 V/5 V Operation 150 Mbps VDD1 Supply Current 5 V/3.3 V Operation 3.3 V/5 V Operation VDD2 Supply Current 5 V/3.3 V Operation 3.3 V/5 V Operation ADuM3442, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current 5 V/3.3 V Operation 3.3 V/5 V Operation VDD2 Supply Current 5 V/3.3 V Operation 3.3 V/5 V Operation Symbol Min Typ Max Unit Test Conditions 0.75 0.43 1.3 0.9 mA mA 0.3 0.5 0.7 1.2 mA mA 3 1.7 3.9 2.4 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 1.2 2 1.7 3 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 120 63 220 110 mA mA 75 MHz logic signal frequency 75 MHz logic signal frequency 17 47 25 55 mA mA 75 MHz logic signal frequency 75 MHz logic signal frequency 2.8 1.6 3.6 2.2 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 1.3 2.3 1.9 2.9 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 101 52 165 80 mA mA 75 MHz logic signal frequency 75 MHz logic signal frequency 29 65 40 80 mA mA 75 MHz logic signal frequency 75 MHz logic signal frequency 2.5 1.5 3.5 2.0 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 1.5 2.5 2.0 3.5 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency IDDI (Q) IDDO (Q) IDD1 (Q) IDD2 (Q) IDD1 (150) IDD2 (150) IDD1 (Q) IDD2 (Q) IDD1 (150) IDD2 (150) IDD1 (Q) IDD2 (Q) Rev. D | Page 7 of 24 ADuM3440/ADuM3441/ADuM3442 Parameter 150 Mbps VDD1 Supply Current 5 V/3.3 V Operation 3.3 V/5 V Operation VDD2 Supply Current 5 V/3.3 V Operation 3.3 V/5 V Operation For All Models Input Currents Logic High Input Threshold 5 V/3.3 V Operation 3.3 V/5 V Operation Logic Low Input Threshold 5 V/3.3 V Operation 3.3 V/5 V Operation Logic High Output Voltages Logic Low Output Voltages SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew 5 Channel-to-Channel Matching, Codirectional Channels 6 Channel-to-Channel Matching, Opposing Directional Channels5 For All Models Output Disable Propagation Delay (High/Low to High Impedance) Output Enable Propagation Delay (High Impedance to High/Low) Output Rise/Fall Time (10% to 90%) 5 V/3 V Operation 3 V/5 V Operation Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate 5 V/3.3 V Operation 3.3 V/5 V Operation Input Dynamic Supply Current per Channel 8 5 V/3.3 V Operation 3.3 V/5 V Operation Output Dynamic Supply Current per Channel8 5 V/3.3 V Operation 3.3 V/5 V Operation Symbol Data Sheet Min Typ Max Unit Test Conditions 83 40 130 66 mA mA 75 MHz logic signal frequency 75 MHz logic signal frequency 40 83 66 130 mA mA 75 MHz logic signal frequency 75 MHz logic signal frequency +0.01 +10 µA 0 ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2, 0 ≤ VE1,VE2 ≤ VDD1 or VDD2 IDD1 (150) IDD2 (150) IIA, IIB, IIC, IID, IE1, IE2 VIH, VEH −10 2.0 1.6 V V VIL, VEL 0.8 0.4 VOAH, VOBH, VOCH, VODH (VDD1 or VDD2) − 0.1 (VDD1 or VDD2) − 0.4 VOAL, VOBL, VOCL, VODL V V V IOx = −20 µA, VIx = VIxH V IOx = −4 mA, VIx = VIxH (VDD1 or VDD2) (VDD1 or VDD2) − 0.2 0.0 0.1 V IOx = 20 µA, VIx = VIxL 0.04 0.2 0.1 0.4 V V IOx = 400 µA, VIx = VIxL IOx = 4 mA, VIx = VIxL 6.67 CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels PW tPSK tPSKCD 15 2 ns Mbps ns ns ps/°C ns ns tPSKOD 5 ns CL = 15 pF, CMOS signal levels tPHL, tPLH PWD 150 20 0.5 3 35 2 tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels tR/tF CL = 15 pF, CMOS signal levels |CMH| 25 3.0 2.5 35 ns ns kV/µs |CML| 25 35 kV/µs 1.2 1.1 Mbps Mbps 0.196 0.076 mA/Mbps mA/Mbps 0.028 0.01 mA/Mbps mA/Mbps fr IDDI (D) IDDO (D) Rev. D | Page 8 of 24 VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Data Sheet ADuM3440/ADuM3441/ADuM3442 1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3440/ADuM3441/ADuM3442 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDO. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. D | Page 9 of 24 ADuM3440/ADuM3441/ADuM3442 Data Sheet PACKAGE CHARACTERISTICS Table 4. Parameter Resistance (Input to Output) 1 Capacitance (Input to Output)1 Input Capacitance 2 IC Junction-to-Case Thermal Resistance, Side 1 IC Junction-to-Case Thermal Resistance, Side 2 1 2 Symbol RI-O CI-O CI θJCI θJCO Min Typ 1012 2.2 4.0 33 28 Max Unit Ω pF pF °C/W °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together and Pin 9 through Pin 16 are shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM344x is approved by the organizations listed in Table 5. Refer to Table 10 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 5. UL Recognized under 1577 component recognition program 1 Single protection, 2500 V rms isolation voltage File E214100 CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage File 205078 VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 2 Reinforced insulation, 560 V peak File 2471900-4880-0001 1 In accordance with UL 1577, each ADuM344x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA). 2 In accordance with DIN V VDE V 0884-10, each ADuM344x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 2500 7.7 min Minimum External Tracking (Creepage) L(I02) 8.1 min Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >175 IIIa Unit Conditions V rms 1-minute duration mm Measured from input terminals to output terminals, shortest distance through air mm Measured from input terminals to output terminals, shortest distance path along body mm Insulation distance through insulation V DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) Rev. D | Page 10 of 24 Data Sheet ADuM3440/ADuM3441/ADuM3442 DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval. Table 7. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC Symbol Characteristic Unit VIORM VPR I to IV I to III I to II 40/105/21 2 560 1050 V peak V peak 896 672 V peak V peak VTR 4000 V peak TS IS1 IS2 RS 150 265 335 >109 °C mA mA Ω VPR VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 seconds Maximum value allowed in the event of a failure (see Figure 4) VIO = 500 V 350 RECOMMENDED OPERATING CONDITIONS 300 Table 8. Parameter Operating Temperature Range, TA Supply Voltage Range, VDD1, VDD2 1 Input Signal Rise and Fall Time 250 SIDE #2 200 150 1 SIDE #1 100 50 0 0 50 100 150 CASE TEMPERATURE (°C) 200 Rating −40°C to +105°C 3.0 V to 5.5 V 1.0 ms All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. 06837-004 SAFETY-LIMITING CURRENT (mA) Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS Conditions Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. D | Page 11 of 24 ADuM3440/ADuM3441/ADuM3442 Data Sheet ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Table 9. Parameter Storage Temperature Range (TST) Ambient Operating Temperature Range (TA) Supply Voltages (VDD1, VDD2) 1 Input Voltage (VIA, VIB, VIC, VID, VE1, VE2)1, 2 Output Voltage (VOA, VOB, VOC, VOD)1, 2 Average Output Current per Pin 3 Side 1 (IO1) Side 2 (IO2) Common-Mode Transients (CMH, CML) 4 Rating −65°C to +150°C −40°C to +105°C −0.5 V to +7.0 V −0.5 V to VDD1 + 0.5 V −0.5 V to VDDO + 0.5 V −18 mA to +18 mA −22 mA to +22 mA −100 kV/µs to +100 kV/µs Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1 All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section. 3 See Figure 4 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Ratings can cause latchup or permanent damage. 2 Table 10. Maximum Continuous Working Voltage 1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Basic Insulation Reinforced Insulation DC Voltage Basic Insulation Reinforced Insulation 1 Max 565 Unit V peak Constraint 50-year minimum lifetime 1131 560 V peak V peak Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 1131 560 V peak V peak Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table 11. Truth Table (Positive Logic) VIX Input 1 H L X X X X 1 2 VEX Input 2 H or NC H or NC L H or NC L X VDDI State1 Powered Powered Powered Unpowered Unpowered Powered VDDO State1 Powered Powered Powered Powered Powered Unpowered VOX Output1 Notes H L Z H Outputs return to the input state within 1 µs of VDDI power restoration. Z Indeterminate Outputs return to the input state within 1 µs of VDDO power restoration if VEX state is H or NC. Outputs return to high impedance state within 8 ns of VDDO power restoration if VEX state is L. VIX and VOX refer to the input and output signals of a given channel (A, B, C, or D). VEX refers to the output enable signal on the same side as the VOX outputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. In noisy environments, connecting VEX to an external logic high or low is recommended. Rev. D | Page 12 of 24 Data Sheet ADuM3440/ADuM3441/ADuM3442 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 16 VDD2 GND1* 2 15 GND2* VIA 3 ADuM3440 14 VOA VIB 4 TOP VIEW (Not to Scale) 13 VOB VIC 5 12 VOC VID 6 11 VOD NC 7 10 VE2 GND1* 8 9 GND2* 06837-005 NC = NO CONNECT *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND2 IS RECOMMENDED. Figure 5. ADuM3440 Pin Configuration Table 12. ADuM3440 Pin Function Descriptions Pin No. 1 2, 8 3 4 5 6 7 9, 15 10 Mnemonic VDD1 GND1 VIA VIB VIC VID NC GND2 VE2 11 12 13 14 16 VOD VOC VOB VOA VDD2 Description Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1. Logic Input A. Logic Input B. Logic Input C. Logic Input D. No Connect. Ground 2. Ground reference for Isolator Side 2. Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected. VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended. Logic Output D. Logic Output C. Logic Output B. Logic Output A. Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V. Rev. D | Page 13 of 24 Data Sheet VDD1 1 16 VDD2 GND1* 2 15 GND2* VIA 3 ADuM3441 14 VOA VIB 4 TOP VIEW (Not to Scale) 13 VOB 12 VOC VOD 6 11 VID VE1 7 10 VE2 GND1* 8 9 GND2* VIC 5 *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND2 IS RECOMMENDED. 06837-006 ADuM3440/ADuM3441/ADuM3442 Figure 6. ADuM3441 Pin Configuration Table 13. ADuM3441 Pin Function Descriptions Pin No. 1 2, 8 3 4 5 6 7 Mnemonic VDD1 GND1 VIA VIB VIC VOD VE1 9, 15 10 GND2 VE2 11 12 13 14 16 VID VOC VOB VOA VDD2 Description Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1. Logic Input A. Logic Input B. Logic Input C. Logic Output D. Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended. Ground 2. Ground reference for Isolator Side 2. Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA, VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended. Logic Input D. Logic Output C. Logic Output B. Logic Output A. Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. Rev. D | Page 14 of 24 ADuM3440/ADuM3441/ADuM3442 VDD1 1 16 VDD2 GND1* 2 15 GND2* VOA VIA 3 ADuM3442 14 VIB 4 TOP VIEW (Not to Scale) 13 VOB 12 VIC VOC 5 VOD 6 11 VID VE1 7 10 VE2 GND1* 8 9 GND2* *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND2 IS RECOMMENDED. 06837-007 Data Sheet Figure 7. ADuM3442 Pin Configuration Table 14. ADuM3442 Pin Function Descriptions Pin No. 1 2, 8 3 4 5 6 7 Mnemonic VDD1 GND1 VIA VIB VOC VOD VE1 9, 15 10 GND2 VE2 11 12 13 14 16 VID VIC VOB VOA VDD2 Function Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1. Logic Input A. Logic Input B. Logic Output C. Logic Output D. Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected. VOC and VOD outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended. Ground 2. Ground reference for Isolator Side 2. Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected. VOA and VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended. Logic Input D. Logic Input C. Logic Output B. Logic Output A. Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V. Rev. D | Page 15 of 24 ADuM3440/ADuM3441/ADuM3442 Data Sheet 140 30 120 25 100 CURRENT (mA) 35 20 5V 15 10 80 5V 60 40 3.3V 3.3V 20 0 0 50 100 DATA RATE (Mbps) 150 0 0 Figure 8. Typical Input Supply Current per Channel vs. Data Rate for 5 V and 3.3 V Operation 50 100 DATA RATE (Mbps) 150 06837-011 5 06837-008 CURRENT/CHANNE L (mA) TYPICAL PERFORMANCE CHARACTERISTICS Figure 11. Typical ADuM3440 VDD1 Supply Current vs. Data Rate for 5 V and 3.3 V Operation 50 14 45 12 35 CURRENT (mA) CURRENT/CHANNEL (mA) 40 10 8 5V 6 30 5V 25 20 15 4 3.3V 3.3V 10 2 0 50 100 DATA RATE (Mbps) 150 0 06837-009 0 0 Figure 9. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3.3 V Operation (No Output Load) 50 100 DATA RATE (Mbps) 150 06837-012 5 Figure 12. Typical ADuM3440 VDD2 Supply Current vs. Data Rate for 5 V and 3.3 V Operation 20 120 18 100 14 CURRENT (mA) CURRENT/CHANNEL (mA) 16 12 5V 10 8 6 80 60 5V 40 3.3V 3.3V 4 20 0 50 100 DATA RATE (Mbps) 150 Figure 10. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3.3 V Operation (15 pF Output Load) 0 0 50 100 DATA RATE (Mbps) 150 Figure 13. Typical ADuM3441 VDD1 Supply Current vs. Data Rate for 5 V and 3.3 V Operation Rev. D | Page 16 of 24 06837-013 0 06837-010 2 Data Sheet ADuM3440/ADuM3441/ADuM3442 90 70 80 60 70 CURRENT (mA) 40 5V 30 60 50 5V 40 30 20 3.3V 3.3V 20 10 0 0 50 100 DATA RATE (Mbps) 150 Figure 14. Typical ADuM3441 VDD2 Supply Current vs. Data Rate for 5 V and 3.3 V Operation 0 0 50 100 DATA RATE (Mbps) 150 06837-015 10 06837-014 CURRENT (mA) 50 Figure 15. Typical ADuM3442 VDD1 or VDD2 Supply Current vs.Data Rate for 5 V and 3.3 V Operation Rev. D | Page 17 of 24 ADuM3440/ADuM3441/ADuM3442 Data Sheet APPLICATIONS INFORMATION PC BOARD LAYOUT VDD1 GND1 VIA VIB VIC/OC VID/OD VE1 GND1 VDD2 GND2 VOA VOB VOC/IC VOD/ID VE2 GND2 06837-017 The ADuM344x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 16). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should be considered unless the ground pair on each package side is connected close to the package. SYSTEM-LEVEL ESD CONSIDERATIONS AND ENHANCEMENTS System-level ESD reliability (for example, per IEC 61000-4-x) is highly dependent on system design, which varies widely by application. The ADuM344x incorporate many enhancements to make ESD reliability less dependent on system design. The enhancements include the following: ESD protection cells added to all input/output interfaces. Key metal trace resistances reduced using wider geometry and paralleling of lines with vias. The SCR effect inherent in CMOS devices is minimized by the use of guarding and isolation techniques between PMOS and NMOS devices. Areas of high electric field concentration eliminated using 45° corners on metal traces. Supply pin overvoltage prevented with larger ESD clamps between each supply pin and its respective ground. Figure 16. Recommended Printed Circuit Board Layout In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device’s absolute maximum ratings, thereby leading to latch-up or permanent damage. See the AN-1109 Application Note for board layout guidelines. PROPAGATION DELAY-RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high. INPUT (VIx) 50% OUTPUT (VOx) tPHL 06837-018 tPLH 50% Figure 17. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved. Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM344x component. Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM344x components operating under the same conditions. While the ADuM344x improve system-level ESD reliability, they are no substitute for a robust system-level design. See the AN-793 application note, ESD/Latch-Up Considerations with iCoupler Isolation Products for detailed recommendations on board layout and system-level design. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 μs, the input side is assumed unpowered or nonfunctional, in which case the isolator output is forced to a default state (see the Absolute Maximum Ratings section) by the watchdog timer circuit. The limitation on the magnetic field immunity of the ADuM344x is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM344x is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. Rev. D | Page 18 of 24 Data Sheet ADuM3440/ADuM3441/ADuM3442 The voltage induced across the receiving coil is given by where: β is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM344x and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 18. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) 100 DISTANCE = 1m 100 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 0.01 1k 10k 100k 1M 10M 100M MAGNETIC FIELD FREQUENCY (Hz) 10 06837-020 V = (−dβ/dt)∑ πr ; n = 1, 2, … , N MAXIMUM ALLOWABLE CURRENT (kA) 1000 2 n Figure 19. Maximum Allowable Current for Various Current-to-ADuM344x Spacings 1 Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. 0.1 0.01 0.001 1k 1M 10k 100k 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 06837-019 POWER CONSUMPTION Figure 18. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM344x transformers. Figure 19 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM344x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM344x to affect the component’s operation. The supply current at a given channel of the ADuM344x isolator is a function of the supply voltage, the channel’s data rate, and the channel’s output load. For each input channel, the supply current is given by IDDI = IDDI (Q) f ≤ 0.5 fr IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5 fr For each output channel, the supply current is given by IDDO = IDDO (Q) f ≤ 0.5 fr −3 IDDO = (IDDO (D) + (0.5 × 10 ) × CL × VDDO) × (2f − fr) + IDDO (Q) f > 0.5 fr where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half of the input data rate expressed in units of Mbps. fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA). To calculate the total VDD1 and VDD2 supply current, the supply currents for each input and output channel corresponding to VDD1 and VDD2 are calculated and totaled. Figure 8 and Figure 9 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 10 provides perchannel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 15 provide total VDD1 and VDD2 supply current as a function of data rate for ADuM3440/ADuM3441/ADuM3442 channel configurations. Rev. D | Page 19 of 24 ADuM3440/ADuM3441/ADuM3442 Data Sheet Note that the voltage presented in Figure 21 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. The insulation lifetime of the ADuM344x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 20, Figure 21, and Figure 22 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the maximum working voltage recommended by Analog Devices. RATED PEAK VOLTAGE 06837-021 Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Figure 20 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. 0V Figure 20. Bipolar AC Waveform RATED PEAK VOLTAGE 06837-022 All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM344x. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower, which allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 10 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross insulation voltage waveform that does not conform to Figure 21 or Figure 22 should be treated as a bipolar ac waveform and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 10. 0V Figure 21. Unipolar AC Waveform RATED PEAK VOLTAGE 06837-023 INSULATION LIFETIME 0V Figure 22. DC Waveform Rev. D | Page 20 of 24 Data Sheet ADuM3440/ADuM3441/ADuM3442 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 03-27-2007-B 1 Figure 23. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1, 2 ADuM3440CRWZ ADuM3441CRWZ ADuM3442CRWZ 1 2 Number of Inputs, VDD1 Side 4 3 2 Number of Inputs, VDD2 Side 0 1 2 Maximum Data Rate (Mbps) 150 150 150 Maximum Propagation Delay, 5 V (ns) 32 32 32 Maximum Pulse Width Distortion (ns) 2 2 2 Z = RoHS Compliant Part. Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option. Rev. D | Page 21 of 24 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W Package Option RW-16 RW-16 RW-16 ADuM3440/ADuM3441/ADuM3442 Data Sheet NOTES Rev. D | Page 22 of 24 Data Sheet ADuM3440/ADuM3441/ADuM3442 NOTES Rev. D | Page 23 of 24 ADuM3440/ADuM3441/ADuM3442 Data Sheet NOTES ©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06837-0-2/12(D) Rev. D | Page 24 of 24