Low Power Differential ADC Driver ADA4932-1/ADA4932-2 Data Sheet ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Line drivers 13 –VS ADA4932-1 12 PD 9 VOCM 07752-001 +VS 8 10 +OUT +FB 4 +VS 7 11 –OUT –IN 3 +VS 5 +IN 2 Figure 1. ADA4932-1 499Ω VIN VOCM 499Ω 5V 499Ω 33Ω + ADA4932-1 – 499Ω 56pF 33Ω IN– VDD1 VDD2 AD7626 IN+ 56pF GND DIGITAL OUTPUTS REF 07752-102 5V Figure 2. ADC Driver Test Circuit (Data Shown in Figure 3) 0 –20 –40 AMPLITUDE (dB) APPLICATIONS 14 –VS 16 –VS –FB 1 15 –VS FUNCTIONAL BLOCK DIAGRAM High performance at low power High speed −3 dB bandwidth of 560 MHz, G = 1 0.1 dB gain flatness to 300 MHz Slew rate: 2800 V/μs, 25% to 75% Fast 0.1% settling time of 9 ns Low power: 9.6 mA per amplifier Low harmonic distortion 100 dB SFDR at 10 MHz 90 dB SFDR at 20 MHz Low input voltage noise: 3.6 nV/√Hz ±0.5 mV typical input offset voltage Externally adjustable gain Can be used with gains less than 1 Differential-to-differential or single-ended-to-differential operation Adjustable output common-mode voltage Input common-mode range shifted down by 1 VBE Wide supply range: +3 V to ±5 V Available in 16-lead and 24-lead LFCSP packages +VS 6 FEATURES –60 –80 –100 –120 –140 –180 0 1.25 2.50 3.75 5.00 FREQUENCY (MHz) 07752-103 –160 Figure 3. AD7626 Output, 64,000 Point, FFT Plot −1 dBFS Amplitude 2.40173 MHz Input Ton, 10.000 MSPS Sampling Rate GENERAL DESCRIPTION The ADA4932 family is the next generation AD8132 with higher performance, and lower noise and power consumption. It is an ideal choice for driving high performance ADCs as a single-ended-to-differential or differential-to-differential amplifier. The output common-mode voltage is user adjustable by means of an internal common-mode feedback loop, allowing the ADA4932 family output to match the input of the ADC. The internal feedback loop also provides exceptional output balance as well as suppression of even-order harmonic distortion products. With the ADA4932 family, differential gain configurations are easily realized with a simple external four-resistor feedback network that determines the closed-loop gain of the amplifier. Rev. D The ADA4932 family is fabricated using the Analog Devices, Inc., proprietary silicon-germanium (SiGe) complementary bipolar process, enabling it to achieve low levels of distortion and noise at low power consumption. The low offset and excellent dynamic performance of the ADA4932 family make it well suited for a wide variety of data acquisition and signal processing applications. The ADA4932-1 is available in a 16-lead LFCSP and the ADA4932-2 is available in a 24-lead LFCSP. The pinout has been optimized to facilitate PCB layout and minimize distortion. The ADA4932 family is specified to operate over the −40°C to +105°C temperature range; both operate on supplies between +3 V and ±5 V. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADA4932-1/ADA4932-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 19 Applications ....................................................................................... 1 Applications Information .............................................................. 20 Functional Block Diagram .............................................................. 1 Analyzing an Application Circuit ............................................ 20 General Description ......................................................................... 1 Setting the Closed-Loop Gain .................................................. 20 Revision History ............................................................................... 2 Estimating the Output Noise Voltage ...................................... 20 Specifications..................................................................................... 3 Impact of Mismatches in the Feedback Networks ................. 21 ±5 V Operation ............................................................................. 3 5 V Operation ............................................................................... 5 Calculating the Input Impedance for an Application Circuit .......................................................................................... 21 Absolute Maximum Ratings ............................................................ 7 Input Common-Mode Voltage Range ..................................... 23 Thermal Resistance ...................................................................... 7 Input and Output Capacitive AC Coupling ............................ 23 Maximum Power Dissipation ..................................................... 7 Setting the Output Common-Mode Voltage .......................... 23 ESD Caution .................................................................................. 7 High Performance Precision ADC Driver .............................. 24 Pin Configurations and Function Descriptions ........................... 8 High Performance ADC Driving ................................................. 25 Typical Performance Characteristics ............................................. 9 Layout, Grounding, and Bypassing .............................................. 26 Test Circuits ..................................................................................... 17 Outline Dimensions ....................................................................... 27 Terminology .................................................................................... 18 Ordering Guide .......................................................................... 27 REVISION HISTORY 3/13—Rev. A to Rev. B 4/14—Rev. C to Rev. D Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 Changes to Features Section, Figure 2, and Figure 3 ................... 1 Changes to Setting the Output Common-Mode Voltage Section .............................................................................................. 23 Added High Performance Precision ADC Driver Section ....... 24 Moved Layout, Grounding, and Bypassing Section ................... 26 8/09—Rev. 0 to Rev. A 1/14—Rev. B to Rev. C Changes to Features Section ............................................................1 Changes to Figure 11.........................................................................9 Changes to Figure 43 and Figure 45 ............................................ 15 Changes to Figure 52, Figure 53, and Figure 54 ......................... 17 Changes to Figure 51 ...................................................................... 16 10/08—Revision 0: Initial Version Rev. D | Page 2 of 28 Data Sheet ADA4932-1/ADA4932-2 SPECIFICATIONS ±5 V OPERATION TA = 25°C, +VS = 5 V, −VS = −5 V, VOCM = 0 V, RF = 499 Ω, RG = 499 Ω, RT = 53.6 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 55 for signal definitions. ±DIN to VOUT, dm Performance Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic Third Harmonic IMD Voltage Noise (RTI) Input Current Noise Crosstalk INPUT CHARACTERISTICS Offset Voltage Test Conditions/Comments Min VOUT, dm = 0.1 V p-p VOUT, dm = 0.1 V p-p, RF = RG = 205 Ω VOUT, dm = 2.0 V p-p VOUT, dm = 2.0 V p-p, RF = RG = 205 Ω VOUT, dm = 2.0 V p-p, ADA4932-1, RL = 200 Ω VOUT, dm = 2.0 V p-p, ADA4932-2, RL = 200 Ω VOUT, dm = 2 V p-p, 25% to 75% VOUT, dm = 2 V step VIN = 0 V to 5 V ramp, G = 2 See Figure 54 for distortion test circuit VOUT, dm = 2 V p-p, 1 MHz VOUT, dm = 2 V p-p, 10 MHz VOUT, dm = 2 V p-p, 20 MHz VOUT, dm = 2 V p-p, 50 MHz VOUT, dm = 2 V p-p, 1 MHz VOUT, dm = 2 V p-p, 10 MHz VOUT, dm = 2 V p-p, 20 MHz VOUT, dm = 2 V p-p, 50 MHz f1 = 30 MHz, f2 = 30.1 MHz, VOUT, dm = 2 V p-p f = 1 MHz f = 1 MHz f = 10 MHz, ADA4932-2 V+DIN = V−DIN = VOCM = 0 V TMIN to TMAX variation Input Bias Current −2.2 −5.2 TMIN to TMAX variation Input Offset Current Input Resistance −0.2 Differential Common mode Input Capacitance Input Common-Mode Voltage Range CMRR Open-Loop Gain OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V 64 Maximum ∆VOUT, single-ended output, RF = RG = 10 kΩ, RL = 1 kΩ 200 kHz, RL, dm = 10 Ω, SFDR = 68 dB ∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 2 V p-p, 1 MHz, see Figure 53 for output balance test circuit Rev. D | Page 3 of 28 −VS + 1.4 to +VS − 1.4 Typ Max Unit 560 1000 360 360 300 100 2800 9 20 MHz MHz MHz MHz MHz MHz V/µs ns ns −110 −100 −90 −72 −130 −120 −105 −80 −91 3.6 1.0 −100 dBc dBc dBc dBc dBc dBc dBc dBc dBc nV/√Hz pA/√Hz dB ±0.5 −3.7 −2.5 −9.5 ±0.025 11 16 0.5 −VS + 0.2 to +VS − 1.8 −100 66 −VS + 1.2 to +VS − 1.2 80 −64 +2.2 −0.1 +0.2 −87 mV µV/°C µA nA/°C µA MΩ MΩ pF V dB dB V −60 mA rms dB ADA4932-1/ADA4932-2 Data Sheet VOCM to VOUT, cm Performance Table 2. Parameter VOCM DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Slew Rate Input Voltage Noise (RTI) VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage VOCM CMRR Gain Test Conditions/Comments Min VOUT, cm = 100 mV p-p VOUT, cm = 2 V p-p VIN = 1.5 V to 3.5 V, 25% to 75% f = 1 MHz V+DIN = V−DIN = 0 V ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V Typ Max 270 105 410 9.6 22 −5.1 0.995 Unit MHz MHz V/µs nV/√Hz −VS + 1.2 to +VS − 1.2 25 ±1 −100 0.998 29 +5.1 −86 1.000 V kΩ mV dB V/V Max Unit 11 10.1 V mA µA/°C mA dB General Performance Table 3. Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio POWER-DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Pin Bias Current per Amplifier Enabled Disabled Test Conditions/Comments Min 3.0 9.0 TMIN to TMAX variation Powered down ΔVOUT, dm/ΔVS, ΔVS = 1 V p-p Powered down Enabled Typ 9.6 35 0.9 −96 1.0 −84 ≤(+VS − 2.5) ≥(+VS − 1.8) 1100 16 PD = 5 V PD = 0 V −10 −240 OPERATING TEMPERATURE RANGE −40 Rev. D | Page 4 of 28 +0.7 −195 V V ns ns +10 −140 µA µA +105 °C Data Sheet ADA4932-1/ADA4932-2 5 V OPERATION TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = 2.5 V, RF = 499 Ω, RG = 499 Ω, RT = 53.6 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 55 for signal definitions. ±DIN to VOUT, dm Performance Table 4. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic Third Harmonic IMD Voltage Noise (RTI) Input Current Noise Crosstalk INPUT CHARACTERISTICS Offset Voltage Test Conditions/Comments Min VOUT, dm = 0.1 V p-p VOUT, dm = 0.1 V p-p, RF = RG = 205 Ω VOUT, dm = 2.0 V p-p VOUT, dm = 2.0 V p-p, RF = RG = 205 Ω VOUT, dm = 2.0 V p-p, ADA4932-1, RL = 200 Ω VOUT, dm = 2.0 V p-p, ADA4932-2, RL = 200 Ω VOUT, dm = 2 V p-p, 25% to 75% VOUT, dm = 2 V step VIN = 0 V to 2.5 V ramp, G = 2 See Figure 54 for distortion test circuit VOUT, dm = 2 V p-p, 1 MHz VOUT, dm = 2 V p-p, 10 MHz VOUT, dm = 2 V p-p, 20 MHz VOUT, dm = 2 V p-p, 50 MHz VOUT, dm = 2 V p-p, 1 MHz VOUT, dm = 2 V p-p, 10 MHz VOUT, dm = 2 V p-p, 20 MHz VOUT, dm = 2 V p-p, 50 MHz f1 = 30 MHz, f2 = 30.1 MHz, VOUT, dm = 2 V p-p f = 1 MHz f = 1 MHz f = 10 MHz, ADA4932-2 V+DIN = V−DIN = VOCM = 2.5 V TMIN to TMAX variation Input Bias Current −2.2 −5.3 TMIN to TMAX variation Input Offset Current Input Resistance −0.25 Differential Common mode Input Capacitance Input Common-Mode Voltage Range CMRR Open-Loop Gain OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V 64 Maximum ∆VOUT, single-ended output, RF = RG = 10 kΩ, RL = 1 kΩ 200 kHz, RL, dm = 10 Ω, SFDR = 67 dB ∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V p-p, 1 MHz, see Figure 53 for output balance test circuit Rev. D | Page 5 of 28 −VS + 1.15 to +VS − 1.15 Typ Max Unit 560 990 315 320 120 200 2200 10 20 MHz MHz MHz MHz MHz MHz V/µs ns ns −110 −100 −90 −72 −120 −100 −87 −70 −91 3.6 1.0 −100 dBc dBc dBc dBc dBc dBc dBc dBc dBc nV/√Hz pA/√Hz dB ±0.5 −3.7 −3.0 −9.5 ±0.025 11 16 0.5 −VS + 0.2 to +VS − 1.8 −100 66 −VS + 1.02 to +VS − 1.02 53 −64 +2.2 −0.23 +0.25 −87 mV µV/°C µA nA/°C µA MΩ MΩ pF V dB dB V −60 mA rms dB ADA4932-1/ADA4932-2 Data Sheet VOCM to VOUT, cm Performance Table 5. Parameter VOCM DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Slew Rate Input Voltage Noise (RTI) VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage VOCM CMRR Gain Test Conditions/Comments Min VOUT, cm = 100 mV p-p VOUT, cm = 2 V p-p VIN = 1.5 V to 3.5 V, 25% to 75% f = 1 MHz V+DIN = V−DIN = 2.5 V ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V Typ Max 260 90 360 9.6 22 −6.5 0.995 Unit MHz MHz V/µs nV/√Hz −VS + 1.2 to +VS − 1.2 25 −3.0 −100 0.998 29 +6.5 −86 1.000 V kΩ mV dB V/V General Performance Table 6. Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio POWER-DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Pin Bias Current per Amplifier Enabled Disabled Test Conditions/Comments Min 3.0 8.2 TMIN to TMAX variation Powered down ΔVOUT, dm/ΔVS, ΔVS = 1 V p-p Powered down Enabled Typ 8.8 35 0.7 −96 Max Unit 11 9.5 V mA µA/°C mA dB 0.8 −84 ≤(+VS − 2.5) ≥(+VS − 1.8) 1100 16 PD = 5 V PD = 0 V −10 −100 OPERATING TEMPERATURE RANGE −40 Rev. D | Page 6 of 28 +0.7 −70 V V ns ns +10 −40 µA µA +105 °C Data Sheet ADA4932-1/ADA4932-2 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Power Dissipation Input Current, +IN, −IN, PD Storage Temperature Range Operating Temperature Range ADA4932-1 ADA4932-2 Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 11 V See Figure 4 ±5 mA −65°C to +125°C −40°C to +105°C −40°C to +105°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. The power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. RMS voltages and currents must be used in these calculations. Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads/ exposed pad from metal traces, through holes, ground, and power planes reduces θJA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the single 16-lead LFCSP (91°C/W) and the dual 24-lead LFCSP (65°C/W) on a JEDEC standard 4-layer board with the exposed pad soldered to a PCB pad that is connected to a solid plane. 3.5 MAXIMUM POWER DISSIPATION (W) THERMAL RESISTANCE θJA is specified for the device (including exposed pad) soldered to a high thermal conductivity 2s2p circuit board, as described in EIA/JESD 51-7. Table 8. Thermal Resistance Package Type ADA4932-1, 16-Lead LFCSP (Exposed Pad) ADA4932-2, 24-Lead LFCSP (Exposed Pad) θJA 91 65 Unit °C/W °C/W MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the ADA4932 family package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4932 family. Exceeding a junction temperature of 150°C for an extended period can result in changes in the silicon devices, potentially causing failure. 3.0 2.5 ADA4932-2 2.0 1.5 ADA4932-1 1.0 0.5 0 –40 –20 0 20 40 60 AMBIENT TEMPERATURE (°C) 80 100 07752-204 Table 7. Figure 4. Maximum Power Dissipation vs. Ambient Temperature for a 4-Layer Board ESD CAUTION Rev. D | Page 7 of 28 ADA4932-1/ADA4932-2 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 20 PD1 ADA4932-2 TOP VIEW (Not to Scale) 10 +OUT TOP VIEW (Not to Scale) 15 –VS2 –FB2 5 14 PD2 VOCM2 11 +VS2 9 +OUT2 12 NOTES 1. SOLDER EXPOSED PADDLE ON BACK OF PACKAGE TO GROUND PLANE OR TO A POWER PLANE. +VS2 10 –IN2 7 13 –OUT2 +FB2 8 07752-005 +IN2 6 NOTES 1. SOLDER EXPOSED PADDLE ON BACK OF PACKAGE TO GROUND PLANE OR TO A POWER PLANE. Figure 5. ADA4932-1 Pin Configuration 07752-006 9 VOCM +VS 8 19 –OUT1 22 –VS1 21 –VS1 +VS1 3 +VS1 4 +VS 5 +FB 4 18 +OUT1 17 VOCM1 16 –VS2 11 –OUT +VS 7 –IN 3 –IN1 1 +FB1 2 ADA4932-1 +VS 6 +IN 2 24 +IN1 12 PD –FB 1 23 –FB1 13 –VS 15 –VS 14 –VS 16 –VS ADA4932-2 Figure 6. ADA4932-2 Pin Configuration Table 9. ADA4932-1 Pin Function Descriptions Pin No. 1 2 3 4 5 to 8 9 10 11 12 13 to 16 17 (EPAD) Mnemonic −FB +IN −IN +FB +VS VOCM +OUT −OUT PD −VS Exposed Paddle (EPAD) Description Negative Output for Feedback Component Connection. Positive Input Summing Node. Negative Input Summing Node. Positive Output for Feedback Component Connection. Positive Supply Voltage. Output Common-Mode Voltage. Positive Output for Load Connection. Negative Output for Load Connection. Power-Down Pin. Negative Supply Voltage. Solder the exposed paddle on the back of the package to a ground plane or to a power plane. Table 10. ADA4932-2 Pin Function Descriptions Pin No. 1 2 3, 4 5 6 7 8 9, 10 11 12 13 14 15, 16 17 18 19 20 21, 22 23 24 25 (EPAD) Mnemonic −IN1 +FB1 +VS1 −FB2 +IN2 −IN2 +FB2 +VS2 VOCM2 +OUT2 −OUT2 PD2 −VS2 VOCM1 +OUT1 −OUT1 PD1 −VS1 −FB1 +IN1 Exposed Paddle (EPAD) Description Negative Input Summing Node 1. Positive Output Feedback 1. Positive Supply Voltage 1. Negative Output Feedback 2. Positive Input Summing Node 2. Negative Input Summing Node 2. Positive Output Feedback 2. Positive Supply Voltage 2. Output Common-Mode Voltage 2. Positive Output 2. Negative Output 2. Power-Down Pin 2. Negative Supply Voltage 2. Output Common-Mode Voltage 1. Positive Output 1. Negative Output 1. Power-Down Pin 1. Negative Supply Voltage 1. Negative Output Feedback 1. Positive Input Summing Node 1. Solder the exposed paddle on the back of the package to a ground plane or to a power plane. Rev. D | Page 8 of 28 Data Sheet ADA4932-1/ADA4932-2 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, +VS = 5 V, −VS = −5 V, VOCM = 0 V, RG = 499 Ω, RF = 499 Ω, RT = 53.6 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted. Refer to Figure 52 for test setup. Refer to Figure 55 for signal definitions. 2 NORMALIZED CLOSED-LOOP GAIN (dB) 1 GAIN = 1 GAIN = 2 0 –1 –2 –3 –4 –5 –6 –7 –8 1M 10M 100M FREQUENCY (Hz) –1 –2 –3 –4 –5 –6 –7 –8 1G 10M 100M FREQUENCY (Hz) 1M Figure 10. Large Signal Frequency Response for Various Gains 2 2 VOUT, dm = 100mV p-p RF = RG = 499Ω RF = RG = 205Ω 1 VOUT, dm = 2V p-p RF = RG = 499Ω 1 0 CLOSED-LOOP GAIN (dB) 0 –1 –2 –3 –4 –5 RF = RG = 205Ω –1 –2 –3 –4 –5 –6 07752-008 –6 –8 1M 10M 100M FREQUENCY (Hz) 1G –7 –8 10G 1 10 100 07752-058 –7 1k FREQUENCY (MHz) Figure 11. Large Signal Frequency Response for Various RF and RG Figure 8. Small Signal Frequency Response for Various RF and RG 2 2 VOUT, dm = 2V p-p VOUT, dm = 100mV p-p 1 1 0 CLOSED-LOOP GAIN (dB) 0 VS = ±5V VS = ±2.5V –1 –2 –3 –4 –5 VS = ±5V VS = ±2.5V –1 –2 –3 –4 –5 –6 07752-009 –6 –7 –8 1M 10M 100M FREQUENCY (Hz) 07752-012 CLOSED-LOOP GAIN (dB) GAIN = 1 GAIN = 2 0 1G Figure 7. Small Signal Frequency Response for Various Gains CLOSED-LOOP GAIN (dB) VIN = 2V p-p RF = 499Ω RG = 499Ω, 249Ω 1 07752-010 VIN = 100mV p-p RF = 499Ω RG = 499Ω, 249Ω 07752-007 NORMALIZED CLOSED-LOOP GAIN (dB) 2 –7 –8 1M 1G 10M 100M FREQUENCY (Hz) 1G Figure 12. Large Signal Frequency Response for Various Supplies Figure 9. Small Signal Frequency Response for Various Supplies Rev. D | Page 9 of 28 ADA4932-1/ADA4932-2 Data Sheet 2 2 VOUT, dm = 2V p-p 1 1 0 0 CLOSED-LOOP GAIN (dB) –1 TA = –40°C TA = +25°C TA = +105°C –2 –3 –4 –5 TA = –40°C TA = +25°C TA = +105°C –2 –3 –4 –5 07752-013 –7 –8 1M 10M 100M FREQUENCY (Hz) 07752-016 –6 –6 –7 –8 1M 1G Figure 13. Small Signal Frequency Response for Various Temperatures 1G 2 VOUT, dm = 100mV p-p 1 RL = 1kΩ RL = 200Ω VOUT, dm = 2V p-p 1 0 RL = 1kΩ RL = 200Ω CLOSED-LOOP GAIN (dB) 0 –1 –2 –3 –4 –5 –6 –1 –2 –3 –4 –5 07752-014 –6 –7 –8 1M 10M 100M FREQUENCY (Hz) –7 –8 1G 1M Figure 14. Small Signal Frequency Response at Various Loads 10M 100M FREQUENCY (Hz) 1G Figure 17. Large Signal Frequency Response at Various Loads 2 2 VOUT, dm = 2V p-p VOUT, dm = 100mV p-p 1 1 0 0 CLOSED-LOOP GAIN (dB) –1 VOCM = 0V VOCM = +2.5V VOCM = –2.5V –2 –3 –4 –5 –6 –1 VOCM = 0V VOCM = +2.5V VOCM = –2.5V –2 –3 –4 –5 07752-015 –6 –7 –8 1M 10M 100M FREQUENCY (Hz) 07752-018 CLOSED-LOOP GAIN (dB) 10M 100M FREQUENCY (Hz) Figure 16. Large Signal Frequency Response for Various Temperatures 2 CLOSED-LOOP GAIN (dB) –1 07752-017 CLOSED-LOOP GAIN (dB) VOUT, dm = 100mV p-p –7 –8 1G 1M Figure 15. Small Signal Frequency Response for Various VOCM Levels 10M 100M FREQUENCY (Hz) 1G Figure 18. Large Signal Frequency Response for Various VOCM Levels Rev. D | Page 10 of 28 Data Sheet ADA4932-1/ADA4932-2 4 4 VOUT, dm = 100mV p-p VOUT, dm = 2V p-p 2 CLOSED-LOOP GAIN (dB) CL = 0pF CL = 0.9pF CL = 1.8pF –2 –4 –6 1M 10M 100M FREQUENCY (Hz) 1G CL = 0pF CL = 0.9pF CL = 1.8pF –2 –4 –6 –8 07752-019 –8 0 –10 10M 10G Figure 19. Small Signal Frequency Response at Various Capacitive Loads 1G 0.5 VOUT, dm = 100mV p-p VOUT, dm = 2V p-p 0.4 0.3 0.3 0.2 0.1 0 –0.1 ADA4932-1, ADA4932-1, ADA4932-2, ADA4932-2, ADA4932-2, ADA4932-2, –0.2 –0.3 –0.4 R L = 1kΩ R L = 200Ω CH 1, R L = CH 1, R L = CH 2, R L = CH 2, R L = 1kΩ 200Ω 1kΩ 200Ω 100M 10M FREQUENCY (Hz) 0 –0.1 ADA4932-1, ADA4932-1, ADA4932-2, ADA4932-2, ADA4932-2, ADA4932-2, –0.2 –0.3 –0.5 1M 0.2 0.1 –0.4 R L = 1kΩ R L = 200Ω CH 1, R L = CH 1, R L = CH 2, R L = CH 2, R L = 1kΩ 200Ω 1kΩ 200Ω 07752-023 CLOSED-LOOP GAIN (dB) 0.4 07752-020 CLOSED-LOOP GAIN (dB) 100M FREQUENCY (Hz) Figure 22. Large Signal Frequency Response at Various Capacitive Loads 0.5 –0.5 1G 100M 10M FREQUENCY (Hz) 1M Figure 20. 0.1 dB Flatness Small Signal Frequency Response for Various Loads 1G Figure 23. 0.1 dB Flatness Large Signal Frequency Response for Various Loads 2 2 VOUT, cm = 100mV p-p 1 1 0 0 –1 VOUT, cm = 2V p-p VOCM GAIN (dB) –1 VOCM (DC) = 0V VOCM (DC) = +2.5V VOCM (DC) = –2.5V –2 –3 –4 –2 –3 –4 –5 –5 –6 –6 07752-021 VOCM GAIN (dB) 07752-022 0 –7 –8 1M 10M 100M FREQUENCY (Hz) –7 –8 1M 1G VOCM (DC) = 0V VOCM (DC) = +2.5V VOCM (DC) = –2.5V 10M 100M FREQUENCY (Hz) Figure 21. VOCM Small Signal Frequency Response at Various DC Levels 1G 07752-224 CLOSED-LOOP GAIN (dB) 2 Figure 24. VOCM Large Signal Frequency Response at Various DC Levels Rev. D | Page 11 of 28 ADA4932-1/ADA4932-2 –60 –70 –80 –90 –100 –110 07752-025 –120 –130 –140 100k 1M 10M FREQUENCY (Hz) ±5.0V ±5.0V ±2.5V ±2.5V –90 –100 –110 –120 –130 –140 100k 1M 10M FREQUENCY (Hz) –30 –110 –120 HD2, HD3, HD2, HD3, –60 –70 –90 –100 –110 –120 –70 –80 –90 –100 –110 –4 –3 –2 –1 0 1 VOCM (V p-p) 2 3 2 3 4 5 6 VOUT, dm (V p-p) 7 8 9 10 VOUT = 2V p-p –40 HD2 AT 10MHz HD3 AT 10MHz HD2 AT 30MHz HD3 AT 30MHz –50 –60 –70 –80 –90 –100 07752-030 10MHz 10MHz 30MHz 30MHz –130 1 Figure 29. Harmonic Distortion vs. VOUT, dm and Supply Voltage, f = 10 MHz –20 –120 ±5.0V ±5.0V ±2.5V ±2.5V –80 0 HARMONIC DISTORTION (dBc) –60 100M VOCM = 0V –30 HD2 AT HD3 AT HD2 AT HD3 AT 10M FREQUENCY (Hz) –140 VOUT = 2V p-p –50 1M –130 07752-027 HARMONIC DISTORTION (dBc) –100 100M Figure 26. Harmonic Distortion vs. Frequency at Various Supplies –40 –90 –50 HARMONIC DISTORTION (dBc) –80 –80 –40 07752-026 HARMONIC DISTORTION (dBc) HD2, HD3, HD2, HD3, =1 =1 =2 =2 Figure 28. Harmonic Distortion vs. Frequency at Various Gains –60 –70 –70 G G G G –140 100k 100M VOUT, dm = 2V p-p VOCM = 0V –50 HD2, HD3, HD2, HD3, –60 –130 Figure 25. Harmonic Distortion vs. Frequency at Various Loads –40 VOUT, dm = 2V p-p –50 RL = 1kΩ RL = 1kΩ RL = 200Ω RL = 200Ω 07752-028 HD2, HD3, HD2, HD3, HARMONIC DISTORTION (dBc) –50 HARMONIC DISTORTION (dBc) –40 VOUT, dm = 2V p-p 07752-029 –40 Data Sheet –110 –120 4 1.4 Figure 27. Harmonic Distortion vs. VOCM at Various Frequencies, ±5 V Supplies 1.6 1.8 2.0 2.2 2.4 2.6 VOCM (V) 2.8 3.0 3.2 3.4 Figure 30. Harmonic Distortion vs. VOCM at Various Frequencies, +5 V Supply Rev. D | Page 12 of 28 Data Sheet ADA4932-1/ADA4932-2 –40 –70 –80 –90 –100 –110 –120 –130 –140 100k 1M 10M FREQUENCY (Hz) –110 –120 0 RL = 200Ω –90 –100 RL = 1kΩ –120 –130 1M 10M FREQUENCY (Hz) 100M –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 29.6 100M 29.7 29.8 29.9 30.0 30.1 30.2 30.3 30.4 30.5 FREQUENCY (MHz) Figure 35. 30 MHz Intermodulation Distortion –20 0 RL, dm = 200Ω RL, dm = 200Ω –20 –40 –40 PSSR (dB) –50 –60 –70 –60 –80 –PSRR –100 –80 +PSRR –100 1M 10M 100M FREQUENCY (Hz) 1G –120 07752-036 –90 07752-033 CMMR (dB) 10M FREQUENCY (Hz) VOUT, dm = 2V p-p Figure 32. Spurious-Free Dynamic Range vs. Frequency at Various Loads –30 1M –10 NORMALIZED SPECTRUM (dBc) –70 07752-032 SPURIOUS-FREE DYNAMIC RANGE (dBc) –100 10 –60 –140 100k –90 Figure 34. Harmonic Distortion vs. Frequency at Various RF and RG –50 –110 –80 –140 100k 100M VOUT, dm = 2V p-p –80 –70 RF = RG = 499Ω RF = RG = 499Ω RF = RG = 200Ω RF = RG = 200Ω –130 Figure 31. Harmonic Distortion vs. Frequency at Various VOUT, dm –40 HD2, HD3, HD2, HD3, –60 07752-235 –60 VOUT, dm = 2V p-p –50 2V p-p 2V p-p 4V p-p 4V p-p HARMONIC DISTORTION (dBc) HD2, HD3, HD2, HD3, 07752-031 HARMONIC DISTORTION (dBc) –50 07752-034 –40 –140 1M Figure 33. CMRR vs. Frequency 10M 100M FREQUENCY (Hz) Figure 36. PSRR vs. Frequency Rev. D | Page 13 of 28 1G ADA4932-1/ADA4932-2 Data Sheet –10 80 90 60 45 RL, dm = 200Ω –20 0 GAIN –45 GAIN (dB) 20 –40 –90 0 PHASE –20 –135 –40 –180 –60 –225 –50 PHASE (Degrees) OUTPUT BALANCE (dB) 40 –30 10M 100M 1G FREQUENCY (Hz) –80 1k 10k 100M 1G –270 10G 100 OUTPUT IMPEDANCE (Ω) S-PARAMETERS (dB) 10M Figure 40. Open-Loop Gain and Phase vs. Frequency INPUT SINGLE-ENDED, 50Ω LOAD TERMINATION OUTPUT DIFFERENTIAL, 100Ω SOURCE TERMINATION S11: COMMON-MODE-TO-COMMON-MODE S22: DIFFERENTIAL-TO-DIFFERENTIAL –10 1M FREQUENCY (Hz) Figure 37. Output Balance vs. Frequency 0 100k 07752-240 –70 1M 07752-237 –60 –20 S22 –30 RL = 200Ω S11 –40 10 1 –60 1M 10M 100M FREQUENCY (Hz) 0.1 100k 1G 1M 100M 10M 1G FREQUENCY (Hz) Figure 38. Return Loss (S11, S22) vs. Frequency 07752-241 07752-038 –50 Figure 41. Closed-Loop Output Impedance Magnitude vs. Frequency, G = 1 100 10 2 × VIN 6 VOUT, dm VOLTAGE (V) 4 10 2 0 –2 –4 –6 07752-039 1 10 100 10k 1k FREQUENCY (Hz) 100k –8 –10 1M 0 100 200 300 400 500 600 700 800 TIME (ns) Figure 42.Overdrive Recovery, G = 2 Figure 39. Voltage Noise Spectral Density, Referred to Input Rev. D | Page 14 of 28 900 1000 07752-242 INPUT VOLTAGE NOISE (nV/√Hz) 8 Data Sheet ADA4932-1/ADA4932-2 1.5 0.06 1.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.04 0.02 0 –0.02 0.5 0 –0.5 –1.0 07752-146 –0.04 –1.5 0 5 10 15 20 25 30 TIME (ns) 0 07752-059 –0.06 Figure 43. Small Signal Pulse Response 5 10 15 TIME (ns) 20 25 30 Figure 46. Large Signal Pulse Response 0.08 1.5 0.06 1.0 OUTPUT VOLTAGE (V) 0.02 0 –0.02 CL = 0pF CL = 0.9pF CL = 1.8pF 10 15 20 25 30 TIME (ns) Figure 44. Small Signal Pulse Response for Various Capacitive Loads 0.04 1.0 –0.02 15 20 25 30 Figure 47. Large Signal Pulse Response for Various Capacitive Loads 1.5 0 10 TIME (ns) 0.06 0.02 5 0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) –1.5 07752-244 –0.08 5 CL = 0pF CL = 0.9pF CL = 1.8pF –0.5 –1.0 –0.06 0 0 07752-247 –0.04 0.5 –0.04 0.5 0 –0.5 –0.06 0 5 10 15 20 25 TIME (ns) 30 07752-060 –1.0 07752-148 OUTPUT VOLTAGE (V) 0.04 –1.5 0 5 10 15 TIME (ns) 20 25 Figure 48. VOCM Large Signal Pulse Response Figure 45. VOCM Small Signal Pulse Response Rev. D | Page 15 of 28 30 ADA4932-1/ADA4932-2 Data Sheet 1.2 0.4 0.1 OUTPUT 0 0.8 0 ERROR –0.4 –0.1 –0.8 –0.2 –1.2 –0.3 –1.6 –0.4 –2.0 –0.5 0 2 4 6 8 10 12 TIME (ns) 14 16 18 20 0 0.2 –2 0 –4 –0.2 –6 –0.4 –8 –0.6 –60 –80 –100 –120 07752-150 1M 10M 100M FREQUENCY (Hz) 0.5 1.0 1.5 2.0 2.5 3.0 Figure 51. PD Response Time CHANNEL 1 TO CHANNEL 2 CHANNEL 2 TO CHANNEL 1 –160 –10 0 TIME (µs) VOUT, dm = 2V p-p RL, dm = 200Ω –140 2 0.4 0 –40 4 VOUT, dm 0.6 Figure 49. Settling Time –20 6 1G Figure 50. Crosstalk vs. Frequency, ADA4932-2 Rev. D | Page 16 of 28 3.5 4.0 PD VOLTAGE (V) 0.2 PD OUTPUT VOLTAGE (V) INPUT 0.8 1.0 ERROR (%) 0.3 07752-149 0.4 1.2 8 GAIN = 9 RL, dm = 200Ω 07752-252 0.5 1.6 CROSSTALK (dB) VOLTAGE (V) 2.0 Data Sheet ADA4932-1/ADA4932-2 TEST CIRCUITS 499Ω DC-COUPLED GENERATOR +5V 50Ω 499Ω 53.6Ω VIN VOCM 1kΩ ADA4932-x 499Ω 07752-043 25.5Ω –5V 499Ω Figure 52. Equivalent Basic Test Circuit, G = 1 NETWORK ANALYZER INPUT NETWORK ANALYZER OUTPUT AC-COUPLED 50Ω +5V 50Ω 499Ω VOCM 53.6Ω VIN 49.9Ω 499Ω ADA4932-x 499Ω NETWORK ANALYZER INPUT –5V 499Ω 0.1µF 49.9Ω 50Ω 07752-044 25.5Ω Figure 53. Test Circuit for Output Balance, CMRR 499Ω DC-COUPLED GENERATOR VIN 0.1µF 442Ω 499Ω LOW-PASS FILTER 53.6Ω VOCM 261Ω ADA4932-x 200Ω 2:1 50Ω DUAL FILTER HP LP CT 0.1µF 442Ω 499Ω 25.5Ω –5V 499Ω Figure 54. Test Circuit for Distortion Measurements Rev. D | Page 17 of 28 07752-045 50Ω +5V ADA4932-1/ADA4932-2 Data Sheet TERMINOLOGY Common-Mode Voltage Common-mode voltage refers to the average of two node voltages with respect to the local ground reference. The output commonmode voltage is defined as –FB RG –OUT +IN VOCM ADA4932-x –DIN RG R F –IN RL, dm VOUT, dm +OUT +FB VOUT, cm = (V+OUT + V−OUT)/2 07752-046 +DIN RF Figure 55. Signal and Circuit Definitions Differential Voltage Differential voltage refers to the difference between two node voltages. For example, the output differential voltage (or equivalently, output differential mode voltage) is defined as VOUT, dm = (V+OUT − V−OUT) where V+OUT and V−OUT refer to the voltages at the +OUT and −OUT terminals with respect to a common ground reference. Similarly, the differential input voltage is defined as Balance Output balance is a measure of how close the output differential signals are to being equal in amplitude and opposite in phase. Output balance is most easily determined by placing a wellmatched resistor divider between the differential voltage nodes and comparing the magnitude of the signal at the divider midpoint with the magnitude of the differential signal (see Figure 53). By this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage. VIN, dm = (+DIN − (−DIN)) Output Balance Error = Rev. D | Page 18 of 28 ∆VOUT , cm ∆VOUT , dm Data Sheet ADA4932-1/ADA4932-2 THEORY OF OPERATION The ADA4932 family differs from conventional op amps in that it has two outputs whose voltages move in opposite directions and an additional input, VOCM. Like an op amp, it relies on high open-loop gain and negative feedback to force these outputs to the desired voltages. The ADA4932 family behaves much like a standard voltage feedback op amp and facilitates single-ended-todifferential conversions, common-mode level shifting, and amplifications of differential signals. Like an op amp, the ADA4932 family has high input impedance and low output impedance. Because it uses voltage feedback, the ADA4932 family manifests a nominally constant gain bandwidth product. Two feedback loops are employed to control the differential and common-mode output voltages. The differential feedback, set with external resistors, controls only the differential output voltage. The common-mode feedback controls only the common-mode output voltage. This architecture makes it easy to set the output common-mode level to any arbitrary value within the specified limits. The output common-mode voltage is forced, by the internal common-mode feedback loop, to be equal to the voltage applied to the VOCM input. The internal common-mode feedback loop produces outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. This results in differential outputs that are very close to the ideal of being identical in amplitude and are exactly 180° apart in phase. Rev. D | Page 19 of 28 ADA4932-1/ADA4932-2 Data Sheet APPLICATIONS INFORMATION ANALYZING AN APPLICATION CIRCUIT The ADA4932 family uses high open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. The differential error voltage is defined as the voltage between the differential inputs labeled +IN and −IN (see Figure 55). For most purposes, this voltage can be assumed to be zero. Similarly, the difference between the actual output common-mode voltage and the voltage applied to VOCM can also be assumed to be zero. Starting from these principles, any application circuit can be analyzed. SETTING THE CLOSED-LOOP GAIN Using the approach described in the Analyzing an Application Circuit section, the differential gain of the circuit in Figure 55 can be determined by V IN , dm VnRG1 RG1 VnRF1 RF1 inIN+ R = F RG + inIN– This presumes that the input resistors (RG) and feedback resistors (RF) on each side are equal. VnIN ADA4932-x VnOD VOCM VnRG2 ESTIMATING THE OUTPUT NOISE VOLTAGE RG2 RF2 VnCM VnRF2 07752-047 VOUT , dm input, and the noise currents, inIN− and inIN+, appear between each input and ground. The output voltage due to vnIN is obtained by multiplying vnIN by the noise gain, GN (defined in the GN equation that follows). The noise currents are uncorrelated with the same mean-square value, and each produces an output voltage that is equal to the noise current multiplied by the associated feedback resistance. The noise voltage density at the VOCM pin is vnCM. When the feedback networks have the same feedback factor, as is true in most cases, the output noise due to vnCM is common mode. Each of the four resistors contributes (4kTRxx)1/2. The noise from the feedback resistors appears directly at the output, and the noise from the gain resistors appears at the output multiplied by RF/RG. Table 11 summarizes the input noise sources, the multiplication factors, and the output-referred noise density terms. Figure 56. Noise Model The differential output noise of the ADA4932 family can be estimated using the noise model in Figure 56. The inputreferred noise voltage density, vnIN, is modeled as a differential Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks Input Noise Contribution Differential Input Inverting Input Noninverting Input VOCM Input Gain Resistor, RG1 Gain Resistor, RG2 Feedback Resistor, RF1 Feedback Resistor, RF2 Input Noise Term vnIN inIN− inIN+ vnCM vnRG1 vnRG2 vnRF1 vnRF2 Input Noise Voltage Density vnIN inIN− × (RF2) inIN+ × (RF1) vnCM (4kTRG1)1/2 (4kTRG2)1/2 (4kTRF1)1/2 (4kTRF2)1/2 Output Multiplication Factor GN 1 1 0 RF1/RG1 RF2/RG2 1 1 Differential Output Noise Voltage Density Term vnO1 = GN(vnIN) vnO2 = (inIN−)(RF2) vnO3 = (inIN+)(RF1) vnO4 = 0 V vnO5 = (RF1/RG1)(4kTRG1)1/2 vnO6 = (RF2/RG2)(4kTRG2)1/2 vnO7 = (4kTRF1)1/2 vnO8 = (4kTRF2)1/2 Table 12. Differential Input, DC-Coupled Nominal Gain (dB) 0 6 10 RF (Ω) 499 499 768 RG (Ω) 499 249 243 RIN, dm (Ω) 998 498 486 Differential Output Noise Density (nV/√Hz) 9.25 12.9 18.2 Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω Nominal Gain (dB) 0 6 10 1 RF (Ω) 511 523 806 RG1 (Ω) 499 249 243 RT (Ω) (Std 1%) 53.6 57.6 57.6 RIN, cm (Ω) 665 374 392 RG2 (Ω)1 525 276 270 RG2 = RG1 + (RS||RT). Rev. D | Page 20 of 28 Differential Output Noise Density (nV/√Hz) 9.19 12.6 17.7 Data Sheet ADA4932-1/ADA4932-2 where: β1 = 2 (β1 + β2 ) is the circuit noise gain. RG1 RG2 and β2 = are the feedback factors. RF1 + RG1 RF2 + RG2 When the feedback factors are matched, RF1/RG1 = RF2/RG2, β1 = β2 = β, and the noise gain becomes GN = R 1 =1+ F β RG Note that the output noise from VOCM goes to zero in this case. The total differential output noise density, vnOD, is the root-sumsquare of the individual output noise terms. v nOD = As a practical summarization of the above issues, resistors of 1% tolerance produce a worst-case input CMRR of approximately 40 dB, a worst-case differential-mode output offset of 25 mV due to a 2.5 V VOCM input, negligible VOCM noise contribution, and no significant degradation in output balance error. CALCULATING THE INPUT IMPEDANCE FOR AN APPLICATION CIRCUIT The effective input impedance of a circuit depends on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, as shown in Figure 57, the input impedance (RIN, dm) between the inputs (+DIN and −DIN) is RIN, dm = RG + RG = 2 × RG. RF +VS 8 2 ∑ vnOi RG +DIN +IN VOCM i =1 –DIN Table 12 and Table 13 list several common gain settings, associated resistor values, input impedance, and output noise density for both balanced and unbalanced input configurations. IMPACT OF MISMATCHES IN THE FEEDBACK NETWORKS RG ADA4932-x VOUT, dm –IN –VS RF Figure 57. ADA4932 Family Configured for Balanced (Differential) Inputs As previously mentioned, even if the external feedback networks (RF/RG) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. The amplitudes of the signals at each output remain equal and 180° out of phase. The input-to-output differential mode gain varies proportionately to the feedback mismatch, but the output balance is unaffected. For an unbalanced, single-ended input signal (see Figure 58), the input impedance is R IN , se R G = RF 1− 2 × (RG + R F ) RF The gain from the VOCM pin to VOUT, dm is equal to 2(β1 − β2)/(β1 + β2) +VS RIN, se When β1 = β2, this term goes to zero and there is no differential output voltage due to the voltage on the VOCM input (including noise). The extreme case occurs when one loop is open and the other has 100% feedback; in this case, the gain from VOCM input to VOUT, dm is either +2 or −2, depending on which loop is closed. The feedback loops are nominally matched to within 1% in most applications, and the output noise and offsets due to the VOCM input are negligible. If the loops are intentionally mismatched by a large amount, it is necessary to include the gain term from VOCM to VOUT, dm and account for the extra noise. For example, if β1 = 0.5 and β2 = 0.25, the gain from VOCM to VOUT, dm is 0.67. If the VOCM pin is set to 2.5 V, a differential offset voltage is present at the output of (2.5 V)(0.67) = 1.67 V. The differential output noise contribution is (9.6 nV/√Hz)(0.67) = 6.4 nV/√Hz. Both of these results are undesirable in most applications; therefore, it is best to use nominally matched feedback factors. Mismatched feedback networks also result in a degradation of the ability of the circuit to reject input common-mode signals, RG VOCM ADA4932-x RL VOUT, dm RG –VS RF 07752-049 GN = much the same as for a four-resistor difference amplifier made from a conventional op amp. 07752-048 Similar to the case of a conventional op amp, the output noise voltage densities can be estimated by multiplying the inputreferred terms at +IN and −IN by the appropriate output factor, Figure 58. ADA4932 Family with Unbalanced (Single-Ended) Input The input impedance of the circuit is effectively higher than it is for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor, RG. The common-mode voltage at the amplifier input terminals can be easily determined by noting that the voltage at the inverting input is equal to the noninverting output voltage divided down by the voltage divider that is formed by RF and RG in the lower loop. This voltage is present at both input terminals due to negative voltage feedback and is in phase Rev. D | Page 21 of 28 ADA4932-1/ADA4932-2 Data Sheet Figure 60 shows that the effective RG in the upper feedback loop is now greater than the RG in the lower loop due to the addition of the termination resistors. To compensate for the imbalance of the gain resistors, add a correction resistor (RTS) in series with RG in the lower loop. RTS is the Thevenin equivalent of the source resistance, RS, and the termination resistance, RT, and is equal to RS||RT. Terminating a Single-Ended Input This section describes how to properly terminate a single-ended input to the ADA4932 family with a gain of 1, RF = 499 Ω, and RG = 499 Ω. An example using an input source with a terminated output voltage of 1 V p-p and source resistance of 50 Ω illustrates the four steps that must be followed. Note that because the terminated output voltage of the source is 1 V p-p, the opencircuit output voltage of the source is 2 V p-p. The source shown in Figure 59 indicates this open-circuit voltage. 1. RS VS 2V p-p RTH 50Ω RT 53.6Ω VTH 1.03V p-p 25.9Ω 07752-052 3. with the input signal, thus reducing the effective voltage across RG in the upper loop and partially bootstrapping RG. Figure 61. Calculating the Thevenin Equivalent The input impedance is calculated using the formula RTS = RTH = RS||RT = 25.9 Ω. Note that VTH is greater than 1 V p-p, which was obtained with RT = 50 Ω. The modified circuit with the Thevenin equivalent (closest 1% value used for RTH) of the terminated source and RTS in the lower feedback loop is shown in Figure 62. R 499 = 665 Ω G R IN , se = = 499 RF 1− 1− × + 2 ( 499 499 ) 2 × (R G + R F ) RF 499Ω +VS RF 499Ω VS 2V p-p +VS RS RG 50Ω 499Ω VOCM VTH 1.03V p-p ADA4932-x RTS 25.5Ω Figure 62. Thevenin Equivalent and Matched Gain Resistors Figure 59. Calculating Single-Ended Input Impedance, RIN Figure 62 presents a tractable circuit with matched feedback loops that can be easily evaluated. To match the 50 Ω source resistance, calculate the termination resistor, RT, using RT||665 Ω = 50 Ω. The closest standard 1% value for RT is 53.6 Ω. It is useful to point out two effects that occur with a terminated input. The first is that the value of RG is increased in both loops, lowering the overall closed-loop gain. The second is that VTH is a little larger than 1 V p-p, as it would be if RT = 50 Ω. These two effects have opposite impacts on the output voltage, and for large resistor values in the feedback loops (~1 kΩ), the effects essentially cancel each other out. For small RF and RG, or high gains, however, the diminished closed-loop gain is not canceled completely by the increased VTH. This can be seen by evaluating Figure 62. RF 499Ω +VS RG 499Ω VOCM ADA4932-x RL VOUT, dm RG 499Ω –VS RF 499Ω 07752-051 VS 2V p-p 499Ω 499Ω 07752-050 RF RT 53.6Ω RL VOUT, dm –VS 499Ω RS ADA4932-x RF –VS 50Ω VOCM RG RG RIN, se 50Ω RG 499Ω RL VOUT, dm 499Ω 2. RTH 25.5Ω 07752-053 RIN, se 665Ω Figure 60. Adding Termination Resistor, RT Rev. D | Page 22 of 28 The desired differential output in this example is 1 V p-p because the terminated input signal was 1 V p-p and the closed-loop gain = 1. The actual differential output voltage, however, is equal to (1.03 V p-p)(499/524.5) = 0.98 V p-p. To obtain the desired output voltage of 1 V p-p, a final gain adjustment can be made by increasing RF without modifying any of the input circuitry. This is discussed in Step 4. Data Sheet 4. ADA4932-1/ADA4932-2 INPUT AND OUTPUT CAPACITIVE AC COUPLING The feedback resistor value is modified as a final gain adjustment to obtain the desired output voltage. To make the output voltage VOUT = 1 V p-p, calculate RF using the following formula: RF = (Desired V OUT , dm )(R G + RTS ) VTH = (1 V p − p)(524.5 Ω) = 509 Ω 1.03 V p − p The closest standard 1% value to 509 Ω is 511 Ω, which gives a differential output voltage of 1.00 V p-p. SETTING THE OUTPUT COMMON-MODE VOLTAGE The final circuit is shown in Figure 63. The VOCM pin of the ADA4932 family is internally biased with a voltage divider comprised of two 50 kΩ resistors across the supplies, with a tap at a voltage approximately equal to the midsupply point, [(+VS) + (−VS)]/2. Because of this internal divider, the VOCM pin sources and sinks current, depending on the externally applied voltage and its associated source resistance. Relying on the internal bias results in an output common-mode voltage that is within about 100 mV of the expected value. RF 511Ω +VS 1V p-p RS VS 2V p-p 50Ω RG RT 53.6Ω 499Ω VOCM ADA4932-x RL VOUT, dm 1.00V p-p RG RTS 25.5Ω While the ADA4932 family is best suited to dc-coupled applications, it is nonetheless possible to use it in ac-coupled circuits. Input ac coupling capacitors can be inserted between the source and RG. This ac coupling blocks the flow of the dc common-mode feedback current and causes the ADA4932 family dc input common-mode voltage to equal the dc output common-mode voltage. These ac coupling capacitors must be placed in both loops to keep the feedback factors matched. Output ac coupling capacitors can be placed in series between each output and its respective load. 499Ω 07752-054 –VS RF 511Ω Figure 63. Terminated Single-Ended-to-Differential System with G = 2 INPUT COMMON-MODE VOLTAGE RANGE The ADA4932 family input common-mode range is shifted down by approximately one VBE, in contrast to other ADC drivers with centered input ranges such as the ADA4939 family. The downward-shifted input common-mode range is especially suited to dc-coupled, single-ended-to-differential, and singlesupply applications. For ±5 V operation, the input common-mode range at the summing nodes of the amplifier is specified as −4.8 V to +3.2 V, and is specified as +0.2 V to +3.2 V with a +5 V supply. To avoid nonlinearities, the voltage swing at the +IN and −IN terminals must be confined to these ranges. In cases where more accurate control of the output commonmode level is required, it is recommended that an external source or resistor divider be used with source resistance less than 100 Ω. If an external voltage divider consisting of equal resistor values is used to set VOCM to midsupply with greater accuracy than produced internally, higher values can be used because the external resistors are placed in parallel with the internal resistors. The output common-mode offset listed in the Specifications section assumes that the VOCM input is driven by a low impedance voltage source. It is also possible to connect the VOCM input to a common-mode level (CML) output of an ADC; however, care must be taken to ensure that the output has sufficient drive capability. The input impedance of the VOCM pin is approximately 25 kΩ. If multiple ADA4932 devices share one ADC reference output, a buffer may be necessary to drive the parallel inputs. Rev. D | Page 23 of 28 ADA4932-1/ADA4932-2 Data Sheet least +6.5 V is needed for symmetry about the common-mode voltage of 2.048 V. HIGH PERFORMANCE PRECISION ADC DRIVER Using a differential amplifier to drive an ADC successfully is linked to balancing each side of the differential amplifier correctly. Figure 65 shows the schematic for the ADA4932-1, AD7626, and associated circuitry. In the test circuit used, the signal source is followed by a 2.4 MHz band-pass filter. The band-pass filter eliminates harmonics of the 2.4 MHz signal and ensures that only the frequency of interest will be passed and processed by the ADA4932-1 and AD7626. The ADA4932-1 is particularly useful when driving higher frequency inputs to the AD7626, a 10 MSPS ADC with a switched capacitor input. The resistor (R8, R9) and capacitor (C5, C6) circuit between the ADA4932-1 and AD7626 IN+ and IN− pins acts as a low-pass filter to noise. The filter limits the input bandwidth to the AD7626, but its main function is to optimize the interface between the driving amplifier and the AD7626. The series resistor isolates the driver amplifier from high frequency switching spikes from the ADC switched capacitor front end. The AD7626 data sheet shows values of 20 Ω and 56 pF. In Figure 65, these values were empirically optimized to 33 Ω and 56 pF. The resistor-capacitor combination can be optimized slightly for the circuit and input frequency being converted by simply varying the R-C combination—however, keep in mind that having the incorrect combination limits the THD and linearity performance of the AD7626. Also, increasing the bandwidth as seen by the ADC introduces more noise. Another aspect of optimization is the selection of the power supply voltages for the ADA4932-1. In the circuit, the output common-mode voltage (VCM pin) of the AD7626 is 2.048 V for the internal reference voltage of 4.096 V, and each input (IN+, IN−) swings between 0 V and 4.096 V, 180° out of phase. This provides an 8.2 V full-scale differential input to the ADC. The ADA4932-1 output stage requires about 1.4 V headroom with respect to each supply voltage for linear operation. Optimum distortion performance is obtained when the supply voltages are approximately symmetrical about the common-mode voltage. If a negative supply of −2.5 V is chosen, then a positive supply of at 07752-064 Experiments performed indicate that a positive supply of 7.25 V gives the best overall distortion for a 2.4 MHz tone. Using a low jitter clock source and a single tone −1 dBFS amplitude, 2.402 MHz input to the AD7626 yielded the results shown in Figure 64 of 88.49 dB SNR and −86.17 dBc THD. At this input level, the ADC limits the SFDR to 83.8 dB. As can be seen from the plot, the harmonics of the fundamental alias back into the pass band. For example, when sampling at 10 MSPS the 3rd harmonic (7.206 MHz) will alias into the pass band at 10.000 MHz – 7.206 MHz = 2.794 MHz. FREQUENCY (MHz) Figure 64. AD7626 Output, 64,000 Point, FFT Plot −1 dBFS Amplitude 2.40173 MHz Input Ton, 10.000 MSPS Sampling Rate The nonharmonic noise admitted through the pass band of the band-pass filter used in the circuit is replaced by the average noise across the Nyquist bandwidth when calculating the SNR and THD. The performance of this or any high speed circuit is highly dependent on proper PCB layout. This includes, but is not limited to, power supply bypassing, controlled impedance lines (where required), component placement, signal routing, and power and ground planes. For a more detailed analysis of this circuit, refer to Circuit Note CN-0105. +5V 0.1µF 0.1µF +2.048V AD8031 +7.25V 5 0.1µF 6 7 8 +5V R6 499Ω 1 2.4MHz BPF R3 499Ω 2 R2 53.6Ω R1 53.6Ω C1 2.2nF R4 39Ω 11 +IN 9 VOCM 3 –IN –OUT R8 33Ω R7 499Ω 4 +2.5V 0.1µF +2.5V 0.1µF +4.096V TO 0V VCM IN– VDD1 VDD2 VIO C5 56pF ADA4932-1 0.1µF R5 499Ω 0.1µF +VS –FB AD7626 +OUT 10 R9 33Ω IN+ C6 56pF +FB GND 0V TO +4.096V –VS PAD 16 15 –2.5V 14 13 0.1µF Figure 65. ADA4932-1 Driving the AD7626 (All Connections and Decoupling Not Shown) Rev. D | Page 24 of 28 07752-065 FROM 50Ω SIGNAL SOURCE Data Sheet ADA4932-1/ADA4932-2 HIGH PERFORMANCE ADC DRIVING In this example, the signal generator has a 1 V p-p symmetric, ground-referenced bipolar output when terminated in 50 Ω. The VOCM input is bypassed for noise reduction, and set externally with 1% resistors to maximize output dynamic range on the tight 3.3 V supply. The ADA4932 family is ideally suited for broadband dc-coupled applications. The circuit in Figure 66 shows a front-end connection for an ADA4932-1 driving an AD9245, a 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS ADC, with dc coupling on the ADA4932-1 input and output. (The AD9245 achieves its optimum performance when driven differentially.) The ADA4932-1 eliminates the need for a transformer to drive the ADC and performs a single-ended-to-differential conversion and buffering of the driving signal. Because the inputs are dc-coupled, dc common-mode current flows in the feedback loops, and a nominal dc level of 0.84 V is present at the amplifier input terminals. A fraction of the output signal is also present at the input terminals as a common-mode signal; its level is equal to the ac output swing at the noninverting output, divided down by the feedback factor of the lower loop. In this example, this ripple is 0.5 V p-p × [524.5/(524.5 + 511)] = 0.25 V p-p. This ac signal is riding on the 0.84 V dc level, producing a voltage swing between 0.72 V and 0.97 V at the input terminals. This is well within the specified limits of 0.2 V to 1.5 V. The ADA4932-1 is configured with a single 3.3 V supply and a gain of 1 for a single-ended input to differential output. The 53.6 Ω termination resistor, in parallel with the single-ended input impedance of approximately 665 Ω, provides a 50 Ω termination for the source. The additional 25.5 Ω (524.5 Ω total) at the inverting input balances the parallel impedance of the 50 Ω source and the termination resistor driving the noninverting input. With an output common-mode voltage of 1.65 V, each ADA4932-1 output swings between 1.4 V and 1.9 V, opposite in phase, providing a gain of 1 and a 1 V p-p differential signal to the ADC input. The differential RC section between the ADA4932-1 output and the ADC provides single-pole low-pass filtering and extra buffering for the current spikes that are output from the ADC input when its SHA capacitors are discharged. The AD9245 is configured for a 1 V p-p full-scale input by connecting its SENSE pin to VREF, as shown in Figure 66. 511Ω VOUT, dm = 1V p-p VOUT, cm = 1.65V 3.3V 0.1µF 10kΩ 1% 50Ω 499Ω 2V p-p SIGNAL GENERATOR 0.1µF 33Ω VOCM 53.6Ω 10kΩ 1% 0.1µF ADA4932-1 AVDD 20pF 499Ω 33Ω 25.5Ω VIN– 0.1µF AD9245 VIN+ VREF SENSE AGND 10µF + 511Ω Figure 66. ADA4932-1 Driving an AD9245 ADC with DC-Coupled Input and Output Rev. D | Page 25 of 28 07752-270 1V p-p CENTERED AT GROUND ADA4932-1/ADA4932-2 Data Sheet LAYOUT, GROUNDING, AND BYPASSING Bypass the power supply pins as close to the device as possible and directly to a nearby ground plane. High frequency ceramic chip capacitors should be used. It is recommended that two parallel bypass capacitors (1000 pF and 0.1 μF) be used for each supply. Place the 1000 pF capacitor closer to the device. Further away, provide low frequency bulk bypassing using 10 μF tantalum capacitors from each supply to ground. As a high speed device, the ADA4932 family is sensitive to the PCB environment in which it operates. Realizing its superior performance requires attention to the details of high speed PCB design. The first requirement is a solid ground plane that covers as much of the board area around the ADA4932 family as possible. However, the area near the feedback resistors (RF), gain resistors (RG), and the input summing nodes (Pin 2 and Pin 3) should be cleared of all ground and power planes (see Figure 67). Clearing the ground and power planes minimizes any stray capacitance at these nodes and thus minimizes peaking of the response of the amplifier at high frequencies. Signal routing should be short and direct to avoid parasitic effects. Wherever complementary signals exist, provide a symmetrical layout to maximize balanced performance. When routing differential signals over a long distance, keep PCB traces close together, and twist any differential wiring to minimize loop area. Doing this reduces radiated energy and makes the circuit less susceptible to interference. The thermal resistance, θJA, is specified for the device, including the exposed pad, soldered to a high thermal conductivity 4-layer circuit board, as described in EIA/JESD51-7. 1.30 0.80 07752-055 07752-056 1.30 0.80 Figure 68. Recommended PCB Thermal Attach Pad Dimensions (Millimeters) Figure 67. Ground and Power Plane Voiding in Vicinity of RF and RG 1.30 TOP METAL GROUND PLANE 0.30 PLATED VIA HOLE 07752-057 POWER PLANE BOTTOM METAL Figure 69. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters) Rev. D | Page 26 of 28 Data Sheet ADA4932-1/ADA4932-2 OUTLINE DIMENSIONS 3.00 BSC SQ 0.60 MAX 0.45 TOP VIEW 13 16 12 (BOTTOM VIEW) 1 2.75 BSC SQ EXPOSED PAD 9 0.50 BSC 0.80 MAX 0.65 TYP 12° MAX 1.00 0.85 0.80 0.30 0.23 0.18 8 5 4 0.25 MIN 1.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM SEATING PLANE PIN 1 INDICATOR *1.45 1.30 SQ 1.15 0.20 REF 072208-A PIN 1 INDICATOR 0.50 0.40 0.30 *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 70. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-16-2) Dimensions shown in millimeters 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 0.50 BSC 24 19 18 PIN 1 INDICATOR 1 2.40 2.30 SQ 2.20 EXPOSED PAD 6 13 0.80 0.75 0.70 SEATING PLANE 0.50 0.40 0.30 12 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.30 0.25 0.20 7 BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 01-18-2012-A TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8. Figure 71. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-24-14) Dimensions shown in millimeters ORDERING GUIDE Model1 ADA4932-1YCPZ-R2 ADA4932-1YCPZ-RL ADA4932-1YCPZ-R7 ADA4932-1YCP-EBZ ADA4932-2YCPZ-R2 ADA4932-2YCPZ-RL ADA4932-2YCPZ-R7 ADA4932-2YCP-EBZ 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ Evaluation Board 24-Lead LFCSP_WQ 24-Lead LFCSP_WQ 24-Lead LFCSP_WQ Evaluation Board Z = RoHS Compliant Part. Rev. D | Page 27 of 28 Package Option CP-16-2 CP-16-2 CP-16-2 Ordering Quantity 250 5,000 1,500 CP-24-14 CP-24-14 CP-24-14 250 5,000 1,500 Branding H1K H1K H1K ADA4932-1/ADA4932-2 Data Sheet NOTES ©2008–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07752-0-4/14(D) Rev. D | Page 28 of 28