AD AD8139ARD

Low Noise Rail-to-Rail
Differential ADC Driver
AD8139
FEATURES
APPLICATIONS
Fully differential
Low noise
2.25 nV/√Hz
2.1 pA/√Hz
Low harmonic distortion
98 dBc SFDR @ 1 MHz
85 dBc SFDR @ 5 MHz
72 dBc SFDR @ 20 MHz
High speed
410 MHz, 3 dB BW (G = 1)
800 V/µs slew rate
45 ns settling time to 0.01%
69 dB output balance @ 1 MHz
80 dB dc CMRR
Low offset: ±0.5 mV max
Low input offset current: 0.5 µA max
Differential input and output
Differential-to-differential or single-ended-to-differential
operation
Rail-to-rail output
Adjustable output common-mode voltage
Wide supply voltage range: 5 V to 12 V
Available in small SOIC package
ADC drivers to 18 bits
Single-ended-to-differential converters
Differential filters
Level shifters
Differential PCB board drivers
Differential cable drivers
GENERAL DESCRIPTION
The AD8139 is available in an 8-lead SOIC package with an
exposed paddle (EP) on the underside of its body and a 3 mm ×
3 mm LFCSP. It is rated to operate over the temperature range
of −40°C to +125°C.
8
+IN
VOCM 2
7
NC
V+ 3
6
V–
+OUT 4
5
–OUT
NC = NO CONNECT
04679-0-001
–IN 1
Figure 1.
100
10
1
10
04679-0-078
The AD8139 is manufactured on ADI’s proprietary second generation XFCB process, enabling it to achieve low levels of distortion with input voltage noise of only 1.85 nV/√Hz.
AD8139
INPUT VOLTAGE NOISE (nV/ Hz)
The AD8139 is an ultralow noise, high performance differential
amplifier with rail-to-rail output. With its low noise, high SFDR,
and wide bandwidth, it is an ideal choice for driving ADCs with
resolutions to 18 bits. The AD8139 is easy to apply, and its internal common-mode feedback architecture allows its output
common-mode voltage to be controlled by the voltage applied
to one pin. The internal feedback loop also provides outstanding output balance as well as suppression of even-order
harmonic distortion products. Fully differential and singleended-to-differential gain configurations are easily realized by
the AD8139. Simple external feedback networks consisting of a
total of four resistors determine the amplifier’s closed-loop gain.
FUNCTIONAL BLOCK DIAGRAM
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
1G
Figure 2. Input Voltage Noise vs. Frequency
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD8139
TABLE OF CONTENTS
VS = ±5 V, VOCM = 0 V Specifications.............................................. 3
Typical Connection and Definition of Terms ........................ 18
VS = 5 V, VOCM = 2.5 V Specifications ............................................. 5
Applications..................................................................................... 19
Absolute Maximum Ratings............................................................ 7
Estimating Noise, Gain, and Bandwidth with Matched
Feedback Networks .................................................................... 19
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 18
REVISION HISTORY
8/04—Data Sheet Changed from a Rev. 0 to Rev. A.
Added 8-Lead LFCSP.........................................................Universal
Changes to General Description .................................................... 1
Changes to Figure 2.......................................................................... 1
Changes to VS = ±5 V, VOCM = 0 V Specifications ......................... 3
Changes to VS = 5 V, VOCM = 2.5 V Specifications......................... 5
Changes to Table 4............................................................................ 7
Changes to Maximum Power Dissipation Section....................... 7
Changes to Figure 26 and Figure 29............................................. 12
Inserted Figure 39 and Figure 42.................................................. 14
Changes to Figure 45 to Figure 47................................................ 15
Inserted Figure 48........................................................................... 15
Changes to Figure 52 and Figure 53............................................. 16
Changes to Figure 55 and Figure 56............................................. 17
Changes to Table 6.......................................................................... 19
Changes to Voltage Gain Section.................................................. 19
Changes to Driving a Capacitive Load Section .......................... 22
Changes to Ordering Guide .......................................................... 24
Updated Outline Dimensions ....................................................... 24
5/04—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD8139
VS = ±5 V, VOCM = 0 V SPECIFICATIONS
@ 25°C, Diff. Gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
Table 1.
Parameter
DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.01%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
SFDR
Third-Order IMD
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Output Balance Error
VOCM to VO, cm PERFORMANCE
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Gain
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Input Bias Current
CMRR
Conditions
Min
Typ
VO, dm = 0.1 V p-p
VO, dm = 2 V p-p
VO, dm = 0.1 V p-p
VO, dm = 2 V Step
VO, dm = 2 V Step, CF = 2 pF
G = 2, VIN, dm = 12 V p-p Triangle Wave
340
210
410
240
45
800
45
30
MHz
MHz
MHz
V/µs
ns
ns
98
85
72
−90
2.25
2.1
dB
dB
dB
dBc
nV/√Hz
pA/√Hz
VO, dm = 2 V p-p, fC = 1 MHz
VO, dm = 2V p-p, fC = 5 MHz
VO, dm = 2 V p-p, fC = 20 MHz
VO, dm = 2 V p-p, fC = 10.05 MHz ± 0.05 MHz
f = 100 KHz
f = 100 KHz
VIP = VIN = VOCM = 0 V
TMIN to TMAX
TMIN to TMAX
−500
±150
1.25
2.25
0.12
114
−4
Differential
Common Mode
Common Mode
∆VICM = ±1 V dc, RF = RG = 10 kΩ
Each Single-Ended Output, RF = RG = 10 kΩ
Each Single-Ended Output,
RL, dm = Open Circuit, RF = RG = 10 kΩ
Each Single-Ended Output
f = 1 MHz
80
0.999
−900
∆VOCM/∆VO, dm, ∆VOCM = ±1 V
74
Rev. A | Page 3 of 24
8.0
0.5
Unit
µV
µV/ºC
µA
µA
dB
+4
V
kΩ
MΩ
pF
dB
+VS – 0.20
+VS – 0.15
V
V
100
−69
mA
dB
515
250
1.000
MHz
V/µs
V/V
−3.8
VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 0 V
f = 100 kHz
+500
600
1.5
1.2
84
−VS + 0.20
−VS + 0.15
VO, cm = 0.1 V p-p
VO, cm = 2 V p-p
Max
1.001
+3.8
3.5
±300
3.5
1.3
88
+900
4.5
V
MΩ
µV
nV/√Hz
µA
dB
AD8139
Parameter
POWER SUPPLY
Operating Range
Quiescent Current
+PSRR
−PSRR
OPERATING TEMPERATURE RANGE
Conditions
Min
Typ
4.5
Change in +VS = ±1V
Change in −VS = ±1V
Rev. A | Page 4 of 24
95
95
−40
24.5
112
109
Max
Unit
±6
25.5
V
mA
dB
dB
°C
+125
AD8139
VS = 5 V, VOCM = 2.5 V SPECIFICATIONS
@ 25°C, Diff. Gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
Table 2.
Parameter
DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.01%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
SFDR
Third-Order IMD
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Output Balance Error
VOCM to VO, cm PERFORMANCE
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Gain
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Input Bias Current
CMRR
Conditions
Min
Typ
VO, dm = 0.1 V p-p
VO, dm = 2 V p-p
VO, dm = 0.1 V p-p
VO, dm = 2 V Step
VO, dm = 2 V Step
G = 2, VIN, dm = 7 V p-p Triangle Wave
330
135
385
165
34
540
55
35
MHz
MHz
MHz
V/μs
ns
ns
99
87
75
−87
2.25
2.1
dB
dB
dB
dBc
nV/√Hz
pA/√Hz
VO, dm = 2 V p-p, fC = 1 MHz
VO, dm = 2 V p-p, fC = 5 MHz, (RL = 800 Ω)
VO, dm = 2 V p-p, fC = 20 MHz, (RL = 800 Ω)
VO, dm = 2 V p-p, fC = 10.05 MHz ± 0.05 MHz
f = 100 kHz
f = 100 kHz
VIP = VIN = VOCM =0 V
TMIN to TMAX
TMIN to TMAX
−500
±150
1.25
2.2
0.13
112
1
Differential
Common-Mode
Common-Mode
∆VICM = ±1 V dc, RF = RG = 10 kΩ
Each Single-Ended Output, RF = RG = 10 kΩ
Each Single-Ended Output,
RL, dm = Open Circuit, RF = RG = 10 kΩ
Each Single-Ended Output
f = 1 MHz
75
0.999
−1.0
∆VOCM/∆VO(dm), ∆VOCM = ±1 V
67
Rev. A | Page 5 of 24
7.5
0.5
Unit
µV
µV/ºC
μA
µA
dB
4
V
KΩ
MΩ
pF
dB
+VS − 0.15
+VS − 0.10
V
V
80
−70
mA
dB
440
150
1.000
MHz
V/μs
V/V
1.0
VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 2.5 V
f = 100 KHz
+500
600
1.5
1.2
79
−VS + 0.15
−VS + 0.10
VO, cm = 0.1 V p-p
VO, cm = 2 V p-p
Max
1.001
3.8
3.5
±0.45
3.5
1.3
79
+1.0
4.2
V
MΩ
mV
nV/√Hz
μA
dB
AD8139
Parameter
POWER SUPPLY
Operating Range
Quiescent Current
+PSRR
−PSRR
OPERATING TEMPERATURE RANGE
Conditions
Min
Typ
+4.5
Change in +VS = ±1 V
Change in −VS = ±1 V
Rev. A | Page 6 of 24
86
92
−40
21.5
97
105
Max
Unit
±6
22.5
V
mA
dB
dB
°C
+125
AD8139
ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Parameter
Supply Voltage
VOCM
Power Dissipation
Input Common-Mode Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
Rating
12 V
±VS
See Figure 3
±VS
–65°C to +125°C
–40°C to +125°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Airflow reduces θJA. Also, more metal directly in contact with
the package leads from metal traces, through holes, ground, and
power planes will reduce the θJA.
Figure 3 shows the maximum safe power dissipation in the
package versus the ambient temperature for the exposed paddle
(EP) SOIC-8 (θJA = 70°C/W) package and LFCSP (θJA =
70°C/W) on a JEDEC standard 4-layer board. θJA values are
approximations.
4.0
Table 4. Thermal Resistance
3.5
Package Type
SOIC-8 with EP/4-Layer
LFCSP/4-Layer
θJA
70
70
MAXIMUM POWER DISSIPATION (W)
θJA is specified for the worst-case conditions, i.e., θJA is specified
for device soldered in circuit board for surface-mount packages.
Unit
°C/W
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8139 package is
limited by the associated rise in junction temperature (TJ) on the
die. At approximately 150°C, which is the glass transition temperature, the plastic will change its properties. Even temporarily
exceeding this temperature limit may change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8139. Exceeding a junction temperature of
175°C for an extended period of time can result in changes in the
silicon devices potentially causing failure.
3.0
2.5
2.0
1.5
SOIC
AND LFCSP
1.0
04679-0-055
Table 3.
0.5
0
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
100
120
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Rev. A | Page 7 of 24
AD8139
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
8
+IN
VOCM 2
7
NC
V+ 3
6
V–
+OUT 4
5
–OUT
NC = NO CONNECT
04679-0-003
AD8139
–IN 1
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
3
4
5
6
7
8
V+
+OUT
−OUT
V−
NC
+IN
Description
Inverting Input.
An internal feedback loop drives the output common-mode voltage to be equal to the
voltage applied to the VOCM pin, provided the amplifier’s operation remains linear.
Positive Power Supply Voltage.
Positive Side of the Differential Output.
Negative Side of the Differential Output.
Negative Power Supply Voltage.
No Internal Connection.
Noninverting Input.
RF
50Ω
VTEST
CF
RG = 200Ω
60.4Ω
VOCM
RL, dm = 1kΩ
AD8139
60.4Ω
TEST
SIGNAL
SOURCE
RG = 200Ω
–
VO, dm
+
04679-0-072
Mnemonic
−IN
VOCM
CF
50Ω
RF
Figure 5. Basic Test Circuit
RF = 200Ω
50Ω
RS
RG = 200Ω
60.4Ω
VTEST
VOCM
CL, dm
AD8139
60.4Ω
TEST
SIGNAL
SOURCE
RG = 200Ω
RS
50Ω
RF = 200Ω
Figure 6. Capacitive Load Test Circuit, G = +1
Rev. A | Page 8 of 24
–
RL, dm VO, dm
+
04679-0-075
Pin No.
1
2
AD8139
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, Diff. Gain = +1, RG = RF = 200 Ω, RL, dm = 1 kΩ, VS = ±5 V, TA = 25°C, VOCM = 0 V. Refer to the basic test circuit in
Figure 5 for the definition of terms.
2
2
G=2
–1
–2
–3
–4
–5
G=5
–6
–7
G = 10
–8
–9
–10
RG = 200Ω
VO, dm = 0.1V p-p
–13
1
10
100
FREQUENCY (MHz)
–6
–8
–9
–10
–11
RG = 200Ω
VO, dm = 2.0V p-p
10
100
FREQUENCY (MHz)
1000
Figure 10. Large Signal Frequency Response for Various Gains
3
2
1
2
0
1
–1
0
VS = ±5V
–1
–2
–3
–4
–5
–6
–2
VS = ±5V
–3
–4
VS = +5V
–5
–6
–7
–8
–9
04679-0-005
–7
–8
VO, dm = 0.1V p-p
–10
10
100
FREQUENCY (MHz)
–10
–11
3
1000
3
–1
CLOSED-LOOP GAIN (dB)
0
–1
–2
–3
–4
–40°C
–6
–7
–8
+85°C
–2
–3
–4
–5
–6
–7
–8
–9
VO, dm = 0.1V p-p
+25°C
100
FREQUENCY (MHz)
04679-0-006
–9
–10
1000
1
0
–5
+125°C
2
+85°C
1
100
FREQUENCY (MHz)
Figure 11. Large Signal Frequency Response for Various Power Supplies
+125°C
2
VO, dm = 2.0V p-p
–12
10
Figure 8. Small Signal Frequency Response for Various Power Supplies
–12
10
G = 10
–7
1
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
–5
–13
VS = +5V
3
CLOSED-LOOP GAIN (dB)
–4
1000
5
4
–11
G=2
–3
–12
Figure 7. Small Signal Frequency Response for Various Gains
–9
G=5
–2
04679-0-008
–12
–1
–40°C
–10
–11
–12
10
1000
Figure 9. Small Signal Frequency Response at Various ΩTemperatures
Rev. A | Page 9 of 24
VO, dm = 2.0V p-p
100
FREQUENCY (MHz)
+25°C
04679-0-009
–11
0
04679-0-007
NORMALIZED CLOSED-LOOP GAIN (dB)
0
G=1
1
G=1
04679-0-004
NORMALIZED CLOSED-LOOP GAIN (dB)
1
1000
Figure 12. Large Signal Frequency Response at Various Temperatures
AD8139
3
RL = 200Ω
2
RL = 100Ω
1
0
0
–1
–1
–2
RL = 500Ω
–3
–4
–5
–6
–7
–8
RL = 1kΩ
100
FREQUENCY (MHz)
3
1
–5
–6
–7
–8
RL = 1kΩ
–9
VO, dm = 2.0V p-p
–13
10
1000
2
1000
CF = 1pF
0
CLOSED-LOOP GAIN (dB)
–1
–2
CF = 2pF
–4
CF = 0pF
1
–1
–3
RL = 200Ω
100
FREQUENCY (MHz)
Figure 16. Large Signal Frequency Response for Various Loads
CF = 1pF
0
–5
–6
–7
–8
–2
CF = 2pF
–3
–4
–5
–6
–7
–8
–9
04679-0-011
–10
VO, dm = 0.1V p-p
–12
10
100
FREQUENCY (MHz)
–11
–12
VOCM = +4.3V
5
1000
VOCM = +4V
NORMALIZED CLOSED-LOOP GAIN (dB)
3
VOCM = –4V
2
1
0
VOCM = 0V
–1
–2
–3
–4
–5
04679-0-012
–6
–7
VO, dm = 0.1V p-p
100
FREQUENCY (MHz)
100
FREQUENCY (MHz)
1000
Figure 17. Large Signal Frequency Response for Various CF
0.5
VOCM = –4.3V
4
VO, dm = 2.0V p-p
–13
10
Figure 14. Small Signal Frequency Response for Various CF
6
04679-0-014
–10
–9
RL = 100Ω
(VO, dm = 0.1V p-p)
0.4
RL = 100Ω
(VO, dm = 2.0V p-p)
0.3
RL = 1kΩ
(VO, dm = 2.0V p-p)
0.2
0.1
RL = 1kΩ
(VO, dm = 0.1V p-p)
0
–0.1
–0.2
–0.3
04679-0-042
CLOSED-LOOP GAIN (dB)
–4
–12
CF = 0pF
2
CLOSED-LOOP GAIN (dB)
–3
–11
Figure 13. Small Signal Frequency Response for Various Loads
–9
10
–2
04679-0-041
04679-0-040
–11 V
O, dm = 0.1V p-p
–12
10
–8
RL = 500Ω
–10
–9
–10
–11
RL = 100Ω
1
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
2
–0.4
–0.5
1
1000
10
FREQUENCY (Hz)
100
Figure 18. 0.1 dB Flatness for Various Loads and Output Amplitudes
Figure 15. Small Signal Frequency Response at Various VOCM
Rev. A | Page 10 of 24
AD8139
–30
–30
VO, dm = 2.0V p-p
–40
–40
–50
–50
–60
–60
VS = ±5V
DISTORTION (dBc)
–70
–80
VS = +5V
–90
–100
–130
0.1
–90
–100
1
10
FREQUENCY (MHz)
–120
–130
0.1
100
Figure 19. Second Harmonic Distortion vs. Frequency and Supply Voltage
1
10
FREQUENCY (MHz)
100
Figure 22. Third Harmonic Distortion vs. Frequency and Supply Voltage
–30
–30
VO, dm = 2.0V p-p
–40
–50
VO, dm = 2.0V p-p
–50
–60
–60
DISTORTION (dB)
G=1
–70
–80
G=5
–90
–100
G=2
–70
–80
–90
–100
–110
–110
–120
–120
04679-0-016
DISTORTION (dB)
VS = ±5V
–80
04679-0-018
–120
–40
–70
–110
04679-0-015
–110
VS = +5V
–130
–140
0.1
1
10
FREQUENCY (MHz)
G=1
G=2
04679-0-019
DISTORTION (dBc)
VO, dm = 2.0V p-p
–130
–140
0.1
100
Figure 20. Second Harmonic Distortion vs. Frequency and Gain
G=5
1
10
FREQUENCY (MHz)
100
Figure 23. Third Harmonic Distortion vs. Frequency and Gain
–30
–30
VO, dm = 2.0V p-p
VO, dm = 2.0V p-p
–40
–40
–50
–50
RL = 200Ω
–80
–90
RL = 500Ω
–100
–60
RL = 200Ω
–70
–80
–90
–100
RL = 1kΩ
–110
–120
–130
0.1
RL = 500Ω
–110
1
10
FREQUENCY (MHz)
04679-0-020
DISTORTION (dBc)
–70
RL = 100Ω
04679-0-017
DISTORTION (dBc)
RL = 100Ω
–60
–120
RL = 1kΩ
–130
0.1
100
Figure 21. Second Harmonic Distortion vs. Frequency and Load
1
10
FREQUENCY (MHz)
100
Figure 24. Third Harmonic Distortion vs. Frequency and Load
Rev. A | Page 11 of 24
AD8139
–30
–30
VO, dm = 2.0V p-p
–40
–40
–50
–50
–60
–60
RF = 200Ω
–80
RF = 500Ω
–90
–100
–110
–70
–80
–90
RF = 200Ω
–100
04679-0-021
–110
RF = 1kΩ
–120
–130
0.1
1
10
FREQUENCY (MHz)
RF = 1kΩ
–120
RF = 500Ω
–130
0.1
100
Figure 25. Second Harmonic Distortion vs. Frequency and RF
1
10
FREQUENCY (MHz)
–80
FC = 2MHz
FC = 2MHz
VS = ±5V
–90
–90
VS = +5V
VS = +5V
–100
–110
–120
VS = ±5V
–110
–120
–130
–140
–140
04679-0-022
–130
–150
0
1
2
3
4
5
VO, dm (V p-p)
6
7
04679-0-025
DISTORTION (dBc)
–100
–150
8
0
Figure 26. Second Harmonic Distortion Vs. Output Amplitude
1
2
3
4
5
VO, dm (V p-p)
6
7
8
Figure 29. Third Harmonic Distortion vs. Output Amplitude
–60
–60
VO, dm = 2V p-p
FC = 2MHz
VO, dm = 2V p-p
FC = 2MHz
–70
–80
–80
–90
DISTORTION (dBc)
–70
SECOND HARMONIC
–100
–110
–90
SECOND HARMONIC
–100
–110
THIRD HARMONIC
–130
0
0.5
1.0
1.5
2.0
2.5
3.0
VOCM (V)
–120
04679-0-023
–120
3.5
4.0
4.5
04679-0-026
DISTORTION (dBc)
100
Figure 28. Third Harmonic Distortion vs. Frequency and RF
–80
DISTORTION (dBc)
04679-0-024
–70
DISTORTION (dBc)
DISTORTION (dBc)
VO, dm = 2.0V p-p
THIRD HARMONIC
–130
–5
5.0
Figure 27. Harmonic Distortion vs. VOCM, VS = +5 V
–4
–3
–2
–0
0
1
VOCM (V)
2
3
4
Figure 30. Harmonic Distortion vs. VOCM, VS = ±5 V
Rev. A | Page 12 of 24
5
AD8139
100
2.5
VO, dm = 100mV p-p
CF = 0pF
4V p-p
2.0
75
CF = 2pF
1.5
CF = 0pF
50
VO, dm (V)
1.0
VO, dm
(CF = 2pF, VS = ±5V)
VO, dm (V)
CF = 0pF
(CF = 0pF,
VS = ±5V)
25
0
–25
CF = 2pF
0.5
2V p-p
0
–0.5
–1.0
–50
–2.0
5ns/DIV
–2.5
TIME (ns)
TIME (ns)
Figure 31. Small Signal Transient Response for Various CF
0.100
04679-0-044
5ns/DIV
–100
04679-0-043
–1.5
–75
Figure 34. Large Signal Transient Response For CF
1.5
RS = 31.6Ω
CL, dm = 30pF
RS = 63.4Ω
CL, dm = 15pF
0.075
1.0
0.050
RS = 31.6Ω
CL, dm = 30pF
0.5
RS = 63.4Ω
CL, dm = 15pF
VO, dm (V)
VO, dm (V)
0.025
0
0
–0.025
–0.5
–1.0
04679-0-064
–0.075
5ns/DIV
–0.100
5ns/DIV
–1.5
TIME (ns)
TIME (ns)
Figure 35. Large Signal Transient Response for Capacitive Loads
600
1.0
400
0.5
200
0
0
ERROR
–0.5
–200
VO, dm
–1.0
–400
35ns/DIV
VIN
–1.5
9.95 10.05 10.15 10.25 10.35 10.45 10.55
FREQUENCY (MHz)
–600
TIME (ns)
Figure 36. Settling Time (0.01%)
Figure 33. Intermodulation Distortion
Rev. A | Page 13 of 24
ERROR (µV) 1DIV = 0.01%
CF = 2pF
VO, dm = 2.0V p-p
04679-0-034
AMPLITUDE (V)
1.5
04679-0-027
NORMALIZED OUTPUT (dBc)
Figure 32. Small Signal Transient Response for Capacitive Loads
5
0 VO, dm = 2V p-p
–5 FC1 = 10MHz
–10 FC2 = 10.1MHz
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
9.55 9.65 9.75 9.85
04679-0-065
–0.050
AD8139
6
±5V
5
4
1.0
CLOSED-LOOP GAIN (dB)
+5V
0
–0.5
VO, cm = 2V p-p
VIN, dm = 0V
1
0
VO, cm = 0.1V p-p
–1
–2
VS = ±5V
–3
10ns/DIV
–1.5
–5
–7
VS = +5V
–8
–9
10
TIME (ns)
0
VIN, cm = 0.2V p-p
INPUT CMRR = ∆VO, cm/∆VIN, cm
–10
–30
–30
VOCM CMRR (dB)
–20
RF = RG = 10kΩ
–50
–60
RF = RG = 200Ω
–80
–90
1
10
FREQUENCY (MHz)
–40
–50
–60
–70
04679-0-066
–70
100
–80
–90
1
500
10
FREQUENCY (MHz)
500
100
04679-0-079
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
10
1
10
1G
Figure 39. Input Voltage Noise vs. Frequency
04679-0-080
VOCM NOISE (nV/ Hz)
100
INPUT VOLTAGE NOISE (nV/ Hz)
100
Figure 41. VOCM CMRR vs. Frequency
Figure 38. CMRR vs. Frequency
1
10
1000
VO, cm = 0.2V p-p
VOCM CMRR = ∆VO, dm/∆VO, cm
–10
–20
–40
100
FREQUENCY (MHz)
Figure 40. VOCM Frequency Response for Various Supplies
Figure 37. VOCM Large Signal Transient Response
0
VS = ±5V
VO, cm = 2.0V p-p
–4
–6
04679-0-069
–1.0
2
04679-0-045
VOCM (V)
0.5
CMRR (dB)
VS = +5V
3
04679-0-038
1.5
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 42. VOCM Voltage Noise vs. Frequency
Rev. A | Page 14 of 24
1G
AD8139
0
14
RL, dm = 1kΩ
–10 PSRR = ∆VO, dm/∆VS
2 × VIN, dm
G=2
12
8
–30
6
–40
–PSRR
–50
+PSRR
–60
VO, dm
4
VOLTAGE (V)
2
0
–2
–4
–70
–6
04679-0-047
–10
–90
–100
1
10
FREQUENCY (MHz)
100
–12
50ns/DIV
–14
500
TIME (ns)
Figure 46. Overdrive Recovery
Figure 43. PSRR vs. Frequency
0
VO, dm = 1V p-p
OUTPUT BALANCE = ∆VO, cm/∆VO, dm
100
–10
OUTPUT BALANCE (dB)
10
VS = ±5V
1
–20
–30
–40
–50
–60
–70
1
10
FREQUENCY (MHz)
100
–80
1
10
FREQUENCY (MHz)
1000
300
700
600
VOP SWING FROM RAIL (mV)
500
400
VS+ – VOP
200
100
VS = ±5V
0
VS = +5V
–100
–200
VON – VS–
–300
–400
04679-0-068
–500
–600
–700
100
1k
RESISTIVE LOAD (Ω)
500
Figure 47. Output Balance vs. Frequency
Figure 44. Single-Ended Output Impedance vs. Frequency
300
100
250
Figure 45. Output Saturation Voltage vs. Output Load
–100
VS+ – VOP
200
–150
150
–200
VON – VS–
100
50
–40
10k
–50
VS = ±5V
G = 1 (RF = RG = 200Ω)
RL, dm = 1kΩ
–250
–300
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 48. Output Saturation Voltage vs. Temperature
Rev. A | Page 15 of 24
VON SWING FROM RAIL (mV)
0.01
0.1
04679-0-067
0.1
04679-0-028
OUTPUT IMPEDANCE (Ω)
VS = +5V
SINGLE-ENDED OUTPUT SWING FROM RAIL (mV)
04679-0-046
–8
–80
04679-0-077
PSRR (dB)
10
–20
AD8139
170
3.0
26
IOS
25
145
SUPPLY CURRENT (mA)
IOS (nA)
2.0
120
95
70
–20
0
20
40
60
TEMPERATURE (°C)
80
100
24
23
VS = +5V
22
21
04679-0-062
1.5
20
–40
120
Figure 49. Input Bias and Offset Current vs. Temperature
–20
100
120
600
250
400
200
200
VS = +5V
2
0
–2
–4
04679-0-073
–6
–8
–4
–3
–2
–1
0
1
VACM (V)
2
3
4
150
0
VOS, dm
100
–200
50
–400
0
–40
5
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 53. Offset Voltage vs. Temperature
Figure 50. Input Bias Current vs.
Input Common-Mode Voltage
50
5
45
4
–600
–20
COUNT = 350
MEAN = –50µV
STD DEV = 100µV
40
VS = ±2.5V
3
FREQUENCY
35
2
VS = ±5V
1
0
–1
30
25
20
15
–2
–4
–3
–2
–1
0
1
VOCM (V)
2
3
4
0
5
–500
–450
–400
–350
–300
–250
–200
–150
–100
–50
0
50
100
150
200
250
300
350
400
450
500
5
04679-0-048
–4
04679-0-071
10
–3
VOS, dm (µV)
Figure 54. VOS, dm Distribution
Figure 51. VO, cm vs. VOCM Input Voltage
Rev. A | Page 16 of 24
04679-0-061
4
VOS, cm (µV)
VS = ±5V
VOS, dm (µV)
INPUT BIAS CURRENT (µA)
80
VOS, cm
6
–5
–5
20
40
60
TEMPERATURE (°C)
Figure 52. Supply Current vs. Temperature
8
–10
–5
0
300
10
VOUT, cm (V)
IBIAS (µA)
IBIAS
04679-0-060
2.5
1.0
–40
VS = ±5V
AD8139
1.7
6
1.6
4
VOCM CURRENT (µA)
1.3
1.2
1.1
1.0
0.9
04679-0-063
IVOCM (µA)
1.4
0.8
0.7
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 55. VOCM Bias Current vs. Temperature
VS = ±5V
VS = +5V
2
0
–2
–4
–6
–5
04679-0-074
1.5
–4
–3
–2
–1
0
1
VOCM (V)
2
3
4
Figure 56. VOCM Bias Current vs. VOCM Input Voltage
Rev. A | Page 17 of 24
5
AD8139
THEORY OF OPERATION
The AD8139 is a high speed, low noise differential amplifier
fabricated on the Analog Devices second generation eXtra Fast
Complementary Bipolar (XFCB) process. It is designed to
provide two closely balanced differential outputs in response to
either differential or single-ended input signals. Differential
gain is set by external resistors, similar to traditional voltagefeedback operational amplifiers. The common-mode level of the
output voltage is set by a voltage at the VOCM pin and is independent of the input common-mode voltage. The AD8139 has
an H-bridge input stage for high slew rate, low noise, and low
distortion operation and rail-to-rail output stages that provide
maximum dynamic output range. This set of features allows for
convenient single-ended-to-differential conversion, a common
need to take advantage of modern high resolution ADCs with
differential inputs.
balanced differential outputs of identical amplitude and exactly
180 degrees out of phase. The output balance performance does not
require tightly matched external components, nor does it require
that the feedback factors of each loop be equal to each other. Low
frequency output balance is limited ultimately by the mismatch
of an on-chip voltage divider, which is trimmed for optimum
performance.
Output balance is measured by placing a well matched resistor
divider across the differential voltage outputs and comparing
the signal at the divider’s midpoint with the magnitude of the
differential output. By this definition, output balance is equal to
the magnitude of the change in output common-mode voltage
divided by the magnitude of the change in output differentialmode voltage:
TYPICAL CONNECTION AND DEFINITION OF
TERMS
Output Balance =
Figure 57 shows a typical connection for the AD8139, using
matched external RF/RG networks. The differential input
terminals of the AD8139, VAP and VAN, are used as summing
junctions. An external reference voltage applied to the VOCM
terminal sets the output common-mode voltage. The two
output terminals, VOP and VON, move in opposite directions in a
balanced fashion in response to an input signal.
CF
VIP
VAP
VOCM
VAN = VAP
VIN
VON
+
AD8139
RG
VAN
–
(4)
The common-mode feedback loop drives the output commonmode voltage, sampled at the midpoint of the two 500 Ω resistors,
to equal the voltage set at the VOCM terminal. This ensures that
RL, dm VO, dm
VOP
–
(3)
The block diagram of the AD8139 in Figure 58 shows the
external differential feedback loop (RF/RG networks and the
differential input transconductance amplifier, GDIFF) and the
internal common-mode feedback loop (voltage divider across
VOP and VON and the common-mode input transconductance
amplifier, GCM). The differential negative feedback drives the
voltages at the summing junctions VAN and VAP to be essentially
equal to each other.
RF
RG
ΔVO, cm
ΔVO, dm
+
RF
04679-0-050
CF
VOP = VOCM +
(5)
2
and
Figure 57. Typical Connection
VON = VOCM −
The differential output voltage is defined as
VO, dm = VOP − VON
VO, dm
(1)
VIN
VO, dm
(6)
2
RG
RF
10pF
Common-mode voltage is the average of two voltages. The
output common-mode voltage is defined as
VOP + VON
2
GO
VOP
500Ω
VAN
(2)
MIDSUPPLY
GCM
GDIFF
500Ω
VAP
VOCM
Output Balance
GO
Output balance is a measure of how well VOP and VON are
matched in amplitude and how precisely they are 180 degrees
out of phase with each other. It is the internal common-mode
feedback loop that forces the signal component of the output
common-mode towards zero, resulting in the near perfectly
Rev. A | Page 18 of 24
VON
+
10pF
VIP
RG
RF
Figure 58. Block Diagram
04679-0-051
VO, cm =
+
AD8139
APPLICATIONS
ESTIMATING NOISE, GAIN, AND BANDWIDTH
WITH MATCHED FEEDBACK NETWORKS
The contribution from each RF is computed as
Vo _ n4 = 4kTRF
Estimating Output Noise Voltage
Voltage Gain
The total output noise is calculated as the root-sum-squared
total of several statistically independent sources. Since the
sources are statistically independent, the contributions of each
must be individually included in the root-sum-square calculation. Table 6 lists recommended resistor values and estimates of
bandwidth and output differential voltage noise for various
closed-loop gains. For most applications, 1% resistors are
sufficient.
The behavior of the node voltages of the single-ended-todifferential output topology can be deduced from the previous
definitions. Referring to Figure 57, (CF = 0) and setting VIN = 0
one can write
Table 6. Recommended Values of Gain-Setting Resistors and
Voltage Noise for Various Closed-Loop Gains
Gain
1
2
5
10
RG (Ω)
200
200
200
200
RF (Ω)
200
400
1k
2k
3 dB
Bandwidth
(MHz)
400
160
53
26
(10)
Total Output
Noise (nV/√Hz)
5.8
9.3
19.7
37
The differential output voltage noise contains contributions
from the AD8139’s input voltage noise and input current noise
as well as those from the external feedback networks.
The contribution from the input voltage noise spectral density
is computed as
⎛ R ⎞
Vo_n1 = vn ⎜1 + F ⎟ , or equivalently, vn/β
⎝ RG ⎠
VIP − VAP VAP − VON
=
RG
RF
(11)
⎡ RG ⎤
VAN = VAP = VOP ⎢
⎥
⎣ RF + RG ⎦
(12)
Solving the above two equations and setting VIP to Vi gives the
gain relationship for VO, dm/Vi.
VOP − VON = VO, dm =
RF
V
RG i
(13)
An inverting configuration with the same gain magnitude can
be implemented by simply applying the input signal to VIN and
setting VIP = 0. For a balanced differential input, the gain from
VIN, dm to VO, dm is also equal to RF/RG, where VIN, dm = VIP − VIN.
Feedback Factor Notation
When working with differential amplifiers, it is convenient to
introduce the feedback factor β, which is defined as
β=
(7)
RG
RF + RG
(14)
where vn is defined as the input-referred differential voltage
noise. This equation is the same as that of traditional op amps.
This notation is consistent with conventional feedback analysis
and is very useful, particularly when the two feedback loops are
not matched.
The contribution from the input current noise of each input is
computed as
Input Common-Mode Voltage
Vo_n2 = in (RF )
(8)
where in is defined as the input noise current of one input. Each
input needs to be treated separately since the two input currents
are statistically independent processes.
The contribution from each RG is computed as
⎛R ⎞
Vo_n3 = 4kTRG ⎜ F ⎟
⎝ RG ⎠
This result can be intuitively viewed as the thermal noise of
each RG multiplied by the magnitude of the differential gain.
The linear range of the VAN and VAP terminals extends to within
approximately 1 V of either supply rail. Since VAN and VAP are
essentially equal to each other, they are both equal to the amplifier’s input common-mode voltage. Their range is indicated in
the Specifications tables as input common-mode range. The
voltage at VAN and VAP for the connection diagram in Figure 57
can be expressed as
VAN = VAP = VACM =
(V + VIN ) ⎞ ⎛ RG
⎛ RF
⎞
× IP
× VOCM ⎟
⎟+⎜
⎜
+
+
R
R
2
R
R
F
F
G
G
⎠ ⎝
⎝
⎠
(9)
where VACM is the common-mode voltage present at the
amplifier input terminals.
Rev. A | Page 19 of 24
(15)
AD8139
Using the β notation, Equation 15 can be written as
VACM = βVOCM + (1 − β)VICM
For a single-ended signal (for example, when VIN is grounded
and the input signal drives VIP), the input impedance becomes
(16)
RIN =
or equivalently,
VACM = VICM + β(VOCM − VICM )
(17)
RG
RF
1−
2(RG + RF )
(19)
The input impedance of a conventional inverting op amp
configuration is simply RG, but it is higher in Equation 19
because a fraction of the differential output voltage appears at
the summing junctions, VAN and VAP. This voltage partially
bootstraps the voltage across the input resistor RG, leading to
the increased input resistance.
where VICM is the common-mode voltage of the input signal, i.e.,
VIP + VIN
.
VICM =
2
For proper operation, the voltages at VAN and VAP must stay
within their respective linear ranges.
Input Common-Mode Swing Considerations
Calculating Input Impedance
In some single-ended-to-differential applications, when using a
single-supply voltage attention must be paid to the swing of the
input common-mode voltage, VACM.
The input impedance of the circuit in Figure 57 will depend on
whether the amplifier is being driven by a single-ended or a
differential signal source. For balanced differential input signals,
the differential input impedance (RIN, dm) is simply
R IN, dm = 2 RG
Consider the case in Figure 59, where VIN is 5 V p-p swinging
about a baseline at ground and VREF is connected to ground.
(18)
5V
0.1µF
200Ω
2.5V
VOCM
3
8
2
1
VIN
2.7nF
5
+
AVDD
DVDD
IN–
AD8139
–
0.1µF
15Ω
AD7674
4
6
VREF
200Ω
324Ω
15Ω
2.7nF
IN+
DGND AGND REFGND REF REFBUFIN PDBUF
47µF
VACM
WITH VREF = 0
+1.7V
+0.95V
+0.2V
0.1µF
Figure 59. AD8139 Driving AD7674, 18-Bit, 800 kSPS A/D Converter
Rev. A | Page 20 of 24
ADR431
2.5V
REFERENCE
04679-0-052
+2.5V
GND
–2.5V
20Ω
0.1µF
324Ω
AD8139
The circuit has a differential gain of 1.6 and β = 0.38. VICM has
an amplitude of 2.5 V p-p and is swinging about ground. Using
the results in Equation 16, the common-mode voltage at the
AD8139’s inputs, VACM, is a 1.5 V p-p signal swinging about a
baseline of 0.95 V. The maximum negative excursion of VACM in
this case is 0.2 V, which exceeds the lower input common-mode
voltage limit.
One way to avoid the input common-mode swing limitation is
to bias VIN and VREF at midsupply. In this case, VIN is 5 V p-p
swinging about a baseline at 2.5 V and VREF is connected to a
low-Z 2.5 V source. VICM now has an amplitude of 2.5 V p-p and
is swinging about 2.5 V. Using the results in Equation 17, VACM is
calculated to be equal to VICM because VOCM = VICM. Therefore,
VACM swings from 1.25 V to 3.75 V, which is well within the
input common-mode voltage limits of the AD8139. Another
benefit seen in this example is that since VOCM = VACM = VICM no
wasted common-mode current flows. Figure 60 illustrates how
to provide the low-Z bias voltage. For situations that do not
require a precise reference, a simple voltage divider will suffice
to develop the input voltage to the buffer.
5V
0.1µF
VIN
0V TO 5V
This estimate assumes a minimum 90 degree phase margin for
the amplifier loop, which is a condition approached for gains
greater than 4. Lower gains will show more bandwidth than
predicted by the equation due to the peaking produced by the
lower phase margin.
Estimating DC Errors
Primary differential output offset errors in the AD8139 are due
to three major components: the input offset voltage, the offset
between the VAN and VAP input currents interacting with the
feedback network resistances, and the offset produced by the dc
voltage difference between the input and output common-mode
voltages in conjunction with matching errors in the feedback
network.
The first output error component is calculated as
⎛ R + RG ⎞
Vo _ e1 = VIO ⎜ F
⎟ , or equivalently as VIO/β
⎝ RG ⎠
where VIO is the input offset voltage. The input offset voltage of the
AD8139 is laser trimmed and guaranteed to be less than 500 μV.
The second error is calculated as
⎛ R + RG ⎞⎛ RG RF ⎞
Vo _ e2 = I IO ⎜ F
⎟⎜
⎟ = I IO (RF )
⎝ RG ⎠⎝ RF + RG ⎠
324Ω
3
200Ω
8
VOCM
2
1
(21)
5
+
where IIO is defined as the offset between the two input bias
currents.
AD8139
–
(22)
4
6
200Ω
The third error voltage is calculated as
324Ω
TO AD7674 REFBUFIN
5V
0.1µF
Vo _ e3 = ∆enr × (VICM − VOCM )
0.1µF
+
+
AD8031
where Δenr is the fractional mismatch between the two
feedback resistors.
ADR431
2.5V
REFERENCE
–
04679-0-053
10µF
The total differential offset error is the sum of these three error
sources.
Other Impact of Mismatches in the Feedback Networks
Figure 60. Low-Z 2.5 V Buffer
Another way to avoid the input common-mode swing limitation is to use dual power supplies on the AD8139. In this case,
the biasing circuitry is not required.
Bandwidth Versus Closed-Loop Gain
The AD8139’s 3 dB bandwidth decreases proportionally to
increasing closed-loop gain in the same way as a traditional
voltage feedback operational amplifier. For closed-loop gains
greater than 4, the bandwidth obtained for a specific gain can be
estimated as
f − 3 dB,VOUT , dm =
RG
× (300 MHz)
RG + RF
or equivalently, β(300 MHz).
(23)
(20)
The internal common-mode feedback network will still force
the output voltages to remain balanced, even when the RF/RG
feedback networks are mismatched. The mismatch will,
however, cause a gain error proportional to the feedback
network mismatch.
Ratio-matching errors in the external resistors will degrade the
ability to reject common-mode signals at the VAN and VIN input
terminals, much the same as with a four-resistor difference
amplifier made from a conventional op amp. Ratio-matching
errors will also produce a differential output component that is
equal to the VOCM input voltage times the difference between the
feedback factors (βs). In most applications using 1% resistors,
this component amounts to a differential dc offset at the output
that is small enough to be ignored.
Rev. A | Page 21 of 24
AD8139
Driving a Capacitive Load
5
RS = 30.1Ω
4
CL = 15pF
3
2
1
0
–1
–2
RS = 60.4Ω
–3
CL = 15pF
–4
–5
–6
–7
RS = 60.4Ω
–8
CL = 5pF
–9
VS = ±5V
–10
V
= 0.1V p-p
–11 GO,= dm
1 (RF = RG = 200Ω)
–12 R
L, dm = 1kΩ
–13
10M
100M
FREQUENCY (MHz)
Figure 62 shows the AD8139 in a unity-gain configuration
driving the AD6645, which is a 14-bit high speed ADC, and
with the following discussion, provides a good example of how
to provide a proper termination in a 50 Ω environment.
RS = 30.1Ω
CL = 5pF
RS = 0Ω
CL, dm = 0pF
04679-0-076
CLOSED LOOP GAIN (dB)
A purely capacitive load will react with the bondwire and pin
inductance of the AD8139, resulting in high frequency ringing
in the transient response and loss of phase margin. One way to
minimize this effect is to place a small resistor in series with
each output to buffer the load capacitance, see Figure 6 and
Figure 61. The resistor and load capacitance will form a firstorder low-pass filter; therefore, the resistor value should be as
small as possible. In some cases, the ADCs require small series
resistors to be added on their inputs.
The input resistance presented by the AD8139 input circuitry is
seen in parallel with the termination resistor, and its loading
effect must be taken into account. The Thevenin equivalent
circuit of the driver, its source resistance, and the termination
resistance must all be included in the calculation as well. An
exact solution to the problem requires the solution of several
simultaneous algebraic equations and is beyond the scope of
this data sheet. An iterative solution is also possible and simpler,
especially considering the fact that standard 1% resistor values
are generally used.
1G
Figure 61. Frequency Response for
Various Capacitive Load and Series Resistance
The Typical Performance Characteristics that illustrate transient
response versus the capacitive load were generated using series
resistors in each output and a differential capacitive load.
Layout Considerations
Standard high speed PCB layout practices should be adhered to
when designing with the AD8139. A solid ground plane is recommended and good wideband power supply decoupling networks
should be placed as close as possible to the supply pins.
To minimize stray capacitance at the summing nodes, the
copper in all layers under all traces and pads that connect to the
summing nodes should be removed. Small amounts of stray
summing-node capacitance will cause peaking in the frequency
response, and large amounts can cause instability. If some stray
summing-node capacitance is unavoidable, its effects can be
compensated for by placing small capacitors across the feedback
resistors.
Terminating a Single-Ended Input
Controlled impedance interconnections are used in most high
speed signal applications, and they require at least one line
termination. In analog applications, a matched resistive
termination is generally placed at the load end of the line. This
section deals with how to properly terminate a single-ended
input to the AD8139.
The termination resistor, RT, in parallel with the 268 Ω input
resistance of the AD8139 circuit (calculated using Equation 19),
yields an overall input resistance of 50 Ω that is seen by the
signal source. In order to have matched feedback loops, each
loop must have the same RG if they have the same RF. In the
input (upper) loop, RG is equal to the 200 Ω resistor in series
with the (+) input plus the parallel combination of RT and the
source resistance of 50 Ω. In the upper loop, RG is therefore
equal to 228 Ω. The closest standard 1% value to 228 Ω is 226 Ω
and is used for RG in the lower loop. Greater accuracy could be
achieved by using two resistors in series to obtain a resistance
closer to 228 Ω.
Things get more complicated when it comes to determining the
feedback resistor values. The amplitude of the signal source
generator VS is two times the amplitude of its output signal
when terminated in 50 Ω. Thus, a 2 V p-p terminated amplitude
is produced by a 4 V p-p amplitude from VS. The Thevenin
equivalent circuit of the signal source and RT must be used
when calculating the closed-loop gain because in the upper loop
RG is split between the 200 Ω resistor and the Thevenin resistance looking back toward the source. The Thevenin voltage of
the signal source is greater than the signal source output voltage
when terminated in 50 Ω because RT must always be greater
than 50 Ω. In this case, it is 61.9 Ω and the Thevenin voltage
and resistance are 2.2 V p-p and 28 Ω, respectively. Now the
upper input branch can be viewed as a 2.2 V p-p source in series
with 228 Ω. Since this is a unity-gain application, a 2 V p-p
differential output is required, and RF must therefore be 228 ×
(2/2.2) = 206 Ω. The closest standard value to this is 205 Ω.
When generating the Typical Performance Characteristics data,
the measurements were calibrated to take the effects of the
terminations on closed-loop gain into account.
Rev. A | Page 22 of 24
AD8139
Exposed Paddle (EP)
Since this is a single-ended-to-differential application on a
single supply, the input common-mode voltage swing must be
checked. From Figure 62, β = 0.52, VOCM = 2.4 V, and VICM is
1.1 V p-p swinging about ground. Using Equation 16, VACM is
calculated to be 0.53 V p-p swinging about a baseline of 1.25 V,
and the minimum negative excursion is approximately 1 V.
The SOIC-8 and LFCSP packages have an exposed paddle on
the underside of its body. In order to achieve the specified
thermal resistance, it must have a good thermal connection to one
of the PCB planes. The exposed paddle must be soldered to a pad
on top of the board that is connected to an inner plane with several
thermal vias.
5V
3.3V
0.01µF
0.01µF
0.01µF
205Ω
50Ω
VS
SIGNAL
SOURCE
RT
61.9Ω
200Ω
8
VOCM
2
1
226Ω
25Ω
AIN
3
AVCC
DVCC
5
+
AD8139
–
AD6645
4
6
AIN
205Ω
25Ω
GND C1
C2
0.1µF
VREF
0.1µF
2.4V
Figure 62. AD8139 Driving AD6645, 14-Bit, 80 MSPS/105 MSPS A/D Converter
Rev. A | Page 23 of 24
04679-0-054
2V p-p
AD8139
OUTLINE DIMENSIONS
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
8
BOTTOM VIEW
(PINS UP)
2.29 (0.092)
5
1
2.29 (0.092)
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
TOP VIEW
4
1.27 (0.05)
BSC
0.50 (0.020)
× 45°
0.25 (0.010)
1.75 (0.069)
1.35 (0.053)
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
SEATING
0.10
PLANE
0.51 (0.020)
0.31 (0.012)
8°
0.25 (0.0098) 0° 1.27 (0.050)
0.40 (0.016)
0.17 (0.0068)
COMPLIANT TO JEDEC STANDARDS MS-012
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 63. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC/EP], Narrow Body (RD-8-1)—Dimensions shown in millimeters and (inches)
3.00
BSC SQ
0.60 MAX
0.50
0.40
0.30
0.45
1
8
PIN 1
INDICATOR
0.90
0.85
0.80
SEATING
PLANE
2.75
BSC SQ
TOP
VIEW
0.50
BSC
0.25
MIN
0.80 MAX
0.65 TYP
12° MAX
PIN 1
INDICATOR
1.50
REF
EXPOSED
PAD
(BOTTOM VIEW)
5
1.90
1.75
1.60
4
1.60
1.45
1.30
0.05 MAX
0.02 NOM
0.30
0.23
0.18
0.20 REF
Figure 64. 8-Lead Lead Frame Chip Scale Package [LFCSP], 3 mm × 3 mm Body (CP-8-2)—Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8139ARD
AD8139ARD-REEL
AD8139ARD-REEL7
AD8139ARDZ1
AD8139ARDZ-REEL1
AD8139ARDZ-REEL71
AD8139ACP-R2
AD8139ACP-REEL
AD8139ACP-REEL7
AD8139ACPZ-R21
AD8139ACPZ-REEL1
AD8139ACPZ-REEL71
1
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
8-Lead Small Outline Package (SOIC)
8-Lead Small Outline Package (SOIC)
8-Lead Small Outline Package (SOIC)
8-Lead Small Outline Package (SOIC)
8-Lead Small Outline Package (SOIC)
8-Lead Small Outline Package (SOIC)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
Z = Pb-free part.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
D04679–0–8/04(A)
Rev. A | Page 24 of 24
Package Option
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
Branding
HEB
HEB
HEB
HEB
HEB
HEB