SN54HC164, SN74HC164 www.ti.com SCLS115F – DECEMBER 1982 – REVISED OCTOBER 2013 8-Bit Parallel-Out Serial Shift Registers Check for Samples: SN54HC164, SN74HC164 FEATURES DESCRIPTION • • • • • • • • • These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. 1 A B QA QB QC QD GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 B A NC VCC QH Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-μA Max ICC Typical tpd= 20 ns ±4-mA Output Drive at 5 V Low Input Current of 1-μA Max AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs Direct Clear VCC QH QG QF QE CLR CLK QA NC QB NC QC 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QG NC QF NC QE QD GND NC CLK CLR SN54HC164...J OR W PACKAGE SN74HC164...D, N, NS, OR PW PACKAGE (TOP VIEW) 4 NC − No internal connection SN54HC164...FK PACKAGE (TOP VIEW) FUNCTION TABLE (1) (2) INPUTS OUTPUTS CLR CLK A B QA QB L X X X L L L H L X X QA0 QB0 QH0 H ↑ H H H QAn QGn H ↑ L X L QAn QGn H ↑ X L L QAn QGn (1) (2) ... QH QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = the level of QA or QG before the most recent ↑ transition of CLK: indicates a 1-bit shift. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1982–2013, Texas Instruments Incorporated SN54HC164, SN74HC164 SCLS115F – DECEMBER 1982 – REVISED OCTOBER 2013 www.ti.com LOGIC DIAGRAM (POSITIVE LOGIC) CLK A B CLR 8 1 C1 1D R 2 C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R 9 3 4 QA QB 5 QC 6 QD 10 QE 11 QF 12 QG 13 QH Pin numbers shown are for the D, J, N, NS, PW, and W packages. TYPICAL CLEAR, SHIFT, AND CLEAR SEQUENCE Serial Inputs CLR A B CLK QA QB Outputs QC QD QE QF QG QH Clear 2 Submit Documentation Feedback Clear Copyright © 1982–2013, Texas Instruments Incorporated Product Folder Links: SN54HC164 SN74HC164 SN54HC164, SN74HC164 www.ti.com SCLS115F – DECEMBER 1982 – REVISED OCTOBER 2013 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) MIN MAX −0.5 UNITS VCC Supply voltage range IIK Input clamp current VI < 0 or VI > VCC (2) ±20 7 mA IOK Output clamp current VO < 0 or VO > VCC (2) ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA Continuous current through VCC or GND θJA (3) Package thermal impedance Tstg Storage temperature range D package 86 N package 80 NS package 76 PW package (1) (2) (3) V °C/W 113 –65 150 °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) SN54HC164 VCC Supply voltage VCC = 2 V VIH High-level input voltage VCC = 4.5 V VCC = 6 V NOM MAX 2 5 6 Low-level input voltage MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 VCC = 2 V VIL SN74HC164 MIN VCC = 4.5 V VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V Δt/Δv (2) TA (1) (2) Input transition rise/fall time 1000 1000 VCC = 4.5 V 500 500 VCC = 6 V 400 400 −55 Operating free-air temperature 125 −40 125 ns °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. If this device is used in the threshold region (from VIL max = 0.5 V to VIH min = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. Copyright © 1982–2013, Texas Instruments Incorporated Product Folder Links: SN54HC164 SN74HC164 Submit Documentation Feedback 3 SN54HC164, SN74HC164 SCLS115F – DECEMBER 1982 – REVISED OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 μA VOH VI = VIH or VIL IOH = −4 mA IOH = −5.2 mA IOL = 20 μA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II VI = VCC or 0 ICC VI = VCC or 0 IO = 0 Ci SN54HC164 –55°C to 125°C TA = 25°C VCC MAX MIN SN74HC164 –55°C to 85°C MIN TYP 2V 1.9 1.998 1.9 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 4.4 6V 5.9 5.999 5.9 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 3.7 6V 5.48 5.8 MAX MIN Recommended SN74HC164 –55°C to 125°C 5.2 MAX MIN 5.34 UNIT MAX V 5.2 2V 0.002 0.1 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 0.4 6V 0.15 0.26 0.4 0.33 0.4 6V ±0.1 ±100 ±1000 ±1000 ±1000 nA 8 160 80 160 μA 10 10 10 10 pF 6V 2 V to 6 V 3 V TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VCC MIN fclock Clock frequency CLR low tw Pulse duration CLK high or low Data tsu Setup time before CLK↑ CLR inactive th 4 Hold time, data after CLK↑ Submit Documentation Feedback SN54HC164 –55°C to 125°C TA = 25°C MAX MIN Recommended SN74HC164 –55°C to 125°C SN74HC164 –55°C to 85°C MAX MIN MAX MIN 2V 6 4.2 5 4.2 4.5 V 31 21 25 21 6V 36 25 28 25 2V 100 150 125 125 4.5 V 20 30 25 25 6V 17 25 21 21 2V 80 120 100 120 4.5 V 16 24 20 24 6V 14 20 18 20 2V 100 150 125 125 4.5 V 20 30 25 25 6V 17 25 21 25 2V 100 150 125 125 4.5 V 20 30 25 25 6V 17 25 21 25 2V 5 5 5 5 4.5 V 5 5 5 5 6V 5 5 5 5 UNIT MAX MHz ns ns ns Copyright © 1982–2013, Texas Instruments Incorporated Product Folder Links: SN54HC164 SN74HC164 SN54HC164, SN74HC164 www.ti.com SCLS115F – DECEMBER 1982 – REVISED OCTOBER 2013 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETE R FROM (INPUT) TO (OUTPUT ) fmax tPHL tpd tt CLR CLK Any Q Any Q SN54HC164 –55°C to 125°C TA = 25°C VCC MAX MIN SN74HC164 –55°C to 85°C MAX MIN MAX Recommended SN74HC164 –55°C to 125°C MIN TYP 2V 6 10 4.2 5 MIN 4..2 4.5 V 31 54 21 25 21 6V 36 62 25 28 25 UNIT MAX MHz 2V 140 205 295 255 255 4.5 V 28 41 59 51 51 6V 24 35 51 46 46 2V 115 175 265 220 220 4.5 V 23 35 53 44 44 6V 20 30 45 38 38 2V 38 75 110 95 110 4.5 V 8 15 22 19 22 6V 6 13 19 16 19 ns ns OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS TYP UNIT No load 135 pF Copyright © 1982–2013, Texas Instruments Incorporated Product Folder Links: SN54HC164 SN74HC164 Submit Documentation Feedback 5 SN54HC164, SN74HC164 SCLS115F – DECEMBER 1982 – REVISED OCTOBER 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS VCC Input 50% 50% 0V tPLH VCC Reference Input 50% In-Phase Output 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V Out-of-Phase Output 90% 90% VOH 50% 10% VOL tf tPLH 50% 10% tf tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 90% tr th 90% 50% 10% tPHL 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 1982–2013, Texas Instruments Incorporated Product Folder Links: SN54HC164 SN74HC164 SN54HC164, SN74HC164 www.ti.com SCLS115F – DECEMBER 1982 – REVISED OCTOBER 2013 REVISION HISTORY Changes from Revision E (November 2010) to Revision F Page • Updated document to new TI data sheet format - no specification changes. ...................................................................... 1 • Removed ordering information. ............................................................................................................................................ 1 • Updated operating temperature range. ................................................................................................................................. 3 Copyright © 1982–2013, Texas Instruments Incorporated Product Folder Links: SN54HC164 SN74HC164 Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 4-Dec-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-8416201VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8416201VC A SNV54HC164J 5962-8416201VDA ACTIVE CFP W 14 25 TBD A42 N / A for Pkg Type -55 to 125 5962-8416201VD A SNV54HC164W 84162012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84162012A SNJ54HC 164FK 8416201CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8416201CA SNJ54HC164J SN54HC164J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC164J SN74HC164D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164DRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164DT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU | CU SN N / A for Pkg Type -40 to 125 SN74HC164N SN74HC164N3 OBSOLETE PDIP N 14 TBD Call TI Call TI -40 to 125 SN74HC164NE3 PREVIEW PDIP N 14 25 TBD Call TI Call TI -40 to 125 SN74HC164N SN74HC164NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 SN74HC164N SN74HC164NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 4-Dec-2014 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74HC164PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164PWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SNJ54HC164FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84162012A SNJ54HC 164FK SNJ54HC164J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8416201CA SNJ54HC164J SNJ54HC164W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8416201DA SNJ54HC164W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 4-Dec-2014 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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OTHER QUALIFIED VERSIONS OF SN54HC164, SN54HC164-SP, SN74HC164 : • Catalog: SN74HC164, SN54HC164 • Military: SN54HC164 • Space: SN54HC164-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 7-Apr-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC164DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC164DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC164DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 SN74HC164DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 SN74HC164DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC164DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC164DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC164NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC164PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC164PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Apr-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC164DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC164DR SOIC D 14 2500 333.2 345.9 28.6 SN74HC164DR SOIC D 14 2500 364.0 364.0 27.0 SN74HC164DRG3 SOIC D 14 2500 364.0 364.0 27.0 SN74HC164DRG4 SOIC D 14 2500 333.2 345.9 28.6 SN74HC164DRG4 SOIC D 14 2500 367.0 367.0 38.0 SN74HC164DT SOIC D 14 250 367.0 367.0 38.0 SN74HC164NSR SO NS 14 2000 367.0 367.0 38.0 SN74HC164PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HC164PWT TSSOP PW 14 250 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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