SLYT097 - Texas Instruments

Power Management
Texas Instruments Incorporated
UCC28517 100-W PFC power converter
with 12-V, 8-W bias supply, Part 1
By Michael O’Loughlin (Email: [email protected])
Member, Applications Engineering Staff
Introduction
Power factor corrected (PFC) preregulators are generally
used in offline ac/dc power converters with a power level
higher than 75 W or to meet line harmonic requirements
such as EN61000-3-2. PFC is typically done with a boost
converter ac/dc topology due to the continuous input
current that can be manipulated through average currentmode control to achieve a near-unity power factor (PF).
However, due to the high output voltage of a boost
converter, a second dc/dc converter is generally needed to
step down the output to a usable voltage. In the past this
has been accomplished with two pulse-width modulators
(PWMs). One PWM controlled and regulated the PFC
power stage, while the second was used to control the
step-down converter. The UCC28517 controller reduces
the need for two PWMs and combines both of these functions into one control-integrated circuit. The UCC28517
operates the second converter at twice the switching
frequency of the PFC stage, which reduces the size of the
boost magnetics and the ripple current in the boost
capacitor. For more information on this device, please see
Reference 7. This article reviews the design of a 100-W
ac/dc power stage with power factor correction. A review
of the second stage can be found in a future issue of TI’s
Analog Applications Journal.
Variable definitions
∆I
η1
η2
CDIODE
Comp
COSS
fc
fline
fp
fR
fS
fSA
fSB
GID(s)
GCA
Gc(s)
Gco(s)
gm
Gvea
H(s)
IIAC
IMOUT
IPK
Change in boost inductor current
Output A efficiency
Output B efficiency
Boost diode capacitance
Dynamic range of the multiplier comp pin
FET drain-to-source capacitance
Voltage-loop crossover frequency
Input line frequency
Single-pole filter frequency
Ripple frequency
Minimum switching frequency
Output A switching frequency
Output B switching frequency
Power stage gain
Current amplifier gain
Control transfer function
Control to output transfer function
Transconductance amplifier gain
Voltage amplifier gain
Voltage divider gain
Multiplier input current
Multiplier output
Peak inductor current, peak diode current, peak
switch current
RMS device current
IRMS
ISS
UCC28517 soft-start current of 10 µA
K
Constant typically equal to 1/V
PCOND
Device conduction losses
Power dissipated by the FET’s drain-to-source
PCOSS
capacitance
Total loss in the boost diode
PDIODE
PDIODE_CAP Loss due to boost diode capacitance
PFET_TR
FET transition losses
PGATE
Power dissipated by the FET gate
Output A maximum power
POUTA
POUTB
PQ1
P_semi
QGATE
Rθcs
Rθjc
Rθsa
RDS(on)
RIAC
RSENSE
s(f)
Tamb
tblank
tf
tholdup
Tjmax
ton
tr
Ts(f)
Vc
VCSENSE
Vdrop
Vdynamic
Vea
Vf
VGATE
VIN
VOUTA
VOUTB
VP
Vpp
Vripple
VREF
VVFF
ZOUT
Output B maximum power
Total FET losses
Power dissipated by a semiconductor device
FET gate charge
Thermal impedance case-to-sink
Thermal impedance junction-to-case
Thermal impedance sink-to-air
On resistance of the FET
Multiplier input resistance
Current sense resistor
Frequency domain (2πf)
Ambient temperature
Amount of leading-edge blanking time
FET fall time
Boost capacitor hold-up time
Maximum semiconductor temperature
Boost inductor energizing on time
FET rise time
Voltage loop frequency response
Control voltage
Maximum current sense voltage
Amount of voltage the boost capacitor has to hold up
Current sense voltage range
Voltage amplifier output
Forward voltage of a diode
Gate-drive voltage
RMS input voltage
Boost output voltage
Auxiliary output voltage
Oscillator ramp voltage
Output peak-to-peak ripple voltage
Output B ripple voltage
UCC28517 internal reference
Multiplier feed-forward voltage
Compensation impedance
13
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Table 1. Design specifications
MAXIMUM
265 Vrms
410 V
12.6 V
VIN
Output A (VOUTA)
Output B (VOUTB)
Output A efficiency (η1)
Output B efficiency (η2)
POUTA
POUTB
Output ripple A (Vpp)
Output ripple B (Vripple)
Output A THD (% THD)
PF
Output A switching frequency (fSA)
Output B switching frequency (fSB)
TYPICAL
MINIMUM
85 Vrms
370 V
11.4 V
390 V
12 V
85%
50%
100 W
8W
12 V
750 mV
10%
1
10 W
4W
100 kHz
200 kHz
The following design example was generated using
typical parameters rather than worst-case values. Please
refer to Table 1 and Figures 1–3 for design specifications
and component placement. All variables are defined in
the sidebar on page 13.
POUTA × 0.25 × 2
η1
∆I =
VIN(min)
PFC boost ac/dc regulator design (OUTA)
D = 1−
VIN(min) × 2
VOUTA
Inductor selection
The boost inductor is selected based on the maximum
ripple current at the peak of minimum line voltage. The
following equations can be used to calculate the required
inductor for the boost power stage, assuming that the
boost inductor ripple current is 25% of the maximum
input current.
L1 =
VIN(min) × 2 × D
∆I × fSA
Figure 1. PFC power stage schematic
D1
R18
392 kΩ
R24
392 kΩ
TP11
G1756
IAC
L1
1.7 mH
F1
+ 1
HFA08TB60
2
– 3
Q1
IRFP450
D11
PB66
AC_N
P1
R22
562 kΩ
R33
562 kΩ
+
C2
0.47 µF
C3
100 µF
P2
R14
1.5 kΩ
TP1
OUTA–
1
R41
47 Ω
PKLMT
R29
10.0 kΩ
OUTA+
R20
22.1 kΩ
R5
0.33 Ω
R15
3.92 kΩ
5
1
VREF
TP2
2
VIN
C26
47 nF
4
4
AC_L
R44
47 Ω
TP12
D3
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Figure 2. dc/dc power stage schematic
T1
PB2039
OUTA+
P1
3
R3
82 kΩ
Q3
R1
44.2 k Ω
OUTA–
P2
OUTB+
7
VCC
D15
R39
1 2
10 kΩ
4
GND
R43
10 kΩ
C9
100 µF
P4
6
1
3
R2 10 kΩ
D8
2
R9
82 kΩ
C29 +
2.2 µF
9
C30
100 µF
C1
1 µF
4
C12
47 µF
OUTB–
10
D5
Q2
P3
2
5
R4
Note: Star grounding
technique must be used 10 kΩ
1
6
7
VREF
R13
2 kΩ
TP8
C38
100 pF
R26
100 kΩ
TP6
U2
5
VERR
R36
200 kΩ
TP9
6
1
4
2
D14
R16
680 kΩ
C15
3.3 nF
3
TP7
R32
38.3 kΩ
C14
150 nF
D13
1
R31
47 Ω
R35
1 kΩ
2 1
4
R27
10 kΩ
GND2
2
Figure 3. Controller schematic
1
2
4
5
6
R7
10 Ω
R19
3.92 kΩ
1
1
PKLMT
D16
TP3
C22
390 pF
CAOUT
GND
1
17
IAC
C19
2.2 nF
1
C24
100 pF
18
19
20
VERR
ISENSE1
MOUT
CT
VSCLAMP
IAC
VSENSE
VFF
RT
VREF
VAOUT
R40
1 kΩ
R11
1 kΩ
Q4
C10
330 pF
VERR
8
7
1
TP10
GT2 10
VCC 9
ISENSE2
D12 16
R17
7.5 kΩ
GT2
13 SS2
14 PKLMT
15
C6
47 µF
C18
0.1 µF
GT2
11 PWRGND
12 GT1
C16
10 nF
R10
10 Ω
D9
D10
R6
10 Ω
7
VCC
C13
56 pF
C17
100 pF
1
R42
100 Ω
R8
9.09 kΩ
6
1
5
4
D_CLAMP
3
2
1
1
R25
133 kΩ
UCC38517DW
U1
TP5
VREF
R30
30.1 kΩ
R34
1.18 kΩ
C28
2.2 µF
D_CLAMP
R21
1 kΩ
1
TP4
C27
1 µF
C25
150 nF
R28
48.7 kΩ
C23
1.5 µF
1
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The calculated inductance for this design was roughly
1.7 mH. To make the design process easier, Cooper
Electronics designed the inductor (part number
CTX08-14730).
Boost switch (Q1) and boost diode (D3) selection
To select Q1 and D3 properly, a power budget is generally
set for these devices to maintain the desired efficiency goal.
To meet the power budget for this design, an IRFP450
HEX FET and an HFA08TB60 fast-recovery diode from
International Rectifier were chosen.
Equations used to calculate the loss in Q1 were:
IRMS _ FET =
16 × 2 × VIN(min)
POUTA
V
× OUTA × 2 −
3π × VOUTA
η1 × VIN(min) VIN(min)
IRMS _ L =
POUTA × 2
V
× OUTA
η1 × VIN(min) VIN(min)
Heat sinks
The following equation can be used to calculate the minimum required thermal impedance of the heat sinks (Rθsa)
for this design for Q1 and D3.
Tj max − Tamb − P_ semi × (Rθcs + Rθjc )
Rθsa =
P_ semi
The heat sink was designed to ensure that the junction
temperature would not go above 75% of these devices’
rated maximum with convection cooling, assuming a maximum ambient temperature of 60°C. The heat sink required
for Q1 was an AVVID, part number 513201 B 0 25 00.
Output hold-up capacitor (C3) selection
The following equations were used to estimate the minimum
hold-up capacitor (C3) size and the maximum allowable
RMS current through the boost capacitor (IRMS_C3).
C3 ≥ 2 × POUTA ×
PGATE = QGATEVGATE × fS
IRMS _ C3 =
1
2
PCOSS = COSS VOUTA
(min) × fS
2
PQ1 = PGATE + PCOSS + PCOND _ FET + PFET _ TR
POUTA × 2
η1 × VIN(min)
POUTA
16 × VOUTA
×
η1 × VIN(min)
3π × 2 × VIN(min)
PCOND _ DIODE = Vf × I2RMS _ DIODE
PDIODE _ CAP
Resistor dividers R14 and R29, along with current sense
resistor R5, set up the peak-limit comparator of the
UCC28517 that is used to protect the boost switch Q1
from excessive currents. This comparator should be set
up so that it does not interfere with the boost converter’s
power limit or with the pulse-by-pulse current limiting of
the step-down converters. For this design example, the
flyback converter was designed to go into pulse-by-pulse
current limiting at roughly 130% of maximum output
power, and the power limit of the boost converter was set
at 140% of the maximum output power. The peak-current
limit for the boost stage was selected to engage at 150% of
the maximum output power to ensure circuit stability.
The current sense resistor R5 was selected to operate
over a 1-V dynamic range (Vdynamic) with the following
equation.
R5 = RSENSE =
C
2
= DIODE × VOUTA
× fSA
2
PDIODE = PCOND _ DIODE + PDIODE _ CAP
POUTA
16 × VOUTA
−1
×
3π × VIN(min) × 2
VOUTA
Peak-current limit for the boost power stage
1
PFET _ TR = VOUTA × IRMS _ L × tr × fS
2
IRMS _ DIODE =
− ( VOUTA − Vdrop )2
The hold-up capacitor was designed for 16.7 ms of hold-up
time (tholdup), allowing an output voltage drop (Vdrop) of
85 V.
PCOND _ FET = RDS(on ) × I2RMS _ FET
IPK =
tholdup
2
VOUTA
Vdynamic
IPK + 0.5 × ∆I
The following equation can be used to size resistor R14
properly if R29 is first selected as a standard resistance value.
 POUTA × 1.5 × 2

+ ∆I × R5 × R29
 V


IN(min) × η1
R14 =
VREF
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Multiplier
The multiplier output of the UCC28517 is a signal representing the desired input line current. It is an input to the
current amplifier, which programs the current loop to
control the input current to give high-PF operation. As
such, the proper functioning of the multiplier is key to the
success of the design. The output of the multiplier, IMOUT,
can be expressed as
Vea(max) − 1
IMOUT = IIAC
,
2
K × VVFF
where K is a constant typically equal to 1/V.
The IIAC signal is obtained through a high-value resistor
(RIAC = R18 + R24) connected between the rectified ac
line and the IAC pin of the UCC28517. This resistor is
sized to give the maximum IIAC current at the highest
expected line voltage. For the UCC28517 the maximum
IIAC current is about 500 µA. A higher current than this
can drive the multiplier out of its linear range. A smaller
current level is functional; but noise can become an issue,
especially during low line voltages, assuming a universal line
operation of 85 to 265 Vac gives an RIAC value of 750 kΩ.
Because of voltage-rating constraints of standard ¼-W
resistors, two or more lower-value resistors connected in
series are needed to give roughly a 750-kΩ value and to
distribute the high voltage across them.
The current through RIAC is mirrored internally to the
VFF pin, where it is filtered to produce a voltage feedforward signal proportional to line voltage that is free of
the 120-Hz ripple component. This second harmonic ripple
component at the VFF pin is one of the major contributors
to harmonic distortion in the system, so adequate filtering
is crucial (see Reference 4). Assuming that an allocation
of 1.5% total harmonic distortion from this input is
allowed, and that the second harmonic ripple is 66% of
the input ac line voltage, the amount of attenuation
required by this filter is
C20 =
This results in a single-pole filter, which adequately attenuates the harmonic distortion and provides power limiting.
The multiplier’s output resistor R19 is sized to match
the maximum current through the sense resistor (R5) to
the maximum multiplier current. R15 is sized to balance
the offset current in the current amplifier and needs to be
set to the same value as R19. The following equations
were used to size R15 and R19.
IMOUT(max) =
IIAC @ VIN(min) × ( Vea(max) − 1 V )
2
K × VVFF
R19 = R15 =
Vdynamic
IMOUT(max)
Current loop compensation for the boost converter
The following equation defines the gain of the power
stage, where VP is the maximum voltage swing of the
UCC28517 oscillator ramp, roughly 5 V.
GID(s) =
VOUTA × R5
s × L1 × VP
To have a good dynamic response, the crossover frequency of the current loop was set to 1/10 the switching
frequency. This can be achieved by setting the gain of the
current amplifier (GCA ) to the inverse of the current loop
power-stage gain at the crossover frequency. For this
design the current amplifier required a gain of 2.581 at
10 kHz. The following equations were used to compensate
the current amplifier of the boost power stage.
1.5%
≈ 0.022 (see Reference 5).
66%
GCA =
1
= 2.581
GID(s)
R17 = GCA × R19
A ripple frequency (fR) of 120 Hz and an attenuation of
0.022 gives us a single-pole filter with
fp = 120 Hz × 0.022 = 2.6 Hz.
The voltage at the VFF pin not only supplies a voltage
feed-forward signal but also activates input current foldback when the VVFF drops below 1.5 V. Please see
Reference 2 for a detailed explanation of how these control ICs provide power limiting. The following equations
were used to size resistor R30 and filter capacitor C20.
R30 =
1
2π × 30 kΩ × 2.6 Hz
C19 =
C22 =
1
2π × R17 ×
fSA
10
1
2π × R17 ×
fSA
2
1.5 V
VIN(min) × 0.9
(R18 + R24) × 2
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Voltage loop compensation for the boost converter
Figure 4 shows the small-signal-control block diagram
for this application. The following equations describe
small-signal gain as well as the voltage loop frequency
response, Ts(f ).
H(s) =
R20
R20 + R32 + R32
Figure 4. dc/dc converter control loop
VIN
VREF
+
Σ
Gc(s)
Vc
Gco(s)
VOUTA
–
Gc(s) = g m ×
Gco(s) =
s( f ) × R28 × C23 + 1
H(s)
 s( f ) × C23 × C25 
+ 1
s( f ) × (C23 + C25) × 
C23 + 25


∆VOUTA
POUTA
=
Vea(max) × s × VOUTA × C3
∆Vc
Vpp =
Ts( f ) = −H(s) × Gc(s) × Gco(s)
To reduce third-harmonic distortion, the voltage loop
typically crosses over at roughly 10 to 12 Hz. For this
design, the voltage-loop crossover frequency (fc) was
selected to be roughly 10 Hz. The following equations
were used to select the components to compensate the
voltage loop, Ts(f ), to cross over at the desired fc with
45 degrees of phase margin.
VOUTA × η1
R28 = 2π × Vea(max) × fc × C3 ×
g m × POUTA × H(s)
C23 =
1
2π × R28 × fc
C25 was selected to attenuate the 120-Hz output ripple
voltage (Vpp) to 1.5% (% THD) of the voltage amplifier’s
dynamic output range.
POUTA
π × 120 Hz × C3 × VOUTA
Gvea =
% THD × Vea(max)
Vpp × 100
ZOUT =
C25 =
Gvea
H(s) × g m
1
2π × ZOUT
After the design was complete, the frequency response
of the voltage loop, Ts(f ), was measured with a network
analyzer; and the results are shown in Figure 5. It can be
observed that fc was roughly 8 Hz with a phase margin of
roughly 50 degrees.
50
40
30
20
10
0
–10
–20
–30
–40
–50
180
144
108
72
36
0
–36
–72
–108
–144
–180
100
Gain
Phase
1
10
Frequency (Hz)
Phase (degrees)
Gain (dB)
Figure 5. Frequency response of power stage A
18
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Figure 6. Output A THD vs. output power
Figure 7. Output A efficiency vs. output power
VIN = 85 V
VIN = 175 V
VIN = 265 V
25
20
15
10
5
0
Efficiency (%)
Current THD (%)
100
35
30
90
80
60
50
10
20
30
40 50 60 70
Output Power (W)
80
90
100
Figure 8. Output A PF vs. output power
10
20
30
40 50 60 70
Output Power (W)
80
90 100
Figure 9. Output B efficiency vs. output efficiency
1
Efficiency (%)
80
PF
0.95
VIN = 85 V
VIN = 175 V
VIN = 265 V
0.9
0.85
10
VIN = 85 V
VIN = 175 V
VIN = 265 V
70
20
30
50 60 70
40
Output Power (W)
80
90
60
40
20
0
1
4
6
Output Power (W)
100
Summary
This article reviewed the design of a 100-W PFC ac/dc
preregulator, which is the first stage in a two-stage power
converter. The UCC2851X family of combination PWM
controllers is perfect for offline applications that require
PFC and auxiliary power supplies to meet different system
requirements. The performance of this two-stage power
converter is shown in Figures 6–9.
References
For more information related to this article, you can download an Acrobat Reader file at www-s.ti.com/sc/techlit/
litnumber and replace “litnumber” with the TI Lit. # for
the materials listed below.
Document Title
TI Lit. #
1. Laszlo Balogh, “Design Review: 140W,
Multiple Output High Density DC/DC
Converter,” p. 6-9 . . . . . . . . . . . . . . . . . . . . . . . . .slup117
2. Laszlo Balogh, “Unitrode – UC3854A/B and
UC3855A/B Provide Power Limiting With
Sinusoidal Input Current for PFC Front Ends,”
Unitrode Design Note . . . . . . . . . . . . . . . . . . . . .slua196
8
Document Title
TI Lit. #
3. Lloyd Dixon, “Control Loop Cookbook,”
p. 5-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .slup113
4. Lloyd Dixon, “Optimizing the Design of a
High Power Factor Switching Preregulator,”
pp. 7-11–7-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . .slup093
5. James P. Noon, “A 250kHz, 500W Power
Factor Correction Circuit Employing Zero
Voltage Transitions,” pp. 1-11–1-14 . . . . . . . . . .slup106
6. “Practical Considerations in Current Mode
Power Supplies,” Unitrode Application Note . . .slua110
7. “Advanced PFC/PWM Combination
Controllers,” Data Sheet . . . . . . . . . . . . . . . . . . .slus517
8. “UCC28517 EVM User’s Guide” . . . . . . . . . . . . sluu117
Related Web sites
analog.ti.com
www.ti.com/sc/device/TL431
www.ti.com/sc/device/UCC28517
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C011905
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