Data Acquisition Texas Instruments Incorporated Implementation of 12-bit delta-sigma DAC with MSC12xx controller By Hugo Cheung, MSC Group, Data Acquisition Products (Email: [email protected]), and Sreeja Raj, MSC Group, Data Acquisition Products (Email: [email protected]) Introduction Figure 1. High-level block diagram of a PWM or ∆Σ DAC Digital-to-analog converters (DACs) are usually used as an interface between digital systems and continuous analog circuitry. To choose the type of DAC best suited for an application, the designer must consider many important performance measures. • Resolution: Generally, a DAC is specified by the number of bits in the input, or the input width, which represents the number of voltage levels (2N for an N-bit DAC) that can be generated by the DAC. • Full-scale (FS): If a DAC is implemented to represent the voltages from 0 V to the power-supply voltage, VCC, then the lowest DAC input code should represent 0 V and the highest should represent VCC, or the full-scale voltage. Each analog voltage step of an N-bit DAC is given by FS VLSB = N . 2 DACIN [15:0] PWM/ ∆Σ Modulator PWM/∆ΣOUT Bitstream Low-Pass Filter Analog Voltage Figure 2. Bitstream output for PWM and ∆Σ DAC for DACIN = 3011 Sawtooth Waveform 8 7 6 5 4 3 2 1 0 DACIN = 3011 1 0 VCC • Output bitstream: The output of a pulse-width modulator (PWM) or deltasigma (∆Σ) DAC is a stream of pulses, referred to as a bitstream, which is VFS 0 1 0 0 1 0 1 0 passed through a low-pass filter to get the precision analog output voltage (see Figure 1). The frequency of the bitstream decides the complexity and size Frame Period of the filter design. Higher frequencies will result in smaller filters. • Average analog output voltage: The output of the filter is an analog voltage corresponding to the average on-time of the bitstream input to the low-pass filter. If the frame – period (Figure 2) is divided into 2N parts, the on-time is represented as the number of parts in the frame, where the bitstream is 1. The analog voltage is given by On-time × FS . 2N For example, in Figure 2, the average analog output equals 3/8 × VCC. There are various types of DACs based on different methods of conversion. Two of them are: PWM Bitstream ∆Σ Bitstream 1-Bit On-Time PWM DAC: This is the simplest type of DAC. In this method of conversion, a stream of pulses is passed through a low-pass analog filter, and the width of the pulse is determined by the digital input code. Generally, the implementation compares a sawtooth waveform and the DAC input to produce an output pulse with on-time proportional to the DAC input. – ∆Σ DAC: In this method, the output is a stream of pulses of equal width such that the average density of the pulses corresponds to the digital input value. The output stream is then passed through a low-pass filter to produce an analog voltage. 27 Analog Applications Journal 1Q 2005 www.ti.com/sc/analogapps Analog and Mixed-Signal Products Data Acquisition Texas Instruments Incorporated Design of ∆Σ DAC This section explains the structure, operation, theory, and implementation of a ∆Σ DAC. Therefore, the average analog output voltage is 3/8 × FS. Table 2 shows the bitstream for all the inputs of a 3-bit DAC and their corresponding average analog output voltage. Theory of ∆Σ conversion Structure As the name suggests, a ∆Σ DAC makes computations using binary adders (see Figure 3). Their functionality is as follows: • ∆ adder: This adder is used to compute the difference between the DAC input and DAC output. The ∆ feedback signal to the ∆ adder (Figure 3) depends on the DAC output, which is either a 1 or a 0. If it is a 0, then ∆ is an N+2 bit number with all 0s. If it is a 1, then ∆ is the 1’s complement of the highest N bit number, sign-extended to N+2 bits. It is equivalent to two 1s concatenated as MSBs to an N bit number of all 0s. The DACIN is an unsigned number; however, since the outputs of both adders represent signed numbers, it is sign-extended. Therefore, the outputs of the ∆ adder and Σ adder are signed numbers. For example, in the 3-bit case, the output of the adders is 5 bits. When the DAC input is 0, the output is always 0 V. • Σ adder: This adder is used to compute the sum of the ∆ adder output and the current content of the Σ register. The output of the Σ adder is stored in the Σ register. The MSB of the Σ register gives the DAC output (DACOUT). Operation The ∆Σ operation can be explained with a 3-bit example. Table 1 details the bitstream computation steps for a single case, when the DACIN is equal to 3011. At t0, the value of Σ is initialized with 10000. The bitstream from t0 to t7 has three 1s. The ratio of on-time to frame time is 3/8. The Σ adder functions like an integrator, which accumulates the input at a rate or slope proportional to the magnitude of the input. When Σ becomes a negative number—i.e., when the MSB equals 1—the ∆ error signal is subtracted from Σ such that the accumulated value is reduced to a smaller positive value. Then the integration is continued until the overflow takes place again. The MSB of Σ is the DACOUT, and the rate at which the MSB becomes 1 is directly proportional to the DAC input. Therefore, the density of 1s in the DACOUT bitstream is also directly proportional to the input. Implementation of ∆Σ DAC There are different approaches for implementing a DAC, depending on the resources used for the computations. It can be completely implemented with hardware only, software only, or a combination of both. • Hardware-only implementation: This is the best possible method in terms of both performance and accuracy. Since all the computations are done by hardwired circuits, this implementation is also the fastest. • Software-only implementation: In this method, the microcontroller is programmed to perform all the operations involved in the ∆Σ conversion. Although this is inexpensive, as it does not use any hardware resources, it exacts huge penalties of lower speed and loss of accuracy from software-induced errors and uncertainties. Table 1. DACOUT computation steps for DACIN = 3011 ∆ ∆OUT Σ ΣOUT DACOUT t0 11000 11011 10000 01011 t1 00000 00011 01011 01110 t2 00000 00011 01110 10001 t3 11000 11011 10001 01100 TIME t4 00000 00011 01100 01111 t5 00000 00011 01111 10010 t6 11000 11011 10010 01101 t7 00000 00011 01101 10000 t8 11000 11011 10000 01011 1 0 0 1 0 0 1 0 1 Table 2. Bitstream and average analog output voltage for 3-bit DAC inputs Figure 3. ∆Σ modulator DACOUT BITSTREAM Σ [N+1:0] ∆ Adder DACIN N + N+2 ∆ OUT + N+2 ΣOUT Σ Register N+2 DACOUT Σ Adder N+2 ∆ 0 ∆= DACOUT = 0 3 x 2N DACOUT = 1 DACIN 0000 1001 2010 3011 4100 5101 6110 7111 81000 t1 2 3 4 5 6 7 8 00000000 00000010 00100010 01001010 10101010 10110110 11101110 11111110 11111111 ANALOG OUTPUT VOLTAGE (FS = VCC) (V) 0 1/8 × FS 2/8 × FS 3/8 × FS 4/8 × FS 5/8 × FS 6/8 × FS 7/8 × FS FS 28 Analog and Mixed-Signal Products www.ti.com/sc/analogapps 1Q 2005 Analog Applications Journal Data Acquisition Texas Instruments Incorporated • Hardware/software co-implementation: This method, described next, uses part hardware and part software, which helps to minimize the errors induced by software computations. The use of hardware adders improves speed considerably. Hardware/software co-implementation of ∆Σ DAC with MSC12xx The implementation method of the ∆Σ DAC described in this article uses both hardware and software resources of the MSC12xx block (see the Appendix on page 32). One of the adders is implemented with the accumulator/shift (ACCSH) block of the MSC12xx (Figure 4). The summation/ shift feature of this module can be used only when the ADCON bit is set to 0 in the power-down control register (PDCON), and the summation/shift control register (SSCON) has to be appropriately set to enable summation mode. The output of the ∆ adder is obtained by executing a software algorithm with the microcontroller. If the output of the DAC is 0, then the output of the ∆ adder should be the DAC input itself. If the DAC output is 1, then we need to add the 1’s complement of all the 1s sign-extended to N+2 bits. For example, the 1’s complement of FFH (for an 8-bit number, sign-extended to N+2 bits) will be 300H. If this is added to the DAC input, it is equivalent to concatenating two 1s as the MSBs of the DAC input (Table 1). Therefore, we eliminate the ∆ adder and use software to generate ∆OUT : If DACOUT = 0 ∆OUT = DACIN; else ∆OUT = Concatenate 11 with DACIN; end if; The Σ adder of the ∆Σ modulator is implemented directly with the hardwired adder in the ACCSH block. The next step is to send the DAC output to a port of the device so it can be filtered and used for some applications (see Figure 5). There are several means of writing the output of the DAC to an output port of the MSC12xx. The serial peripheral interface (SPI) output can be used to observe the DAC output as a series waveform. The SPI can be run either in the master mode, where it derives a clock Figure 4. Simplified block diagram of ACCSH block ∆OUT Summation/Shift Register (A) (SUMR3-0- 32-Bit) + Summation/Shift Register (B) (SUMR3-0- 32-Bit) Figure 5. SPI port for DAC output ∆ΣOUT PWM t CLK CPU CLK SPI SPIDATA MSC1211 from the CPU itself, or in the slave mode, where the user can provide the clock or the clock can be generated from a timer or PWM. The disadvantage of running the SPI in the master mode is that some clock cycles may be wasted, as the SPI clock is a discrete multiple of the CPU clock speed in the master mode. With the CPU running with a 22-MHz crystal, it takes about 50% of the CPU’s time to run the output bitstream at 150 kHz. Comparing ∆Σ DAC with PWM DAC To compare the performance of the ∆Σ DAC, a PWM DAC was implemented with software and the microcontroller on the same MSC12xx board. In the implementation, a counter was used to count from 0 to 2N–1, and the count value was compared with the DAC input after each increment. The DAC output was maintained at 1 until the counter exceeded the DAC input, when it was pulled down to 0. When the counter expired, the DAC output was set back to 1; so a series of pulses was generated with an on-time proportional to the DAC input. The disadvantage of this type of DAC is that, since the frequency of the output bitstream is the same as the frame rate, it is not possible to achieve very high frequencies for the output as compared with the ∆Σ DAC. Therefore, to obtain an analog output voltage, we will need to design filters with large time constants. For a fair comparison, we chose a PWM implemented with a timer running at a frequency of 10 MHz. For a 12bit DAC, the frame rate would be equal to 2.5 kHz. With a ∆Σ DAC, more than 90% of the DACIN codes will result in a ∆OUT bit frequency greater than 8 kHz. Therefore, the ∆Σ DAC output filter design is much easier than for a PWM DAC. Hence, the disadvantages of using a PWM DAC are as follows: • Requires larger filters. • For very low/high codes, the PWM on/off-time might not accurately represent the code because there might be software overhead that causes the on/off-time to be greater than the exact time representing the code. • Some devices don’t have double-buffered timers. This will cause some software uncertainties during the duty-cycle transition in the PWM DAC, which might result in poor integral/differential nonlinearity (INL/DNL) performance. 29 Analog Applications Journal 1Q 2005 www.ti.com/sc/analogapps Analog and Mixed-Signal Products Data Acquisition Texas Instruments Incorporated Filter design Settling time In the DACs previously described, the DAC outputs are always a stream of pulses. To generate an analog output voltage corresponding to the digital input, the pulse stream is passed through an analog low-pass filter. The filter output is the average signal level of the pulse stream. There are several issues in the design of an RC low-pass filter, including attenuation of high-frequency components, settling time, and INL/DNL performance. These issues will be discussed in detail next, with a DAC of 12-bit resolution used as an example. A very important parametric of the DAC performance is the settling time, which is the time required to settle within the range of 1-LSB voltage without error. The required settling times for 10-, 12-, 14-, and 16-bit DACs are shown in Table 4. The settling time is computed as a factor of the RC time constant. The factor is the number of time constants required to settle to a 1-LSB value. Figure 6 shows the DAC settling time versus bit resolution when the DAC input is changed from 0 to FS and vice versa. Figure 6. DAC settling time vs. bit resolution The maximum ripple allowed in the filtered output has to be less than the voltage corresponding to 1 LSB (see Table 3). For a 12-bit DAC, with the highest voltage (FS) equal to 5 V, this value is 1 20 log 12 = −72 dB. 2 (1) Table 3. Required attenuation 12 FS to 0 (1st RC) 0 to FS (1st RC) 0 to FS (2nd RC) FS to 0 (2nd RC) 10 Resolution (Bits) Attenuation of high-frequency components 8 6 4 2 NO. OF BITS (N) 10 12 14 16 MAX RIPPLE (1 LSB WITH FS = 5 V) (V) 0.0048 0.00122 0.00031 0.000076 0 –0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 Time (s) This attenuation should be attained at the lowest possible frequency. To keep the filter design reasonable, we assume that the DAC input is always above 5% of the total number of codes (2N for an N-bit DAC). For a 12-bit DAC, this value is given by CCH. For the specifications of the board and crystal chosen for the design, the SPI clock rate (bitstream frequency) was found to be 150 kHz, and the frequency corresponding to CCH was 8.9 kHz. The RC time constant of the filter is calculated as follows: H(ω ) = 0.1 VOUT 1 = VIN 1 + (ωRC)2 (2) Solving for RC with Equations 1 and 2, we get RC = 0.0712 s. INL/DNL performance The filter design under discussion is a very simplified form of the output circuitry of a ∆Σ DAC. If the output voltage is measured with only this filter, then a significant degradation in INL/DNL performance is expected. To achieve the desired INL/DNL performance, certain auxiliary circuits have to be designed along with the filter to minimize output transistor resistance and digital power-supply noise (see Figure 7). In addition, for impedance matching, a buffering circuit should follow the filter before the analog voltagemeasuring instrument. The design of these analog circuits is briefly discussed here. The digital bitstream from the DAC (denoted as DIN) is passed through the conditioning circuit, resulting in an analog voltage output that is used for INL/DNL measurements. The optical coupler HCPL-0630 is used to provide isolation between the digital and analog sides, which Table 4. Theoretical calculations for settling times for DACs with different bit resolutions NO. OF BITS (N) 10 12 14 16 5% OF 2N 33H CCH 333H CCCH BITSTREAM FREQUENCY (kHz) 8.9 8.9 8.9 8.9 RC TIME CONSTANT (s) 0.0179 0.0712 0.283 1.128 TYPICAL NO. OF RC TIME CONSTANTS REQUIRED 8 9 11 12 SETTLING TIME (s) 0.143 0.641 3.1176 13.54 30 Analog and Mixed-Signal Products www.ti.com/sc/analogapps 1Q 2005 Analog Applications Journal Data Acquisition Texas Instruments Incorporated LSB significantly reduces the Figure 7. Conditioning circuit to improve INL/DNL performance impact of digital noise on the analog signal. The isolated signal is then passed through C1 10 µF an inverter and the RC filter. U1 T2 R1 Finally, the filtered output is HCPL-0630 2 DIN 332 Ω 1 R3 R4 1 T5 passed through a voltageVCC 8 4.02 kΩ A1 5 U3A A+ 71.5 kΩ 4 2 7 2 3 follower op amp buffer to yield T1 C1 V01 OPA2277 DGND 3 U2 SN74AHCT1G14 6 an analog voltage in the range V02 C2 T4 3 C2 DGND 5 4 of 0 to 5 V. The op amps use 1 µF T6 GND GND A1 A– the 9-V supply voltage, but GND additional circuitry is required T3 to generate a 5-V supply for the V+ R2 inverter and optical coupler. 1.21 kΩ U4 C4 TPS76150 BVR C3 1µF The results of the INL/DNL R5 1 µF 5 1 6 – IN OUT D1 calculation are plotted in 10 Ω 7 2 9-V 1N4148 U3B GND Figures 8 and 9. We can see Supply 5 3 4 + EN NC that the conditioning circuit OPA2277 D2 C5 1N4148 results in excellent DNL per0.1 µF formance (±0.2 LSB) but does T7 not help to correct INL errors V– (±0.6 LSB) to a large extent. GND The INL performance is degraded because of the different gains the RC filter offers to the higher bitstream frequencies and those closer Figure 8. DNL measurements for ∆Σ DAC to 0. The filter needs to have flatter frequency response in the passband. To improve the INL performance, another 0.3 RC filter was cascaded, thus forming a second-order filter. DNL (1st RC) Although this degraded the settling-time performance, it 0.2 DNL (2nd RC) helped reduce the INL error to ±0.2 LSB and the DNL 0.1 error to ±0.15 LSB. Conclusion A ∆Σ DAC is implemented on an MSC1211 microcontroller board with both hardware and software resources. The ∆ adder is implemented with software, and the Σ adder is implemented with the hardware adder on the MSC1211 board. The design results in a very efficient ∆Σ DAC, as it offers much better speed and error-free performance as compared with a software-only implementation. Also, with a higher bit rate, the frequency spectrum is better than that of a PWM DAC, resulting in smaller filters and faster settling times. 0 –0.1 –0.2 –0.3 0 500 1000 1500 2000 2500 3000 3500 4000 DAC Code Figure 9. INL measurements for ∆Σ DAC Related Web sites 1.6 INL (1st RC) INL (2nd RC) 1.2 LSB analog.ti.com www.ti.com/sc/device/partnumber Replace partnumber with MSC1211Y2, OPA2277, SN74AHCT1G14, or TPS76150 0.8 0.4 0 –0.4 0 500 1000 1500 2000 2500 3000 3500 4000 DAC Code 31 Analog Applications Journal 1Q 2005 www.ti.com/sc/analogapps Analog and Mixed-Signal Products Data Acquisition Texas Instruments Incorporated Appendix—C program for 12-bit ∆Σ DAC with MSC12xx #include <REG1210.H> #include <stdio.h> void autobaud (); sbit REQ = P3^7; sbit ACK = P3^6; union intU { int i; struct{ unsigned char b1; unsigned char b0; } byt; }; union intU dacbuf; void INT0_isr(void) interrupt 0 { T0=1; // INL & DNL test /* if ((dacbuf.i % 2)==0) dacbuf.i+=1; else dacbuf.i+=31; if(dacbuf.i==4096) dacbuf.i=0; printf(“\n**%d**\n”,dacbuf.i); */ // Step response test if (dacbuf.i==0) dacbuf.i=4095; else dacbuf.i=0; } void main(void) { unsigned char lut[8] = {1,2,4,8,16,32,64,128}; unsigned char outbuf, bitcnt; autobaud(); // Init SPI PDCON = 0x66; P1DDRH = 0xDD; //b11011101; SS = 0; SSCON = 0; //Clear summation registers SSCON = 0x10; //Enabling summation mode of the ACCSH register SPICON = 0x00; //Setting the SPI control to slave mode SPITCON = 0x08; //Setting drive immediately SPIDATA = 0x00; //Init PWM, used for SPI clk, connect PWM o/p to SCLK PWMCON = 0x09; // Set period, SysClk source, PWM mode PWM = 0x0085; // PWM period PWMCON = 0x00; // Disable PWM/tone PWMCON = 0x19; // Set duty, SysClk source, PWM mode PWM = 0x0042; // PWM duty // INT0 edge interrupt printf(“Delta Sigma DAC\n”); dacbuf.i=0; EX0=1; IT0=1; EA=1; while(1) { bitcnt = 0; outbuf = 0; for(bitcnt=0;bitcnt<8;bitcnt++) { if ((SUMR1&0x20) != 0){ SUMR1 = 0x30 | dacbuf.byt.b1; outbuf = outbuf | lut[bitcnt]; //The i-th bit of OUTBUF is forced to 1 } else SUMR1 = dacbuf.byt.b1; SUMR0 = dacbuf.byt.b0; } while (!(AIE & 0x08)) {} // Wait for SPI TX empty SPIDATA = outbuf; outbuf = SPIDATA ; // Clear SPI RX buf } //Main 32 Analog and Mixed-Signal Products www.ti.com/sc/analogapps 1Q 2005 Analog Applications Journal IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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