LVDS Interface ICs 56bit LVDS Receiver 8:56 DeSerializer BU7985KVT ●Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI. ●Features ■Wide dot clock range : Single(112MHz)/Dual(180MHz)(NTSC, VGA, SVGA, WXGA UXGA) ■Support clock frequency from 20MHz up to 112MHz. ■User programmable LVCMOS data output triggering timing by using either rising or falling edge of clock. ■User programmable LVCMOS data and clock output driving ability. ■Support Fail-Safe Hi-z Operation. ■56bit LVDS transmitter is recommended to use BU7988KVT. ●Applications Flat Panel Display ●Precaution ■This chip is not designed to protect from radioactivity. Jun.2008 ●Block Diagram LVDS Input RB1+/- 1st Link + + - RC1+/- + - RD1+/- + - 28 8 RED1 8 GREEN1 8 BLUE1 VSYNC + - PLL + - RB2+/- + - RC2+/RD2+/RCLK2+/（20 to 90MHz) SERIAL TO PARALLEL 2nd Link RA2+/- 1st Data HSYNC DE MUX RCLK1+/（20 to 112MHz) SERIAL TO PARALLEL RA1+/- LVCMOS Output + + + - 28 PLL R/F DRVSEL XRST Figure-1 Block Diagram 2 / 20 RECEIVER CLOCK OUT （20 to 90MHz) D to D （10 to 56MHz) S to D 8 RED2 8 GREEN2 8 BLUE2 2nd Data ●TQFP100V Package Outline and Specification Product No. 16.0±0.3 14.0±0.2 51 75 76 50 16.0±0.3 14.0±0.2 BU7985KVT 1PIN MARK 100 26 0.5 Lot No. 25 1 1.2MAX 1.0±0.1 0.1±0.1 0.125±0.1 Figure-2 0.2±0.1 0.5 0.1 TQFP100V Package Outline and Specification 3 / 20 G10 R17 R16 53 51 52 G12 G11 54 G13 58 57 55 G14 59 56 G16 G15 61 GND VDD G17 62 60 B11 B10 63 B12 B14 B13 67 64 VDD B15 69 66 65 B16 GND 68 B17 71 70 HSYNC 72 20 21 22 23 24 25 G20 G21 G22 G23 G24 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 R15 GND VDD R14 R13 R12 R11 R10 GND VDD CLKOUT B27 B26 B25 B24 B23 GND VDD B22 B21 B20 G27 GND VDD G26 G25 19 R27 18 R25 R26 15 16 17 14 R24 VDD GND 12 R22 R23 13 11 R21 7 8 GND 9 6 MODE1 10 5 R20 4 R/F DRVSEL 3 GND 2 XRST MODE0 1 100-Pin TQFP (Top View) PLL_GND 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PLL_VDD LVDS GND RA1RA1+ RB1RB1+ LVDS VDD RC1RC1+ RCLK1 RCLK1+ RD1RD1+ LVDS GND RA2RA2+ RB2RB2+ LVDS VDD RC2RC2+ RCLK2RCLK2+ RD2RD2+ LVDS GND 75 DE VSYNC 74 73 ●Pin configuration Figure-3 Pin Diagram (Top View) 4 / 20 ●Pin Description Table 1 : Pin Description Pin Name Pin No. Type RA1+, RA1- 78, 77 RB1+, RB1- 80, 79 RC1+, RC1- 83, 82 RD1+, RD1- 87, 86 RCLK1+, RCLK1- 85, 84 RA2+, RA2- 90, 89 RB2+, RB2- 92, 91 RC2+, RC2- 95, 94 RD2+, RD2- 99, 98 RCLK2+, RCLK2- 97, 96 R17 ～ R10 52, 51, 50, 47, 46, 45, 44, 43 OUT G17 ～ G10 62, 61, 60, 59, 58, 55, 54, 53 OUT B17 ～ B10 72, 71, 68, 67, 66, 65, 64, 63 OUT R27 ～ R20 19, 18, 17, 14, 13, 12, 11, 10 OUT G27 ～ G20 29, 26, 25, 24, 23, 22, 21, 20 OUT B27 ～ B20 39, 38, 37, 36, 35, 32, 31, 30 OUT DE 75 OUT Data Enable Output. VSYNC 74 OUT Vsync Output. HSYNC 73 OUT Hsync Output. CLKOUT 40 OUT Clock Output. LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN DRVSEL 9 IN R/F 8 IN MODE1,MODE0 6, 5 IN Descriptions LVDS Data Input for 1st Link. The 1st pixel input data when Dual Link. + : Positive input of LVDS data differential pair. - : Negative input of LVDS data differential pair. LVDS Clock Input for 1st Link. LVDS Data Input for 2nd Link. These pins are disabled when Single Link. + : Positive input of LVDS data differential pair. - : Negative input of LVDS data differential pair. LVDS Clock Input for 2nd Link. The 1st Pixel Data Outputs. The 2nd Pixel Data Outputs. Output Driverbility Select. L: Data output 2mA / Clock output 4mA H: Data output 4mA / Clock output 8mA Output Clock Triggering Edge Select. H: Rising edge, L: Falling edge. Pixel Data Mode. MODE1 MODE0 L L L H H L H H 5 / 20 Mode Dual Link Single Link Dual Link With Fail-Safe Hiz Single Link With Fail-Safe Hiz Pin Name Pin No. Type Descriptions XRST 4 IN VDD 15, 27, 33, 41, 48, 56, 69 Power H: Normal operation, L: Power down (all outputs are pulled to ground) Power Supply Pins for LVCMOS outputs and digital circuitry. GND 3, 7, 16, 28, 34, 42, 49, 57, 70 Ground Ground Pins for LVCMOS outputs and digital circuitry. LVDS VDD 81,93 Power Power Supply Pins for LVDS inputs. LVDS GND 76, 88, 100 Ground Ground Pins for LVDS inputs. PLL VDD 2 Power Power Supply Pin for PLL circuitry. PLL GND 1 Ground Ground Pin for PLL circuitry. 6 / 20 ●Electrical characteristics ■Rating Table 2 : Absolute maximum rating Item Symbol Supply voltage Input voltage Output voltage Storage temperature range VDD VIN VOUT Tstg Value Min. Max. -0.3 -0.3 -0.3 -55 4.0 VDD+0.3 VDD+0.3 125 Unit V V V ℃ Table 3 : Package Power PACKAGE De-rating (mW/℃) *1 9.0 14.0*2 25.5*2 Power Dissipation (mW) 900 1400*2 2550*2 TQFP100V *1:At temperature Ta >25℃ *2:Package power when mounting on the PCB board. The size of PCB board :70×70×1.6（mm3） / 140×150×1.6（mm3） The material of PCB board : The FR4 glass epoxy board.(3% or less copper foil area) (It is recommended to apply the above package power requirement to PCB board when the small swing input mode is used) Table 4 : Recommended Operating Conditions Parameter Supply Voltage Operating Temperature Range Rating Symbol Units Min Typ Max VDD 3.0 3.3 3.6 V Topr -20 - 85 ℃ 7 / 20 Conditions VDD,LVDSVDD,PLLVDD ■DC characteristics Table 5 : LVCMOS DC Specifications（VDD=3.0V～3.6V, Ta=-20℃～+85℃） Rating Symbol Parameter Units Min Typ Max Conditions VIH High Level Input Voltage VDD×0.8 - VDD V VIL Low Level Input Voltage GND - VDD×0.2 V VOH High Level Output Voltage 2.4 - VDD V VOL Low Level Output Voltage 0.0 - 0.4 V IINC Input Leak Current -10 - +10 μA 0V≤VIN≤VDD IOZ Output Leak Current -10 - +10 μA Output=Hiz, 0V≤VOUT≤VDD IOH = -2mA, -4mA (data) IOH = -4mA, -8mA (clock) IOL = 2mA, 4mA (data) IOL = 4mA, 8mA (clock) Table 6 : LVDS Receiver DC Specifications（VDD=3.0V～3.6V, Ta=-20℃～+85℃） Rating Symbol Parameter Units Min Typ Max Conditions VTH Differential Input High Threshold - - 100 mV VOC=1.2V VTL Differential Input Low Threshold -100 - - mV VOC=1.2V IINL Input Current -20 - +20 μA 8 / 20 VIN=2.4V/0V VDD=3.6 ■Supply Current Table 7 : Supply Current（VDD=3.3V, Ta=25℃） Rating Parameter Symbol Min Typ IRCCG IRCCW IRCCS Receiver supply current (Gray scale pattern) Receiver supply current (Checker pattern) Receiver Power Down Supply Current Max Units Conditions - 88 - mA MODE[1:0]=L L, H L CL=8pF f=90MHz - 62 - mA MODE[1:0]=L H, H H CL=8pF f=112MHz - 137 - mA MODE[1:0]=L L, H L CL=8pF f=90MHz - 89 - mA MODE[1:0]=L H, H H CL=8pF f=112MHz - - 10 μA XRST=L 9 / 20 256 Gray Scale Pattern CLKOUT Rx0/Gx0/Bx0 Rx1/Gx1/Bx1 Rx2/Gx2/Bx2 Rx3/Gx3/Bx3 Rx4/Gx4/Bx4 Rx5/Gx5/Bx5 Rx6/Gx6/Bx6 Rx7/Gx7/Bx7 ｘ=1,2 DE Figure-4 Gray scale pattern Double Checker Pattern CLKOUT R1ｎ/G1ｎ/B1ｎ R2ｎ/G2ｎ/B2ｎ n =0～7 DE Figure-5 Checker pattern 10 / 20 ■AC characteristics Table 8 : Switching Characteristics（VDD=3.0V～3.6V, Ta=-20℃～+85℃） Symbol tRCP Parameter CLK OUT Period Min Typ Max Units Dual-in / Dual-out 11.11 tRCIP 50 ns Single-in / Dual-out 17.85 2tRCIP 100 tRCH CLKOUT High Time - 0.5tRCP - ns ｔRCL CLKOUT Low Time - 0.5tRCP - ns ｔRS LVCMOS Data Setup to CLKOUT 0.3tRCP - - ns ｔRH LVCMOS data hold from CLKOUT 0.3tRCP - - ns tTLH LVCMOS Low to High Transition Time - 3.0 5.0 ns tTHL LVCMOS Low to Low Transition Time - 3.0 5.0 ｔRIP1 Input Data Position0 (TRCIP = 8.9ns) -0.25 0.0 +0.25 ｔRIP0 Input Data Position1 (TRCIP = 8.9ns) ｔRIP6 Input Data Position2 (TRCIP = 8.9ns) ｔRIP5 Input Data Position3 (TRCIP = 8.9ns) ｔRIP4 Input Data Position4 (TRCIP = 8.9ns) tTOP3 Input Data Position5 (TRCIP = 8.9ns) ｔRIP2 Input Data Position6 (TRCIP = 8.9ns) tRCIP -0.25 7 tRCIP 2 -0.25 7 tRCIP 3 -0.25 7 tRCIP 4 -0.25 7 tRCIP 5 -0.25 7 tRCIP 6 -0.25 7 tRCIP 7 tRCIP 2 7 tRCIP 3 7 tRCIP 4 7 tRCIP 5 7 tRCIP 6 7 tRCIP +0.25 7 tTCOP 2 +0.25 7 tRCIP 3 +0.25 7 tRCIP 4 +0.25 7 tRCIP 5 +0.25 7 tRCIP 6 +0.25 7 tRRLL Phase Lock Loop Set - - 10.0 ms tRCIP CLKIN Period 8.9 - 50 ns ｔｃｋ12 Skew Time between RCLK1 and RCLK2 - - ±0.3tRCIP ns 11 / 20 2 ns ns ns ns ns ns ns ●AC Timing ■LVCMOS 80% 80% LVCMOS Output 20% 8pF 20% t TLH LVCMOS Output Load t THL tRCH CLKOUT VDD/2 VDD/2 tRCL VDD/2 R/F=L VDD/2 R/F=H tRCP tRS Rxn tRH VDD/2 VDD/2 X=A,B,C,D n=0,1,2,3,4,5,6 Figure-6 LVCMOS output timing ■Phase-locked loops set time VDD 3.0V RCLK +/- VDD/2 PD tRPLL VDD/2 CLKOUT Figure-7 Phase-locked loops set time 12 / 20 ■AC Timing Diagrams Current cycle Previous cycle Next cycle tRCIP RCLK1 + (Differential) Vdiff=0V Vdiff=0V RA1+/- RA3 RA2 RA1 RA0 RA6 RA5 RB1+/- RB3 RB2 RB1 RB0 RB6 RB5 RC1+/- RC3 RC2 RC1 RC0 RC6 RD1+/- RD3 RD2 RD1 RD0 RD6 RA3 RA2 RA1 RA0 RA6 RB4 RB3 RB2 RB1 RB0 RB6 RC5 RC4 RC3 RC2 RC1 RC0 RC6 RD5 RD4 RD3 RD2 RD1 RD0 RD6 RA4 tRIP1 tRIP0 tRIP6 tRIP5 Figure-7 AC Timing Diagrams tRIP4 tRIP3 tRIP2 Figure-8 LVDS data and clock input timing RCLK1 + (Differential) Vdiff = 0V ｔCK12 RCLK2 + (Differential) Vdiff = 0V Note : Vdiff=(Ryx+)－(Ryx－), (RCLKx+)－(RCLKx－), 13 / 20 ●LVDS Data, Clock Input and Output Timing LVDS Input RA1+/ RA6 RA5 RA4 RA3 RA2 RA1 RA0 RB1+/ RB6 RB5 RB4 RB3 RB2 RB1 RB0 RC1+/ RC6 RC5 RC4 RC3 RC2 RC1 RC0 RD1+/ RD6 RD5 RD4 RD3 RD2 RD1 RD0 RCLK1+/- LVCMOS Output CLKOUT (R/F=L) CLKOUT (R/F=H) RA0～6 VALID VALID RB0～6 VALID VALID RC0～6 VALID VALID VALID VALID RD0～6 , Figure-9 LVDS Data, Clock Input and Output Timing 14 / 20 ●Pixel Map Table for Dual Link Table 9: Pixel Map LSB MSB LSB MSB LSB MSB 1st Pixel Data TFT Panel Data BU7985KVT LVCMOS Output 24Bit 18Bit Pin R10 R10 R11 R11 R12 R10 R12 R13 R11 R13 R14 R12 R14 R15 R13 R15 R16 R14 R16 R17 R15 R17 G10 G10 G11 G11 G12 G10 G12 G13 G11 G13 G14 G12 G14 G15 G13 G15 G16 G14 G16 G17 G15 G17 B10 B10 B11 B11 B12 B10 B12 B13 B11 B13 B14 B12 B14 B15 B13 B15 B16 B14 B16 B17 B15 B17 HSYNC HSYNC HSYNC VSYNC VSYNC VSYNC DE DE DE 2nd Pixel Data TFT Panel Data BU7985KVT LVCMOS Output 24Bit 18Bit Pin LSB R20 R20 R21 R21 R22 R20 R22 R23 R21 R23 R24 R22 R24 R25 R23 R25 R26 R24 R26 MSB R27 R25 R27 LSB G20 G20 G21 G21 G22 G20 G22 G23 G21 G23 G24 G22 G24 G25 G23 G25 G26 G24 G26 MSB G27 G25 G27 LSB B20 B20 B21 B21 B22 B20 B22 B23 B21 B23 B24 B22 B24 B25 B23 B25 B26 B24 B26 MSB B27 B25 B27 HSYNC HSYNC HSYNC VSYNC VSYNC VSYNC DE DE DE 15 / 20 ●CMOS Data Output Timing for Dual Link Example : SXGA+(1400×1050) HSYNC DE CLKOUT R1x/G1x/ B1x #1 #3 #5 #7 1395 #1397 #1399 R2x/G2x/ B2x #2 #4 #6 #8 1396 #1398 #1400 #1 #2 #1399 #1400 X=0~ 7 TFT Panel ( 1400 × 1050) Figure-10 Data Output Timing for Dual Link ●CMOS Data Output Timing for Single Link Example : SXGA+(1400×1050) HSYNC DE CLKO UT R 1 x /G 1 x /B 1 x #1 #2 #1 #2 #3 #4 1398 #1399 #1400 #1399 #1400 x=0~ 7 TFT Panel (1 4 0 0 × 1 0 5 0 ) Figure-11 Data Output Timing for Dual Link 16 / 20 ●LVDS Data Inputs Timing Diagrams in Dual Link (Dual-in / Dual-out Mode) Previous Cycle Current Cycle RCLK1+ RA1+/- R16' R15 R14' R13' R12' G12 R17 R16 R15 R14 R13 R12 G12'' RB1+/- G17' G16 G15' G14' G13' B13 B12 G17 G16 G15 G14 G13 B13'' RC1+/- HSYNC’ B17 B16 B15 B14 DE'' RD1+/- B10' G11' G10' R11' R10' G11 G10 R11 R10 X" B17' B16' B15' B14' DE VSYNC HSYNC X B11 B10 RCLK2+ RA2+/- R26' R25 R24' R23' R22' G22 R27 R26 R25 R24 R23 R22 G22'' RB2+/- G27' G26' G25' G24' G23' B23 B22 G27 G26 G25 G24 G23 B23'' RC2+/- RD2+/- X' B27' B26' B25' B24' X X X B27 B26 B25 B24 X'' B20' G21' G20' R21' R20' X B21 B20 G21 G20 R21 R20 X'' Figure-12 Data Input Timing for Dual Link 17 / 20 ●LVDS Data Inputs Timing Diagrams in Single Link (Single-in / Dual-out Mode) Previous Cycle (2nd Pixel Data) Current Cycle (1st Pixel Data) RCLK1+ RA1+/- G22 R27 R26 R25 R24 R23 R22 G12 R17 R16 R15 R14 R13 R12 G22'' RB1+/- B23 B22 G27 G26 G25 G24 G23 B13 B12 G17 G16 G15 G14 G13 B23'' RC1+/- DE RD1+/- X VSYNC HSYNC B27 B26 B25 B24 DE B21 B20 G21 G20 R21 R20 X VSYNC HSYNC B17 B16 B15 B14 DE'' B11 B10 G11 G10 R11 R10 Figure-13 Data Input Timing for Single Link ●Fail-Saｆe Hi-Z Operation Connector attached (Receive Signal) All Output Toggled Connector released (No Signal) Hiz All Output Figure-14 Fail-Sage Hi-Z Operation 18 / 20 X ●About the Power On Reset Power On Reset is not mandatory for this device. （The PD pin should be set to high level when Power On Reset procedure is not used.） VDD BU7985KVT Figure–9 Terminal connection when Power On Reset is not used However, Power On Reset procedure is strongly recommend for internal logic initialization by following two methods. ① The method of using CR circuit. ② The method of using external specific IC. It is recommend to do enough examination for target application. V DD V DD VDD schottky barrier diode 10KΩ V T XRST 220Ω Be careful of temperature of the capacitor especially over and again. B characteristic ceramics and polymer aluminum are recommended. + XRST 2.2μF Internal Reset td td is approximately equal to 20ms when the left RC coleus are applied. Figure–15 Power On Reset by external a CR circuit V DD VDD power on IC (open drain output) V DD 220KΩ XRST V T XRST VOUT 0.1μF GND Detection voltage VDD Internal Reset B Characteristic ceramics. td Figure–16 Power On Reset by specific IC 19 / 20 + TQFP100V <Dimension> <Packing information> 16.0 ± 0.3 14.0 ± 0.2 51 76 1.2Max. 1.0 ± 0.1 0.1 ± 0.1 0.5 16.0 ± 0.3 14.0 ± 0.2 26 1 0.5 25 0.2 ± 0.1 500pcs Direction of product is fixed in a tray. Direction of feed 50 100 Tray(with dry pack) Quantity 0.125 ± 0.1 1pin 75 Container 0.1 （Unit:mm) ※When you order , please order in times the amount of package quantity. Catalog No.08T242A '08.6 ROHM ©