DATASHEET ADVANCE INFORMATION DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER CONFIDENTIAL IDTV105A General Description Features The V105A LVDS display interface transmitter is designed to support pixel data transmission between a video processing engine and a digital video display. The dual channel LVDS output supports pixel rates up to 150 MHz, enabling compatibility with 1080p and WUXGA display resolutions. • Dual 32+3-bit LVTTL input supports up to 150 MHz pixel rate. • Dual pixel, LVDS output supports 150 MHz pixel rate (compatible with 1080p and WUXGA resolution) Total 67-bit LVCMOS/LVTTL input is provided. The V105A converts the 67 bit parallel input data into two 5-pair LVDS (Low Voltage Differential Signaling) serial data outputs, in odd/even pixel format. Input data can be clocked on the rising or falling edge of the input clock (selectable). In video applications the 35 data bits are normally divided into 10 bits for each R, G and B channel and 5 control bits (which includes VSYNC, HSYNC and DE). • • • • Internal PLL requires no external loop filter • • • • Single 3.3 V supply Selectable rising or falling clock edge for data alignment Compatible with Spread Spectrum clock source Reduced LVDS output voltage swing mode (selectable) to minimize EMI Low power consumption CMOS design Power down mode Available in 144 pin LQFP package (14x14mm body size) Block Diagram TXA1+ TA1[9:0] TB1[9:0] 10 TXA1TXB1+ 10 TC1[9:0] 10 RES1[2:1] 2 35 Serializer TTL Input TA2[9:0] TB2[9:0] TC2[9:0] RES2[2:1] 10 Data TXB1TXC1+ TXC1TXD1+ Data latch, TXD1- 10 Bit Mapper, TXE1+ 2 Demux TXE1- 10 TXD2+ HSYNC TXD2TXE2+ VSYNC 35 DE Data Serializer CTRL 3 TXE2TXA2+ TXA2TXB2+ MAP TXB2- R/F TXC2+ TXC2- RS PD TEST TCLK1+ CLKIN PLL and Device Timing TCLK1TCLK2+ TCLK2- DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 1 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE Pin Assignment NC TC17 TC18 TC19 Vcc GND TA20 TA21 TA22 TA23 TA24 TA25 TA26 TA27 TA28 TA29 Vcc GND TB20 TB21 TB22 TB23 TB24 TB25 TB26 TB27 TB28 TB29 Vcc GND TC20 TC21 TC22 TC23 TC24 TC25 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 TC26 TC27 Vcc GND TC28 TC29 HSYNC VSYNC DE NC NC NC Vcc GND CLKIN NC RES11 RES12 RES21 RES22 R/F RS NC MAP CTRL1 CTRL0 CTRL2 NC NC PD TEST NC NC PGND PVcc PDND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 V105A TC16 TC15 TC14 GND Vcc TC13 TC12 TC11 TC10 TB19 TB18 TB17 TB16 TB15 GND Vcc TB14 TB13 TB12 TB11 TB10 TA19 TA18 TA17 TA16 GND Vcc TA10 TA14 TA13 TA12 TA11 TA10 PGND PVcc PGND 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 LGND TXA1TXA1+ TXB1TXB1+ LVcc LGND TXC1TXC1+ TCLK1TCLK1+ LVcc LGND TXD1TXD1+ TXE1TXE1+ LVcc LGND TXA2TXA2+ TXB2TXA2+ LVcc LGND TXC2TXC2+ TCLK2TCLK2+ LVcc LGND TXD2TXD2+ TXE2TXE2+ LGND DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 2 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE Pin Descriptions Pin Number Pin Name 70, 71 TXA1+, TXA1- 68, 69 TXB1+, TXB1- 64, 65 TXC1+, TXC1- 58, 59 TXD1+, TXD1- 56, 57 TXE1+, TXE1- 52, 53 TXA2+, TXA2- 50,51 TXB2+, TXB2- 46, 47 TXC2+, TXC2- 40, 41 TXD2+, TXD2- 38,39 TXE2+, TXE2- 62, 63 TCLK1+, TCLK1- 44, 45 TCLK2+, TCLK2- 76, 77, 78, 79, 80, 81, 84, 85, 86, 87 TA10 ~TA19 88, 89, 90, 91, 92, 95, 96, 97, 98, 99 TB10 ~ TB19 100, 101, 102, 103, 106, 107, 108, 110, 111, 112 TC10 ~TC19 17, 18 RES11, RES12 115, 116,117, 118, 119, 120, 121, 122, 123, 124 TA20 ~ TA29 127, 128, 129, 130, 131, 132, 133, 134, 135, 136 TB20 ~ TB29 139, 140, 141, 142, 143, 144, 1, 2, 5, 6 TC20 ~ TC29 19, 20 Pin Type Pin Description LVDS Serial Data Output Pairs, Channel 1 LVDS OUT LVDS Serial Data Output Pairs, Channel 2 LVDS OUT LVDS Reference Clock Output Pair IN CMOS/TTL (or small signal) Data Bit Inputs, Channel 1 IN Control Input, Channel 1 IN CMOS/TTL (or small signal) Data Bit Inputs, Channel 2 RES21, RES22 IN Control Input, Channel 2 7 HSYNC IN HSYNC InputI 8 VSYNC IN VSYNC Input 9 DE IN DE Input 25, 26, 27 CTRL0 ~ CTRL2 IN MODE Selection 24 MAP IN MAP MODE Selection 30 PD IN High: Normal device operation Low: Power down; all outputs become high impedance 31 TEST IN Reserved: tie to High or Low DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 3 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE Pin Number Pin Name Pin Type Pin Description 22 RS IN Voltage level on this pin sets LVDS output swing voltage and data input swing voltage; refer to the table at the bottom of this page. 21 R/F IN Input Clock triggering edge select. High: Rising edge; Low: Falling edge. 3, 13,82, 93, 104, 113, 125, 137 VCC Power Power supply pins for TTL inputs and digital circuitry 15 CLKIN IN 4, 14, 83, 94, 105, 114, 126, 138 GND Ground Ground pins for TTL inputs and digital circuitry 43, 49, 55, 61, 67 LVCC Power Power supply pins for LVDS outputs 37, 42, 48, 54, 60, 66, 72 LGND Ground Ground pins for LVDS outputs 35, 74 PVCC Power Power supply pins for PLL circuitry 34, 36, 73, 75 PGND Ground Ground pins for PLL circuitry 10, 11, 12, 16, 23, 28, 29, 32, 33, 109 NC Clock Input Reserved RS Input Voltage LVDS Output Swing CMOS/TTL Input Configuration (Input Voltage Swing) RS Input Voltage LVDS Output Swing CMOS/TTL Input Configuration (Input Voltage Swing VCC 350 mV Standard Input and Output Configuration1 0.6 ~ 1.4 V (VREF1) 350 mV Small Input Swing, Standard Output Swing Configuration1 GND 200 mV Standard Input Swing, Reduced Output Swing Configuration1 1. Refer to DC Electrical Characteristics. DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 4 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE External Components Decoupling capacitors should be used for all power pins. Absolute Maximum Ratings Rating1 Item Supply Voltage, VCC -0.3 V to +4.0 V CMOS/TTL Input Voltage -0.3 V to VCC+0.3 V CMOS/TTL Output Voltage -0.3 V to VCC+0.3 V LVDS Driver Output Voltage -0.3 V to VCC+0.3 V Storage Temperature -55 to +150°C Junction Temperature +125°C LeadTemperature (10 seconds) +260°C Maximum Power Dissipation @ 25°C 1.15 W 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Recommended Operation Conditions Symbol Parameter VCC Power Supply Voltage TA Ambient Operating Temperature CTRL<1:0> = LL (Dual-in/Dual-out) CTRL<1:0> = LH (Dual-in/Single-out) CLK CTRL<1:0> = HL (Single-in/Dual-out) CTRL<1:0> = HH (Single-in/Single-out) DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER Single Edge Input (CTRL<2> = L) Double Edge Input (CTRL<2> = H) Distribution Off (CTRL<2> = L) Distribution On (CTRL<2> = H) 5 CONFIDENTIAL Min. Typ. Max. Units +3 +3.3 +3.6 V 0 +70 °C Input 20 135 MHz LVDS Output 20 135 MHz Input 10 67.5 MHz LVDS Output 20 135 MHz Input 40 150 MHz LVDS Output 20 75 MHz Input 20 135 MHz LVDS Output 20 135 MHz Input 20 135 MHz LVDS Output 20 135 MHz Input 20 135 MHz LVDS Output 20 135 MHz IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE DC Electrical Characteristics VDD=3.3 V ±10%, Ambient temperature 0 to +70°C Parameter Symbol Conditions Min. Typ. Max. Units CMOS/TTL Inputs, Standard Configuration Input High Voltage VIH RS=VCC or GND 2.00 VCC V Input Low Voltage VIL RS=VCC or GND GND 0.80 V Input Current IINC 0V<VIN<VCC ±10 µA 2.8 V CMOS/TTL Inputs, Small Input Swing Configuration Max Input Swing Voltage VCCQ1 VREF = VRS = VCCQ/2 Input Reference Voltage into pin RS VREF High Level Input Voltage (for small input swing condition) VSH2 VREF=VCCQ/2 Low Level Input Voltage (for small input swing condition) VSL2 VREF=VCCQ/2 1.2 V VCCQ/2 VCCQ/2 V +0.1V VCCQ/2 -0.1V V 1. VCCQ voltage defines the max voltage of the small swing input and is not an actual input into the device. 2. Small input swing voltage is applied to TA1[9:0], TB1[9:0], TC1[9:0], RES1[2:1], TA2[9:0],TB2[9:0], TC2[9:0], RES2[2:1], HSYNC, VSYNC, DE, and CLKIN. Parameter Symbol Conditions Min. Typ. Max. Units Normal swing RS = VCC 250 350 450 mV Reduced swing RS = GND 100 200 300 mV 35 mV 1.375 V 35 mV LVDS Transmitter DC Specifications Differential Output Voltage, RL = 100Ω VOD Change in VOD Between Complimentary Output States DVOD Common Mode Voltage VOC Change in VOC Between Complimentary Output States Output Short Circuit Current Output Tri-State Current DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER RL = 100Ω 1.125 1.250 DVOC IOS VOUT = 0V, RL = 100Ω -24 mA IOZ PD = 0V, VOUT = 0V to VCC ±10 µA 6 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER Parameter COMMERCIAL TEMPERATURE RANGE Symbol Conditions CLKIN = 65MHz mA 86 mA CLKIN = 65MHz CTRL<1:0> = HH 68 mA CLKIN = 85MHz Single-in/Single-out CTRL<2> = H Distribution On 89 mA 141 mA 37 mA 38 mA 77 mA 85 mA CTRL<1:0> = HL 54 mA Single-in/Dual-out CTRL<2> = L DDR Input On 71 mA 113 mA 35 mA 46 mA 73 mA 80 mA 104 mA CLKIN = 135MHz 164 mA PDWN = L, All Inputs = Fixed L or H 10 µA CLKIN = 65MHz CLKIN = 85MHz RL = 100Ω CL = 5pF RS = VCC CLKIN = 135MHz CLKIN = 150MHz CLKIN = 65MHz CLKIN = 85MHz CLKIN = 135MHz CTRL<1:0> = HL Single-in/Dual-out CTRL<2> = L DDR Input Off CLKIN = 32.5MHz CTRL<1:0> = LH Dual-in/Single-out CLKIN = 42.5MHz CLKIN = 67.5MHz CLKIN = 65MHz CTRL<1:0> = LL Dual-in/Dual-out CLKIN = 85MHz ITCCS 41 mA CLKIN = 135MHz Transmitter Power Down Supply Current Units 54 CLKIN = 135MHz ITCCW Max CTRL<1:0> = HH Single-in/Single-out CTRL<2> = L Distribution Off CLKIN = 85MHz Supply Current Transmitter Supply Current (worst case pattern) Typ DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 7 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE AC Electrical Characteristics VDD=3.3 V ±10%, Ambient temperature 0 to +70°C, Mode=135 MHz Parameter Symbol Min. Typ. Max. Units 1.0 ns 100.0 ns Switching Characteristics CLK IN Transition Time tTCIT CLK IN Period tTCP 6.7 1 CLK IN High Time tTCH 2.59 3.7 4.81 ns Time1 tTCL 2.59 3.7 4.81 ns CLK IN Low CLK IN to TCLK± Delay tTCD 22.2 ns TTL Data Setup to CLK IN tTS 2.5 ns TTL Data Hold from CLK IN tTH 0 ns LVDS Transition Time tLVT Output Data Position0 tTOP1 Output Data Position1 0.6 1.5 ns -0.2 0.0 0.2 ns tTOP0 0.907 1.057 1.207 ns Output Data Position2 tTOP6 1.814 2.114 2.414 ns Output Data Position3 tTOP5 2.721 3.171 3.621 ns Output Data Position4 tTOP4 3.628 4.228 4.828 ns Output Data Position5 tTOP3 4.535 5.285 6.035 ns Output Data Position6 tTOP2 5.442 6.342 7.242 ns Phase Lock Loop Set tTPLL 10.0 ms 1. See figure 1. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER Symbol Conditions Min. Typ. Max. Units θJA Still air 53 °C/W θJA 1 m/s air flow 40 °C/W θJA 3 m/s air flow 33 °C/W 8 °C/W θJC 8 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE AC Timing Diagrams TTL Input 90% CLKIN 90% 10% 10% tTCL tTCH tTCIT. LVDS Output tTCIT. 80% VDIF = (TA+) - (TA-) 20% 20% tLVT TA+ 5pF 80% tLVT 100Ω TAFigure 1. TTL Inputs tTCP tTCH CLKIN VREF tTCL tTS VIH or VSH VIL or VSL tTH VREF Txy0-Txy9 VIH or VSH VIL or VSL tTCD TCLK+ TCLK- VOC NOTE: CLKIN for R/F = GND, solid line CLKIN for R/F = VCC, dashed line Figure 2. DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 9 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE LVDS Output VDIF = 0V VDIF = 0V TCLK1 OUT (Differential) TXA1 TXA16 TXA15 TXA14 TXA13 TXA12 TXA11 TXA10 TXB1 TXB16 TXB15 TXB14 TXB13 TXB12 TXB11 TXB10 TXC1 TXC16 TXC15 TXC14 TXC13 TXC12 TXC11 TXC10 TXD1 TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 TXE1 TXE16 TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 Previous Cycle tTOP1 Next Cycle tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2 Figure 3. DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 10 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE LVDS Output VDIF = 0V VDIF = 0V TCLK2 OUT (Differential) TXA2 TXA26 TXA25 TXA24 TXA23 TXA22 TXA21 TXA20 TXB2 TXB16 TXB25 TXB24 TXB23 TXB22 TXB21 TXB20 TXC2 TXC26 TXC25 TXC24 TXC23 TXC22 TXC21 TXC20 TXD2 TXD26 TXD25 TXD24 TXD23 TXD22 TXD21 TXD20 TXE2 TXE26 TXE25 TXE24 TXE23 TXE22 TXE21 TXE20 Previous Cycle tTOP1 Next Cycle tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2 Figure 4. DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 11 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE Phase Lock Loop Time 2.0V PD 3.6V 3.0V VCC tTPLL CLKIN VDIF = 0V TCLK1± TCLK2± Figure 5. LVDS Output Data Mapping Single-In, Dual-Out (DDR Off); MODE<2:0> = LHL Single-In, Dual-Out (DDR On) CTRL<2:0> = HHL VCC VCC DE GND CLKIN GND TA1n, TB1n, TC1n n=0-9 HSYNC VSYNC RES 11, 12 1st pixel data 2nd pixel data 1st pixel data 2nd pixel data TA1n, TB1n, TC1n n=0-9 HSYNC VSYNC RES 11, 12 VCC GND 1st pixel data 2nd pixel data 1st pixel data 2nd pixel data 1st pixel data VCC GND NOTE: CTRL2 = H (Double Edge Input) CLKIN for R/F = VCC, solid line CLKIN for R/F = GND, dashed line Figure 6. DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 12 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE Single-in/ Single-out Distribution Off: CTRL<2:0> = LHH LVDS Output Data MAP = 1 MAP = 0 TXA1[0] TA14 TA12 TXA1[1] TA15 TA13 TXA1[2] TA16 TA14 TXA1[3] TA17 TA15 TXA1[4] TA18 TA16 TXA1[5] TA19 TA17 TXA1[6] TB14 TB12 TXB1[0] TB15 TB13 TXB1[1] TB16 TB14 TXB1[2] TB17 TB15 TXB1[3] TB18 TB16 TXB1[4] TB19 TB17 TXB1[5] TC14 TC12 TXB1[6] TC15 TC13 TXC1[0] TC16 TC14 TXC1[1] TC17 TC15 TXC1[2] TC18 TC16 TXC1[3] TC19 TC17 TXC1[4] HSYNC HSYNC TXC1[5] VSYNC VSYNC TXC1[6] DE DE TXD1[0] TA12 TA18 TXD1[1] TA13 TA19 TXD1[2] TB12 TB18 TXD1[3] TB13 TB19 TXD1[4] TC12 TC18 TXD1[5] TC13 TC19 TXD1[6] RES11 RES11 TXE1[0] TA10 TA10 TXE1[1] TA11 TA11 TXE1[2] TB10 TB10 TXE1[3] TB11 TB11 TXE1[4] TC10 TC10 TXE1[5] TC11 TC11 TXE1[6] RES12 RES12 DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 13 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE Single-in/ Single-out Distribution On: CTRL<2:0> = HHH First Link Second Link LVDS Output Data MAP = 1 MAP = 0 LVDS Output Data MAP = 1 MAP = 0 TXA1[0] TA14 TA12 TXA2[0] TA14 TA12 TXA1[1] TA15 TA13 TXA2[1] TA15 TA13 TXA1[2] TA16 TA14 TXA2[2] TA16 TA14 TXA1[3] TA17 TA15 TXA2[3] TA17 TA15 TXA1[4] TA18 TA16 TXA2[4] TA18 TA16 TXA1[5] TA19 TA17 TXA2[5] TA19 TA17 TXA1[6] TB14 TB12 TXA2[6] TB14 TB12 TXB1[0] TB15 TB13 TXB2[0] TB15 TB13 TXB1[1] TB16 TB14 TXB2[1] TB16 TB14 TXB1[2] TB17 TB15 TXB2[2] TB17 TB15 TXB1[3] TB18 TB16 TXB2[3] TB18 TB16 TXB1[4] TB19 TB17 TXB2[4] TB19 TB17 TXB1[5] TC14 TC12 TXB2[5] TC14 TC12 TXB1[6] TC15 TC13 TXB2[6] TC15 TC13 TXC1[0] TC16 TC14 TXC2[0] TC16 TC14 TXC1[1] TC17 TC15 TXC2[1] TC17 TC15 TXC1[2] TC18 TC16 TXC2[2] TC18 TC16 TXC1[3] TC19 TC17 TXC2[3] TC19 TC17 TXC1[4] HSYNC HSYNC TXC2[4] HSYNC HSYNC TXC1[5] VSYNC VSYNC TXC2[5] VSYNC VSYNC TXC1[6] DE DE TXC2[6] DE DE TXD1[0 TA12 TA18 TXD2[0] TA12 TA18 TXD1[1] TA13 TA19 TXD2[1] TA13 TA19 TXD1[2] TB12 TB18 TXD2[2] TB12 TB18 TXD1[3] TB13 TB19 TXD2[3] TB13 TB19 TXD1[4] TC12 TC18 TXD2[4] TC12 TC18 TXD1[5] TC13 TC19 TXD2[5] TC13 TC19 TXD1[6] RES11 RES11 TXD2[6] RES11 RES11 TXE1[0] TA10 TA10 TXE2[0] TA10 TA10 TXE1[1] TA11 TA11 TXE2[1] TA11 TA11 TXE1[2] TB10 TB10 TXE2[2] TB10 TB10 TXE1[3] TB11 TB11 TXE2[3] TB11 TB11 TXE1[4] TC10 TC10 TXE2[4] TC10 TC10 TXE1[5] TC11 TC11 TXE2[5] TC11 TC11 TXE1[6] RES12 RES12 TXE2[6] RES12 RES12 DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 14 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE Single-in/ Dual-out DDR On or OFF: CTRL<2:0> = HHL or LHL First Pixel Data Second Pixel Data LVDS Output Data MAP = 1 MAP = 0 LVDS Output Data MAP = 1 MAP = 0 TXA1[0] TA14 TA12 TXA2[0] TA14 TA12 TXA1[1] TA15 TA13 TXA2[1] TA15 TA13 TXA1[2] TA16 TA14 TXA2[2] TA16 TA14 TXA1[3] TA17 TA15 TXA2[3] TA17 TA15 TXA1[4] TA18 TA16 TXA2[4] TA18 TA16 TXA1[5] TA19 TA17 TXA2[5] TA19 TA17 TXA1[6] TB14 TB12 TXA2[6] TB14 TB12 TXB1[0] TB15 TB13 TXB2[0] TB15 TB13 TXB1[1] TB16 TB14 TXB2[1] TB16 TB14 TXB1[2] TB17 TB15 TXB2[2] TB17 TB15 TXB1[3] TB18 TB16 TXB2[3] TB18 TB16 TXB1[4] TB19 TB17 TXB2[4] TB19 TB17 TXB1[5] TC14 TC12 TXB2[5] TC14 TC12 TXB1[6] TC15 TC13 TXB2[6] TC15 TC13 TXC1[0] TC16 TC14 TXC2[0] TC16 TC14 TXC1[1] TC17 TC15 TXC2[1] TC17 TC15 TXC1[2] TC18 TC16 TXC2[2] TC18 TC16 TXC1[3] TC19 TC17 TXC2[3] TC19 TC17 TXC1[4] HSYNC HSYNC TXC2[4] HSYNC HSYNC TXC1[5] VSYNC VSYNC TXC2[5] VSYNC VSYNC TXC1[6] DE DE TXC2[6] DE DE TXD1[0 TA12 TA18 TXD2[0] TA12 TA18 TXD1[1] TA13 TA19 TXD2[1] TA13 TA19 TXD1[2] TB12 TB18 TXD2[2] TB12 TB18 TXD1[3] TB13 TB19 TXD2[3] TB13 TB19 TXD1[4] TC12 TC18 TXD2[4] TC12 TC18 TXD1[5] TC13 TC19 TXD2[5] TC13 TC19 TXD1[6] RES11 RES11 TXD2[6] RES11 RES11 TXE1[0] TA10 TA10 TXE2[0] TA10 TA10 TXE1[1] TA11 TA11 TXE2[1] TA11 TA11 TXE1[2] TB10 TB10 TXE2[2] TB10 TB10 TXE1[3] TB11 TB11 TXE2[3] TB11 TB11 TXE1[4] TC10 TC10 TXE2[4] TC10 TC10 TXE1[5] TC11 TC11 TXE2[5] TC11 TC11 TXE1[6] RES12 RES12 TXE2[6] RES12 RES12 DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 15 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE Dual-in/ Single-out: CTRL<2:0> = HLH or LLH First Pixel Data Second Pixel Data LVDS Output Data MAP = 1 MAP = 0 LVDS Output Data MAP = 1 MAP = 0 TXA1[0](n) TA14 TA12 TXA1[0](n+1) TA24 TA22 TXA1[1](n) TA15 TA13 TXA1[1](n+1) TA25 TA23 TXA1[2](n) TA16 TA14 TXA1[2(]n+1) TA26 TA24 TXA1[3](n) TA17 TA15 TXA1[3](n+1) TA27 TA25 TXA1[4](n) TA18 TA16 TXA1[4](n+1) TA28 TA26 TXA1[5](n) TA19 TA17 TXA1[5](n+1) TA29 TA27 TXA1[6](n) TB14 TB12 TXA1[6](n+1) TB24 TB22 TXB1[0](n) TB15 TB13 TXB1[0](n+1) TB25 TB23 TXB1[1](n) TB16 TB14 TXB1[1](n+1) TB26 TB24 TXB1[2](n) TB17 TB15 TXB1[2](n+1) TB27 TB25 TXB1[3](n) TB18 TB16 TXB1[3](n+1) TB28 TB26 TXB1[4](n) TB19 TB17 TXB1[4](n+1) TB29 TB27 TXB1[5](n) TC14 TC12 TXB1[5](n+1) TC24 TC22 TXB1[6](n) TC15 TC13 TXB1[6](n+1) TC25 TC23 TXC1[0](n) TC16 TC14 TXC1[0](n+1) TC26 TC24 TXC1[1](n) TC17 TC15 TXC1[1](n+1) TC27 TC25 TXC1[2](n) TC18 TC16 TXC1[2](n+1) TC28 TC26 TXC1[3](n) TC19 TC17 TXC1[3](n+1) TC29 TC27 TXC1[4](n) HSYNC HSYNC TXC1[4](n+1) HSYNC HSYNC TXC1[5](n) VSYNC VSYNC TXC1[5](n+1) VSYNC VSYNC TXC1[6](n) DE DE TXC1[6](n+1) DE DE TXD1[0](n) TA12 TA18 TXD1[0](n+1) TA22 TA28 TXD1[1](n) TA13 TA19 TXD1[1](n+1) TA23 TA29 TXD1[2](n) TB12 TB18 TXD1[2](n+1) TB22 TB28 TXD1[3](n) TB13 TB19 TXD1[3](n+1) TB23 TB29 TXD1[4](n) TC12 TC18 TXD1[4](n+1) TC22 TC28 TXD1[5](n) TC13 TC19 TXD1[5](n+1) TC23 TC29 TXD1[6](n) RES11 RES11 TXD1[6](n+1) RES21 RES21 TXE1[0](n) TA10 TA10 TXE1[0](n+1) TA20 TA20 TXE1[1](n) TA11 TA11 TXE1[1](n+1) TA21 TA21 TXE1[2](n) TB10 TB10 TXE1[2](n+1) TB20 TB20 TXE1[3](n) TB11 TB11 TXE1[3](n+1) TB21 TB21 TXE1[4](n) TC10 TC10 TXE1[4](n+1) TC20 TC20 TXE1[5](n) TC11 TC11 TXE1[5](n+1) TC21 TC21 TXE1[6](n) RES12 RES12 TXE1[6](n+1) RES22 RES22 DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 16 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE Dual-in/ Dual-out: CTRL<2:0> = HLL or LLL First Pixel Data Second Pixel Data LVDS Output Data MAP = 1 MAP = 0 LVDS Output Data MAP = 1 MAP = 0 TXA1[0] TA14 TA12 TXA2[0] TA24 TA22 TXA1[1] TA15 TA13 TXA2[1] TA25 TA23 TXA1[2] TA16 TA14 TXA2[2] TA26 TA24 TXA1[3] TA17 TA15 TXA2[3] TA27 TA25 TXA1[4] TA18 TA16 TXA2[4] TA28 TA26 TXA1[5] TA19 TA17 TXA2[5] TA29 TA27 TXA1[6] TB14 TB12 TXA2[6] TB24 TB22 TXB1[0] TB15 TB13 TXB2[0] TB25 TB23 TXB1[1] TB16 TB14 TXB2[1] TB26 TB24 TXB1[2] TB17 TB15 TXB2[2] TB27 TB25 TXB1[3] TB18 TB16 TXB2[3] TB28 TB26 TXB1[4] TB19 TB17 TXB2[4] TB29 TB27 TXB1[5] TC14 TC12 TXB2[5] TC24 TC22 TXB1[6] TC15 TC13 TXB2[6] TC25 TC23 TXC1[0] TC16 TC14 TXC2[0] TC26 TC24 TXC1[1] TC17 TC15 TXC2[1] TC27 TC25 TXC1[2] TC18 TC16 TXC2[2] TC28 TC26 TXC1[3] TC19 TC17 TXC2[3] TC29 TC27 TXC1[4] HSYNC HSYNC TXC2[4] HSYNC HSYNC TXC1[5] VSYNC VSYNC TXC2[5] VSYNC VSYNC TXC1[6] DE DE TXC2[6] DE DE TXD1[0 TA12 TA18 TXD2[0] TA22 TA28 TXD1[1] TA13 TA19 TXD2[1] TA23 TA29 TXD1[2] TB12 TB18 TXD2[2] TB22 TB28 TXD1[3] TB13 TB19 TXD2[3] TB23 TB29 TXD1[4] TC12 TC18 TXD2[4] TC22 TC28 TXD1[5] TC13 TC19 TXD2[5] TC23 TC29 TXD1[6] RES11 RES11 TXD2[6] RES21 RES21 TXE1[0] TA10 TA10 TXE2[0] TA20 TA20 TXE1[1] TA11 TA11 TXE2[1] TA21 TA21 TXE1[2] TB10 TB10 TXE2[2] TB20 TB20 TXE1[3] TB11 TB11 TXE2[3] TB21 TB21 TXE1[4] TC10 TC10 TXE2[4] TC20 TC20 TXE1[5] TC11 TC11 TXE2[5] TC21 TC21 TXE1[6] RES12 RES12 TXE2[6] RES22 RES22 DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 17 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE Package Outline and Package Dimensions (144-pin LQFP) Package dimensions are kept current with JEDEC Publication No. 95, variation ACD. D θ D2 Ref. L INDEX AREA E1 E2 Ref. E N e 1 2 3 A D1 A2 -C- ccc C A1 b SEALING PLATE c ALL DIMENSIONS ARE IN MILLIMETERS. SYMBOL In Millimeters COMMON DIMENSIONS In Inches1 COMMON DIMENSIONS MIN MIN MAX N 144 MAX 144 A — 1.60 — .063 A1 0.05 0.15 .002 .006 A2 1.35 1.45 .053 .057 b 0.17 0.27 .007 .011 c 0.09 0.20 .004 .008 D 22.00 BASIC .866 BASIC D1 20.00 BASIC .787 BASIC D2 17.50 Ref. .689 Ref. E 22.00 BASIC .866 BASIC E1 20.00 BASIC .787 BASIC E2 17.50 Ref. .689 Ref. e 0.50 BASIC .02 BASIC L 0.45 0.75 .018 .03 q 0° 7° 0° 7° ccc — 0.08 — .003 1. For reference only. Controlling dimensions are in mm. DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER 18 CONFIDENTIAL IDTV105A 7121/3 IDTV105A DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER COMMERCIAL TEMPERATURE RANGE Ordering Information IDT XXXX Device Type X Package X Temp. Range X Shipping Carrier CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 8 Tape and Reel Blank Commercial (0°C to +70°C) DAG Thin Quad Flat PAck - Green V105A Dual-Channe, Triple 10-Bit LVDS Transmitter for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: [email protected] © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA