EN27SN1G08 - Eon Silicon Solution Inc.

EN27SN1G08
EN27SN1G08
1 Gigabit (128 Mx 8), 1.8 V NAND Flash Memory
Features
• Voltage Supply: 1.7V ~ 1.95V
• Hardware Data Protection
- Program/Erase Lockout During Power
Transitions
• Organization
- Memory Cell Array :
(128M + 4M) x 8bit for 1Gb
- Data Register : (2K + 64) x 8bit
• Reliable CMOS Floating-Gate Technology
- ECC Requirement: 1 bit/528 bytes
- Endurance: 100K Program/Erase Cycles
- Data Retention: 10 Years
• Automatic Program and Erase
- Page Program : (2K + 64) bytes
- Block Erase : (128K + 4K) bytes
• Command Register Operation
• Page Read Operation
- Page Size : (2K + 64) bytes
- Random Read : 25µs (Max.)
- Serial Access : 45ns (Min.)
• Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
• NOP: 4 cycles
• Memory Cell: 1bit/Memory Cell
• Cache Program/Read Operation
• Fast Write Cycle Time
- Page Program Time : 250µs (Typ.)
- Block Erase Time : 2ms (Typ.)
• Copy-Back Operation
• EDO mode
• Command/Address/Data Multiplexed I/O Port
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
• OTP Operation
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
General Description
The device is a 128Mx8bit with spare 4Mx8bit capacity. The device is offered in 1.8V VCC Power
Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid
data while old data is erased.
The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32
series connected Flash cells. A program operation allows to write the 1056-Word page in typical 250us
and an erase operation can be performed in typical 2ms on a 128K-Byte for device block.
Data in the page mode can be read out at 45ns cycle time per Byte. The I/O pins serve as the ports for
address and command inputs as well as data input/output. The copy back function allows the
optimization of defective blocks management: when a page program operation fails the data can be
directly programmed in another page inside the same array section without the time consuming serial
data insertion phase. The cache program feature allows the data insertion in the cache register while
the data register is copied into the Flash array. This pipelined program operation improves the program
throughput when long files are written inside the memory. A cache read feature is also implemented.
This feature allows to dramatically improving the read throughput when consecutive pages have to be
streamed out. This device includes extra feature: Automatic Read at Power Up.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Pin Configuration
(TOP VIEW)
(BGA 63L, 9mm X 11mm X 1.0mm Body, 0.8mm Pin Pitch)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Table 1. Pin Description
Symbol
I/O0 – I/O7
CLE
ALE
CE#
RE#
WE#
WP#
R/B#
Pin Name
Function
The I/O pins are used to input command, address and data, and
Data Inputs/Outputs to output data during read operations. The I/O pins float to Hi-Z
when the chip is deselected or when the outputs are disabled.
The CLE input controls the activating path for commands sent to
Command Latch
the command register. When active high, commands are latched
Enable
into the command register through the I/O ports on the rising edge
of the WE# signal.
The ALE input controls the activating path for address to the
Address Latch
internal address registers. Addresses are latched on the rising
Enable
edge of WE# with ALE high.
The CE# input is the device selection control. When the device is
in the Busy state, CE# high is ignored, and the device does not
Chip Enable
return to standby mode in program or erase operation. Regarding
CE# control during read operation, refer to ’Page read’ section of
Device operation.
The RE# input is the serial data-out control, and when active
drives the data onto the I/O bus. Data is valid tREA after the falling
Read Enable
edge of RE# which also increments the internal column address
counter by one.
The WE# input controls writes to the I/O port. Commands,
Write Enable
address and data are latched on the rising edge of the WE# pulse.
The WP# pin provides inadvertent program/erase protection
Write Protect
during power transitions. The internal high voltage generator is
reset when the WP# pin is active low.
The R/B# output indicates the status of the device operation.
When low, it indicates that a program, erase or random read
Ready/Busy Output
operation is in process and returns to high state upon completion.
It is an open drain output and does not float to Hi-Z condition
when the chip is deselected or when outputs are disabled.
VCC
Power Supply
VSS
Ground
NC
No Connection
VCC is the power supply for device.
Lead is not internally connected.
Note: Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC
or VSS disconnected.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Block Diagram
Functional Block Diagram
Vcc
Vss
X-Buffers
Latches
& Decoders
A12 – A27
1,024M + 32M Bit for 1Gb
NAND Flash Array
Y-Buffers
Latches
& Decoders
A0 – A11
Data Register & S/A
Y - Gating
Command
Command
Register
Vcc
I/O Buffers & Latches
Vss
Control Logic
& High Voltage
Generator
CE#
RE#
WE#
Global Buffers
Output
Driver
I/O0
I/O7
CLE ALE
WP#
Array Organization
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Address Cycle Map
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Address
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
Column Address
2nd Cycle
A8
A9
A10
A11
L*
L*
L*
L*
Column Address
3rd Cycle
A12
A13
A14
A15
A16
A17
A18
A19
Row Address
4th Cycle
Note:
A20
A21
A22
A23
A24
A25
A26
A27
Page Address
1. Column Address : Starting Address of the Register.
2. * L must be set to “Low”.
3. * The device ignores any additional input of address cycles than required.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Ordering Information
EN27SN
1G
08 -
45
CE
I
P
PACKAGING CONTENT
P = RoHS compliant
TEMPERATURE RANGE
I = Industrial (-40℃ to +85℃)
PACKAGE
CE = 63L 9x11x1.0mm BGA, pitch: 0.8mm,
ball: 0.45mm
SPEED OPTION for BURST ACCESS TIME
45 = 45ns
Data Length
08 = 8-bit width
DENSITY
1G = 1Gigabit [(128M + 4M) x 8 Bit]
BASE PART NUMBER
EN = Eon Silicon Solution Inc.
27SN = 1.8V Operation NAND Flash
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Product Introduction
The device is a 1,056Mbit memory organized as 64K rows (pages) by 2,112x8 columns. Spare 64x8
columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to
memory cell arrays accommodating data transfer between the I/O buffers and memory during page read
and page program operations. The program and read operations are executed on a page basis, while
the erase operation is executed on a block basis. The memory array consists of 1,024 separately
erasable 128K-byte blocks. It indicates that the bit-by-bit erase operation is prohibited on the device.
The device has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and
allows system upgrades to future densities by maintaining consistency in system board design.
Command, address and data are all written through I/O's by bringing WE# to low while CE# is low.
Those are latched on the rising edge of WE#. Command Latch Enable (CLE) and Address Latch Enable
(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands
require one bus cycle. For example, Reset Command, Status Read Command, etc require just one
cycle bus. Some other commands, like page read and block erase and page program, require two
cycles: one cycle for setup and the other cycle for execution.
In addition to the enhanced architecture and interface, the device incorporates copy-back program
feature from one page to another page without need for transporting the data to and from the external
buffer memory.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Command Set
Function
1st Cycle
2nd Cycle
Read
00h
30h
Read for Copy Back
00h
35h
Read ID
90h
-
Reset
FFh
-
Page Program
80h
10h
Copy-Back Program
85h
10h
Block Erase
60h
D0h
85h
-
Random Data Input
(1)
(1)
05h
E0h
Read Status
Cache Program
Cache Read
70h
80h
31h
15h
-
Read Start for Last Page
Cache Read
3Fh
-
Random Data Output
Acceptable Command during Busy
O
O
Note:
1. Random Data Input / Output can be executed in a page.
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Temperature Under Bias
Storage Temperature
Short Circuit Current
Symbol
VCC
VIN
VI/O
TBIAS
TSTG
IOS
Rating
-0.6 to +2.45
-0.6 to +2.45
-0.6 to VCC + 0.3 (< 2.45)
-40 to +125
Unit
V
℃
℃
mA
-65 to +150
5
Note:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, TA = – 40°C to 85°C)
Parameter
Supply Voltage
Supply Voltage
Symbol
VCC
VSS
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Min.
1.7
0
Typ.
1.8
0
Max.
1.95
0
Unit
V
V
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
DC AND OPERATION CHARACTERISTICS
(Recommended operating conditions otherwise noted)
Parameter
Page Read with
Serial Access
Operating
Program
Current
Erase
Stand-by Current (TTL)
Stand-by Current (CMOS)
Symbol
Test Conditions
Min.
Typ.
Max.
ICC1
tRC=45ns, CE# =VIL, IOUT=0mA
-
15
30
ICC2
ICC3
ISB1
ISB2
CE# =VIH, WP# =0V/VCC
CE# = VCC -0.2, WP# =0V/ VCC
-
15
15
10
VIN=0 to VCC (max)
-
-
30
30
1
50
±10
Input Leakage Current
ILI
Output Leakage Current
VIH
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current (R/B#)
uA
-
-
±10
uA
0.8 x VCC
-
VCC +0.3
V
(1)
IOH=-100uA
IOL=+100uA
VOL=0.1V
-0.3
VCC -0.1
3
4
0.2 x VCC
0.1
-
V
V
V
mA
VOUT=0 to VCC (max)
VIL
VOH
VOL
IOL (R /B#)
VALID BLOCK
Min.
1,004
Typ.
-
Max.
1,024
Unit
Blocks
Note:
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may
develop while being used. The number of valid blocks is presented as first shipped. Invalid blocks
are defined as blocks that contain one or more bad bits which cause status failure during program
and erase operation. Do not erase or program factory-marked bad blocks. Refer to the attached
technical notes for appropriate management of initial invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of
shipment and is guaranteed to be a valid block up to 1K program/erase cycles with 1 bit/528 bytes
ECC.
AC TEST CONDITION
(TA = – 40°C to 85°C, VCC=1.7V~1.95V)
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
mA
uA
-
Note:
1. VIL can undershoot to -0.4V and VIH can overshoot to VCC+0.4V for durations of 20ns or less.
2. Typical value are measured at VCC =1.8V, TA = 25℃. And not 100% tested.
Symbol
NVB
mA
(1)
ILO
Input High Voltage
Unit
Condition
0V to VCC
5 ns
VCC /2
1 TTL Gate and CL=30pF
Note:
* Refer to Ready / Busy# section, R/B output’s Busy to Ready time is decided by the pull-up resistor (RP) tied to
R/B# pin.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
CAPACITANCE
(TA = 25°C, VCC=1.8V, f =1.0MHz)
Item
Symbol
Test Condition
Input / Output Capacitance
CI/O
VIL = 0V
Input Capacitance
CIN
VIN = 0V
Note: Capacitance is periodically sampled and not 100% tested.
Min.
-
Max.
10
10
Unit
pF
pF
MODE SELECTION
CLE
ALE
CE#
H
L
L
WE#
RE#
WP#
H
X
Mode
Command Input
Read Mode
L
H
L
H
X
H
L
L
H
H
Address Input (4 clock)
Command Input
Write Mode
L
H
L
H
H
L
L
L
H
H
Data Input
L
L
L
X
Data Output
H
X
X
X
X
H
X
X
X
X
X
X
H
X
X
X
X
X
H
X
X (1)
X
X
X
L
X
X
H
X
X
0V/VCC(2)
Note:
1. X can be VIL or VIH.
2. WP# should be biased to CMOS high or CMOS low for stand-by.
Address Input (4 clock)
During Read (Busy)
During Program (Busy)
During Erase (Busy)
Write Protect
Stand-by
Program / Erase Characteristics
(TA = – 40°C to 85°C, VCC=1.7V~1.95V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Program Time
tPROG
250
700
us
Dummy Busy Time for Cache
3
700
us
tCBSY
Program
Number of Partial Program Cycles
4
Cycle
NOP
in the Same Page
Block Erase Time
tBERS
2
10
ms
Note:
1. Typical program time is defined as the time within which more than 50% of the whole pages are
programmed at 1.8V VCC and 25°C temperature.
2. tPROG is the average program time of all pages. Users should be noted that the program time
variation from page to page is possible.
3. Max. time of tCBSY depends on timing between internal program completion and data in.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min.
Max.
Unit
tCLS(1)
CLE Setup Time
25
ns
CLE Hold Time
tCLH
10
ns
CE# Setup Time
tCS
35
ns
CE# Hold Time
tCH
10
ns
WE# Pulse Width
tWP
25
ns
ALE Setup Time
tALS(1)
25
ns
ALE Hold Time
tALH
10
ns
Data Setup Time
tDS(1)
20
ns
Data Hold Time
tDH
10
ns
Write Cycle Time
tWC
45
ns
WE# High Hold Time
tWH
15
ns
ALE to Data Loading Time
tADL(2)
100
ns
Note:
1. The transition of the corresponding control pins must occur only once while WE# is held low.
2. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data
cycle.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
AC Characteristics for Operation
Parameter
Data Transfer from Cell to Register
ALE to RE# Delay
CLE to RE# Delay
Ready to RE# Low
RE# Pulse Width
WE# High to Busy
WP Low to WE# Low (disable mode)
WP High to WE# Low (enable mode)
Read Cycle Time
RE# Access Time
CE# Access Time
RE# High to Output Hi-Z
CE# High to Output Hi-Z
CE# High to ALE or CLE Don’t Care
RE# High to Output Hold
RE# Low to Output Hold
CE# High to Output Hold
RE# High Hold Time
Output Hi-Z to RE# Low
RE# High to WE# Low
WE# High to RE# Low
Read
Device Resetting
Program
Time during ...
Erase
Ready
Cache Busy in Read Cache
(following 31h and 3Fh)
Symbol
Min.
Max.
Unit
tR
tAR
tCLR
tRR
tRP
tWB
10
10
20
25
-
25
100
us
ns
ns
ns
ns
ns
tWW
100
-
ns
tRC
tREA
tCEA
tRHZ
tCHZ
tCSD
tRHOH
tRLOH
tCOH
tREH
tIR
tRHW
tWHR
45
0
15
5
15
15
0
100
60
-
30
45
100
30
5
10
500
5(1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
us
-
30
us
tRST
tDCBSYR
Note:
1. If reset command (FFh) is written at Ready state, the device goes into Busy for maximum 5us.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
NAND Flash Technical Notes
Mask Out Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is
not guaranteed by Eon. Information regarding the initial invalid block(s) is so called as the initial invalid
block information. Devices with initial invalid block(s) have the same quality level as devices with all
valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the
performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the initial invalid block(s) via address
mapping.
The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K
program/erase cycles with 1 bit/528 bytes ECC.
Identifying Initial Invalid Block(s) and Block Replacement Management
Unpredictable behavior may result from programming or erasing the defective blocks. The under figure
illustrates an algorithm for searching factory-mapped defects, and the algorithm needs to be executed
prior to any erase or program operations.
A host controller has to scan blocks from block 0 to the last block using page read command and check
the data at the column address of 0 or 2,047. If the read data is not FFh, the block is interpreted as an
invalid block. The initial invalid block information is erasable, and which is impossible to be recovered
once it has been erased. Therefore, the host controller must be able to recognize the initial invalid block
information and to create a corresponding table to manage block replacement upon erase or program
error when additional invalid blocks develop with Flash memory usage.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Algorithm for Bad Block Scanning
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Error in Write or Read Operation
Within its lifetime, the additional invalid blocks may develop with NAND Flash memory. Refer to the
qualification report for the actual data. The following possible failure modes should be considered to
implement a highly reliable system. In the case of status read failure after erase or program, block
replacement should be done. Because program status fail during a page program does not affect the
data of the other pages in the same block, block replacement can be executed with a page-sized buffer
by finding an erased empty block and reprogramming the current target data and copying the rest of the
replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it
is recommended that the read or verification failure due to single bit error be reclaimed by ECC without
any block replacement. The additional block failure rate does not include those reclaimed blocks.
Failure
Write
Read
Detection and Countermeasure sequence
Erase Failure
Program Failure
Single Bits Failure
Read Status after Erase → Block Replacement
Read Status after Program → Block Replacement
Verify ECC → ECC Correction
Note:
1. Error Correcting Code --> Hamming Code etc.
2. Example: 1bit correction / 528 Byte
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Program Flow Chart
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Erase Flow Chart
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Read Flow Chart
START
CMD 00h
Write Address
CMD 30h
Read Data
ECC Generation
Reclaim the
Error
No
Verify ECC
Yes
Page Read
Completed
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Block Replacement
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (Least Significant Bit) page
of the block to MSB (Most Significant Bit) pages of the block. Random page address programming is
prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed.
Therefore, LSB page doesn’t need to be page 0.
Page 63
(64)
(64)
Page 63
:
Page 31
:
(32)
(1)
Page 31
:
:
Page 2
(3)
Page 2
(3)
Page 1
(2)
Page 1
(32)
Page 0
(1)
Page 0
(2)
Data register
Data register
From the LSB page to MSB page
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
DATA IN: Data (1)
Data (64)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Data (64)
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
System Interface Using CE# don’t-care
For an easier system interface, CE# may be inactive during the data-loading or serial access as shown
below. The internal 2,112 bytes page registers are utilized as separate buffers for this operation and the
system design gets more flexible. In addition, for voice or audio applications that use slow cycle time on
the order of u-seconds, de-activating CE# during the data-loading and serial access would provide
significant savings in power consumption.
Program / Read Operation with “CE# not-care”
Address Information
DATA
Data In / Out
2,112 bytes
I/O
I/Ox
I/O0~ I/O7
Col. Add1
A0 ~ A7
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
ADDRESS
Col. Add2
Row Add1
A8 ~ A11
A12 ~ A19
Row Add2
A20 ~ A27
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Command Latch Cycle
Address Latch Cycle
Input Data Latch Cycle
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Serial access Cycle after Read (CLE = L, ALE = L, WE# = H)
Note:
1. Dout transition is measured at ±200mV from steady state voltage at I/O with load.
2. tRHOH starts to be valid when frequency is lower than 20MHz.
Serial access Cycle after Read (EDO Type CLE = L, ALE = L, WE# = H)
Note:
1. Transition is measured at ±200mV from steady state voltage with load.
2. This parameter is sampled and not 100% tested.
3. tRLOH is valid when frequency is higher than 20MHz.
4. tRHOH starts to be valid when frequency is lower than 20MHz.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Status Read Cycle
Read Operation
Read Operation (Intercepted by CE#)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Random Data Output In a Page
Page Program Operation
Note: tADL is the time from WE# rising edge of final address cycle to the WE# rising edge of first data
cycle.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Page Program Operation with Random Data Input
Note: tADL is the time from WE# rising edge of final address cycle to the WE# rising edge of first data
cycle.
Copy-Back Program Operation with Random Data Input
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Cache Program Operation
Cache Read Operation
CE#
CLE
ALE
WE
RE#
I/Ox
[7..0]
R/B#
CE#
CLE
ALE
WE
RE#
I/Ox
[7..0]
R/B#
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Block Erase Operation
Read ID Operation
ID Definition Table
ID Access command = 90h
1st Cycle
(Maker Code)
C8hh
1st Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
2nd Cycle
(Device Code)
A1h
3rd Cycle
4th Cycle
5th Cycle
80h
15h
40h
Description
Maker Code
Device Code
Internal Chip Number, Cell Type, etc.
Page Size, Block Size, etc.
Plane Number, Plane Size, ECC Level
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
3rd ID Data
Internal Chip Number
Cell Type
Number of
Simultaneously
Programmed Page
Interleave Program
Between multiple
chips
Cache Program
Description
1
2
4
8
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
1
2
4
8
Not Support
I/O7
I/O6
I/O5
I/O4
0
0
1
1
0
1
0
1
I/O5
I/O4
I/O3
I/O2
0
0
1
1
0
1
0
1
I/O3
I/O2
I/O1
0
0
1
1
I/O0
0
1
0
1
I/O1
0
0
1
1
I/O0
0
1
0
1
0
Support
1
Not Support
Support
0
1
Description
1KB
2KB
4KB
8KB
8
16
64KB
128KB
256KB
512KB
x8
x16
45ns
Reserved
Reserved
Reserved
I/O7
4th ID Data
Page Size
(w/o redundant area)
Redundant Area Size
(byte/512byte)
Block Size
(w/o redundant area)
Organization
Serial Access
Minimum
I/O6
0
1
0
0
1
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
5th ID Data
This Data Sheet may be revised by subsequent versions
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©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
ECC Level
Plane Number
Plane Size
(w/o redundant area)
Reserved
Description
1 bit ECC/512Byte
2 bit ECC/512Byte
4 bit ECC/512Byte
Reserved
1
2
4
8
64Mb
128Mb
256Mb
512Mb
1Gb
2Gb
4Gb
8Gb
Reserved
I/O7
I/O6
0
0
0
0
1
1
1
1
I/O5
0
0
1
1
0
0
1
1
I/O4
I/O3
I/O2
0
0
1
1
0
1
0
1
I/O1
0
0
1
1
I/O0
0
1
0
1
0
1
0
1
0
1
0
1
0
DEVICE OPERATION
Page Read
Upon initial device power up, the device defaults to Read mode. This operation is also initiated by
writing 00h command, four-cycle address, and 30h command. After initial power up, the 00h command
can be skipped because it has been latched in the command register. The 2,112Byte of data on a page
are transferred to cache registers via data registers within 25us (tR). Host controller can detect the
completion of this data transfer by checking the R/B# output. Once data in the selected page have been
loaded into cache registers, each Byte can be read out in 45ns cycle time by continuously pulsing RE#.
The repetitive high-to-low transitions of RE# clock signal make the device output data starting from the
designated column address to the last column address.
The device can output data at a random column address instead of sequential column address by using
the Random Data Outputcommand. Random Data Output command can be executed multiple times in a
page.
After power up, device is in read mode so 00h command cycle is not necessary to start a read operation.
A page read sequence is illustrated in under figure, where column address, page address are placed in
between commands 00h and 30h. After tR read time, the R/B# de-asserts to ready state. Read Status
command (70h) can be issued right after 30h. Host controller can toggle RE to access data starting with
the designated column address and their successive bytes.
Read Operation
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Random Data Output In a Page
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Page Program
The device is programmed based on the unit of a page, and consecutive partial page programming on
one page without intervening erase operation is strictly prohibited. Addressing of page program
operations within a block should be in sequential order. A complete page program cycle consists of a
serial data input cycle in which up to 2,112 byte of data can be loaded into data register via cache
register, followed by a programming period during which the loaded data are programmed into the
designated memory cells.
The serial data input cycle begins with the Serial Data Input command (80h), followed by a four-cycle
address input and then serial data loading. The bytes not to be programmed on the page do not need to
be loaded. The column address for the next data can be changed to the address follows Random Data
Input command (85h). Random Data Input command may be repeated multiple times in a page. The
Page Program Confirm command (10h) starts the programming process. Writing 10h alone without
entering data will not initiate the programming process. The internal write engine automatically executes
the corresponding algorithm and controls timing for programming and verification, thereby freeing the
host controller for other tasks. Once the program process starts, the host controller can detect the
completion of a program cycle by monitoring the R/B# output or reading the Status bit (I/O6) using the
Read Status command. Only Read Status and Reset commands are valid during programming. When
the Page Program operation is completed, the host controller can check the Status bit (I/O0) to see if
the Page Program operation is successfully done. The command register remains the Read Status
mode unless another valid command is written to it.
A page program sequence is illustrated in under figure, where column address, page address, and data
input are placed in between 80h and 10h. After tPROG program time, the R/B# de-asserts to ready state.
Read Status command (70h) can be issued right after 10h.
Program & Read Status Operation
Random Data Input In a page
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Cache Program
Cache Program is an extension of Page Program, which is executed with 2,112 byte data registers, and
is available only within a block. Since the device has 1 page of cache memory, serial data input may be
executed while data stored in data register are programmed into memory cell.
After writing the first set of data up to 2,112 bytes into the selected cache registers, Cache Program
command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to
start internal program operation. To transfer data from cache registers to data registers, the device
remains in Busy state for a short period of time (tCBSY) and has its cache registers ready for the next
data-input while the internal programming gets started with the data loaded into data registers. Read
Status command (70h) may be issued to find out when cache registers become ready by polling the
Cache-Busy status bit (I/O6). Pass/fail status of only the previous page is available upon the return to
Ready state. When the next set of data is inputted with the Cache Program command, tCBSY is affected
by the progress of pending internal programming. The programming of the cache registers is initiated
only when the pending program cycle is finished and the data registers are available for the transfer of
data from cache registers. The status bit (I/O5) for internal Ready/Busy may be polled to identity the
completion of internal programming. If the system monitors the progress of programming only with R/B#,
the last page of the target programming sequence must be programmed with actual Page Program
command (10h).
Cache Program (available only within a block)
Note:
1. Since programming the last page does not employ caching, the program time has to be that of Page
Program. However, if the previous program cycle with the cache data has not finished, the actual
program cycle of the last page is initiated only after completion of the previous cycle, which can be
expressed as the following formula.
2. tPROG = Program time for the last page + Program time for the (last-1)th page – (Program command
cycle time + Last page data loading time)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Copy-Back Program
Copy-Back Program is designed to efficiently copy data stored in memory cells without time-consuming
data reloading when there is no bit error detected in the stored data. The benefit is particularly obvious
when a portion of a block is updated and the rest of the block needs to be copied to a newly assigned
empty block. Copy-Back operation is a sequential execution of Read for Copy-Back and of Copy-Back
Program with Destination address. A Read for Copy-Back operation with “35h” command and the
Source address moves the whole 2,112byte data into the internal buffer. The host controller can detect
bit errors by sequentially reading the data output. Copy-Back Program is initiated by issuing Page-Copy
Data-Input command (85h) with Destination address. If data modification is necessary to correct bit
errors and to avoid error propagation, data can be reloaded after the Destination address. Data
modification can be repeated multiple times as shown in under figure. Actual programming operation
begins when Program Confirm command (10h) is issued. Once the program process starts, the Read
Status command (70h) may be entered to read the status register. The host controller can detect the
completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status
Register. When the Copy-Back Program is complete, the Status Bit (I/O0) may be checked. The
command register remains Read Status mode until another valid command is written to it.
Page Copy-Back Program Operation
Page Copy-Back Program Operation with Random Data Input
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Block Erase
The block-based Erase operation is initiated by an Erase Setup command (60h), followed by a two-cycle
row address, in which only Plane address and Block address are valid while Page address is ignored.
The Erase Confirm command (D0h) following the row address starts the internal erasing process. The
two-step command sequence is designed to prevent memory content from being inadvertently changed
by external noise. At the rising edge of WE# after the Erase Confirm command input, the internal
control logic handles erase and erase-verify. When the erase operation is completed, the host controller
can check Status bit (I/O0) to see if the erase operation is successfully done. The under figure illustrates
a block erase sequence, and the address input (the first page address of the selected block) is placed in
between commands 60h and D0h. After tBERASE erase time, the R/B# de-asserts to ready state. Read
Status command (70h) can be issued right after D0h to check the execution status of erase operation.
Block Erase Operation
Read Status
A status register on the device is used to check whether program or erase operation is completed and
whether the operation is completed successfully. After writing 70h command to the command register, a
read cycle outputs the content of the status register to I/O pins on the falling edge of CE or RE ,
whichever occurs last. These two commands allow the system to poll the progress of each device in
multiple memory connections even when R/B pins are common-wired. RE or CE does not need to
toggle for status change.
The command register remains in Read Status mode unless other commands are issued to it. Therefore,
if the status register is read during a random read cycle, a read command (00h) is needed to start read
cycles.
Status Register Definition for 70h Command
I/O
Page
Program
Block Erase
Read
Cache Read
I/O0
Pass / Fail
Pass / Fail
NA
NA
I/O1
I/O2
I/O3
I/O4
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
I/O5
NA
NA
Ready / Busy
True Ready / Busy
I/O6
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
I/O7
Write Protect
Write Protect
Write Protect
Write Protect
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Definition
Pass: 0
Fail: 1
Don’t cared
Don’t cared
Don’t cared
Don’t cared
Busy: 0
Ready: 1
Busy: 0
Ready: 1
Protected: 0
Not Protected: 1
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register,
followed by an address input of 00h. Four read cycles sequentially output the manufacturer code (C8h),
and the device code and 3rd, 4th and 5th cycle ID respectively. The command register remains in Read
ID mode until further commands are issued to it.
Read ID Operation
ID Definition Table
Maker Code
Device Code
3rd Cycle
4th Cycle
5th Cycle
C8h
A1h
80h
15h
40h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is
in Busy State during random read, program or erase mode, the reset operation will abort these
operations. The contents of memory cells being altered are no longer valid, as the data will be partially
programmed or erased. The command register is cleared to wait for the next command, and the Status
Register is cleared to value C0h when WP# is high. If the device is already in reset state a new reset
command will be accepted by the command register. The R/B# pin changes to low for tRST after the
Reset command is written. Refer to Figure below.
Reset Operation
Device Status Table
Operation mode
After Power-up
00h Command is latched
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
After Reset
Waiting for next command
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Cache Read
Cache Read is an extension of Page Read, and is available only within a block. The normal Page Read
command (00h-30h) is always issued before invoking Cache Read. After issuing the Cache Read
command (31h), read data of the designated page (page N) are transferred from data registers to cache
registers in a short time period of tDCBSYR, and then data of the next page (page N+1) is transferred to
data registers while the data in the cache registers are being read out. Host controller can retrieve
continuous data and achieve fast read performance by iterating Cache Read operation. The Read Start
for Last Page Cache Read command (3Fh) is used to complete data transfer from memory cells to data
registers.
Read Operation with Cache Read
CLE
CE#
WE
ALE
RE#
I/Ox
R/B#
CLE
CE#
WE
ALE
RE#
I/Ox
R/B#
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
READY/BUSY#
The device has an R/B# output that provides a hardware method of indicating the completion of a page
program, erase and random read completion. The R/B# pin is normally high but transitions to low after
program or erase command is written to the command register or random read is started after address
loading. It returns to high when the internal controller has finished the operation. The pin is an opendrain driver thereby allowing two or more R/B# outputs to be Or-tied. Because pull-up resistor value is
related to tr (R/B#) and current drain during busy (ibusy), an appropriate value can be obtained with the
following reference chart. Its value can be determined by the following guidance.
Ready/ Busy# Pin Electrical Specifications
R/B#
RP value guidance
1.85V
Rp (min)
3 mA
where IL is the sum of the input currents of all devices tied to the R/ B# pin.
RP (max) is determined by maximum permissible limit of tr
This Data Sheet may be revised by subsequent versions
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©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Data Protection & Power-up sequence
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power
on sequence. During the initialization the device R/B# signal indicates the Busy state as shown in the
figure below. In this time period, the acceptable commands are 70h.
The WP# signal is useful for protecting against data corruption at power on/off.
AC Waveforms for Power Transition
Write Protect Operation
Enabling WP during erase and program busy is prohibited. The erase and program operations are
enabled and disabled as follows:
Enable Programming:
NOTE: WP# keeps “High” until programming finish.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Disable Programming:
Enable Erasing:
NOTE: WP keeps “High” until erasing finish.
Disable Erasing:
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
One-Time Programmable (OTP) Operations
This flash device offers one-time programmable memory area. Thirty full pages of OTP data are
available on the device, and the entire range is guaranteed to be good. The OTP area is accessible only
through the OTP commands.
The OTP area leaves the factory in an unwritten state. The OTP area cannot be erased, whether it is
protected or not. Protecting the OTP area prevents further programming of that area.
The OTP area is only accessible while in OTP operation mode. To set the device to OTP operation
mode, issue the Set Feature (EFh-90h-01h) command. When the device is in OTP operation mode,
subsequent Read and/or Page Program are applied to the OTP area. When you want to come back to
normal operation, you need to use EFh-90h-00h for OTP mode release. Otherwise, device will stay in
OTP mode.
To program an OTP page, issue the Serial Data Input (80h) command followed by 4 address cycles.
The first two address cycles are column address. For the third cycle, select a page in the range of 00h
through 1Dh. The fourth cycle is fixed at 00h. Next, up to 2,112 bytes of data can be loaded into data
register. The bytes other than those to be programmed do not need to be loaded. This device supports
Random Data Input (85h) command, which can be operated multiple times in a page. The column
address for the next data to be entered may be changed to the address follows the Random Data Input
command. The Page Program confirm (10h) command initiates the programming process. The internal
control logic automatically executes the programming algorithm, timing and verification. Please note that
no partial-page program is allowed in the OTP area. In addition, the OTP pages must be programmed in
the ascending order. A programmed OTP page will be automatically protected.
Similarly, to read data from an OTP page, set the device to OTP operation mode and then issue the
Read (00h-30h) command. The device may output random data (not in sequential order) in a page by
writing Random Data Output (05h-E0h) command, which can be operated multiple times in a page. The
column address for the next data to be output may be changed to the address follows the Random Data
Output command.
All pages in the OTP area will be protected simultaneously by issuing the Set Feature (EFh-90h-03h)
command to set the device to OTP protection mode. After the OTP area is protected, no page in the
area is programmable and the whole area cannot be unprotected.
The Read Status (70h) command is the only valid command for reading status in OTP operation mode.
OTP Modes and Commands
Set feature
OTP Operation mode
OTP Protection mode
OTP Release mode
Read
Page Program
Program Protect
Leave OTP mode
EFh-90h-01h
EFh-90h-01h
EFh-90h-03h
EFh-90h-00h
Command
00h-30h
80h-10h
80h-10h
OTP Area Details
Description
Number of OTP pages
OTP page address
Number of partial page programs for each page in the OTP area
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Value
30
01h – 1Eh
1
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
PACKAGE DIMENSION
63L 9x11x1.0mm BGA, pitch: 0.8mm, ball: 0.45mm
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21
EN27SN1G08
Revisions List
Revision No
Description
Date
A
Initial Release
Remove 48-pin TSOP package option and Commercial (0℃ to +70℃)
Temperature option.
2012/03/30
B
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2012/05/21
©2011 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2012/05/21