EN27LN4G08 EN27LN4G08 4 Gigabit (512M x 8), 3.3 V NAND Flash Memory Features • Voltage Supply: 2.7V ~ 3.6V • Reliable CMOS Floating-Gate Technology - ECC Requirement: 4 bit/512 Byte - Endurance: 100K Program/Erase Cycles - Data Retention: 10 Years • Organization - Memory Cell Array : (512M + 16M) x 8bit - Data Register : (2K + 64) x 8bit • Command Register Operation • Automatic Program and Erase - Page Program : (2K + 64) bytes - Block Erase : (128K + 4K) bytes • Automatic Page 0 Read at Power-Up Option - Boot from NAND support - Automatic Memory Download • Page Read Operation - Page Size : (2K + 64) bytes - Random Read : 25µs (Max.) - Serial Access : 25ns (Min.) • NOP: 4 cycles • Cache Program Operation for High Performance Program • Cache Read Operation • Memory Cell: 1bit/Memory Cell • Copy-Back Operation - EDO mode - OTP Operation - Two-Plane Operation • Fast Write Cycle Time - Page Program Time : 250µs (Typ.) - Block Erase Time : 2ms (Typ.) • Command/Address/Data Multiplexed I/O Port • Hardware Data Protection - Program/Erase Lockout During Power Transitions This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 1 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 General Description The device is a 512Mx8bit with spare 16Mx8bit capacity. The device is offered in 3.3V VCC Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 4096 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells. A program operation allows to write the 2112-Word page in typical 250us and an erase operation can be performed in typical 2ms on a 128K-Byte for X8 device block. Data in the page mode can be read out at 25ns cycle time per Word. The I/O pins serve as the ports for address and command inputs as well as data input/output. The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. The cache program feature allows the data insertion in the cache register while the data register is copied into the Flash array. This pipelined program operation improves the program throughput when long files are written inside the memory. A cache read feature is also implemented. This feature allows to dramatically improving the read throughput when consecutive pages have to be streamed out. This device includes extra feature: Automatic Read at Power Up. Pin Configuration (TOP VIEW) (TSOPI 48L, 12mm X 20mm Body, 0.5mm Pin Pitch) NC NC NC NC NC NC RY/B# RE# CE# NC NC Vcc Vss NC NC CLE ALE WE# WP# NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Standard TSOP This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 2 NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC NC Vcc Vss NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Table 1. Pin Description Symbol I/O0 – I/O7 CLE ALE CE# RE# WE# WP# R/B# Pin Name Function The I/O pins are used to input command, address and data, and Data Inputs/Outputs to output data during read operations. The I/O pins float to Hi-Z when the chip is deselected or when the outputs are disabled. The CLE input controls the activating path for commands sent to Command Latch the command register. Commands are latched into the command Enable register through the I/O ports on the rising edge of the WE# signal with CLE high. The ALE input controls the activating path for address sent to the internal address registers. Addresses are latched into the address Address Latch register through the I/O ports on the rising edge of WE# with ALE Enable high. The CE# input is the device selection control. When the device is in the Busy state, CE# high is ignored, and the device does not Chip Enable return to standby mode in program or erase operation. Regarding CE# control during read operation, refer to ’Page read’ section of Device operation. The RE# input is the serial data-out control, and when it is low, it active drives the data onto the I/O bus. Data is valid tREA after the Read Enable falling edge of RE# which also increments the internal column address counter by one. The WE# input controls writes to the I/O port. Commands, Write Control address and data are latched on the rising edge of the WE# pulse. The WP# pin provides inadvertent program/erase protection Write Protect during power transitions. The internal high voltage generator is reset when the WP# pin is active low. The R/B# output indicates the status of the device operation. When low, it indicates that a program, erase or random read Ready/Busy Output operation is in process and returns to high state upon completion. It is an open drain output and does not float to Hi-Z condition when the chip is deselected or when outputs are disabled. VCC Power Supply VSS Ground NC No Connection VCC is the power supply for device. Lead is not internally connected. Note: Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 3 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Block Diagram Functional Block Diagram Array Organization This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 4 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Address Cycle Map I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Address 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 Column Address 2nd Cycle A8 A9 A10 A11 L* L* L* L* Column Address 3rd Cycle A12 A13 A14 A15 A16 A17 A18 A19 Row Address 4th Cycle A20 A21 A22 A23 A24 A25 A26 A27 Row Address 5th Cycle Note: A28 A29 L* L* L* L* L* L* Row Address 1. Column Address : Starting Address of the Register. 2. * L must be set to “Low”. 3. * The device ignores any additional input of address cycles than required. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 5 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Ordering Information EN27LN 4G 08 - 25 T C P PACKAGING CONTENT P = RoHS compliant TEMPERATURE RANGE C = Commercial (0℃ to +70℃) I = Industrial (-40℃ to +85℃) PACKAGE T = 48-pin TSOP SPEED OPTION for BURST ACCESS TIME 25 = 25ns Data Length 08 = 8-bit width DENSITY 4G = 4Gigabit [(512M + 16M) x 8 Bit] BASE PART NUMBER EN = Eon Silicon Solution Inc. 27LN = 3.0V Operation NAND Flash This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 6 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Product Introduction The device is a 4,224Mbit memory organized as 256K rows (pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 4096 separately erasable 128K-byte blocks. It indicates that the bit-by-bit erase operation is prohibited on the device. The device has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE# to low while CE# is low. Those are latched on the rising edge of WE#. Command Latch Enable (CLE) and Address Latch Enable (ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Command Set Function 1st Cycle 2nd Cycle 30h 35h 10h 10h D0h E0h 30h 35h E0h 81h-10h 81h-10h D0h 15h 33h 81h-15h Acceptable Command during Busy Read 00h Read for Copy Back 00h Read ID 90h Reset FFh O Page Program 80h Copy-Back Program 85h Block Erase 60h Random Data Input (1) 85h Random Data Output (1) 05h Read Status 70h O Read Status 2 F1h O Two-Plane Read (3) 60h-60h Two-Plane Read for Copy-Back 60h-60h Two-Plane Random Data Output (1) (3) 00h-05h (2) Two-Plane Page Program 80h-11h Two-Plane Copy-Back Program (2) 85h-11h Two-Plane Block Erase 60h-60h Cache Program 80h Cache Read 31h Read Start For Last Page Cache Read 3Fh (3) Two-Plane Cache Read 60h-60h Two-Plane Cache Program (2) 80h-11h Note: 1. Random Data Input / Output can be executed in a page. 2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h and FFh. 3. Two-Plane Random Data Output must be used after Two-Plane Read operation or Two-Plane Cache Read operation. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 7 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Temperature Under Bias Storage Temperature Short Circuit Current Symbol VCC VIN VI/O TBIAS TSTG IOS Rating -0.6 to +4.6 -0.6 to +4.6 Unit V -0.6 to VCC + 0.3 (< 4.6) -40 to +125 ℃ ℃ mA -65 to +150 5 Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, TA = 0 to 70°C or – 40°C to 85°C) Parameter Symbol Min. Supply Voltage VCC 2.7 Supply Voltage VSS 0 Typ. 3.3 0 Max. 3.6 0 Unit V V DC AND OPERATION CHARACTERISTICS (Recommended operating conditions otherwise noted) Parameter Page Read with Serial Access Operating Program Current Erase Stand-by Current (TTL) Stand-by Current (CMOS) Symbol Test Conditions Min. Typ. Max. ICC1 tRC=25ns, CE# =VIL, IOUT=0mA - 15 30 ICC2 ICC3 ISB1 ISB2 CE# =VIH, WP# =0V/VCC CE# = VCC -0.2, WP# =0V/ VCC - 15 15 10 Unit mA Input Leakage Current ILI VIN=0 to VCC (max) - - 30 30 1 50 ±10 Output Leakage Current ILO VOUT=0 to VCC (max) - - ±10 uA 0.8 x VCC -0.3 2.4 8 10 VCC +0.3 0.2 x VCC 0.4 - V V V V mA Input High Voltage Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current (R/B#) (1) VIH (1) VIL VOH VOL IOL (R /B#) IOH=-400uA IOL=2.1mA VOL=0.4V Note: 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC+0.4V for durations of 20ns or less. 2. Typical value are measured at VCC =3.3V, TA = 25℃. And not 100% tested. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 8 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 mA uA uA EN27LN4G08 VALID BLOCK Symbol NVB Min. 4,016 Typ. - Max. 4,096 Unit Blocks Note: 1. The device may include initial invalid blocks when first shipped. The number of valid blocks is presented as first shipped. Invalid blocks are defined as blocks that contain one or more bad bits which cause status failure during program and erase operation. Do not erase or program factorymarked bad blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment and is guaranteed to be a valid block up to 1K program/erase cycles with 4 bit/512 bytes ECC. AC TEST CONDITION (TA = 0 to 70°C or – 40°C to 85°C, VCC=2.7V~3.6V, unless otherwise noted) Parameter Condition Input Pulse Levels 0V to VCC Input Rise and Fall Times 5 ns Input and Output Timing Levels VCC /2 Output Load 1 TTL Gate and CL=50pF Note: Refer to Read/ Busy# section, R/B# output’s Busy to Ready time is decided by the pull-up resistor (Rp) tied to the R/B# pin. CAPACITANCE (TA = 25°C, VCC=3.3V, f =1.0MHz) Item Symbol Test Condition Input / Output Capacitance CI/O VIL = 0V Input Capacitance CIN VIN = 0V Note: Capacitance is periodically sampled and not 100% tested. Min. - Max. 8 8 Unit pF pF MODE SELECTION CLE ALE CE# H L L WE# RE# WP# L H X H L H X H L L H H L H L H H L L L H H Data Input L L L X Data Output H Mode Read Mode Command Input Address Input (5 clock) Write Mode Command Input Address Input (5 clock) X X X X H X During Read (Busy) X X X X X H During Program (Busy) X X X X X H During Erase (Busy) (1) X X X X X L Write Protect X X H X X 0V/VCC(2) Stand-by Note: 1. X can be VIL or VIH. 2. WP# should be biased to CMOS high or CMOS low for standby. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 9 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Program / Erase Characteristics (TA = 0 to 70°C or – 40°C to 85°C, VCC=2.7V~3.6V) Parameter Average Program Time Dummy Busy Time for Cache Program Number of Partial Program Cycles in the Same Page Block Erase Time Dummy Busy Time for Two-Plane Page Program Symbol tPROG(1) Min. - Typ. 250 Max. 750 Unit us tCBSY(2) - 3 750 us NOP - - 4 Cycle tBERS - 2 10 ms 0.5 1 us tDBSY Note: 1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V VCC and 25°C temperature. 2. tPROG is the average program time of all pages. Users should be noted that the program time variation from page to page is possible. 3. Max. time of tCBSY depends on timing between internal program completion and data in. AC Timing Characteristics for Command / Address / Data Input Parameter Symbol Min. Max. Unit (1) CLE Setup Time tCLS 12 ns CLE Hold Time tCLH 5 ns CE# Setup Time tCS 20 ns CE# Hold Time tCH 5 ns WE# Pulse Width tWP 12 ns ALE Setup Time tALS(1) 12 ns ALE Hold Time tALH 5 ns Data Setup Time tDS(1) 12 ns Data Hold Time tDH 5 ns Write Cycle Time tWC 25 ns WE# High Hold Time tWH 10 ns ALE to Data Loading Time tADL(2) 70 (2) ns Note: 1. The transition of the corresponding control pins must occur only once while WE# is held low. 2. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 10 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 AC Characteristics for Operation Parameter Symbol Min. Max. Unit Data Transfer from Cell to Register tR 25 us ALE to RE# Delay tAR 10 ns CLE to RE# Delay tCLR 10 ns Ready to RE# Low tRR 20 ns RE# Pulse Width tRP 12 ns WE# High to Busy tWB 100 ns WP# Low to WE# Low (disable mode) tWW 100 ns WP# High to WE# Low (enable mode) Read Cycle Time tRC 25 ns RE# Access Time tREA 20 ns CE# Access Time tCEA 25 ns RE# High to Output Hi-Z tRHZ 100 ns CE# High to Output Hi-Z tCHZ 30 ns CE# High to ALE or CLE Don’t Care tCSD 0 ns RE# High to Output Hold tRHOH 15 ns RE# Low to Output Hold tRLOH 5 ns CE# High to Output Hold tCOH 15 ns RE# High Hold Time tREH 10 ns Output Hi-Z to RE# Low tIR 0 ns RE# High to WE# Low tRHW 100 ns WE# High to RE# Low tWHR 60 ns Read 5(1) us (1) Device Resetting Program 10 us tRST Time during ... Erase 500 us us Ready 5(1) Cache Busy in Read Cache (following tDCBSYR 30 us 31h and 3Fh) Note: 1. If reset command (FFh) is written at Ready state, the device goes into Busy for maximum 5us. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 11 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 NAND Flash Technical Notes Mask Out Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Eon. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 4 bit/512 bytes ECC. Identifying Initial Invalid Block(s) and Block Replacement Management Unpredictable behavior may result from programming or erasing the defective blocks. Figure on next page illustrates an algorithm for searching factory-mapped defects, and the algorithm needs to be executed prior to any erase or program operations. A host controller has to scan blocks from block 0 to the last block using page read command and check the data at the 1st byte column address in the spare area of the 1st and 2nd page in the block. If the read data is not FFh, the block is interpreted as an invalid block. The initial invalid block information is erasable, and which is impossible to be recovered once it has been erased. Therefore, the host controller must be able to recognize the initial invalid block information and to create a corresponding table to manage block replacement upon erase or program error when additional invalid blocks develop with Flash memory usage. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 12 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 13 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Error in Write or Read Operation Within its lifetime, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data. The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error should be reclaimed by ECC without any block replacement. The block failure rate in the qualification report does not include those reclaimed blocks. Failure Write Read Detection and Countermeasure sequence Read Status after Erase → Block Replacement Erase Failure Program Failure Up to eight bits failure Read Status after Program → Block Replacement Verify ECC → ECC Correction ECC: 1. Error Correcting Code --> RS Code or BCH Code etc. 2. Example: 4bit correction / 512 bytes Program Flow Chart This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 14 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Erase Flow Chart Read Flow Chart This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 15 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Block Replacement Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (Least Significant Bit) page of the block to MSB (Most Significant Bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB page doesn’t need to be page 0. Page 63 (64) (64) Page 63 : Page 31 : (32) (1) Page 31 : : Page 2 (3) Page 2 (3) Page 1 (2) Page 1 (32) Page 0 (1) Page 0 (2) Data register Data register From the LSB page to MSB page Ex.) Random page program (Prohibition) DATA IN: Data (1) DATA IN: Data (1) Data (64) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 16 Data (64) ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 System Interface Using CE# don’t-care For an easier system interface, CE# may be inactive during the data-loading or serial access as shown below. The internal 2,112 bytes page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE# during the data-loading and reading would provide significant savings in power consumption. Program / Read Operation with “ CE# don’t-care “ Address Information I/O I/Ox I/O0~7 DATA Data In / Out 2112 bytes Col. Add1 A0 ~ A7 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Col. Add2 A8 ~ A11 17 ADDRESS Row Add1 A12 ~ A19 Row Add2 A20 ~ A27 Row Add3 A28 ~ A29 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Command Latch Cycle Address Latch Cycle This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 18 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Input Data Latch Cycle Serial access Cycle after Read (CLE = L, ALE = L, WE# = H) Note: 1. Dout Transition is measured at ±200mV from steady state voltage with load. 2. tRHOH starts to be valid when frequency is lower than 33MHz. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 19 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Serial access Cycle after Read (EDO Type CLE = L, ALE = L, WE# = H) Note: 1. Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 2. tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz. Status Read Cycle This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 20 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Read Operation (Read One Page) Read Operation (Intercepted by CE#) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 21 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Random Data Output In a Page Page Program Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 22 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Page Program Operation with Random Data Input Note: tADL is the time from WE# rising edge of final address cycle to the WE# rising edge of first data cycle. Copy-Back Program Operation with Random Data Input This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 23 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Cache Program Operation Cache Read Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 24 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Block Erase Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 25 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Read ID Operation Two-plane Page Read Operation with Two-plane Random Data Out This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 26 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Two-plane Cache Read Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 27 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Note: 1. The column address will be reset to 0 by the 3Fh command input. 2. Cache Read operation is available only within a block. 3. Make sure to terminate the operation with 3Fh command. If the operation is terminated by 31h command, monitor I/O6 (Ready/Busy) by issuing Status Read Command (70h) and make sure the previous page read operation is completed. If the page read operation is completed, issue FFh reset before next operation. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 28 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Two-plane Page Program Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 29 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Two-plane Cache Program Operation Two-plane Block Erase Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 30 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 ID Definition Table ID Access command = 90h Maker Code Device Code 3rd Cycle 4th Cycle 5th Cycle C8h DCh 90h 95h 54h 1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte Description Maker Code Device Code Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc. Page Size, Block Size, Redundant Area Size, Organization, Serial Access Minimum Plane Number, Plane Size 3rd ID Data Internal Chip Number Cell Type Number of Simultaneously Programmed Page Interleave Program Between multiple chips Cache Program Description 1 2 4 8 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell 1 2 4 8 Not Support I/O7 I/O6 I/O4 0 0 1 1 I/O3 I/O2 0 0 1 1 0 1 0 1 I/O1 0 0 1 1 0 1 0 1 0 Support Not Support Support I/O5 1 0 1 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 31 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 I/O0 0 1 0 1 EN27LN4G08 4th ID Data Page Size (w/o redundant area) Redundant Area Size (byte/512byte) Block Size (w/o redundant area) Organization Serial Access Time Descriptio n 1KB 2KB 4KB 8KB 8 16 64KB 128KB 256KB 512KB x8 x16 45ns Reserved 25ns Reserved I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 0 0 1 1 0 1 0 1 I/O1 I/O0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 5th ID Data Plane Number Plane Size (w/o redundant area) Reserved Descriptio n 1 2 4 8 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb Reserved I/O7 I/O6 I/O5 0 0 0 0 1 1 1 1 I/O4 0 0 1 1 0 0 1 1 32 I/O2 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. I/O3 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 DEVICE OPERATION Page Read Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h command, five-cycle address, and 30h command. After initial power up, the 00h command can be skipped because it has been latched in the command register. The 2,112Byte of data on a page are transferred to cache registers via data registers within 25us (tR). Host controller can detect the completion of this data transfer by checking the R/B# output. Once data in the selected page have been loaded into cache registers, each Byte can be read out in 25ns cycle time by continuously pulsing RE# . The repetitive high-to-low transitions of RE# clock signal make the device output data starting from the designated column address to the last column address. The device can output data at a random column address instead of sequential column address by using the Random Data Output command. Random Data Output command can be executed multiple times in a page. After power up, device is in read mode so 00h command cycle is not necessary to start a read operation. A page read sequence is illustrated in the following figure, where column address, page address are placed in between commands 00h and 30h. After tR read time, the R/B# de-asserts to ready state. Read Status command (70h) can be issued right after 30h. Host controller can toggle RE# to access data starting with the designated column address and their successive bytes. Read Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 33 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Random Data Output In a Page This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 34 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Page Program The device is programmed based on the unit of a page, and consecutive partial page programming on one page without intervening erase operation is strictly prohibited. Addressing of page program operations within a block should be in sequential order. A complete page program cycle consists of a serial data input cycle in which up to 2,112byte (1,056word) of data can be loaded into data register via cache register, followed by a programming period during which the loaded data are programmed into the designated memory cells. The serial data input cycle begins with the Serial Data Input command (80h), followed by a five-cycle address input and then serial data loading. The bytes not to be programmed on the page do not need to be loaded. The column address for the next data can be changed to the address follows Random Data Input command (85h). Random Data Input command may be repeated multiple times in a page. The Page Program Confirm command (10h) starts the programming process. Writing 10h alone without entering data will not initiate the programming process. The internal write engine automatically executes the corresponding algorithm and controls timing for programming and verification, thereby freeing the host controller for other tasks. Once the program process starts, the host controller can detect the completion of a program cycle by monitoring the R/B# output or reading the Status bit (I/O6) using the Read Status command. Only Read Status and Reset commands are valid during programming. When the Page Program operation is completed, the host controller can check the Status bit (I/O0) to see if the Page Program operation is successfully done. The command register remains the Read Status mode unless another valid command is written to it. A page program sequence is illustrated in following figure, where column address, page address, and data input are placed in between 80h and 10h. After tPROG program time, the R/B# de-asserts to ready state. Read Status command (70h) can be issued right after 10h. Program & Read Status Operation Random Data Input In a page This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 35 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Cache Program Cache Program is an extension of Page Program, which is executed with 2,112 byte (x8) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell. After writing the first set of data up to 2,112 bytes (x8) into the selected cache registers, Cache Program command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time (tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy status bit (I/O6). Pass/fail status of only the previous page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit (I/O5) for internal Ready/Busy may be polled to identity the completion of internal programming. If the system monitors the progress of programming only with R/B#, the last page of the target programming sequence must be programmed with actual Page Program command (10h). Cache Program (available only within a block) Note: 1. Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula. 2. tPROG = Program time for the last page + Program time for the (last-1)th page – (Program command cycle time + Last page data loading time) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 36 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Copy-Back Program Copy-Back Program is designed to efficiently copy data stored in memory cells without time-consuming data reloading when there is no bit error detected in the stored data. The benefit is particularly obvious when a portion of a block is updated and the rest of the block needs to be copied to a newly assigned empty block. Copy-Back operation is a sequential execution of Read for Copy-Back and of Copy-Back Program with Destination address. A Read for Copy-Back operation with “35h” command and the Source address moves the whole 2,112 byte data into the internal buffer. The host controller can detect bit errors by sequentially reading the data output. Copy-Back Program is initiated by issuing Page-Copy Data-Input command (85h) with Destination address. If data modification is necessary to correct bit errors and to avoid error propagation, data can be reloaded after the Destination address. Data modification can be repeated multiple times as shown in the following figure. Actual programming operation begins when Program Confirm command (10h) is issued. Once the program process starts, the Read Status command (70h) may be entered to read the status register. The host controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register. When the Copy-Back Program is complete, the Status Bit (I/O0) may be checked. The command register remains Read Status mode until another valid command is written to it. Page Copy-Back Program Operation Page Copy-Back Program Operation with Random Data Input This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 37 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Block Erase The block-based Erase operation is initiated by an Erase Setup command (60h), followed by a threecycle row address, in which only Plane address and Block address are valid while Page address is ignored. The Erase Confirm command (D0h) following the row address starts the internal erasing process. The two-step command sequence is designed to prevent memory content from being inadvertently changed by external noise. At the rising edge of WE# after the Erase Confirm command input, the internal control logic handles erase and erase-verify. When the erase operation is completed, the host controller can check Status bit (I/O0) to see if the erase operation is successfully done. The following figure illustrates a block erase sequence, and the address input (the first page address of the selected block) is placed in between commands 60h and D0h. After tBERASE erase time, the R/B# de-asserts to ready state. Read Status command (70h) can be issued right after D0h to check the execution status of erase operation. Block Erase Operation Read Status A status register on the device is used to check whether program or erase operation is completed and whether the operation is completed successfully. After writing 70h/F1h command to the command register, a read cycle outputs the content of the status register to I/O pins on the falling edge of CE# or RE#, whichever occurs last. These two commands allow the system to poll the progress of each device in multiple memory connections even when R/B# pins are common-wired. RE# or CE# does not need to toggle for status change. The command register remains in Read Status mode unless other commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command (00h) is needed to start read cycles. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 38 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Status Register Definition for 70h Command I/O Page Program Block Erase Read Cache Read I/O0 Pass / Fail Pass / Fail Not Use Not Use Not Use Not Use Not Use Not Use Not Use Not Use True Ready / Busy I/O1 Not Use (Pass/Fail, OTP) Definition Pass: ”0” Fail: ”1” Don’t cared I/O2 I/O3 I/O4 Not Use Not Use Not Use Not Use Not Use Not Use Not Use Not Use Not Use I/O5 Not Use Not Use Not Use I/O6 Ready / Busy Ready / Busy Ready / Busy Ready / Busy I/O7 Write Protect Write Protect Write Protect Write Protect Don’t cared Don’t cared Don’t cared Busy: ”0” Ready: ”1” Busy: ”0” Ready: ”1” Protected: ”0” Not Protected: ”1” Status Register Definition for F1h Command I/O Page Program Block Erase Cache Program Read Cache Read I/O0 Chip Pass / Fail Chip Pass / Fail Chip Pass / Fail (N) Not Use Not Use I/O1 Plane0 Pass / Fail Plane0 Pass / Fail Plane0 Pass / Fail (N) Not Use Not Use I/O2 Plane1 Pass / Fail Plane1 Pass / Fail Plane1 Pass / Fail (N) Not Use Not Use I/O3 Not Use Not Use Plane0 Pass / Fail (N-1) Not Use Not Use I/O4 Not Use Not Use Plane1 Pass / Fail (N-1) Not Use Not Use I/O5 Not Use Not Use True Ready / Busy Not Use True Ready / Busy I/O6 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy I/O7 Write Protect Write Protect Write Protect Write Protect Write Protect Definition Pass: ”0” Fail: ”1” Pass: ”0” Fail: ”1” Pass: ”0” Fail: ”1” Pass: ”0” Fail: ”1” Pass: ”0” Fail: ”1” Busy: ”0” Ready: ”1” Busy: ”0” Ready: ”1” Protected: ”0” Not Protected: ”1” Note: 1. I/Os defined NA are recommended to be masked out when Read Status is being executed. 2. N : current page, N-1 : previous page. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 39 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacturer code (C8h), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Read ID Operation ID Definition Table ID Access command = 90h 1st Cycle Maker Code C8h 2nd Cycle Device Code DCh 3rd Cycle 4th Cycle 5th Cycle 90h 95h 54h Description st 1 Byte 2nd Byte 3rd Byte 4th Byte 5th Byte Maker Code Device Code Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc. Page Size, Block Size, Redundant Area Size, Organization, Serial Access Minimum Plane Number, Plane Size This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 40 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Reset The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP# is high. If the device is already in reset state a new reset command will be accepted by the command register. The R/B# pin changes to low for tRST after the Reset command is written. Refer to the following figure. Device Status Operation mode After Power-up 00h Command is latched After Reset Waiting for next command Cache Read Cache Read is an extension of Page Read, and is available only within a block. The normal Page Read command (00h-30h) is always issued before invoking Cache Read. After issuing the Cache Read command (31h), read data of the designated page (page N) are transferred from data registers to cache registers in a short time period of tDCBSYR, and then data of the next page (page N+1) is transferred to data registers while the data in the cache registers are being read out. Host controller can retrieve continuous data and achieve fast read performance by iterating Cache Read operation. The Read Start for Last Page Cache Read command (3Fh) is used to complete data transfer from memory cells to data registers. Read Operation with Cache Read This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 41 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Two-Plane Page Read Two-Plane Page Read is an extension of Page Read, for a single plane with 2,112 byte data registers. Since the device is equipped with two memory planes, activating the two sets of 2,112 byte data registers enables a random read of two pages. Two-Plane Page Read is initiated by repeating command 60h followed by three address cycles twice. In this case, only same page of same block can be selected from each plane. After Read Confirm command (30h) the 4,224 bytes of data within the selected two page are transferred to the cache registers via data registers in less than 25us (tR). The system controller can detect the completion of data transfer (tR) by monitoring the output of R/B# pin. Once the data is loaded into the cache registers, the data output of first plane can be read out by issuing command 00h with five address cycles, command 05h with two column address and finally E0h. The data output of second plane can be read out using the identical command sequences. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 42 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Two-Plane Cache Read Two-Plane Cache Read is an extension of Cache Read, for a single plane with 2,112 byte data registers. Since the device is equipped with two memory planes, the two sets of 2,112 byte data registers enables a cache read of two pages. Two-Plane Cache Read is initiated by repeating command 60h followed by three address cycles twice. In this case only same page of same block can be selected from each plane. After Read Confirm command (33h) the 4,224 bytes of data within the selected two page are transferred to the cache registers via data registers in less than 25us (tR). After issuing Cache Read command (31h), read data in the data registers is transferred to cache registers for a short period of time (tDBSY). Once the data is loaded into the cache registers from data registers, the data output of first plane can be read out by issuing command 00h with five address cycles, command 05h with two column address and finally E0h. The data output of second plane can be read out using the identical command sequences. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 43 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Two-Plane Page Program Two-Plane Page Program is an extension of Page Program, for a single plane with 2,112 byte data registers. Since the device is equipped with two memory planes, activating the two sets of 2112 byte data registers enables a simultaneous programming of two pages. After writing the first set of data up to 2,112 byte into the selected data registers via cache registers, Dummy Page Program command (11h) instead of actual Page Program command (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved, R/B# remains in busy state for a short period of time (tDBSY). Read Status command (70h) may be issued to find out when the device returns to ready state by polling the R/B status bit (I/O 6). Then the next set of data for the other plane is inputted after 81h command and address sequences. After inputting data for the last page, actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Although two planes are programmed simultaneously, pass/fail is not available for each page when the program operation completes. Status bit of I/O 0 is set to “1” when any of the pages fails. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 44 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Two-Plane Copy-Back Program Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 2,112 byte data registers. Since the device is equipped with two memory planes, activating the two sets of 2,112 byte data registers enables a simultaneous programming of two pages. Two-Plane Copy-Back Program This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 45 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Two-Plane Copy-Back Program with Random Data Input This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 46 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Two-Plane Cache Program Two-Plane Cache Program is an extension of Cache Program, for a single plane with 2,112 byte data registers. Since the device is equipped with two memory planes, activating the two sets of 2,112 byte data registers enables a simultaneous programming of two pages. Note: 1. It is noticeable that same row address except for A20 is applied to the two blocks 2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh. 3. Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula. tPROG = Program time for the last page + Program time for the (last – 1)th page – (Program command cycle time + Last page data loading time) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 47 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Two-Plane Block Erase Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command 60h followed by three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane. The Erase Confirm command (D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/Busy status bit (I/O 6). Ready/Busy# The device has an R/B# output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B# pin is normally high but transition to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an opendrain driver thereby allowing two or more R/B# outputs to be Or-tied. Because pull-up resistor value is related to tr (R/B#) and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart (the following figure). Its value can be determined by the following guidance. Read / Busy Pin Electrical Specifications This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 48 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 RP vs tRHOH vs CL RP value guidance where IL is the sum of the input currents of all devices tied to the R/ B# pin. RP (max) is determined by maximum permissible limit of tr Data Protection & Power-up sequence The timing sequence shown in the following figure is necessary for the power-on/off sequence. The device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. During the initialization the device R/B# signal indicates the Busy state as shown in the following figure. In this time period, the acceptable commands are 70h. The WP# signal is useful for protecting against data corruption at power on/off. AC Waveforms for Power Transition This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 49 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Write Protect Operation Enable WP# during erase and program busy is prohibited. The erase and program operations are enabled and disable as follows. Program enable mode: Note: WP# keeps “High” until programming finish Program disable mode: This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 50 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Erase enable mode: Note: WP# keeps “High” until erasing finish Erase disable mode: This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 51 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 PACKAGE DIMENSION 48L TSOP 12mm x 20mm package outline This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 52 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23 EN27LN4G08 Revisions List Revision No Description Date A Initial Release 2013/01/23 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 53 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. A, Issue Date: 2013/01/23