DLP-FPGA

DLP-FPGA
LEAD-FREE
USB - FPGA MODULE
MOSFET
Power
Switch
5V
3.3V
PWREN
USB Type 'B'
Connector to
Host Windows/
Linux/Mac PC
5V
VREGs
VCCIO
Dual Channel USB IC
VCC
USBDP
USBDM
XILINX
FPGA
CH B
50-pin,
0.9-inch
Wide
Interface
Headers
XC3S250E
-4TQ144
FTDI FT2232D
6MHz
Clock
CH A
SPI Flash
128K x 8
SRAM
APPLICATIONS:
FEATURES:
- Rapid Prototyping
- Educational Tool
- Industrial/Process
Control
- Training Manual/Tutorial Available
- Built-In Configuration Loader—Writes Bit File Directly
to SPI Flash via Full-Speed USB Interface
- 40 I/O Channels: 27 Input/Output; 13 Input Only
- Xilinx XC3S250E-4TQ144 FPGA
- On-Board 128K x 8, 70nS SRAM
- USB Port Powered
- USB 1.1 and 2.0 Compatible Interface
- Small Footprint: 2.8 x 1.-Inch PCB
- Standard 50-Pin, 0.9-Inch DIP Interface
Rev. 1.3 (June 2008)
1
© DLP Design, Inc.
1.0 INTRODUCTION
The DLP-FPGA Module is a low-cost, compact prototyping module that can be used for rapid proof of
concept or for educational environments. The module is based on the Xilinx Spartan 3E and Future
Technology Devices International’s FT2232D Dual-Channel USB IC. Used by itself or with the
optional 200-page training manual, the DLP-FPGA provides both the beginner as well as the
experienced engineer with a rapid path to developing FPGA-based designs. When combined with the
free WebPACK™ Tools from Xilinx, this module is more than sufficient for creating anything from
basic logical functions to a highly complex system controller.
As a bonus feature, one channel of the dual-channel USB interface is used to load user bit files
directly to the SPI Flash—no external programmer is required. This represents a savings of as much
as $200 in that no additional programming cable is required for configuring the FPGA. All that is
needed to load bit files to the DLP-FPGA is a Windows software utility (free with purchase), a
Windows PC and a USB cable. The module can also be programmed from within the Xilinx ISE tool
environment using a Xilinx programming cable (purchased separately).
The DLP-FPGA is fully compatible with the free ISE™ WebPACK™ tools from Xilinx. ISE WebPACK
offers the ideal development environment for FPGA designs with HDL synthesis and simulation,
implementation, device fitting and JTAG programming.
The DLP-FPGA has on-board voltage regulators that generate all required power supply voltages
from a single 5-volt source. Power for the module can be taken from either the host USB port or from
a user-supplied, external 5-volt power supply.
Connection to user electronics is made via a 50-pin, 0.9-inch wide, industry-standard 0.025 square
inch post DIP header. Other on-board features include a 128K x 8 static RAM IC for user projects,
and both JTAG and SPI Flash interface ports for connection to Xilinx programming tools.
2.0 TRAINING MANUAL
A 200+ page training manual for the DLP-FPGA is also available. While this manual is designed to
provide entry-level instruction for those new to designing with FPGAs, it is recommended for
developers who have some experience with FPGA products and associated development tools. An
ISE™ WebPACK™ Software installation DVD is included with the manual.
The manual is comprised of 5 Chapters and 4 Labs as outlined below:
Chapter 1: Installing the Xilinx ISE WebPACK tools and Understanding the Design Flow
Chapter 2: Lab 1: Implementing a Simple AND Gate: Create a New Project, Implement the Design,
View the Synthesized Design, View the Placed and Routed Design
Chapter 3: Lab 2: Heartbeat: Understanding the Digital Clock Manager (DCM), Methods of Starting
ISE Project Navigator, VHDL Module Structure, Utilizing Hierarchy, Adding the DCM Component,
Adding the Heartbeat Component, Connecting the Components, Synthesizing the Design Using XST,
Simulating the Design Using the ISE Simulator, Adding the User Constraint File, Implementing the
Design, Download the Design to the FPGA
Rev. 1.3 (June 2008)
2
© DLP Design, Inc.
Chapter 4: Lab 3: Memory Test: Block Diagram, DCM Design, SRAM State Machine, Bi-Directional
Buffers, Test Failed Indicator, User Constraint File, Synthesize the Memory Test Design, Simulate the
Memory Test Design, Implementing the Design, Download the Design to the FPGA
Chapter 5: Lab 4: USB Loopback: Initial Design, USB State Machine Module, Language Template,
Bi-Directional Buffers, Synthesize, Simulate, Pin Constraints, Implement, Download the Design to the
FPGA
(The completed design files for each lab are available for download from the DLP Design website
upon purchase of the DLP-FPGA and Lab Manual.)
3.0 FPGA SPECIFICATIONS
The FPGA device used on the DLP-FPGA is the Xilinx Spartan 3E: XC3S250E-4VQ100.
•
•
•
Part Number: XC3S250E
System Gates: 250K
Equivalent Logic Cells: 5,508
•
CLB Array
o
o
o
o
•
•
•
•
Rows: 34
Columns: 26
Total CLB’s: 612
Total Slices: 2,448
Distributed RAM Bits: 38K
Block RAM Bits: 216K
Dedicated Multipliers: 12
DCM’s: 4
4.0 BITLOADAPP SOFTWARE
Windows software is provided for use with the DLP-FPGA that will load an FPGA configuration (.bit)
file directly to the SPI Flash device via the USB interface. This app (shown below) will allow the user
to erase the flash, verify the erasure and then program and verify the flash:
Rev. 1.3 (June 2008)
3
© DLP Design, Inc.
5.0 JTAG INTERFACE
The easiest way to load an FPGA configuration (bit file) to the FPGA is to run the BitLoadApp
software, then select and program a file from the local hard drive directly to the SPI flash. Once
written to the SPI flash, the configuration will load to the FPGA and execute. Alternatively, a
traditional JTAG header location is provided on the DLP-FPGA giving the user access to the pins on
the FPGA required by the development tools. (Refer to the schematic at the end of this datasheet for
details.)
6.0 EEPROM SETUP / MPROG
The DLP-FPGA has a dual-channel USB interface to the host PC. Channel A is used exclusively to
load an FPGA configuration (bit file) to the SPI flash. This configuration data is automatically
transferred to the FPGA when power is applied to the module. Channel B is used for communication
between the FPGA and host PC at run time. A 93C56B EEPROM connected to the USB interface IC
is used to store the setup for the two channels. The parameters stored in the EEPROM include the
Vendor ID (VID), Product ID (PID), Serial Number, Description String, driver selection (VCP or D2XX)
and port type (UART serial or FIFO parallel).
As mentioned above, Channel A is used exclusively for loading the FPGA’s configuration to the SPI
flash, and Channel B is used for communication between the host PC and the DLP-FPGA. As such,
the D2XX drivers and FIFO mode must be selected in the EEPROM for Channel A. Channel B must
use the FIFO mode, but can use either the VCP or D2XX drivers. The VCP drivers make the DLPFPGA appear as an RS232 port to the host app. The D2XX drivers provide faster throughput, but
require working with a .lib or .dll library in the host app.
The operational modes and other EEPROM selections are written to the EEPROM using the MPROG
utility. This utility and its manual are available for download from the bottom of the page at
www.dlpdesign.com.
7.0 TEST BIT FILE
A test file is provided as a download from the DLP Design website that provides rudimentary access
to the I/O features of the DLP-FPGA.
The following features are provided:
•
Ping
•
Read the High/Low State of the Input-Only Pins
•
Drive I/O Pins High/Low or Read their High/Low State
•
Simple Loopback on Channel B
•
Simple Read/Write of Each Address in the SRAM
This bit file is available from the DLP-FPGA’s download page.
Rev. 1.3 (June 2008)
4
© DLP Design, Inc.
8.0 USB DRIVERS
USB drivers for the following operating systems are available for download from the DLP Design
website at http://www.dlpdesign.com:
Mac OSX
Mac OS9
Mac OS8
L in u x
Windows XP x64
Windows Server 2003
Windows 2000
Windows 98, ME
Notes:
1. The bit file load utility only runs on the Windows platforms.
2. The bit file load utility requires the use of USB channel A, and channel A is dedicated to this
function.
3. If you are using the dual-mode drivers from FTDI (CDM2.02.04) and wish to use the Virtual
COM Port (VCP) drivers for Channel B communications, then it may be necessary to disable
the D2XX drivers first via Device Manager. To do so, right click on the Channel B entry under
USB Controllers that appears when the DLP-FPGA is connected, select Properties, select the
Advanced tab, check the option for “Load VCP” and click OK. Once you unplug and then
replug the DLP-FPGA, a COM port should appear in Device Manager under Ports (COM &
LPT).
9.0 USING THE DLP-FPGA
Select a power source via Header Pins 23 and 24, and connect the DLP-FPGA to the PC to initiate
the loading of USB drivers. The easiest way to do this is to connect Pins 23 and 24 to each other.
This will result in operational power being taken from the host PC. Once the drivers are loaded, the
DLP-FPGA is ready for use.
Pin 50
Pin 1
SRAM
FPGA
U
SB
Pin 26
Pin 25
Top View (Interface Headers on bottom of PCB)
Rev. 1.3 (June 2008)
5
© DLP Design, Inc.
TABLE 1
NN (dec)*
NN (hex)*
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
30
31
32
33
34
35
36
37
38
39
40
Read: 29,
>40
Write: 14,
15, >30
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1E
1F
20
21
22
23
24
25
26
27
28
Read:1D,
>29
Write: E, F,
>1E
Name
FPGA Pin
JP2 Pin
user_io(0)
user_io(1)
user_io(2)
user_io(3)
user_io(4)
user_io(5)
user_io(6)
user_io(7)
user_io(8)
user_io(9)
user_io(10)
user_io(11)
user_io(12)
user_io(13)
user_in(14) [INPUT ONLY!]
user_in(15) [INPUT ONLY!]
user_io(16)
user_io(17)
user_io(18)
user_io(19)
user_io(20)
user_io(21)
user_io(22)
user_io(23)
user_io(24)
user_io(25)
user_io(26)
user_io(27)
user_io(28)
user_in(0)
user_in(1)
user_in(2)
user_in(3)
user_in(4)
user_in(5)
user_in(6)
user_in(7)
user_in(8)
user_in(9)
user_in(10)
Returns Read Pin Error E4
U5 Pin 58
U5 Pin 59
U5 Pin 93
U5 Pin 94
U5 Pin 96
U5 Pin 97
U5 Pin 103
U5 Pin 104
U5 Pin 105
U5 Pin 106
U5 Pin 112
U5 Pin 113
U5 Pin 116
U5 Pin 117
U5 Pin 119
U5 Pin 120
U5 Pin 122
U5 Pin 123
U5 Pin 124
U5 Pin 125
U5 Pin 126
U5 Pin 130
U5 Pin 131
U5 Pin 132
U5 Pin 134
U5 Pin 135
U5 Pin 139
U5 Pin 140
U5 Pin 142
U5 Pin 10
U5 Pin 12
U5 Pin 29
U5 Pin 31
U5 Pin 36
U5 Pin 38
U5 Pin 41
U5 Pin 47
U5 Pin 48
U5 Pin 66
U5 Pin 69
n/a
JP2 Pin 2
JP2 Pin 4
JP2 Pin 5
JP2 Pin 6
JP2 Pin 7
JP2 Pin 8
JP2 Pin 9
JP2 Pin 10
JP2 Pin 12
JP2 Pin 13
JP2 Pin 14
JP2 Pin 15
JP2 Pin 16
JP2 Pin 17
JP2 Pin 18
JP2 Pin 19
JP2 Pin 20
JP2 Pin 21
JP2 Pin 22
JP2 Pin 27
JP2 Pin 29
JP2 Pin 30
JP2 Pin 31
JP2 Pin 32
JP2 Pin 33
JP2 Pin 34
JP2 Pin 35
JP2 Pin 36
JP2 Pin 37
JP2 Pin 49
JP2 Pin 48
JP2 Pin 47
JP2 Pin 46
JP2 Pin 45
JP2 Pin 44
JP2 Pin 43
JP2 Pin 42
JP2 Pin 41
JP2 Pin 39
JP2 Pin 38
n/a
Returns Write Pin Error E2 for Pin
Clear (low), or E3 for Pin Set
(high)
Ground
FPGA_RESET
5VIN – Module power source
PORTVCC – Power from Host PC
VCCSW – 5V power after host
enumerates the USB port
n/a
n/a
128
1,11,25,26,40,50
3
23
24
28
*Note: This is the I/O number for use with the Test Bit File described in Section 7.
Rev. 1.3 (June 2008)
6
© DLP Design, Inc.
10.0 MECHANICAL DIMENSIONS IN INCHES (MM) (PRELIMINARY)
0.65 typ
(16.5 typ)
0.21 typ
(5.3 typ)
0.44 typ
(11.2 typ)
0.23 typ
(5.8 typ)
0.1 typ
(2.5 typ)
0.1 typ
(2.5 typ)
0.29 typ
(7.3 typ)
1.2 typ
(30.5 typ)
2.8 typ
(71.1 typ)
.9 typ
(22.9 typ)
1.2 typ
(30.5 typ)
Rev. 1.3 (June 2008)
7
© DLP Design, Inc.
11.0 DISCLAIMER
© DLP Design, Inc., 2007
Neither the whole nor any part of the information contained herein nor the product described in this
manual may be adapted or reproduced in any material or electronic form without the prior written
consent of the copyright holder.
This product and its documentation are supplied on an as-is basis, and no warranty as to their
suitability for any particular purpose is either made or implied. DLP Design, Inc. will not accept any
claim for damages whatsoever arising as a result of the use or failure of this product. Your statutory
rights are not affected. This product or any variant of it is not intended for use in any medical
appliance, device, or system in which the failure of the product might reasonably be expected to result
in personal injury.
This document provides preliminary information that may be subject to change without notice.
12.0 CONTACT INFORMATION
DLP Design, Inc.
1605 Roma Lane
Allen, TX 75013
Phone: 469-964-8027
Fax:
415-901-4859
Email Sales:
[email protected]
Email Support: [email protected]
Website URL: http://www.dlpdesign.com
Rev. 1.3 (June 2008)
8
© DLP Design, Inc.
D
C
B
A
1
2
3
4
C12
0.47uF
R3
27
CR1
6.00MHz
4
FB1
Ferrite Bead
2
R2
27
C3
0.1uF
C11
47pF
C34
10uF
5VCC
C4
0.033uF
1.5K
2
47
2
1
48
4
44
43
5
7
8
6
1
500mA 240-2390-2
MI0805K601R-10
1
C1
0.01uF
R6
2.2K
FB2
Ferrite Bead
R1
470
C2
0.1uF
3V3OUT
USBDM
USBDP
RSTOUT#
XTIN
XTOUT
RESET#
EECS
EESK
EEDATA
TEST
C6
C7
C8
3
0.1uF
0.033uF
3
R5
2.2K
Q2
IRLML6402
C5
0.1uF
27
27
R28
10K 5%
FTDI_SI
FTDI_RXF
FTDI_TXE
FTDI_RD
FTDI_WR
FTDI_D0
FTDI_D1
FTDI_D2
FTDI_D3
FTDI_D4
FTDI_D5
FTDI_D6
FTDI_D7
SPI_PROG
C10
0.1uF
3V3X
FPGA_RESET
SPI_INIT
SPI_CSO_B
SPI_CLK
SPI_MOSI
SPI_DIN
I/O Set at
3.3V
R16
R17
NC
U2
FT2232D
3V3X
41
26
30
29
28
27
40
39
38
37
36
35
33
32
10
15
13
12
11
24
23
22
21
20
19
17
16
C39
0.1uF
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AC0
AC1
AC2
AC3
PWREN
SI/WUB
BC0
BC1
BC2
BC3
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
SI/WUA
0.01uF
14
31
5VIN
PORTVCC
6MHz
1
2
3
4
R4
EEPROM, 2 MHz, 128x16
U3
CS
SK
DIN
DOUT
93C56B
VCC
NC
ORG
GND
10K
VCCIOA
VCCIOB
CN1
CN-USB
5VCC
NC
8
7
6
5
R7
4
3
42
5
Universal
Serial Bus
Connector
5
46
GND
GND
GND
GND
VCC
VCC
AGND
9
18
25
34
AVCC
45
5
2
C33
10uF
VCCSW
1
DLP-FPGA
Page 1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
JP2
CONN PCB 25x2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1
GND
USER_IN0
USER_IN1
USER_IN2
USER_IN3
USER_IN4
USER_IN5
USER_IN6
USER_IN7
USER_IN8
GND
USER_IN9
USER_IN10
USER_IO28
USER_IO27
USER_IO26
USER_IO25
USER_IO24
USER_IO23
USER_IO22
USER_IO21
USER_IO20
VCCSW
USER_IO19
GND
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
For FPGA configuration via
SPI only.
R13
Downloading
FPGA Code
UPLOAD
150 5%
GND
USER_IO0
FPGA_RESET
USER_IO1
USER_IO2
USER_IO3
USER_IO4
USER_IO5
USER_IO6
USER_IO7
GND
USER_IO8
USER_IO9
USER_IO10
USER_IO11
USER_IO12
USER_IO13
USER_IN11
USER_IN12
USER_IO16
USER_IO17
USER_IO18
5VIN
PORTVCC
GND
RED
2
D
C
B
A
D
C
B
A
T1
U1
D0
D1
D2
D3
D4
D5
D6
D7
NC
VCC
GND
CE2
CE1
5
OE
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
32
5
20
19
18
17
16
15
14
13
3
2
31
1
12
4
11
7
10
1
2
3
3V3X
C43
0.1uF
C40
0.01uF
SRAM_OE
SRAM_WE
C36
0.1uF
C29
0.01uF
C44
0.1uF
SRAM_A0
SRAM_A1
SRAM_A2
SRAM_A3
SRAM_A4
SRAM_A5
SRAM_A6
SRAM_A7
SRAM_A8
SRAM_A9
SRAM_A10
SRAM_A11
SRAM_A12
SRAM_A13
SRAM_A14
SRAM_A15
SRAM_A16
SRAM, 128K x 8
21
22
23
25
26
27
28
29
9
8
24
6
30
C37
0.01uF
C41
0.01uF
PROM TYPE SEL
C31
0.1uF
C30
0.1uF
C35
0.01uF
C27
0.1uF
CY62128DV30LL-70ZI / TSOP32
SRAM_D0
SRAM_D1
SRAM_D2
SRAM_D3
SRAM_D4
SRAM_D5
SRAM_D6
SRAM_D7
3V3X
C13
0.1uF
3V3X
C21
0.01uF
C28
0.01uF
C24
0.1uF
1V2 (VCCINT)
C32
0.01uF
C45
0.1uF
2V5 (VCCAUX)
C38
0.01uF
5
SRAM_A0
SRAM_A1
SRAM_A2
SRAM_A3
SRAM_D1
USER_IN0
SRAM_D0
USER_IN1
FTDI_RXF
6MHz
SRAM_A7
SRAM_A8
SRAM_A9
FTDI_SI
SRAM_D7
SRAM_A11
LEDR_HEARTB
FTDI_TXE
SRAM_A12
SRAM_A13
USER_IN2
USER_IO4
SRAM_A14
SRAM_A15
SRAM_A16
SRAM_WE
USER_IN4
USER_IO1
USER_IN5
USER_IN6
SRAM_A4
USER_IN7
USER_IN8
SRAM_A6
SRAM_OE
FTDI_D0
FTDI_D5
USER_IO2
SRAM_D2
SRAM_D3
USER_IO0
SPI_CLK
SPI_CSO_B
SPI_MOSI
SPI_DIN
USER_IN9
USER_IN10
2V5
2
3
4
5
52
10
51
12
6
56
15
16
17
18
22
23
21
74
24
25
26
29
96
32
33
34
35
36
59
38
41
7
43
47
48
14
50
81
87
93
53
54
57
58
71
39
44
63
66
67
68
69
70
62
138
121
79
100
42
64
49
13
28
115
45
80
9
65
137
102
30
R31
U5
4
IO_L01P_3
IO_L01N_3
IO_L02P_3
R26
360
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_PROG_B
JTAG_DONE
IO_L01N_2/INIT_B
IO_L08N_0/VREF_0
IP
IO_L08P_0
IO
IO_L07N_0/GCLK11
IO_L07P_0/GCLK10
IP_L06N_0/GCLK9
IP_L06P_0/GCLK8
IO_L05N_0/GCLK7
IO_L05P_0/GCLK6
IO/VREF_0
IO_L04N_0/GCLK5
IO_L04P_0/GCLK4
IP_L03N_0
IP_L03P_0
IO_L02N_0
IO_L02P_0
IP
IO_L01N_0
IO_L01P_0
IP
IO/VREF_3 ****
IO_L06P_3/LHCLK4
IO_L02P_1/A14
IO_L02N_1/A13
IO_L03N_3
IO_L10N_0/HSWAP
IO_L01N_1/A15
IP
IO_L10N_1/LDC2
IO_L10P_1/LDC1
IO_L09N_1/LDC0
IO_L09P_1/HDC
IP
IO_L10P_0
IP
IO_L09N_0
IO_L09P_0
IO_L03N_1/A11
IO_L08N_1/A1
IO/A0
IP/VREF_1
IO_L07N_1/A3/RHCLK7
IO_L06N_1/A5/RHCLK5
IO_L06P_1/A6/RHCLK4
3V3X
IO/M1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IP
IO_L05N_1/A7/RHCLK3
IO_L04N_1/A9/RHCLK1
IO_L04P_1/A10/RHCLK0
IP
IO/VREF_1
IP
HB
RED
D?
GREEN
XC3S250E-4VQ100
IO_L02N_3/VREF_3
IO/D5
IP ****
IO_L04N_2/D6/GCLK13
IP/VREF_3
IP
IP_L06P_2/RDWR_B/GCLK0
IO_L04N_3/LHCLK1
IO_L05P_3/LHCLK2
IO_L05N_3/LHCLK3
IP
IO_L07P_3/LHCLK6
IO_L07N_3/LHCLK7
IO_L06n_3/LHCLK5
IO_L01P_1/A16
IP
IO_L08P_3
IO_L08N_3
IP ****
IO_L08P_1/A2
IO_L09P_3
IO_L09N_3
IO_L10P_3
IO_L10N_3
IP
IO_L07N_2/D1/GCLK3
IP
IP
IO_L03P_3
IO_L02P_2/DOUT/BUSY
IP_L03P_2
IP_L03N_2/VREF_2
IO_L04P_3/LHCLK0
IO_L04P_2/D7/GCLK12
IO_L03P_1/A12
IO_L05P_1/A8/RHCLK2
IO_L07P_1/A4/RHCLK6
IO_L05P_2/D4/GCLK14
IO_L05N_2/D3/GCLK15
IP_L06N_2/M2/GCLK1
IO_L07P_2/D2/GCLK2
IO_L10N_2/CCLK
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L08N_2/DIN/D0
IO/VREF_2 ****
IO_L09P_2/VS2/A19
IO_L09N_2/VS1/A18
IP
IO_L10P_2/VS0/A17
IO_L08P_2/M0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_2
VCC0_2
VCCO_2
VCCO_3
VCCO_3
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
LEDR_HEARTB
330
LEDG_DONE
4
110
108
144
109
1
72
40
135
136
134
132
131
130
129
128
126
125
124
123
122
120
119
117
116
114
113
112
111
31
20
76
77
8
143
75
107
106
105
104
103
101
142
141
140
139
82
97
98
95
94
92
91
89
88
86
85
84
83
78
60
99
90
55
46
27
73
37
11
19
133
61
118
127
3
R21
R29
4.7K
4.7K
2V5
LEDG_DONE
SPI_INIT
USER_IO25
USER_IO24
USER_IO23
USER_IO22
USER_IO21
USER_IO3
USER_IO5
USER_IO27
USER_IO26
USER_IO28
USER_IO9
USER_IO8
USER_IO7
USER_IO6
USER_IN3
USER_IO11
USER_IO10
FPGA_RESET
USER_IO20
USER_IO19
USER_IO18
USER_IO17
USER_IO16
USER_INB
USER_INA
USER_IO13
USER_IO12
SRAM_A10
SRAM_D5
SRAM_D6
SRAM_A5
SRAM_D4
FDTI_D1
FDTI_WR
FTDI_RD
FDTI_D7
FDTI_D6
FTDI_D4
FDTI_D3
FDTI_D2
3
3V3X
J2
2V5
JP1
PROG
JTAG_TCK
JTAG_TMS
JTAG_DIN
JTAG_DOUT
SPI_PROG
1
2
1
2
3
4
5
6
Traditional JTAG
VCCSW
2
JTAG_TCK
JTAG_DOUT
JTAG_DIN
JTAG_TMS
DLP-FPGA
Page 2
J3
Xilinx Parallel Cable Header
1
2
3
4
5
6
R10
4.7K
4
5
6
2
3.3V REGULATOR
U6
EN
GND
IN
BYPASS
OUT
4
5
200mA Maximum
1
2
3
TPS79333DBVRQ1/SOT23-5
2.5V REGULATOR
1
EN
GND
IN
BYPASS
OUT
4
5
200mA Maximum
2
3
U7
TPS79325DBVR / SOT23-5
1
C17
0.01 uF
0603
2V5
C14
0.01 uF
0603
L1
3.3uH
R14
24.9K 1%
Q3
IRLML6401
3V3X
C19
2.2 uF
0805
C15
2.2 uF
0603
C22
22 uF
TANT
1V2
100 5%
R30
2.5 mS ramp up
C20
0.1uF
0603
R12
1
220K 5%
D1
BAT54CT
1.2V REGULATOR
1
3
1.5A Maximum
FB
SW
U8
ST1S03 DFN6
VIN_SW
VIN_A
NC
GND
R15
49.9K 1%
SPI
Flash
SPI_MOSI
SPI_DIN
SPI_CSO_B
SPI_CLK
3V3X
>Din
<Dout
C
S
W
HOLD
C18
0.1uF
0603
C23
4.7uF
0603
5
2
6
1
3
7
M25P20
U4
3V3X
R33
4.7K
TDI
TDO
TMS
TCK
PRELIMINARY
3V3x
R11
4.7K
R9
4.7K
3V3
R8
4.7K
2
8
VCC
VSS
4
C42
0.1uF
0603
D
C
B
A