HD151TS307ARP Spread Spectrum Clock for EMI Solution REJ03D0022-0400Z Rev.4.00 Jul. 08, 2004 Description The HD151TS307ARP is a high-performance Spread Spectrum Clock modulator. It is suitable for low EMI solution. Features • Supports 10 MHz to 60 MHz operation. (Designed for XIN = 24 MHz and 48 MHz) • 1 copy of clock out with spread spectrum modulation @3.3 V • Programmable spread spectrum modulation (±0.25%, ±0.5%, ±1.5% central spread modulation and spread spectrum disable mode.) • SOP–8pin Key Specifications • • • • • Supply voltages : VDD = 3.3 V±0.165 V Ta = 0 to 70°C operating range Clock output duty cycle = 50±5% Cycle to cycle jitter = ±250 ps typ. Ordering Information Part Name HD151TS307ARPEL Package Type SOP-8 pin (JEDEC) Package Code FP-8DC Package Abbreviation RP Taping Abbreviation (Quantity) EL (2,500 pcs / Reel) Note: Please consult the sales office for the above package availability. Block Diagram VDD GND NC XIN OSC 1/m Synthesizer XOUT R=1 MΩ 1/n SSC Modulator SEL0 R=100 kΩ Mode Control SEL1 R=100 kΩ Rev.4.00 Jul. 08, 2004 page 1 of 8 SSCCLKOUT HD151TS307ARP Pin Arrangement XIN 1 8 VDD XOUT 2 7 SEL0 SEL1 3 6 SSCCLKOUT NC 4 5 GND (Top view) SSC Function Table SEL1 :0 Spread Percentage 00 ±0.5% 01 ±1.5% 10 SSC OFF 11 ±0.25% Note: ±1.5% SSC is selected for default by internal pull-up & down resistors. Clock Frequency Table XIN(MHz) SSCCLKOUT(MHz) *1 48 48 24 24*1 Notes: 1. With spread spectrum modulation. Pin Descriptions Pin name No. Type Description GND 5 Ground GND pin VDD 8 Power Power supplies pin. Normally 3.3 V. NC 4 NC Don’t connect any signal or VDD or GND. This pin is used for Renesas Test. SSCCLKOUT 6 Output Spread spectrum modulated clock output. XIN 1 Input Oscillator input. XOUT 2 Output Oscillator output. SEL0 7 Input SSC mode select pin. LVCMOS level input. Pull-up by internal resistor (100 kΩ). SEL1 3 Input SSC mode select pin. LVCMOS level input. Pull–down by internal resistor (100 kΩ). Rev.4.00 Jul. 08, 2004 page 2 of 8 HD151TS307ARP Absolute Maximum Ratings Item Symbol Supply voltage Ratings Unit Conditions VDD –0.5 to 4.6 Input voltage VI –0.5 to 4.6 V Output voltage *1 VO –0.5 to VDD+0.5 V Input clamp current IIK –50 mA Output clamp current IOK –50 mA VO < 0 Continuous output current IO ±50 mA VO = 0 to VDD 0.7 W –65 to +150 °C Maximum power dissipation at Ta = 55°C (in still air) Storage temperature Tstg V VI < 0 Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Symbol Supply voltage Min VDD DC input signal voltage Typ Max Unit 3.135 3.3 3.465 V –0.3 — VDD+0.3 V High level input voltage VIH 2.0 — VDD+0.3 V Low level input voltage VIL –0.3 — 0.8 V Operating temperature Ta 0 — 70 °C 45 50 55 % Input clock duty cycle Conditions DC Electrical Characteristics Ta = 0 to 70°C, VDD = 3.3 V±5% Item Symbol Min Typ Max Unit Test Conditions Input low voltage VIL — — 0.8 V Input high voltage VIH 2.0 — — V Input current II — — ±10 µA — — ±100 1 — 4 V / ns 20% – 80% — — 4 pF SEL0, SEL1 — 7 — mA XIN = 24 MHz, CL = 0 pF, VDD = 3.3 V Input slew rate Input capacitance CI Operating current Rev.4.00 Jul. 08, 2004 page 3 of 8 VI = 0 V or 3.465 V, VDD = 3.465 V, XIN pin VI = 0 V or 3.465 V, VDD = 3.465 V, SEL0, SEL1 pins HD151TS307ARP DC Electrical Characteristics / SSC Clock Output Ta = 0 to 70°C, VDD = 3.3 V±5% Item Symbol Output voltage 1 Output current * Note: Min Typ Max Unit Test Conditions VOH 3.1 — — V IOH = –1 mA, VDD = 3.3 V VOL — — 50 mV IOL = 1 mA, VDD = 3.3 V IOH — –30 — mA VOH = 1.5 V IOL — 30 — VOL = 1.5 V 1. Parameters are target of design. Not 100% tested in production. AC Electrical Characteristics / SSC Clock Output Ta = 25°C, VDD = 3.3 V, CL = 15 pF Item Symbol Cycle to cycle jitter *1, 2 tCCS Output frequency *1, 2 Slew rate*1 Clock duty cycle tSL *1 Min Typ Max Unit Test Conditions | 250 | | 300 | — | 250 | | 300 | SSCCLKOUT, 48 MHz — | 250 | | 300 | SSCCLKOUT, 24 MHz — | 250 | | 300 | SSCCLKOUT, 48 MHz — | 250 | | 300 | SSCCLKOUT, 24 MHz — | 250 | | 300 | SSCCLKOUT, 48 MHz SSC= ±1.5% SEL1:0 = 01 Fig1 23.8 — 24.2 SSCCLKOUT, XIN = 24 MHz SSCOFF SEL1:0 = 10 47.3 — 48.7 SSCCLKOUT, XIN = 48 MHz 23.7 — 24.3 SSCCLKOUT, XIN = 24 MHz 47.2 — 48.8 SSCCLKOUT, XIN = 48 MHz 23.4 — 24.6 SSCCLKOUT, XIN = 24 MHz 46.6 — 49.4 SSCCLKOUT, XIN = 48 MHz 0.8 — — V/ns ps MHz 45 50 55 % Output impedance *1 — 40 — Ω Spread spectrum modulation frequency *1 — 33 — KHz Input clock frequency 10 — 60 MHz Stabilization time *1,3 — — 2 ms SSCCLKOUT, 24 MHz Notes — @48 MHz SSCOFF SEL1:0 = 10 Fig1 SSC=±0.25% SEL1:0 = 11 Fig1 SSC= ±0.25% SEL1:0 = 11 SSC= ±1.5% SEL1:0 = 01 0.4 V to 2.4 V @48 MHz, SSCCLKOUT Notes: 1. Parameters are target of design. Not 100% tested in production. 2. Cycle to cycle jitter and output frequency are included spread spectrum modulation. 3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after power up. Rev.4.00 Jul. 08, 2004 page 4 of 8 HD151TS307ARP SSCCLKOUT tcycle n tcycle n+1 t CCS = (tcycle n) - (tcycle n+1) Figure 1 Cycle to cycle jitter Application Information 1. Recommended Circuit Configuration The power supply circuit of the optimal performance on the application of a system should refer to Fig. 2. VDD decoupling is important to both reduce Jitter and EMI radiation. The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. The C2 decoupling capacitor shown should be a tantalum type. XIN (Crystal or Reference input) 1 8 XOUT (Crystal or Not connection) 2 7 SEL1 3 6 NC 4 5 C1 SEL0 C2 VDD GND GND R1 SSCCLKOUT GND Notes: C1 = High frequency supply decoupling capacitor. (0.1 µF recommended) C2 = Low frequency supply decoupling capacitor. (22 µF tantalum type recommended) R1 = Match value to line impedance. (22 Ω Reference value) Figure 2 Recommended circuit configuration Rev.4.00 Jul. 08, 2004 page 5 of 8 HD151TS307ARP 2. Example Board Layout Configuration VDD (+3.3 V Supply) P 22 µF FB G 0.1 µF Crystal connection or Reference input 1 Crystal connection or Not connection 2 7 3 6 G 22 Ω SSCCLKOUT R1 4 Note: 5 G Via to GND plane R1 = Match value to line impedance. (22 Ω Reference value) FB = Ferrite bead. Figure 3 Example Board Layout Rev.4.00 Jul. 08, 2004 page 6 of 8 G HD151TS307ARP 3. Example of TS300 EMI Solution IC’s Application Spread Spectrum Modulated Clock XTAL XOUT TS30X CPU & ASIC SSC CLKOUT Memory System BUS XIN Graphics System Cont. Ref. Clock 3.3 V CMOS level ref. Clock Fig 4 Ref. Clock Input Example XIN XTAL XOUT TS30X CPU & ASIC SSC CLKOUT System BUS Spread Spectrum Modulated Clock Memory Graphics System Cont. Fig 5 XTAL Ref. Clock Input Example Rev.4.00 Jul. 08, 2004 page 7 of 8 HD151TS307ARP Package Dimensions As of January, 2003 Unit: mm 3.95 4.90 5.3 Max 5 8 *0.22 ± 0.03 0.20 ± 0.03 4 1.75 Max 1 0.75 Max + 0.10 6.10 – 0.30 1.08 *0.42 ± 0.08 0.40 ± 0.06 0.14 – 0.04 1.27 + 0.11 0˚ – 8˚ + 0.67 0.60 – 0.20 0.15 0.25 M *Dimension including the plating thickness Base material dimension Rev.4.00 Jul. 08, 2004 page 8 of 8 Package Code JEDEC JEITA Mass (reference value) FP-8DC Conforms — 0.085 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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