an2149 application note

AN2149
APPLICATION NOTE
INTEGRATED BUSHOLD CIRCUITRY
1. ABSTRACT
Unused CMOS inputs which are left floating will experience a gradual charging of the gate input
capacitance. A floating input may see an increase in static current, as both the NMOS and PMOS outputs
will turn on and conduct current simultaneously. Or, if the gate voltage reaches the threshold level with
voltages between 0.8V and 2.0V applied to the inputs, the outputs will tend to oscillate. Large numbers of
gates left floating, in a 16 bit bus driver for example, will cause large amounts of current to be drawn by
the IC. The floating gate charges up at a rate determined by its leakage current. Intermittent or random
circuit errors may be seen with floating inputs, as outputs switch to a different state for no apparent reason.
A common solution for this is to connect the floating inputs to VCC or to ground through a pull-up or pulldown resistor. The disadvantage of this is an extra component needed as well as extra board space, and
the resistor dissipates extra power. Hence, this pull-up resistor method is recommended for ac-powered
systems and not for battery-operated equipment where power consumption is critical. Instead, a special
feature called Bus hold circuit is used.
Bus hold is an improved version of the internal pull-up resistor. It is a weak latch that recalls the last valid
state of a pin when it is three-stated. Bus hold provides a small positive feedback current on device inputs.
When an input changes logic state, the bus-hold circuit will return a small current back to the device input,
effectively adding to the transition of the input. This positive feedback will then hold the final logic level until
an active driver toggles the input voltage to the opposite logic state, where bus-hold will then again hold
the logic state. A number of logic families use an integrated bus hold circuit which eliminates the need for
external resistors and saves board space. The circuit is shown in figure 1:
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Figure 1. Generic Bus Hold Circuitry
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2. ADVANTAGES OF BUS HOLD
- Reduces part count by eliminating the pull-up resistors
- Saves board space
- Prevents floating busses and thereby avoids device oscillations.
- Reduces bus loading
- Does not toggle the bus when the bus is released
- Reduces power dissipation
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AN2149 - APPLICATION NOTE
Bus hold circuitry holds the input of the devices at the last known state. This feature eliminates the need
for using pull-up resistors to prevent the device inputs from floating and causing potential system errors.
Eliminating pull-up resistors significantly reduces part count and assembly costs. Thus, the bus hold
option is particularly important in applications where space and cost are at a premium and the elimination
of pull-up resistors is a possibility.
In floating inputs, there is a possibility that the external bias appearing on the input buffer makes the buffer
operate around its threshold point. In such cases, the floating inputs might start oscillating.Since a floating
input has very high impedance, noise injected from other components on the board can cause the input
to move around the threshold point of the input buffer. Each time the input voltage crosses the threshold
point, the input buffer changes state, adding noise to the system which can potentially cause the device
to oscillate. These oscillations can also increase the power consumption of the device. The heat
dissipation thereof might also damage the device.
Adding a pull-up resistor adds bus loading every time the bus toggles low. With bus-hold, the devices are
optimally sized to reduce loading on the bus. Once the transition has been made through the toggle point,
the bus-hold input will be assisting the driver rather than fighting it and causing a current drain. This way,
it consumes much less current compared to a circuit with a pull-up resistor when the device switches low.
In other words, it is easier to overdrive a bus-hold input than to drive a pull-up resistor of equivalent value
LOW.
When using pull-up resistors, the bus will be pulled high when released, causing unnecessary transitions
where the logic was initially LOW. Bus-hold components always retain the last known state, thus avoiding
transitions. Thus, there is no toggling when the bus is released.
In all power sensitive applications, the current leakage of the pull-up resistor (when the bus is low) can be
avoided with a bus-hold input. Also, since the input will avoid unnecessary transitions through the input
threshold, the device power dissipation will be reduced (DIcc).
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3. CIRCUIT OPERATION
The Integrated Bus-hold circuits act like dynamic pull-up/pull-down resistors as follows (Refer to figure 2):
- When the input is “low”, the output of the inverter is "high" so that the lower NMOS is ON and acts like a
pull-down resistor.
- When the input is "high", the output of the inverter is "low" so that the upper PMOS is activated and acts
like a pull-up resistor.
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Figure 2. Bus Hold Schematic Representation
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When the input voltage rises, the input current flowing into the circuit slowly increases, since the NMOS
is conducting. Around the threshold of the CMOS, the PMOS starts conducting and NMOS stops
conducting. At that point, the input current reverses direction and starts flowing out of the circuit. As the
input voltage continues to increase, the current slowly decreases till the input voltage reaches VCC.
While the input remains below VCC, the bulk terminal of the PMOS remains connected to VCC. When the
input exceeds VCC by 0.7V, the bulk terminal is switched to the input. This mechanism prevents the input
over-voltage from affecting the VCC.
4. ELECTRICAL SPECIFICATION
Bus-hold specifications identify the current required to sustain the logic at the threshold levels (Vih and Vih)
and the overdrive current required to toggle the logic state of the device when there is a genuine signal
from an external driver. The input current levels of a bus-hold circuit should approach zero when the input
voltage approaches zero or VCC. As shown in Figure 3, current levels are at the highest near the input
toggle point as the bus hold circuit attempts to pull the device away from the threshold region.
The Bus hold current is specified as II(HOLD) for sustaining both LOW and HIGH states. For the VCXH
family, the sustaining current is normally ±75mA minimum.
II(HOLD) = - 75 mA implies the minimum current the bus hold circuit is guaranteed to sink if a logic LOW
input is raised to 0.8V
II(HOLD) = + 75 mA implies the minimum current the bus hold circuit is guaranteed to source if a logic HIGH
input is lowered to 2.0V
II(HOLD) = ± 500 mA implies the maximum current that the external driver has to sink/source to switch a
bus-hold input from logic HIGH to LOW or vice versa.
Figure 3. Bus Hold Characteristics for VCXH Family at VCC = 3.0V
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If "n" bus-hold enabled inputs are tied to a data-bus, the bus driver should be capable of driving (n x 500
mA), as the overdrive currents are additive for every bus-hold circuit on a data-bus.
5. EXTERNAL RESISTOR WITH BUS HOLD CIRUITRY
Pull-up resistors should not be used with an IC that has bus-hold circuitry on its input pins. Adding a pullup resistor to a pin with bus-hold will cause higher than necessary current demand on the bus-hold driver.
If the pull-up resistor is weak, it would not be able to switch the logic state from initial low to high in the
time required.
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If the initial state of the bus-hold circuitry is "High" and the driver is pulling the line LOW, the pull-up
resistors contend with the driver. Then the output driver has to sink enough current to overcome the pullup resistor in addition to the hold current of the bus-hold circuit.
In some applications, the bus should become HIGH when all the outputs driving the bus are in tri-state.
This is normally accomplished using a pull-up resistor. As the pull-up resistor value increases, the over
drive current required to toggle the logic state also increases. The driver has to sink/source more current
to power up the bus-hold device that is held LOW initially.
The bus with pull-up can be modeled as an RC circuit with the bus and interconnect capacitance given by
C. The worst case value of a pull-up resistor is calculated using the maximum over-drive current
guaranteed by the device. R T can be computed as:
Figure 4. RC Circuit at Input of Bus Hold Circuitry
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RT £ (Vcc - Vth) / IIHOLDMAX
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For example, as in the case of 74VCXH1632245, for VCC = 3.6V, threshold voltage Vth = 1.8V and
IIHOLDMAX = 500 mA, the pull-up resistor of the RC circuit should not be more than 3.6 kW .
If the resistor size is increased beyond RT, the bus-hold latch will prevent the capacitor from being charged
to a voltage that is high enough to override the bus-hold.
Therefore, the circuit will never transition out of the initial LOW state into the required HIGH state. Having
a high value pull-up resistor also increases the switching time of the device as the RC time constant
increases and the overdrive current sunk/sourced by the bus hold driver is increased. This calculation
holds true when a resistor is pulling a switch or other device up from ground.
This effect is also demonstrated graphically. Figure 5 shows the typical bus-hold characteristics and the
effect of various pull-up resistors on the circuit. The maximum current here is at the most 250 mA. So, as
for calculations done earlier, the pull-up resistor should not exceed 7 or 8 kW .
For pull-up resistors less than 8 kW, there is no intersection of the load line with the bus-hold
characteristics. So there is no problem in pulling up an initial low state bus-hold to logic high as required.
For larger resistance values, the load line intersects the bus-hold characteristics and the intersection point
becomes the maximum voltage level up to which the bus hold is pulled up from LOW. The input is never
pulled HIGH beyond this point.
There is a consequent increase in the bus-hold sustaining current to hold the device in the last valid logic
state against the influence of the pull-up resistor, thereby increasing the current consumption.
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Figure 5. Typical Bus Hold Characteristics of 74VCXH1632245 and the Effect of Various Pull-up
Resistor Values
0.0012
5K pull-up resistor
8K pull-up resistor
0.001
10K pull-up resistor
Typical Bus hold
3.6K pull-up resistor
0.0008
0.0006
0.0004
0.0002
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6. CONCLUSION
To summarize, an optimum pull-up resistor should be high enough to keep the power dissipation low, but
at the same time low enough to switch logic states within the time required. More importantly, it should
guarantee that the voltage level on the bus is a valid logic state. Due to such complex influencing factors,
it is strongly recommended to avoid using pull-up resistors on bus-hold inputs unless absolutely
necessary.
Components with bus-hold offer several advantages over the use of external pull-up or pull-down
resistors. The bus-hold circuit holds the last known valid state of the input when the bus starts to float. It
acts as a weak clamp at the output and maintains the last known state. Since it is weak, it requires only a
relatively small current to keep the input in the required state. The bus-hold also does not need much
current to overcome the clamp once an active driver toggles the input. In this way, bus hold circuitry
effectively replaces pull-up resistors, reducing power dissipation and increasing the savings on space and
component costs.
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7. REVISION HISTORY
Table 1: Review History
Date
Revision
Description of Change
May 16 2005
1
First Release
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AN2149 - APPLICATION NOTE
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