ST1284-01A8 - STMicroelectronics

ST1284
Parallel port single termination network
with ±15 kV ESD protection
Datasheet - production data
Applications
• Desktops
• Notebooks
• Workstations
• Servers
• PC peripherals
• Set top box
QSOP 28
Description
Features
• One device for parallel port termination
• Compliant with IEEE1284 standard
• EMI / RFI noise filtering
• Highly integrated solution in 28 pins QSOP
package
• One single device provides the proper
termination for 8 data lines, 1 strobe line, 4
control lines and 4 status lines
• In system ESD protection of ±15 kV (air
discharge) as per IEC 61000-4-2 level 4
• ECOPACK®2 compliant component
The ST1284 is a highly integrated termination for
enhanced high speed parallel ports. The
integrated termination complies to the IEEE1284
Standard recommendations and government
EMC compatibility requirements. It is built around
two basic cells. The first one (cell 1) provides line
termination, EMI filtering and ESD protection for
the strobe and data lines while the second one
(cell 2) provides EMI filtering and ESD protection
for the control and status lines.
In addition, ST1284 provides extra protection
against ESD. When tested according to
IEC 61000-4-2, they withstand ±8 kV contact
discharges and ±15 kV air-discharges, thereby
providing to the system the necessary robustness
to meet up to level 4 of IEC 61000-4-2, without
the need for additional ESD protection
components.
Complies with the following standards:
• IEC 61000-4-2 level 4
– ±15 kV (air discharge)
– ±8 kV (contact discharge)
MIL STD 883G - Method 3015-7 Class 3
– ±25 kV (human body model)
TM: IPAD is a trademark of STMicroelectronics.
July 2014
This is information on a product in full production.
DocID6976 Rev 5
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www.st.com
Characteristics
1
ST1284
Characteristics
Figure 1. Component schematic diagram
1
2
3
Vcc
Vcc
R1
R1
R1
Vcc
R2
Vcc
C
C
C
C
27
Vcc
Rs
R1
C
Rs
26
Vcc
R1
4
Rs
5
25
Vcc
R1
C
24
Vcc
C
R1
Rs
6
C
Rs
7
28
Vcc
23
Vcc
R1
Gnd
C
22
R2
8
C
Rs
9
Vcc
21
Vcc
R1
Vcc
C
20
R2
10
C
Rs
11
19
Vcc
R1
18
Vcc
C
R2
12
Rs
13
17
Vcc
C
R1
C
Rs
14
C
16
Vcc
Vcc
R1
R2
15
C
Table 1. Device component values
2/9
R1
R2
Rs
C
Code 01
4.7 kΩ
4.7 kΩ
33 Ω
180 pF
Tolerance
± 10%
± 10%
± 10%
± 20%
DocID6976 Rev 5
ST1284
Characteristics
Table 2. Absolute maximum ratings (Tamb = 25 °C)
Symbol
Parameter
Value
Unit
ESD discharge IEC 61000-4-2, air discharge
±16
ESD discharge IEC 61000-4-2, contact discharge
±9
IESD discharge - MIL STD 883E - Method 3015-7
± 25
Supply voltage
5.5
V
Pr
Power rating per resistor
100
mW
PP
Package power rating
1
W
Top
Operating temperature range
0 to + 70
°C
Tstg
Storage temperature range
- 55 to + 150
°C
125
°C
VPP
VCC
Tj
Maximum operating junction temperature
kV
Table 3. Electrical characteristics (Tamb = 25 °C)
Symbol
IR
VBR
VF
1.1
Parameter
Test condition
Leakage current
VCC = 5.0 V
Breakdown voltage
IR = 1 mA
Forward voltage drop
IF = 50 mA
Min.
Typ.
Max.
Unit
10
µA
6
V
0.9
V
Basic cell configurations
The ST1284 is built around the two basic cells described Figure 2 and Figure 3 which
integrate the recommended IEEE1284 network and the ESD protection compatible with
IEC 61000-4-2 level 4.
Figure 2. Cell 1 for line termination, EMI
filtering and ESD protection for the data
lines and strobe signals
Figure 3. Cell 2 for EMI filtering and ESD
protection of the control and status
signals
Vcc
Vcc
IEEE1284
Recommendation
Rp
IEEE1284
Recommendation
Rp
Rs
C
C
Gnd
Gnd
There are 9 of these cells in the ST1284
DocID6976 Rev 5
There are 8 of these cells in the ST1284
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Application information
ST1284
Figure 4. Functional diagram
ST1284-xxA8
Vcc
17 Select in
16 Reset
1
15 Error
14 Autofeed
2
Vcc
28
27
20
1
1 Strobe
2 Bit 1
3 Bit 2
4 Bit 3
5 Bit 4
6 Bit 5
7 Bit 6
8 Bit 7
9 Bit 8
10
11
12
13
2
Acknowledge
Busy
Paper Out
Select paper
3
4
5
6
7
9
11
13
14
Vcc
8
14
26
25
24
23
21
19
18
17
16
12
10
15
22
25
Gnd
13
Application information
The functional diagram here above presents a IEEE1284-A connector pinout and show how
to connect the ST1284 in order to correctly terminate and filter the 17 signal lines. The
IEEE1284-A connector is the PC standard for the host connection.
Control and status lines (from 10 to 17) only require a pull-up resistor (Rp) and a filter
capacitor (C).
The data lines (from 2 to 9) and the strobe (pin 1) also require a termination series resistor
(Rs) in addition to the pull-up resistor and a filter capacitor. The VCC is connected to pin 20
and the ground to pin 22.
The ST1284 can be used with all 3 types of connectors defined in the IEEE1284 standard:
4/9
•
IEEE1284-A is a DB 25 connector which is the PC standard for the host connection.
•
IEEE1284-B is a 36 pin, 0.085 inch center line connector used on the peripheral
device.
•
IEEE1284-C is a new 36 pin, 0.050 inch center line connector which can be used for
both host and peripherals.
DocID6976 Rev 5
ST1284
Technical information
3
Technical information
3.1
Frequency behavior of data and strobe signals
Figure 5. Measurement conditions
Figure 6. S21 typical frequency response
curve for data and strobe signals
dB
0.00
-5.00
+5V
TRACKING
GENERATOR
SPECTRUM
ANALYSER
-10.00
50Ω
-15.00
ST1284
50Ω
Vg
Vin
-20.00
Vout
-25.00
F (MHz)
-30.00
1
3.2
3
10
30
100
300
1,000
ESD protection
In addition to the requirements of termination and EMC compatibility, computing devices are
required to be tested for ESD susceptibility. This test is described in the IEC 61000-4-2. This
test requires that a device tolerates ESD events and remain operational without user
intervention.
The ST1284 is particularly optimized to perform ESD protection. ESD protection is based on
the use of device which clamps at:
Vouput = VBR + Rd · IPP
This protection function is split in 2 stages. As shown in Figure 7, the ESD strikes are
clamped by the first stage S1 and then its remaining overvoltage is applied to the second
stage through the resistor R. Such a configuration makes the voltage very low at the output.
Figure 7. ST1284 ESD clamping behavior
Rg
S1
Rd
VBR
ESD Surge
R
S2
Rd
Vinput
Rload
Voutput
ST1284-xxA8
DocID6976 Rev 5
VBR
Device
to be
protected
5/9
9
Technical information
ST1284
To have a good approximation of the remaining voltages at both Vin and Vout stages, we give
the typical dynamic resistance value Rd.
Taking into account these hypothesis Rt>Rd, Rg>Rd and Rload>Rd, gives these formulas:
Vinput =
Rg · VBR + Rd · VPP
Rg
Voutput =
Rt · VBR + Rd · Vinput
Rt
The results of the calculation done for VPP = 8 kV, Rg = 330 Ω (IEC 61000-4-2 standard),
VBR = 7 V (typ.) and Rd = 1 Ω (typ.) give:
Vinput = 31.2 V
Voutput = 7.95 V
This confirms the very low remaining voltage across the device to be protected. It is also
important to note that in this approximation the parasitic inductance effect was not taken into
account. This could be few tenths of volts during few ns at the input side. This parasitic
effect is not present at the output side due to the low current involved after the resistance R.
The measurements in Figure 9 clearly show the high efficiency of the ESD protection:
•
No influence of the parasitic inductances on Vout stage
•
Voutput clamping voltage very close to VBR (positive strike) and -VF (negative strike)
Figure 8. Measurement conditions
ESD
SURGE
ST1284
Vinput
Voutput
Figure 9. Remaining voltage at the input and output of the device during a ±16 kV ESD
surge (IEC 61000-4-2)
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DocID6976 Rev 5
ST1284
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 10. QSOP 28 dimension definitions
L
A
b
S
a1
e
b1
E
D
28
15
1
14
F
Table 4. QSOP 28 dimension values
Dimensions
Ref.
Millimeters
Inches
Min.
Max.
Min.
Max.
A
1.55
1.75
0.061
0.069
a1
0.10
0.25
0.004
0.010
b
0.20
0.30
0.008
0.012
b1
0.18
0.25
0.007
0.010
D
9.80
9.98
0.386
0.393
E
3.80
3.98
0.15
0.157
e
0.64 typ.
0.025 typ.
F
5.79
6.20
0.228
0.244
L
0.40
0.90
0.016
0.035
S
8° max
8° max
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Ordering information
ST1284
Figure 11. Footprint (dimensions in mm)
0.64
0.40
1.50
3.70 6.70
Table 5. Package mechanical specifications
5
Lead plating
Tin-lead
Lead plating thickness
7 µm min. 25 µm max.
Lead material
Copper Alloy
Lead coplanarity
0.102 mm (0.004”)
Body material
Molded epoxy
Resin
Meets UL94V-0 standard
Ordering information
Table 6. Ordering information
Order code
Marking
ST1284-01A8
ST1284-01
ST1284-01A8RL
6
Package
Weight
QSOP 28
0.147 g
Base qty
Delivery mode
48
Tube
2500
Tape and Reel
ST1284-01
Revision history
Table 7. Document revision history
8/9
Date
Revision
Changes
Oct-2003
2B
12-Mar-2010
3
Updated table in Figure 1 and Figure 11.
11-May-2012
4
Updated Table 4.
09-Jul-2014
5
Corrected typographical error in Table 2.
Last release.
DocID6976 Rev 5
ST1284
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