STMICROELECTRONICS ESDAXXSCX

ESDAxxSCx
®
QUAD TRANSIL™ ARRAY
FOR ESD PROTECTION
ASD™
MAIN APPLICATIONS
Where transient overvoltage protection in ESD
sensitive equipment is required, such as:
■
■
■
■
■
■
Computers
Printers
Communication systems
Cellular phone handsets and accessories
Other telephone set
Set top boxes
FEATURES
■ 4 Unidirectional Transil™ Functions
■ Low leakage current: IR max. < 20 mA at VBR
■
400 W Peak pulse power (8/20 µs)
DESCRIPTION
The ESDAxxSC5 and ESDAxxSC6 are monolithic
voltage suppressors designed to protect components which are connected to data and transmission lines against ESD.
They clamp the voltage just above the logic level
supply for positive transients, and to a diode drop
below ground for negative transient.
SOT23-5L (SC-59)
ESDAxxSC5
Table 1: Order Code
Part Number
ESDAxxSCx
■
■
Marking
See page 9
Figure 1: ESDAxxSC5 Functional Diagram
1
5
2
3
BENEFITS
■ High ESD protection level: up to 25 kV
■ High integration
■ Suitable for high density boards
COMPLIES WITH THE FOLLOWING STANDARDS:
SOT23-6L (SC-59)
ESDAxxSC6
4
Figure 2: ESDAxxSC6 Functional Diagram
IEC61000-4-2 level 4:
15kV (air discharge)
8kV (contact discharge)
1
6
MIL STD 883E-Method 3015-7: class3B
(Human Body Model)
2
5
3
4
TM: ASD is a trademark of STMicroelectronics.
November 2004
REV. 8
1/10
ESDAxxSCx
Table 2: Absolute Ratings (Tamb = 25°C)
Symbol
VPP
PPP
Tj
Parameter
ESD discharge
Peak pulse power (8/20µs)
Value
Unit
MIL STD 883E - Method 3015-7
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
25
kV
ESDA5V3SCx
ESDA6V1SCx
500
400
W
ESDA14V2SCx
ESDA17SC6
ESDA19SC6
ESDA25SC6
300
W
150
°C
-55 to +150
°C
260
°C
-40 to +125
°C
Junction temperature
Tstg
Storage temperature range
TL
Maximum lead temperature for soldering during 10 s at 5mm for
case
Top
Operating temperature range
Table 3: Electrical Characteristics (Tamb = 25°C)
Symbol
Parameter
I
IF
VRM
Stand-off voltage
VBR
Breakdown voltage
VCL
Clamping voltage
IRM
Leakage current
IPP
Peak pulse current
αT
Voltage temperature coefficient
VF
Forward voltage drop
C
Capacitance
Rd
Dynamic resistance
VBR
min.
V
I RM
Rd
VBR @
Types
VF
V RM
VCL
IR
max.
I PP
IRM @ VRM
Rd
αT
C
max.
typ.
max.
typ.
note 1
VF @ IF
max.
note 2 0V bias
V
V
mA
mA
V
mΩ
10-4/°C
pF
V
mA
ESDA5V3SC5
ESDA5V3SC6
5.3
5.9
1
2
3
230
5
280
1.25
200
ESDA6V1SC5
ESDA6V1SC6
6.1
7.2
1
20
5.25
350
6
190
1.25
200
ESDA14V2SC5
ESDA14V2SC6
14.2
15.8
1
5
12
650
10
100
1.25
200
ESDA17SC6
ESDA19SC6
17
19
19
21
1
1
0.075
0.1
14
15
700
800
10
8.5
85
80
1.2
1.2
10
10
ESDA25SC6
25
30
1
1
24
1000
10
60
1.2
10
Note 1: Square pulse, IPP = 15A, tp=2.5µs.
Note 2: ∆ VBR = αT* (Tamb -25°C) * VBR (25°C).
2/10
ESDAxxSCx
1. CALCULATION OF THE CLAMPING VOLTAGE USE OF THE DYNAMIC RESISTANCE
The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB designers need to
calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the
classical parameters. The voltage across the protection cell can be calculated with the following formula:
VCL = VBR + Rd IPP
Where IPP is the peak current through the ESDA cell.
As the value of the dynamic resistance remains stable for a surge duration lower than 20ms, the 2.5ms
rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic
phenomenon during the measurement of Rd.
2. DYNAMIC RESISTANCE MEASUREMENT
The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the
classical 8/20µs and 10/1000µs surges.
Figure 3: 2.5µs duration measurement wave
I
Ipp
t
2µs
tp = 2.5µs
Figure 4: Peak power dissipation versus initial
junction temperature
Figure 5: Peak pulse power versus exponential
pulse duration (Tj initial = 25 °C)
PPP[Tj initial] / PPP[Tj initial=25°C]
PPP(W)
1.1
5000
1.0
0.9
ESDA5V3SC5/SC6
&
ESDA6V1SC5/SC6
0.8
0.7
1000
0.6
0.5
ESDA14V2SC5/SC6
ESDA17SC6
ESDA19SC6
ESDA25SC6
0.4
0.3
0.2
0.1
tp(µs)
Tj initial (°C)
100
0.0
0
®
25
50
75
100
125
150
1
10
100
3/10
ESDAxxSCx
Figure 6: Clamping voltage versus peak pulse
current (Tj initial = 25 °C).
Rectangular waveform (tp = 2.5 ms)
Figure 7: Capacitance versus reverse applied
voltage (typical values)
C(pF)
IPP(A)
500
50.0
F=1MHz
VOSC=30mVRMS
ESDA25SC6
ESDA19SC6
10.0
ESDA5V3SC5/SC6
ESDA17SC6
100
ESDA14V2SC5/SC6
ESDA6V1SC5/SC6
ESDA6V1SC5/SC6
1.0
ESDA5V3SC5/SC6
ESDA14V2SC5/SC6
ESDA17SC6
ESDA19SC6
tp=2.5µs
VCL(V)
0.1
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
Figure 8: Relative variation of leakage current
versus junction temperature (typical values)
IR[Tj] / IR[Tj=25°C]
1
5
10
20
50
IFM(A)
ESDA5V3SC5/SC6
ESDA17SC6
&
ESDA19SC6
ESDA14V2SC5/SC6
&
ESDA6V1SC5/SC6
ESDA14V2SC5/SC6
&
ESDA6V1SC5/SC6
100
2
Figure 9: Peak forward voltage drop versus
peak forward current (typical values)
5.00
500
ESDA25SC6
VR(V)
10
ESDA19SC6
ESDA17SC6
1.00
ESDA25SC6
ESDA25SC6
0.10
10
Tj(°C)
Tj = 25°C
ESDA5V3SC5/SC6
VFM(V)
0.01
1
25
50
75
100
125
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
3. ESD PROTECTION BY ESDAxxSCx
Electrostatic discharge (ESD) is a major cause of failure in electronic systems.
Transient Voltage Suppressors (TVS) are an ideal choice for ESD protection. They are capable of
clamping the incoming transient overvoltage to a low enough level such that damage to the protected
semiconductor is prevented.
Surface mount TVS arrays offer the best choice for minimal lead inductance.
They serve as parallel protection elements, connected between the signal line and ground. As the
transient rises above the operating voltage of the device, the TVS array becomes a low impedance path
diverting the transient current to ground.
4/10
ESDAxxSCx
Figure 10: ESDAxxSCx array protection against ESD
I/ O LINES
ESD
sensitive
device
GND
ESDAxxxSC6 (1connection to GND for ESDAxxSC5)
The ESDAxxSCx array is the ideal board level protection of ESD sensitive semiconductor components.
The tiny SOT23-5L and SOT23-6L packages allow design flexibility in the high density boards where the
space saving is at a premium. This enables to shorten the routing and contributes to hardening against
ESD.
4. ADVICE FOR OPTIMIZING CIRCUIT BOARD LAYOUT
Circuit board layout is a critical design step in the suppression of ESD induced transients. The following
guidelines are recommended:
■
■
■
■
■
The ESDAxxSC5/6 should be placed as close as possible to the input terminals or connectors.
The path length between the ESD suppressor and the protected line should be minimized
All conductive loops, including power and ground loops should be minimized
The ESD transient return path to ground should be kept as short as possible
Ground planes should be used whenever possible
5. TECHNICAL INFORMATION
ESD protection
The ESDA19SC6 is particularly optimized to perform ESD protection. ESD protection is achieved by
clamping the unwanted overvoltage. The clamping voltage is given by the following formula :
VCL = VBR + Rd . IPP
As shown in figure 11, the ESD strikes are clamped by the transient voltage suppressor.
Figure 11: ESD clamping behavior (example)
Rg
Rd
Voutput
Vg
Rload
VBR
ESD Surge
®
ESDA19SC6
Device
to be
protected
5/10
ESDAxxSCx
To have a good approximation of the remaining voltages at both VI/O side, we provide the typical dynamical resistance value Rd. By taking into account the following hypothesis :
Rg > Rd and Rload > Rd
we have:
we have:
Vg
V output = V BR + R d × ------Rg
The results of the calculation done for Vg = 8 kV, Rg = 330 Ω (IEC61000-4-2 standard), VBR = 19 V (typ.)
and Rd = 0.80 Ω (typ.) give:
Vouput = 38.4 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be a few
tenths of volts during a few nanoseconds at the output side.
Figure 12: Ordering information scheme
ESDA
ESD Array
Breakdown Voltage (min)
6V1 = 6.1 Volt
Package
SC5 = SOT23-5L
SC6 = SOT23-6L
6/10
6V1
SC6
ESDAxxSCx
Figure 13: SOT23-5L Package Mechanical Data
DIMENSIONS
A
H
REF.
A2
e
D
b
e
A1
L
Millimeters
Min.
A
0.90
A1
0
M
E
Max.
Inches
Min.
Typ.
Max.
1.45 0.035
0.057
0.15
0.006
0
A2
0.90
1.30 0.035
0.051
b
0.35
0.50 0.014
0.020
c
0.09
0.20 0.004
0.008
D
2.80
3.00
0.118
E
1.50
e
c
Typ.
0.11
1.75 0.059
0.95
0.069
0.037
H
2.60
3.00 0.102
0.118
L
0.10
0.60 0.004
0.024
M
10°
10°
Figure 14: Foot Print Dimensions (in millimeters)
®
1
0.040
3.6
0.137
1.3
0.051
0.65
0.025
mm
inch
7/10
ESDAxxSCx
Figure 15: SOT23-6L Package Mechanical Data
DIMENSIONS
REF.
A2
A
D
b
A1
L
H
E
A
0.90
A1
0
c
e
e
0.60
1.20
8/10
2.30
0.95
1.10
Max.
Inches
Min.
Typ.
Max.
1.45 0.035
0.057
0.10
0.004
0
0.90
1.30 0.035
0.051
b
0.35
0.50 0.014
0.02
C
0.09
0.20 0.004
0.008
D
2.80
3.05 0.110
0.120
E
1.50
1.75 0.059
0.95
0.069
0.037
H
2.60
3.00 0.102
0.118
L
0.10
0.60 0.004
0.024
θ
Figure 16: Foot Print Dimensions (in millimeters)
Typ.
A2
e
θ
3.50
Millimeters
Min.
10°
10°
ESDAxxSCx
Table 4: Ordering Information
■
Part Number
Marking
ESDA5V3SC5
EC53
ESDA6V1SC5
EC61
ESDA14V2SC5
EC15
ESDA5V3SC6
ES53
ESDA6V1SC6
ES61
ESDA14V2SC6
ES15
ESDA17SC6
ES17
ESDA19SC6
ES19
ESDA25SC6
ES25
Package
Weight
Base qty
Delivery mode
16.7 mg
3000
Tape & reel
SOT23-5L
SOT23-6L
Epoxy meets UL94-V0 standard
Table 5: Revision History
®
Date
Revision
Nov-2003
7F
4-Nov-2004
8
Description of Changes
Last update.
SOT23-6L package dimensions change for reference “D”
from 3.0 millimeters (0.118 inches) to 3.05 millimeters
(0.120 inches).
9/10
ESDAxxSCx
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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