L4984D
CCM PFC controller
Datasheet - production data
Table 1.
Device summary
Order code
L4984D
L4984DTR
Package
SSOP10
Packaging
Tube
Tape and reel
SSOP10
Features
• Line-modulated fixed-off-time (LM-FOT)
control of CCM-operated PFC pre-regulators
• Proprietary LM-FOT modulator for nearly fixedfrequency operation
• Proprietary multiplier design for minimum THD
of AC input current
• Fast “bi-directional” input voltage feedforward
(1/V2 correction)
• Accurate adjustable output overvoltage
protection
• Protection against feedback loop failure
(latched shutdown)
• Inductor saturation protection
• AC brownout detection
• Digital leading-edge blanking on current sense
• Soft-start
• 1% (at Tj = 25 °C) internal reference voltage
• - 600 / + 800 mA totem pole gate driver with
active pull-down during UVLO and voltage
clamp
• SSOP10 package
Applications
• PFC pre-regulators for:
– IEC61000-3-2 and JEIDA-MITI compliant
SMPS in excess of 1 KW
– Desktop PC, server, web server
April 2013
This is information on a product in full production.
DocID024474 Rev 1
1/35
www.st.com
35
Contents
L4984D
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1
Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
Feedback failure detection (FFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8
Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10
Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11
THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12
Power management and housekeeping functions . . . . . . . . . . . . . . . . 30
13
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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DocID024474 Rev 1
L4984D
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
IC consumption vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IC consumption vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VCC Zener voltage vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Startup & UVLO vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Feedback reference vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
E/A output clamp levels vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
UVLO saturation vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OVP levels vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Inductor saturation threshold vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Vcs clamp vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Timer pin charging current vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Brownout threshold (on VFF) vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RFF discharge vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Line drop detection threshold vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VMULTpk - VVFF dropout vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PFC_OK enable threshold vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
FFD threshold vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Multiplier characteristics at VFF=1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Multiplier characteristics at VFF=3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Multiplier gain vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Gate drive clamp vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Gate drive output saturation vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Delay to output vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Line-modulated fixed-off-time modulator: a) internal block diagram; b) key waveforms. . . 17
Typical frequency change along a line half-cycle in a boost PFC
operated in LM-FOT (left) and TM (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Line-modulated fixed-off-time-controlled boost PFC: current waveforms . . . . . . . . . . . . . . 19
Line-modulated fixed-off-time-controlled boost PFC: input current harmonic contents . . . 20
Output voltage setting, OVP and FFD functions: internal block diagram . . . . . . . . . . . . . . 21
Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic . . . 23
RFF·CFF as a function of 3rd harmonic distortion introduced in the input current . . . . . . . . 25
Startup mechanisms and activations of the soft-start function . . . . . . . . . . . . . . . . . . . . . . 26
Effect of boost inductor saturation on MOSFET current and detection method . . . . . . . . . 27
THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
HD optimization: standard PFC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Interface circuits that let DC-DC converter controller IC disable the L4984D . . . . . . . . . . . 30
SSO10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DocID024474 Rev 1
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Description
1
L4984D
Description
The L4984D is a current-mode PFC controller operating with line-modulated fixed-off-time
(LM-FOT) control. A proprietary LM-FOT modulator allows fixed-frequency operation for
boost PFC converters as long as they are operated in CCM (continuous conduction mode).
The chip comes in a 10-pin SO package and offers a low-cost solution for CCM-operated
boost PFC pre-regulators in EN61000-3-2 and JEIDA-MITI compliant applications, in a
power range that spans from few hundred W to 1 KW and above.
The highly linear multiplier includes a special circuit, able to reduce the crossover distortion
of the AC input current, that allows wide-range-mains operation with a reasonably low THD,
even over a large load range.
The output voltage is controlled by means of a voltage-mode error amplifier and an accurate
(1% at Tj = 25 °C) internal voltage reference. Loop stability is optimized by the voltage
feedforward function (1/V2 correction), which in this IC uses a proprietary technique that
also significantly improves line transient response in the case of mains drops and surges
(“bi-directional”).
The device features low consumption and includes a disable function suitable for IC remote
on/off. These features allow use in applications which also comply with the latest energy
saving requirements (Blue Angel, ENERGY STAR®, Energy 2000, etc.).
In addition to overvoltage protection able to keep the output voltage under control during
transient conditions, the IC is also provided with protection against feedback loop failures or
erroneous settings. Other onboard protection functions allow that brownout conditions and
boost inductor saturation can be safely handled. Soft-start limits peak current and extends
off-time to prevent flux runaway in the initial cycles.
The totem pole output stage, capable of 600 mA source and 800 mA sink current, is suitable
for big MOSFETs or IGBT drive.
4/35
DocID024474 Rev 1
DocID024474 Rev 1
MULT
INV
COMP
3
1
2
6
Brownout
2.5 V
1.66 V
2.5 V
2.4 V
-
+
+
-
-
+
+
-
+
-
L_OVP
+
0.8 V
0.88 V
5
VFF
Ideal rectifier
Error Amplifier
OVP
Disable
1/V2
Stop
MAINS DROP
DETECTOR
MULTIPLIER
Q1
LM-FOT
MODULATOR
-
+
0.88 V
LEB
Internal Supply Bus
Voltage
references
R
S
…
PFC_OK
0.23 V
0.27 V
7
1.7 V
-
+
OVP
Brownout
Disable
Q1
VOLTAGE
REGULATOR
300 us
Q
DRIVER
& CLAMP
Monostable
DISABLE
UVLO
UVLO
Stop
R
S
UVLO
L_OVP
10
Vcc
4
8
9
CS
GND
GD
2
TIMER
L4984D
Block diagram
Block diagram
Figure 1. Electrical diagram
AM13217v1
5/35
Block diagram
L4984D
Table 2. Absolute maximum ratings
Symbol
Pin
Parameter
VCC
10
-
1, 3, 6
-
2, 4, 5, 7
VFF pin
5
Other pins
1 to 4
6 to 10
Value
Unit
IC supply voltage (Icc = 20 mA)
Self-limited
V
Max. pin voltage (Ipin = 1 mA)
Self-limited
V
-0.3 to 8
V
+/- 1500
V
+/- 2000
V
Analog inputs & outputs
Maximum withstanding voltage range
test condition: ANSI/ESDA/JEDEC JS001
Figure 2. Pin connection (top view)
INV
1
10
Vcc
COMP
2
9
GD
MULT
3
8
GND
CS
4
7
TIMER
VFF
5
6
PFC_OK
AM13218v1
Table 3. Thermal data
Symbol
Parameter
Rth j-amb
Ptot
Tj
Tstg
Value
Unit
Max. thermal resistance, junction-to-ambient
120
°C/W
Power dissipation at Tamb = 50 °C
0.75
W
Junction temperature operating range
-40 to 150
°C
Storage temperature
-55 to 150
°C
Table 4. Pin functions
N.
Name
Function
1
INV
Inverting input of the error amplifier. The information on the output voltage of
the PFC pre-regulator is fed into the pin through a resistor divider. The pin
normally features high impedance.
COMP
Output of the error amplifier. A compensation network is placed between this
pin and INV (pin 1) to achieve stability of the voltage control loop and ensure
high power factor and low THD. To avoid uncontrolled rise of the output
voltage at zero load, when the voltage on the pin falls below 2.4 V the gate
driver output is inhibited (burst-mode operation).
2
6/35
DocID024474 Rev 1
L4984D
Block diagram
Table 4. Pin functions (continued)
N.
3
4
5
6
7
8
Name
Function
MULT
Main input to the multiplier. This pin is connected to the rectified mains
voltage via a resistor divider and provides the sinusoidal reference to the
current loop. The voltage on this pin is used also to derive the information on
the RMS mains voltage. At startup this pin is used also to perform soft-start.
This pin can also be used as a remote ON-OFF control input by means of the
internal brownout comparator. In this case the IC performs the soft-start
function when the pin is released.
CS
Input to the PWM comparator. The current flowing in the MOSFET is sensed
through a resistor; the resulting voltage is applied to this pin and compared to
an internal sinusoidal-shaped reference, generated by the multiplier, to
determine the turn-off instant of the external Power MOSFET. The pin is
equipped with about 220 ns digital leading-edge blanking for improved noise
immunity. A second comparison level set at 1.7 V detects abnormal currents
(e.g. due to boost inductor saturation) and, on this occurrence, activates a
safety procedure that temporarily stops the converter and limits the stress of
the power components.
VFF
Second input to the multiplier for 1/V2 function. A capacitor and a parallel
resistor must be connected from the pin to GND. They complete the internal
peak-holding circuit that derives the information on the RMS mains voltage.
The resistor should range from 100 kΩ (minimum) to 2 MΩ (maximum). The
voltage on this pin, a DC level equal to the peak voltage on pin MULT (3),
compensates the control loop gain dependence on the mains voltage. This
pin is also internally connected to a comparator in order to provide brownout
(AC mains undervoltage) protection. A voltage below 0.8 V shuts down (not
latched) the IC and brings its consumption to a considerably lower level. The
IC restarts as the voltage at the pin goes above 0.88 V. Never connect the pin
directly to GND.
PFC_OK
PFC pre-regulator output voltage monitoring/disable function. This pin
senses the output voltage of the PFC pre-regulator through a resistor divider
and is used for protection purposes. If the voltage on the pin exceeds 2.5 V,
the IC stops switching and restarts as the voltage falls below 2.4 V. However,
if at the same time the voltage on the INV pin falls below 1.66 V, a feedback
failure is assumed. In this case the device is latched off. Normal operation
can be resumed only by cycling VCC. If the voltage on this pin is brought
below 0.23 V, the IC is shut down. To restart the IC the voltage on the pin
must go above 0.27 V. This pin can also be used as a burst-mode control
input to synchronize the burst-mode of the IC to the one of a D2D converter
controller. Do not use this pin as remote ON/OFF control input because the
soft-start function is performed only at the startup by PFC_OK but not on the
following releases.
TIMER
LM-FOT modulator setting. A capacitor connected between this pin and
ground is charged by an accurate internal generator during the off-time of the
external Power MOSFET (i.e. while pin GD is low), therefore generating a
voltage ramp. As the voltage ramp equals the voltage on the MULT pin, the
off-time of the Power MOSFET is terminated, the GD pin is driven high and
the ramp is reset at zero.
GND
Ground. Current return for both the signal part of the IC and the gate driver.
Keep the PCB trace that goes from this pin to the “cold” end of the sense
resistor separate from the trace that collects the grounding of the bias
components (output voltage sensing divider, multiplier bias divider and LMFOT modulator setting).
DocID024474 Rev 1
7/35
Block diagram
L4984D
Table 4. Pin functions (continued)
N.
9
10
8/35
Name
Function
GD
Gate driver output. The totem pole output stage is able to drive Power
MOSFETs and IGBTs. It is capable of 600 mA source current and 800 mA
sink current (minimum values). The high-level voltage of this pin is clamped
at about 12 V to avoid excessive gate voltages in case the pin is supplied
with a high VCC.
VCC
Supply voltage of both the signal part of the IC and the gate driver.
Sometimes a small bypass capacitor (0.1 µF typ.) to GND may be useful in
order to get a clean bias voltage for the signal part of the IC. The voltage on
the pin is internally clamped at 22.5 V min. to protect the internal circuits from
excessive supply voltages.
DocID024474 Rev 1
L4984D
3
Electrical characteristics
Electrical characteristics
(Tj = -25 to 125 °C, VCC = 12 V,(a) CTIMER = 470 pF, Co = 1 nF between pin GD and GND,
CFF = 1 µF and RFF = 1 MΩ between pin VFF and GND; unless otherwise specified.)
Table 5. Electrical characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
22.5
V
Supply voltage
VCC
VCCOn
VCCOff
VCCrestart
Operating range
After turn-on
Turn-on threshold
(1)
11
12
13
V
Turn-off threshold
(1)
8.7
9.5
10.3
V
VCC for resuming from latch
OVP latched
5
6
7
V
2.7
V
25
28
V
Hys
Hysteresis
VZ
Zener voltage
10.3
2.3
Icc = 20 mA
22.5
Supply current
Istart-up
Iq
ICC
Iqdis
Iq
Startup current
Before turn-on, VCC = 10 V
65
150
µA
Quiescent current
After turn-on, VMULT = 1 V
4
5
mA
Operating supply current
At 70 kHz
5
6.0
mA
VPFC_OK > VPFC_OK_S
and
VINV < VINVD
200
280
µA
VPFC_OK < VPFC_OK_D
1.5
2.2
mA
VPFC_OK > VPFC_OK_S
or
VCOMP < 2.3 V
2.2
3
mA
VMULT = 0 to 3 V
-0.2
-1
µA
Idle state quiescent current
Quiescent current
Multiplier input
IMULT
Input bias current
VMULT
Linear operation range
0 to 3
VCLAMP
Internal clamp level
IMULT = 1 mA
ΔV CS
--------------------ΔV MULT
Output max. slope
Gain(2)
KM
V
9
9.5
V
VMULT = 0 to 0.4 V
VVFF = 0.915 V
VCOMP = upper clamp
0.935
1.34
V/V
VMULT = VCOMP = 0.915 V VCOMP
=4V
0.248
0.304
0.360
V
Tj = 25 °C
2.475
2.5
2.525
V
10.3 V < VCC < 22.5 V (1)
2.455
Error amplifier
VINV
Voltage feedback input
threshold
2.545
a. Adjust VCC above VCCOn before setting at 12 V.
DocID024474 Rev 1
9/35
Electrical characteristics
L4984D
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
2
5
mV
-0.2
-1
µA
Line regulation
VCC = 10.3 V to 22.5 V
Input bias current
VINV = 0 to 4 V
Internal clamp level
IINV = 1 mA
8
9
V
Gv
Voltage gain
Open loop
60
80
dB
GB
Gain-bandwidth product
1
MHz
IINV
VINVCLAMP
ICOMP
VCOMP
Source current
VCOMP = 4 V, VINV = 2.4 V
2
4
mA
Sink current
VCOMP = 4 V, VINV = 2.6 V
2.5
4.5
mA
Upper clamp voltage
ISOURCE = 0.5 mA
5.7
6.2
6.7
Burst-mode threshold
(1)
2.3
2.4
2.5
2.1
2.25
2.4
Lower clamp voltage
ISINK = 0.5
mA (3)
V
Current sense comparator
ICS
Input bias current
tLEB
Leading edge blanking
145
Delay to output
td(H-L)
VCSclamp
Current sense reference
clamp
Vcsofst
Current sense offset (2)
VCS = 0
1
µA
220
400
ns
100
200
300
ns
0.84
0.88
0.93
V
VMULT = 0, VVFF = 3 V
35
47
mV
VMULT = 3 V, VVFF = 3 V
10
VCOMP = upper clamp
VMULT = VVFF = 0.915 V (1)
Boost inductor saturation detector
VCS_th
IINV
tSTART
Threshold on current sense
(1)
E/A input pull-up current
VCS > VCS_th, before restart
1.6
1.7
1.8
V
5
10
13
µA
Restart delay
300
µs
Pfc_ok functions
IPFC_OK
Input bias current
VPFC_OK = 0 to 2.6 V
Clamp voltage
IPFC_OK = 1 mA
VPFC_OK_S
OVP threshold
(1)
VPFC_OK_R
Restart threshold after OVP
VPFC_OK_C
VPFC_OK_D
VPFC_OK_E
-0.1
-1
µA
9
9.5
V
Voltage rising
2.435
2.5
2.565
V
(1)
Voltage falling
2.34
2.4
2.46
V
Disable threshold
(1)
Voltage falling
0.12
0.23
0.35
V
Enable threshold
(1)
Voltage rising
0.15
0.27
0.38
V
1.61
1.66
1.71
V
3
V
Feedback failure detection
VINVD
Feedback failure detection
threshold (on VINV)
(1)
Voltage falling,
VPFC_OK = VPFC_OK_S
Voltage feedforward
VVFF
10/35
Linear operation range
1
DocID024474 Rev 1
L4984D
Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol
ΔV
Parameter
Test condition
Dropout VMULTpk-VVFF
Min
Typ
Max
Unit
Before turn-on
800
mV
After turn-on
20
ΔVVFF
Line drop detection threshold
Below peak value
25
60
100
mV
ΔVVFF
Line drop detection threshold
Below peak value Tj = 0 to 100 °C
40
70
100
mV
RDISCH
Internal discharge resistor
5
10
20
kΩ
VDIS
Disable threshold
(1)
VEN
Enable threshold
(1)
Voltage falling
0.745
0.8
0.855
V
Voltage rising
0.845
0.88
0.915
V
Fixed-off-time modulator
ITIMER
Programming current
VMULT = 1 V
142
153
163
µA
TOFF
Programmed off-time
VMULT = 1 V
2.88
3.09
3.30
µs
RDIS
Discharge resistance
35
60
120
W
CTIMER
Timing capacitor range
0.1
2.2
nF
TOFF_pk
Programming range
1.45
50
µs
On the peak of VMULT
Soft-start
TSS
Activation time
VMULTx
Pull-up voltage
VOL
300
µs
10 kΩ from MULT to GND
4.1
V
Output low voltage
Isink = 100 mA
0.6
VOH
Output high voltage
Isource = 5 mA
Isrcpk
Peak source current
-0.6
A
Isnkpk
Peak sink current
0.8
A
Gate driver
9.8
1.2
10.3
V
V
tf
Voltage fall time
30
60
ns
tr
Voltage rise time
45
110
ns
12
15
V
1.1
V
VOclamp
Output clamp voltage
Isource = 5 mA; Vcc = 20 V
10
UVLO saturation
VCC = 0 to VCCon, Isink = 2 mA
1. Parameters tracking each other.
2. The multiplier output is given by:
(
V
⋅ V
− 2.5
COMP
Vcs = VCS_O fst + K M ⋅ MULT
2
V
VFF
DocID024474 Rev 1
)
11/35
Typical electrical performance
4
L4984D
Typical electrical performance
Figure 3. IC consumption vs. VCC
Figure 4. IC consumption vs. Tj
10
100
Operating
10
Quiescent
Disabled or
during OVP
1
Co=1nF
f =70kHz
Tj = 25 C
Icc [mA]
VCC=12V
Co = 1nF
f =70kHz
Ic current (mA)
1
0.1
Latched off
0.1
Before Start up
0.01
VccOFF
VccON
0.01
0.001
0
5
10
15
20
25
-50
30
Vcc [V]
-25
0
25
50
75
100
125
150
175
Tj (C)
AM13219v1
Figure 5. VCC Zener voltage vs. Tj
AM13220v1
Figure 6. Startup & UVLO vs. Tj
28
13
27
12
VCC-ON
11
26
VCC-OFF
V
V
10
25
9
24
8
23
7
6
22
-50
-25
0
25
50
75
100
125
150
-50
175
Tj (C)
-25
0
25
Figure 7. Feedback reference vs. Tj
50
75
100
125
150
Tj (C)
AM13221v1
175
AM13222v1
Figure 8. E/A output clamp levels vs. Tj
2.6
7
Uper Clamp
6
VCC = 12V
2.55
5
VCOMP (V)
pin INV (V)
VCC = 12V
2.5
4
3
Lower Clamp
2
2.45
1
0
2.4
-50
-50
-25
0
25
50
75
Tj (C)
12/35
100
125
150
-25
0
25
50
75
100
125
150
175
175
AM13223v1
DocID024474 Rev 1
Tj (C)
AM13224v1
L4984D
Typical electrical performance
Figure 9. UVLO saturation vs. Tj
Figure 10. OVP levels vs. Tj
2.5
1
0.9
2.48
VCC = 0V
0.8
OVP Th
2.46
PFC_OK levels (V)
0.7
V
0.6
0.5
0.4
2.44
2.42
2.4
0.3
Restart Th
0.2
2.38
0.1
2.36
-50
0
-50
-25
0
25
50
75
Tj (C)
100
125
150
-25
0
25
50
175
75
100
125
150
175
Tj (C)
AM13225v1
AM13226v1
Figure 11. Inductor saturation threshold vs. Tj
Figure 12. Vcs clamp vs. Tj
0.9
1.9
VCC = V
1.8
0.89
VCOMP = Upper Clamp
1.7
0.88
Vcs clamp (V)
CS pin (V)
1.6
1.5
1.4
0.87
1.3
0.86
1.2
1.1
-50
-25
0
25
50
75
100
125
150
175
0.85
-50
Tj (C)
-25
0
25
50
AM13227v1
Figure 13. Timer pin charging current vs. Tj
75
100
125
150
175
AM13228v1
Tj (C)
Figure 14. Brownout threshold (on VFF) vs. Tj
200
1
190
180
0.9
Enable
170
0.8
Disable
150
V
I TMER (uA)
160
0.7
140
0.6
130
120
0.5
110
0.4
100
-50
-25
0
25
50
75
Tj (C)
100
125
150
175
AM13229v1
DocID024474 Rev 1
-50
-25
0
25
50
75
Tj (C)
100
125
150
175
AM13230v1
13/35
Typical electrical performance
L4984D
Figure 15. RFF discharge vs. Tj
Figure 16. Line drop detection threshold vs. Tj
20
90
18
80
16
70
14
60
12
mV
kOhm
50
10
40
8
30
6
20
4
10
2
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
Tj (C)
25
50
2
0.4
1.5
0.35
1
0.3
0.5
0.25
0
75
100
125
150
175
AM13232v1
Figure 18. PFC_OK enable threshold vs. Tj
ON
0.2
-0.5
0.15
-1
0.1
-1.5
0.05
-2
OFF
0
-50
-25
0
25
50
75
Tj (C)
100
125
150
175
-50
AM13233v1
Figure 19. FFD threshold vs. Tj
2
1.9
1.8
VINVD (V)
0
Tj (C)
Th (V)
D (mV)
Figure 17. VMULTpk - VVFF dropout vs. Tj
1.7
1.6
1.5
1.4
-50
-25
0
25
50
Tj(C)
14/35
-25
AM13231v1
75
100
125
150
175
AM13235v1
DocID024474 Rev 1
-25
0
25
50
75
Tj (C)
100
125
150
175
AM13234v1
L4984D
Typical electrical performance
Figure 20. Multiplier characteristics at VFF=1 V
Figure 21. Multiplier characteristics at VFF=3 V
500
1.2
VCOMP
VCOMP
1.1
450
VFF = 3 V
1.0
400
Upper voltage clamp
Upper voltage clamp
0.9
5.5 V
350
0.8
5.5 V
5.0 V
300
4.5 V
0.6
0.5
4.0 V
VCS (mV)
VCS (V)
0.7
5.0 V
250
4.5 V
200
0.4
3.5 V
4.0 V
150
0.3
3.5 V
100
0.2
3.0 V
3.0 V
50
0.1
2.6 V
2.6 V
0.0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
1.1
0.5
1
1.5
Figure 22. Multiplier gain vs. Tj
2.5
3
3.5
VMULT (V)
AM13236v1
VMULT (V)
2
AM13237v1
Figure 23. Gate drive clamp vs. Tj
Multiplier Gain vs. Tj
12.9
0.5
VCC = 20V
12.85
0.4
Gain (1/V)
12.8
V
VCC = 12V
VCOMP = 4V
VMULT = VFF = 1V
12.75
0.3
12.7
0.2
-50
-25
0
25
50
75
100
125
150
12.65
175
Tj (C)
-50
-25
0
25
50
AM13238v1
Figure 24. Gate drive output saturation vs. Tj
75
Tj (C)
100
125
150
175
AM13239v1
Figure 25. Delay to output vs. Tj
12
300
High level
10
250
TD(H-L) (ns)
V
8
6
200
VCC = 12V
150
4
100
Low level
2
50
0
-50
-25
0
25
50
75
Tj (C)
100
125
150
-50
175
AM13240v1
DocID024474 Rev 1
-25
0
25
50
75
Tj (C)
100
125
150
175
AM13241v1
15/35
Application information
L4984D
5
Application information
5.1
Theory of operation
The L4984D implements conventional “peak” current mode control, where the on-time TON
of the external power switch is determined by the peak inductor current reaching the
programmed value. The off-time TOFF, instead, is determined by a special fixed-off-time
(FOT) modulator in such a way that the resulting switching period is constant as long as the
boost converter is operated in CCM (i.e. the current in the boost inductor remains greater
than zero in a switching cycle).
To understand how TOFF needs to be modulated to achieve a fixed switching frequency
independent of the instantaneous line voltage and the load, it is useful to consider the V·s
balance equation for the boost inductor under the assumption of CCM operation:
Equation 1
TON Vpk sinθ = TOFF ( Vout − Vpk sinθ )
where Vpk is the peak line voltage, Vout the regulated output voltage and θ the
instantaneous phase angle of the line voltage. Solving for TON, we get:
Equation 2
⎛ Vout
⎞
TON = ⎜⎜
− 1⎟⎟ TOFF
⎝ Vpk sinθ ⎠
then, the switching period TSW is:
Equation 3
⎛ Vout
⎞
Vout
− 1⎟⎟ TOFF + TOFF =
Tsw = TON + TOFF = ⎜⎜
TOFF
Vpk sin θ
⎝ Vpk sin θ ⎠
In the end, if TOFF is changed proportionally to the instantaneous line voltage, i.e. if:
Equation 4
TOFF = K t Vpk sin θ
then TSW is equal to Kt·Vout and, since Vout is regulated by the voltage loop, also TSW (and
fSW = 1/TSW) is fixed. This result is based on the sole assumption that the instantaneous line
voltage and the output load are such that the boost inductor operates in CCM.
16/35
DocID024474 Rev 1
L4984D
Application information
Figure 26. Line-modulated fixed-off-time modulator: a) internal block diagram; b) key
waveforms
MULT
TIMER
0
COMP
MULT
TOFF
CS
+
t
t
-
Multiplier
R
-
ITimer
TON
S
PWM
Comparator
S
+
t
Q
Q
GD
TIMER
Driver
R
t
ON
GD
PWM Latch
OFF
CT
Multiplier output
CS
t
t
a)
b)
AM13242v1
With reference to the schematic and the relevant key waveforms in Figure 26, an off-time
proportional to the instantaneous line voltage is achieved by charging the capacitor CT with
a constant current ITIMER, accurately fixed internally and temperature compensated, while
the MOSFET is off and commanding MOSFET turn-on (and resetting CT at zero) as the
voltage across CT equals that on the MULT pin. The voltage on this pin is:
Equation 5
VMULT = K P Vpk sin θ
where KP is the divider ratio of the resistors biasing the MULT pin. As a result:
Equation 6
TOFF =
CT
ITIMER
K P Vpk sinθ →
Kt =
CT
ITIMER
KP
and the switching frequency is:
Equation 7
fsw =
ITIMER
1
1
=
=
Tsw K P C T Vout K t Vout
The timing capacitor CT, therefore, is selected with the following design formula:
Equation 8
CT =
ITIMER
K P Vout fsw
Vout and fsw are design specifications, KP is chosen so that the voltage on the MULT pin is
within the multiplier linearity range (0 to 3 V) and ITIMER is specified in Section 3: Electrical
characteristics.
DocID024474 Rev 1
17/35
Application information
L4984D
Along a line half-cycle, TOFF goes all the way from a minimum near the zero-crossing to a
maximum on the sinusoid peak. It is important to check that the off-time occurring on the
peak of the voltage sinusoid at minimum input voltage is greater then the minimum
programmable value:
Equation 9
TOFF min =
CT
ITIMER
K P Vpk min > 1.45 μs
This constraint limits the maximum programmable frequency at:
Equation 10
fsw. max = 690
Vpk min
[kHz]
Vout
As the line RMS voltage is increased and/or the output load is decreased, the boost inductor
current tends to become discontinuous starting from the region around the zero-crossings.
As a result, the switching frequency is no longer constant and tends to increase. However,
the frequency rise is significantly lower as compared to that in a transition-mode (TM)
operated boost PFC stage, as illustrated in Figure 25. The switching frequency can exceed
fsw.max in the region where the inductor current is discontinuous.
Figure 27. Typical frequency change along a line half-cycle in a boost PFC operated
in LM-FOT (left) and TM (right)
Transition -mode operated PFC
LM -FOT operated PFC
1.6
9
Vin = 264 Vac
Vin = 230 Vac
8
1.4
Normalized switching frequency
Normalized switching frequency
Vin = 230 Vac
1.2
1
Vin = 88 Vac
0.8
Vin = 115 Vac
0.6
7
6
5
4
Vin = 115 Vac
3
Vin = 88 Vac
2
1
Vin = 264 Vac
0.4
0
0.52
1.05
1.57
2.09
2.62
0
3.14
0
0.52
Line voltage phase angle (rad)
1.05
1.57
2.09
2.62
3.14
Line voltage phase angle (rad)
AM13243v1
In this example the voltage ripple appearing across the output capacitor Cout has been
neglected. This ripple at twice the line frequency fL has peak amplitude ΔVout proportional
to the output current Iout:
Equation 11
ΔVout =
Iout
4 π fL Cout
As a consequence, fsw is not exactly constant but is modulated at 2fL, which spreads the
spectrum of the electrical noise injected back into the power line and facilitates the
compliance with conducted EMI emission regulations. The relative frequency change due to
the output voltage ripple is:
18/35
DocID024474 Rev 1
L4984D
Application information
Equation 12
Δfsw
=
fsw
ΔVout
Vout
ΔVout
1+
Vout
Figure 28. Line-modulated fixed-off-time-controlled boost PFC: current waveforms
Vin = 88 Vac
Line current
Vin = 88 Vac
Boost inductor
current envelope
Vin = 190 Vac
Vin = 264 Vac
Vin = 264 Vac
Inductor current (A)
Line current (A)
Vin = 230 Vac
Line voltage phase angle (rad)
Line voltage phase angle (rad)
AM13244v1
As a result of the operation of the circuit in Figure 26, the current that the boost PFC preregulator draws from the power line is not exactly sinusoidal but is affected by distortion that
is lower as the current ripple in the boost inductor is smaller as compared to its peak value.
Figure 28 shows some theoretical waveforms, relevant to full load condition, in a line cycle
at different input voltages.
In the diagram on the left-hand side the line (input) current waveform is shown for different
line voltages, while on the right-hand side the envelope of the inductor current at minimum
and maximum line voltage is shown.
The input current waveform relevant to Vin = 88 Vac shows no visible sign of distortion; the
operation of the boost inductor is CCM throughout the entire line cycle as testified by the
inductor current envelope. The brown waveform is relevant to Vin = 190 Vac, which is the
condition where CCM operation no longer occurs at zero-crossings (this voltage value, for a
given power level, depends on the inductance value of the boost inductor); a certain degree
of distortion is already visible.
DocID024474 Rev 1
19/35
Application information
L4984D
% Harmonic amplitude
(normalized to fundamental)
Figure 29. Line-modulated fixed-off-time-controlled boost PFC: input current
harmonic contents
Vin = 264Vac
THD = 17.7%
Harmonic order (n)
AM13245v1
The waveform relevant to Vin = 264 Vac shows the highest degree of distortion and the
largest portion of the line cycle where boost inductor operates in discontinuous mode
(DCM). However, its harmonic content, shown in Figure 29, is still so low that it is not an
issue for EMC compliance. Almost all the distortion is concentrated in the third harmonic,
whose amplitude is 17% of the fundamental one, while the THD is 17.7%.
20/35
DocID024474 Rev 1
L4984D
6
Overvoltage protection (OVP)
Overvoltage protection (OVP)
Normally, the voltage control loop keeps the output voltage Vout of the PFC pre-regulator
close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A
pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a
separate resistor divider (R3 high, R4 low, see Figure 30). This divider is selected so that
the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually
larger than the maximum Vout that can be expected.
Figure 30. Output voltage setting, OVP and FFD functions: internal block diagram
Vout
R3a
R3
L4984D
R3b
6
+
Disable
2.5 V
2.4 V
PFC_OK
R1a
0.23 V
0.27 V
-
OVP
L_OVP
+
R1
1.66 V
R1b
+
-
Frequency
compensation
COMP
2
1
R4
R2
INV
2.5 V
+
Error Amplifier
AM13246v1
Note:
Example: Vout = 400 V, Voutx = 434 V.
Select: R3 = 8.8 M; then: R4 = 8.8 M ·2.5/(434-2.5) = 51 k.
When this function is triggered, the gate drive activity is immediately stopped until the
voltage on the pin PFC_OK drops below 2.4 V. Notice that R1, R2, R3 and R4 can be
selected without any constraints. The unique criterion is that both dividers must sink a
current from the output bus which needs to be significantly higher than the bias current of
both pins INV and PFC_OK (< 1 μA).
DocID024474 Rev 1
21/35
Feedback failure detection (FFD)
7
L4984D
Feedback failure detection (FFD)
The OVP function handles “normal” overvoltage conditions, i.e. those resulting from an
abrupt load/line change or occurring at startup. If the overvoltage is generated by a
feedback failure, for instance when the upper resistor of the output divider (R1) fails open,
eventually the error amplifier output (COMP) saturates high and the voltage on its inverting
input (INV) drops from its steady-sate value (2.5 V). An additional comparator monitors the
voltage on the INV pin, comparing it against a reference located at 1.66 V. When the voltage
on pin PFC_OK exceeds 2.5 V and, simultaneously, that on the INV pin falls below 1.66 V,
the FFD function is triggered: the gate drive activity is immediately stopped, the device is
shut down and its quiescent consumption reduced. This condition is latched and to restart
the IC it is necessary to recycle the input power, so that the VCC voltage goes below 6 V.
The pin PFC_OK doubles its function as a not-latched IC disable: a voltage below 0.23 V
shuts down the IC, reducing its consumption below 2 mA. To restart, simply let the voltage
on the pin go above 0.27 V. Note that these functions offer complete protection against not
only feedback loop failures or erroneous settings, but also against a failure of the protection
itself. Either resistor of the PFC_OK divider failing short or open or a pin PFC_OK floating
results in shutting down the IC and stopping the pre-regulator.
22/35
DocID024474 Rev 1
L4984D
8
Voltage feedforward
Voltage feedforward
The power stage gain of PFC pre-regulators varies with the square of the RMS input
voltage. So does the crossover frequency fc of the overall open-loop gain because the gain
has a single pole characteristic. This leads to large trade-offs in the design.
For example, setting the gain of the error amplifier to get fc = 20 Hz at 264 Vac means
having fc = 4 Hz at 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow
control loop causes large transient current flow during rapid line or load changes that are
limited by the dynamics of the multiplier output. This limit is considered when selecting the
sense resistor to let the full load power pass under minimum line voltage conditions, with
some margin. But a fixed current limit allows excessive power input at high line, whereas a
fixed power limit requires the current limit to vary inversely with the line voltage.
Input voltage feedforward compensates for the gain variation with the line voltage and
allows all of the above-mentioned issues to be minimized. It consists of deriving a voltage
proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit
(1/V2 corrector) and providing the resulting signal to the multiplier that generates the current
reference for the inner current control loop (see Figure 31).
Figure 31. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer
characteristic
Rectified mains
E/A output
(V COMP )
current
reference
(Vcsx)
L4984D
Vcsx
2
MULTIPLIER
1.5
V COMP=4V
"ideal" diode
1/V
-
2
Actual
Ideal
3
1
+
9.5V
MULT
MAINS DROP
DETECTOR
0.5
5
VFF
C FF
0
0
R FF
0.8
1
2
3
4
V FF=V MULT
AM13248v1
In this way, if the line voltage doubles the amplitude of the multiplier, output is halved and
vice versa, so that the current reference is adapted to the new operating conditions with
(ideally) no need to invoke the slow response of the error amplifier. Additionally, the loop
gain is constant throughout the input voltage range, which improves significantly dynamic
behavior at low line and simplifies loop design.
Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration,
which has its own time constant. If it is too small, the voltage generated is affected by a
considerable amount of ripple at twice the mains frequency that causes distortion of the
current reference (resulting in high THD and poor PF); if it is too large there is a
considerable delay in setting the right amount of feedforward, resulting in excessive
overshoot and undershoot of the pre-regulator output voltage in response to large line
voltage changes. Clearly, a trade-off is required.
The L4984D realizes a new voltage feedforward that, using just two external parts, strongly
minimizes this time constant trade-off issue whichever voltage change occurs on the mains,
DocID024474 Rev 1
23/35
Voltage feedforward
L4984D
both surges and drops. A capacitor CFF and a resistor RFF, connected from the VFF pin to
ground, complete an internal peak-holding circuit that provides a DC voltage equal to the
peak of the voltage applied on the MULT pin. In this way, in case of sudden line voltage rise,
CFF is rapidly charged through the low impedance of the internal diode; in case of line
voltage drop, an internal “mains drop” detector enables a low impedance switch that
suddenly discharges CFF, therefore reducing the settling time needed to reach the new
voltage level. The discharge of CFF is stopped when either its voltage equals the voltage on
the MULT pin or the voltage on the VFF pin falls below 0.88 V, to prevent the “brownout
protection” function from being improperly activated (see Section 12: Power management
and housekeeping functions). With this functionality, an acceptably low steady-state ripple of
the VFF voltage (and, then, low current distortion) can be achieved with a limited
undershoot or overshoot on the pre-regulator output during line transients.
The twice-mains-frequency (2⋅ fL) ripple appearing across CFF is triangular with peak-topeak amplitude that, with good approximation, is given by:
Equation 13
ΔVFF =
2 VMULTpk
1+ 4fLRFF CFF
where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this
ripple, related to the amplitude of its 2⋅ fL component, is:
Equation 14
D3 % =
100
2π fLRFF CFF
Figure 32 shows a diagram that helps choose the time constant RFF·CFF based on the
amount of maximum desired 3rd harmonic distortion. Note, however, that there is a
minimum value for the time constant RFF·CFF below which improper activation of the VFF
fast discharge may occur. In fact, the twice-mains-frequency ripple across CFF under
steady-state conditions must be lower than the minimum line drop detection threshold
(ΔVVFF_min = 40 mV). Therefore:
Equation 15
2
RFF ⋅ CFF >
VMULTpk _ max
ΔVVFF _ min
4 fL _ min
−1
Always connect RFF and CFF to the pin; the IC does not work properly if the pin is left
floating or may be damaged if connected directly to ground.
24/35
DocID024474 Rev 1
L4984D
Voltage feedforward
Figure 32. RFF·CFF as a function of 3rd harmonic distortion introduced in the input
current
10
1
f L = 50 Hz
RFF · CFF [s]
0.1
f L= 60 Hz
0.01
0.1
1
D3 %
DocID024474 Rev 1
10
AM13247v1
25/35
Soft-start
9
L4984D
Soft-start
To reduce inrush energy at startup or after an auto-restart protection tripping, the L4984D
uses soft-start. Please refer to Table in Section 12: Power management and housekeeping
functions for more details of the events triggering soft-start.
The function is performed by internally pulling the voltage on the MULT pin towards an
asymptotic level located at about 4.1 V as the device wakes up. This has a twofold effect: on
the one hand, the output of the multiplier is lowered through the voltage feedforward
function, therefore programming a lower peak current; on the other hand, the off-time of the
power switch is considerably prolonged with respect to the normal values programmed by
the capacitor connected to the TIMER pin. In this way, both the current inrush and the risk of
saturating the boost inductor at startup are minimized.
After 300 μs from its activation, the pull-up is released. The voltage on the MULT pin decays
with the time constant determined by the resistor divider that biases the pin and the bypass
capacitor typically connected between the pin and ground to reduce noise pick-up. At the
same time, CFF is discharged by turning on the internal low impedance discharge switch
(see Section 8: Voltage feedforward).
The soft-start function is performed at turn-on by VCC Turn-on threshold (VCCOn), by the
brownout function and at startup by PFC_OK. On the following activations by PFC_OK (like
during burst-mode operation driven by a D2D converter controller) the soft-start function is
not performed. Figure 33 shows the different startup mechanisms and the activations of the
soft-start function.
Figure 33. Startup mechanisms and activations of the soft-start function
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DocID024474 Rev 1
L4984D
10
Inductor saturation detection
Inductor saturation detection
Boost inductor hard saturation may be a fatal event for a PFC pre-regulator: the current
upslope becomes so large (50-100 times steeper, see Figure 34) that, during the current
sense propagation delay, the current may reach abnormally high values. The voltage drop
caused by this abnormal current on the sense resistor reduces the gate-to-source voltage,
so that the MOSFET may work in the active region and dissipate a huge amount of power,
which leads to a catastrophic failure after few switching cycles.
However, even a well-designed boost inductor may occasionally saturate when the boost
stage recovers after a missing line cycle. This happens when the restart occurs at an
unfavorable line voltage phase, i.e. when the output voltage is lower than the rectified input
voltage as this reappears. As a result, in the boost inductor the inrush current coming from
the bridge rectifier and going to the output capacitor adds up to the switched current.
Furthermore, there is little or no voltage available for demagnetization.
To cope with a saturated inductor, the L4984D is provided with a second comparator on the
current sense pin (CS, pin 4) that stops the IC if the voltage, normally limited within 0.88 V,
exceeds 1.7 V. After that, the IC is restarted by the internal starter circuitry; the starter
repetition time is low enough (300 μs typ.) to guarantee low stress for the inductor, the
Power MOSFET and the boost diode.
Figure 34. Effect of boost inductor saturation on MOSFET current and detection
method
Vcs
Vcs
Vcs
1.7V
Multiplier
Output
Inductor not
saturating
1.7V
DIL
DIL
Multiplier
Output
DIL
Tdelay
1.7V
t
Tdelay
Inductor slightly
saturating
Multiplier
Output
t
t
Tdelay
Inductor saturating
hard
AM13249v1
DocID024474 Rev 1
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THD optimizer circuit
11
L4984D
THD optimizer circuit
The L4984D is provided with a special circuit that reduces the conduction dead-angle
occurring at the AC input current near the zero-crossings of the line voltage (crossover
distortion). In this way the THD (total harmonic distortion) of the current is considerably
reduced.
A major cause of this distortion is the inability of the system to transfer energy effectively
when the instantaneous line voltage is very low. This effect is magnified by the highfrequency filter capacitor placed after the bridge rectifier, which retains some residual
voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input
current flow to temporarily stop.
To overcome this issue the device forces the PFC pre-regulator to process more energy
near the line voltage zero-crossings as compared to that commanded by the control loop.
This results in both minimizing the time interval where energy transfer is lacking and fully
discharging the high-frequency filter capacitor after the bridge.
Figure 35. THD optimizer circuit
t
t
1/V
VFF
t
2
COMP
MULTIPLIER
MULT
+
to PWM
comparator
+
t
OFFSET
GENERATOR
t
@ Vac1
@ Vac2 > Vac1
t
AM13250v1
28/35
DocID024474 Rev 1
L4984D
THD optimizer circuit
Figure 36. HD optimization: standard PFC controller
Figure 35 shows the internal block diagram of the THD optimizer circuit.
To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor
after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large
capacitance, in fact, introduces a conduction dead-angle of the AC input current - even with
an ideal energy transfer by the PFC pre-regulator - therefore reducing the effectiveness of
the optimizer circuit.
Essentially, the circuit artificially increases the on-time of the power switch with a positive
offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.
This offset is reduced as the instantaneous line voltage increases, so that it becomes
negligible as the line voltage moves toward the top of the sinusoid. Furthermore, the offset is
modulated by the voltage on the VFF pin (see Section 8: Voltage feedforward) so as to have
little offset at low line, where energy transfer at zero-crossings is typically quite good, and a
larger offset at high line where the energy transfer gets worse.
The effect of the circuit is shown in Figure 36, where the key waveforms of a standard PFC
controller are compared to those of this chip. Note the significant reduction in the region
around the zero-crossing where the drain voltage cannot reach the output voltage and how
switching frequency drops dramatically near the zero-crossing.
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Power management and housekeeping functions
12
L4984D
Power management and housekeeping functions
A communication line with the control IC of the cascaded DC-DC converter can be
established via the disable function included in the PFC_OK pin (see Section 7: Feedback
failure detection (FFD) for more details). Typically this line is used to allow the PWM
controller of the cascaded DC-DC converter to shut down the L4984D in case of light load
and to minimize the no-load input consumption. Should the residual consumption of the chip
be an issue, it is also possible to cut down the supply voltage. Interface circuits like those
are shown in Figure 37. Needless to say, this operation assumes that the cascaded DC-DC
converter stage works as the master and the PFC stage as the slave or, in other words, that
the DC-DC stage starts first; it powers both controllers and enables/disables the operation of
the PFC stage.
Figure 37. Interface circuits that let DC-DC converter controller IC disable the L4984D
L6566A
6
VCC 5
VCC_PFC
L4984D
VCC
10
PFC_OK 6
L6599A
9
PFC_STOP
8
PFC_STOP
L4984D
PFC_OK 6
L6591
L4984D
AM13252v1
Another available function is brownout protection, which is basically a not-latched shutdown
function that is activated when a condition of mains undervoltage is detected. This condition
may cause overheating of the primary power section due to an excess of RMS current.
Brownout can also cause the PFC pre-regulator to work in open loop, which may be
dangerous to the PFC stage itself and the downstream converter, should the input voltage
return abruptly to its rated value. Another problem is the spurious restarts that may occur
during converter power-down and that cause the output voltage of the converter to not
decay to zero monotonically. For these reasons it is usually preferable to shut down the unit
in the case of brownout. The brownout threshold is internally fixed at 0.8 V and is sensed on
the VFF pin while the voltage is falling. An 80 mV hysteresis prevents rebounding at input
voltage turn-off.
The soft-start function is performed by PFC_OK enable threshold (VPFC_OK_E) only at
startup, but not on the following activations, to ensure a proper burst-mode operation (as
described in Figure 33). For this reason pin MULT is suggested to be used as remote
ON/OFF control.
In Table 6 it is possible to find a summary of all of the above mentioned working conditions
that cause the device to stop operating.
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DocID024474 Rev 1
L4984D
Power management and housekeeping functions
Table 6. Summary of L4984D idle states
Condition
UVLO
Standby
Caused or revealed by IC behavior
Restart
condition
Typical IC
SS
consumption activation
VCC < VCCOff
Disabled
VCC > VCCOn
65 µA
Yes
VPFC_OK < VPFC_OK_D
Stop
switching
VPFC_OK >
VPFC_OK_E
1.5 mA
No
Stop
switching
VVFF > VEN
1.5 mA
Yes
AC brownout VVFF < VDIS
OVP
VPFC_OK > VPFC_OK_S
Stop
switching
VPFC_OK <
VPFC_OK_R
2.2 mA
No
Feedback
failure
VPFC_OK > VPFC_OK_S
AND
VINV < 1.66 V
Latched-off
VCC < VCCrestart
then
VCC > VCCOn
180 µA
Yes
Burst mode
VCOMP > 2.4 V
1.8 mA
No
Stop
switching
Auto restart
after 300 ìs
4 mA
No
Low
V
< 2.4 V
consumption COMP
Saturated
boost
inductor
Vcs > VCS_th
DocID024474 Rev 1
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Package mechanical data
13
L4984D
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Table 7. SSO10 mechanical data
Databook (mm)
Dim
Typ
Min
A
32/35
Max
1.75
A1
0.10
0.25
A2
1.25
b
0.31
0.51
c
0.17
0.25
D
4.90
4.80
5
E
6
5.80
6.20
E1
3.90
3.80
4
e
1
h
0.25
0.50
L
0.40
0.90
K
0°
8°
DocID024474 Rev 1
L4984D
Package mechanical data
Figure 38. SSO10 package dimensions
8140761 rev. A
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Revision history
14
L4984D
Revision history
Table 8. Document revision history
34/35
Date
Revision
15-Apr-2013
1
Changes
Initial release.
DocID024474 Rev 1
L4984D
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