POWERINT PFS706EG

PFS704-729EG
HiperPFS Family
™
High Power PFC Controller with Integrated
High-Voltage MOSFET
Key Benefits
• Single chip solution for boost power factor correction (PFC)
• EN61000-3-2 Class C and D compliant
• High light load efficiency at 10% and 20% load
• >95% efficiency from 10% load to full load
• <130 mW no-load consumption at 230 VAC with output in
regulation
• <50 mW no-load consumption at 230 VAC in remote off state
• Frequency adjusted over line voltage, and line cycle
• Spread-spectrum across >60 kHz window to simplify EMI
filtering requirements
• Lower boost inductance
• Provides up to 1 kW peak output power
• >1 kW peak power delivery in power limit voltage regulation
mode
• High integration allows smaller form factor, higher power density
designs
• Incorporates control, gate driver, and high-voltage power
MOSFET
• Internal current sense reduces component count and system
losses
• Protection features include: UV, OV, OTP, brown-in/out, cycleby-cycle current limit, and power limiting for overload protection
• Halogen free and RoHS compliant
Applications
• PC
• Printer
• LCD TV • Video game consoles Output Power Table
Maximum Continuous
Output Power Rating at
90 VAC
Peak Output Power
Rating at 90 VAC
PFS704EG
110 W
120 W
PFS706EG
140 W
150 W
PFS708EG
190 W
205 W
PFS710EG
240 W
260 W
PFS712EG
300 W
320 W
PFS714EG
350 W
385 W
PFS716EG
388 W
425 W
Product
Maximum Continuous
Output Power Rating at
180 VAC
Peak Output Power
Rating at 180 VAC
PFS723EG
255 W
280 W
PFS724EG
315 W
350 W
PFS725EG
435 W
480 W
PFS726EG
540 W
600 W
PFS727EG
675 W
750 W
PFS728EG
810 W
900 W
PFS729EG
900 W
1000 W
Product
Table 1.
Output Power Table (see Notes on page 9)
•
High power adaptors
• High power LED lighting
• Industrial and appliance
• Generic PFC converters
+
VCC
D
AC
IN
VCC
HiperPFS
S
Figure 1.
www.powerint.com V
CONTROL
FB
DC
OUT
G
Typical Application Schematic.
PI-6021-110810
December 2011
PFS704-729EG
Section List
Description................................................................................................................................................................... 3
Product Highlights....................................................................................................................................................... 3
Pin Functional Description.......................................................................................................................................... 4
Pin Configuration....................................................................................................................................................... 4
Functional Block Diagram......................................................................................................................................... 4
Functional Description ................................................................................................................................................ 5
Output Power Table.................................................................................................................................................. 9
Application Example.............................................................................................................................................10-11
Design, Assembly, and Layout Considerations..................................................................................................... 12
Absolute Maximum Ratings...................................................................................................................................... 19
Parameter Table.................................................................................................................................................19-25
Typical Performance Characteristics....................................................................................................................... 26
Package Details ......................................................................................................................................................... 27
Part Ordering Information......................................................................................................................................... 28
Part Marking Information ......................................................................................................................................... 28
2
Rev. D 12/11
www.powerint.com
PFS704-729EG
Description
The HiperPFS device family members incorporate a continuous
conduction mode (CCM) boost PFC controller, gate driver, and
high voltage power MOSFET in a single, low-profile eSIP™
power package that is able to provide near unity input power
factor. The HiperPFS devices eliminate the PFC converter’s
need for external current sense resistors, the power loss
associated with those components, and leverages an innovative
control technique that adjusts the switching frequency over
output load, input line voltage, and even input line cycle. This
control technique is designed to maximize efficiency over the
entire load range of the converter, particularly at light loads.
Additionally, this control technique significantly minimizes the
EMI filtering requirements due to its wide-bandwidth spread
spectrum effect. HiperPFS includes Power Integrations’
standard set of comprehensive protection features, such as
integrated soft-start, UV, OV, brown-in/out, and hysteretic thermal
shutdown. HiperPFS also provides cycle-by-cycle current limit
for the power MOSFET, power limiting of the output for overload protection, and pin-to-pin short-circuit protection.
HiperPFS’s innovative variable-frequency continuous conduction
mode of operation (VF-CCM) minimizes switching losses by
maintaining a low average switching frequency, while also
varying the switching frequency in order to suppress EMI, the
traditional challenge with continuous-conduction-mode
solutions. Systems using HiperPFS typically reduce the total X
and Y capacitance requirements of the converter, the inductance
of both the boost choke and EMI noise suppression chokes,
reducing overall system size and cost. Additionally, compared
with designs that use discrete MOSFETs and controllers,
HiperPFS devices dramatically reduce component count and
board footprint while simplifying system design and enhancing
reliability. The innovative variable-frequency, continuous
conduction mode controller enables the HiperPFS to realize all
of the benefits of continuous-conduction mode operation while
leveraging low-cost, small, simple EMI filters.
Many regions mandate high power factor for many electronic
products with high power requirements. These rules are
combined with numerous application-specific standards that
require high power supply efficiency across the entire load
range, from full load to as low as 10% load. High efficiency at
light load is a challenge for traditional PFC approaches in which
fixed MOSFET switching frequencies cause fixed switching
losses on each cycle, even at light loads. HiperPFS simplifies
compliance with new and emerging energy-efficiency standards
over a broad market space in applications such as PCs, LCD
TVs, notebooks, appliances, pumps, motors, fans, printers, and
LED lighting.
HiperPFS advanced power packaging technology and high
efficiency simplifies the complexity of mounting the package
and thermal management, while providing very high power
capabilities in a single compact package; these devices are
suitable for PFC applications from 75 W to 1 kW
Product Highlights
Protected Power Factor Correction Solution
• Incorporates high-voltage power MOSFET, controller, and gate
driver
• EN61000-3-2 Class D compliance
• Integrated protection features reduce external component count
• Accurate built-in brown-in/out protection
• Accurate built-in undervoltage (UV) protection
• Accurate built-in overvoltage (OV) protection
• Hysteretic thermal shutdown (OTP)
• Internal power limiting function for overload protection
• Cycle-by-cycle power switch current limit
• No external current sense required
• Provides “lossless” internal sensing via sense-FET
• Reduces component count and system losses
• Minimizes high current gate drive loop area
• Minimizes output overshoot and stresses during start-up
• Integrated power limit and frequency soft start
• Improve dynamic response
• Input line feed-forward gain adjustment for constant loop
gain across entire input voltage range
• Eliminates up to 40 discrete components for higher reliability
and lower cost
Intelligent Solution for High Efficiency and Low EMI
• Continuous conduction mode PFC uses novel constant volt/
amp-second control engine
• High efficiency across load using a UF boost diode
• Low cost EMI filter
• Universal input device (PFS704 – PFS716) utilize frequency
sliding technique for light load efficiency improvements
• >95% efficiency from 10% load to full load at low line input
voltage
• >96% efficiency from 10% load to full load at high line input
voltage
• High line input device (PFS723 – PFS729) maintain higher
average switching frequency to minimize boost inductance
and core size
• >94% efficiency from 10% load to full load
• Variable switching frequency to simplify EMI filter design
• Varies over line input voltage to maximize efficiency and
minimize EMI filter requirements
• Varies with input line cycle voltage by >60 kHz to maximize
spread spectrum effect
Advanced Package for High Power Applications
• Up to 1 kW peak output power capability in a highly compact
package
• Simple clip mounting to heat sink
• Can be directly connected to heat sink with insulation pad
• Provides thermal impedance equivalent to a TO-220
• Staggered pin arrangement for simple routing of board traces
and high voltage creepage requirements
• Single package solution for PFC converter reduces assembly
costs and layout size
3
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Rev. D 12/11
PFS704-729EG
Pin Functional Description
SIGNAL GROUND (G) Pin:
Discrete components used in the feedback circuit, including
loop compensation, decoupling capacitors for the supply (VCC)
and line-sense (V) must be referenced to the G pin. The
SIGNAL GROUND pin must not be tied to the SOURCE pin.
VOLTAGE MONITOR (V) Pin:
The V pin is tied to the rectified AC rail through an external
resistor. Internal circuitry detects the peak of the input line
voltage which resembles a full-wave rectified waveform. The
rectified high-voltage bus is connected directly to the V pin
voltage through a large resistor (4 MW for PFS70x and PFS71x;
9 MW for PFS72x) to minimize power dissipation and standby
power consumption. A small ceramic capacitor (0.1 mF for
PFS70x and PFS71x; 0.047 mF for PFS72x) is required from the
VOLTAGE MONITOR pin to SIGNAL GROUND pin to bypass
any switching noise present on the rectified bus. This pin also
features both brown-in and brown-out protection.
SOURCE (S) Pin:
This pin is the source connection of the power switch.
DRAIN (D) Pin:
This is the tab and drain connection of the internal power switch.
E Package (eSIP-7G)
Exposed Metal (On Edge)
Internally Connected
to GROUND Pin
FEEDBACK (FB) Pin:
The FEEDBACK pin is high input-impedance reference terminal
that connects to a feedback resistor network. This pin will also
feature fast overvoltage and undervoltage detection circuitry
that will disengage the internal power MOSFET in the event of a
system fault. A 10 nF capacitor is required between the
FEEDBACK to SIGNAL GROUND pins; this capacitor must be
placed very close to the device on the PCB to bypass any
switching noise. This pin is also used for loop compensation.
7
54 3 2 1
D
V
FB
VCC
G
S
Exposed Pad
(Backside)
Internally
Connected to
DRAIN Pin
(see eSIP-7G
Package
Drawing)
PI-5334-083110
Pin Configuration.
VOLTAGE MONITOR (V)
BIAS POWER (VCC)
INPUT
LINE INTERFACE
Peak
Detector
MON IVPK
7
D
Figure 2.
1 23 4 5
S
G
VCC
FB
V
BIAS POWER (VCC) Pin:
This is a 10-12 VDC bias supply used to power the IC. The bias
voltage must be externally clamped to prevent the VCC pin
from exceeding 13.4 VDC.
Exposed Metal
(On Edge)
Internally
Connected to
DRAIN Pin
DRAIN (D)
+
INTERNAL
SUPPLY
VCC+
-
OTP
Input UV
(IUV-/IUV+)
6V
Input Voltage
Emulation
SOFT
START
“Off-time derived with
constant Volt-Sec
VO-VIN
+
CINT
-
7 kHz
Filter
VOFF is a function of the error-voltage (VE) and is used to reduce the average
operating frequency as a function of output power for increased efficiency
(PFS704-716).
(VOFF = 0.8 V for PFS723-729).
Frequency
I
Internal
Reference
VREF
FEEDBACK (FB)
Transconductance
Error-Amplifier
FBUV/
FBOFF
+
-
+
-
OFF
VOFF
V
E
VE
1 kHz
Filter
+
-
FBOV
Slide
V
VPK
Comparator
Latch
Input UV
FBOV/UV
MON IS
Sense
FET
VCC
Power
MOSFET
+
Comparator
OTP
Driver
+
IS
LEB
-
MON is the switch current
sense scale factor which
is function of peak line
voltage derived from IVIN
Fast OV
Comparator
-
TIMER
SUPERVISOR
The internal derived error-voltage (VE)
regulates the output voltage
+
OCP
-
IOCP
CINT
UV Comparator
SIGNAL GROUND (G)
SOURCE (S)
PI-5333-113010
Figure 3.
Functional Block Diagram.
4
Rev. D 12/11
www.powerint.com
PFS704-729EG
The HiperPFS is a variable switching frequency boost PFC
solution. More specifically, it employs a constant amp-second
on-time and constant volt-second off-time control algorithm.
This algorithm is used to regulate the output voltage and shape
the input current to comply with regulatory harmonic current
limits (high power factor). Integrating the switch current and
controlling it to have a constant amp-sec product over the
on-time of the switch allows the average input current to follow
the input voltage. Integrating the difference between the output
and input voltage maintains a constant volt-second balance
dictated by the electro-magnetic properties of the boost inductor
and thus regulates the output voltage and power.
More specifically, the control technique sets constant voltseconds for the off-time (tOFF). The off-time is controlled such
that:
(1)
Since the volt-seconds during the on-time must equal the
volt-seconds during the off-time, to maintain flux equilibrium in
the PFC choke, the on-time (tON) is controlled such that:
(2)
The controller also sets a constant value of charge during each
on-cycle of the power MOSFET. The charge per cycle is varied
gradually over many switching cycles in response to load
changes so it can be regarded as substantially constant for a
half line cycle. With this constant charge (or amp-second)
control, the following relationship is therefore also true:
(3)
Substituting tON from (2) into (3) gives:
(4)
The relationship of (4) demonstrates that by controlling a constant
amp-second on-time and constant volt-second off-time, the input
current IIN is proportional to the input voltage VIN, therefore
providing the fundamental requirement of power factor correction.
This control produces a continuous mode power switch current
waveform that varies both in frequency and peak current value
across a line half-cycle to produce an input current proportional
to the input voltage.
Control Engine
The controller features a low bandwidth error-amplifier which
connects its non-inverting terminal to an internal voltage
reference of 6 V. The inverting terminal of the error-amplifier is
available on the external FEEDBACK pin which connects to the
external feedback resistor divider, transient load speed-up and
compensation networks to regulate the output voltage.
The internal sense-FET switch current is integrated and scaled
by the input voltage peak detector current sense gain (MON) and
compared with the error-amplifier signal (VE) to determine the
PI-5335-111610
Functional Description
VE
IS dt
Latch
RESET
VOFF
(VOUT-VIN)dt
Latch
SET
Gate
Drive (Q)
Maximum
ON-time
Minimum
OFF-time
Figure 4.
Timing
Supervisor
Idealized Converter Waveforms.
cycle on-time. Internally the difference between the input and
output voltage is derived and the resultant is scaled, integrated,
and compared to a voltage reference (VOFF) to determine the
cycle off-time. Careful selection of the internal scaling factors
produce input current waveforms with very low distortion and
high power factor.
The input voltage is internally synthesized using the switch duty
cycle and a 7 kHz low pass filter. This synthesized input voltage
representation is subtracted from a fixed reference voltage (6 V)
to derive a current source proportional to (VO-VIN). Please refer to
Figure 3.
Line Feed-Forward Scaling Factor (MON)
The VOLTAGE MONITOR (V) pin current is used internally to
derive the peak of the input line voltage which is used to scale
the gain of the current sense signal through the MON variable.
This contribution is required to reduce the dynamic range of the
control feedback signal as well maintain a constant loop gain
over the operating input line range. This line-sense feedforward gain adjustment is proportional to the square of the
peak rectified AC line voltage and is adjusted as a function of V
pin current. The line-sense feed-forward gain is also important
in providing a switch power limit over the input line range.
Besides modifying brown- in/out thresholds, the V pin resistor
also affects power limit of the device
This characteristic is optimized to maintain a relatively constant
internal error-voltage level at full load from an input line of 100
to 230 VAC input (PFS704-716).
Beyond the specified peak power rating of the device, the
internal power limit feature will regulate the output voltage
below the set regulation threshold as a function of output
overload beyond the peak power rating. Figure 5 illustrates the
typical regulation characteristic as function of load.
Soft-Start with Pin-to-Pin Short-Circuit Protection
Since the FEEDBACK pin is the interface for output voltage
regulation (resistor voltage divider to output voltage) as well as
loop compensation (series RC), the typical application circuit of
the HiperPFS requires an external transistor network to overcome
the inherently slow feedback loop response. Specifically, an
5
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Rev. D 12/11
1.2
PI-6216-113010
Normalized to Set Output Voltage
Regulation Threshold
PFS704-729EG
1
Soft-Start
Check
Sequence
0.8
0.6
Is
VCC >
VCC+
0.4
NO
Apply
6 mA V pin
Current Sink
Detect Input
Voltage Peak
YES
0.2
Apply 0.5 µA
on FB to
Check Open FB
0
0
0.2
0.4
0.6
0.8
1
1.2
Is VFB > FBOFF
1.4
NO
Start
Converter
Normalized to Peak Power Rating
Typical Normalized Output Voltage Characteristics as Function of Normalized Peak Load Rating
Is
VFB > FBOFF
and
VFB < FBOV
Internal Error-Voltage (VE)
YES
Remove
6 mA V pin
Current Sink
Slew Power-Limit
Over Soft-Start
Duration
VCC+
Is IV > IUV+
tSTART-DELAY
NO
YES
PI-5337-110910
tSOFT
Figure 7.
~5 V
t
PI-5336-110810
Figure 6.
NO
YES
VCC
Voltage
Figure 5.
Power Limit Soft-Start Function.
NPN and PNP transistor are tied between the output voltage
divider resistors to limit the maximum overshoot and undershoot during a load transient response. To reduce switch and
output diode current stress at start-up, the HiperPFS slews the
internal error-voltage from zero to its steady-state value at
start-up. Figure 6 illustrates the relative relationship between
the application of VCC and power limit soft-start function through
the internal error-voltage.
The error-voltage has a controlled slew rate of 0.25 V/ms at
start-up, corresponding to the tSOFT time duration for a full scale
error voltage of 5 V.
The beginning of soft-start is gated by the VCC+, IUV+ and
FEEDBACK pin voltage thresholds in the sequence described
below. Once the applied VCC is above the VCC+ threshold, the
sensed V pin current is above IUV+ and the feedback pin voltage
is above FBOFF, the IC applies a ~6 mA current sink through the
VOLTAGE MONITOR pin and checks that the FEEDBACK pin
voltage is still above the FBOFF threshold. This checks to ensure
that the FEEDBACK and V pins are not shorted together. In the
event that the FEEDBACK pin voltage is below the FBOFF
Start-Up Sequence.
threshold the V pin holds the 6 mA current sink indefinitely until
the FEEDBACK pin is above the FBOFF. If the FEEDBACK pin
voltage is above FBOFF, the IC releases the current source and
resumes with normal soft-start and operation. Figure 7
illustrates this sequence.
Timing Supervisor and Operating Frequency Range
Since the controller is expected to operate with a variable
switching frequency over the line frequency half-cycle, typically
spanning a range of 24 – 95 kHz, the controller also features a
timing supervisor function which monitors and limits the
maximum switch on-time and off-time as well as ensures a
minimum cycle off-time. The timer supervisor limits the normal
operating frequency range for loads in excess of 10% of the
device peak power rating.
Figure 8a shows the typical half-line frequency profile of the
device switching frequency as a function of input voltage at
peak load conditions. Figure 8b shows for a given line condition
the effect of EcoSmart to the switching frequency as a function
of load (PFS704-716). The switching frequency is not a function
of boost choke inductance.
EcoSmart
The PFS704-716 controllers includes an EcoSmart mode
wherein the internal error signal (VE) is used to detect the
converter output power. Since the internal error-signal is
directly proportional to the output power, this signal level is used
to set the average switching frequency as a function of output
power. The off-time integrator control reference (VOFF) is
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Rev. D 12/11
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Frequency (kHz)
100
180 VAC
135 VAC
115 VAC
90 VAC
90
80
70
60
50
40
Expected Frequency
Range at Peak
Rated Load
VIN = 115 VAC
100
30
100% Peak Load
90
PI-6218-102910
230 VAC
120
110
Frequency (kHz)
120
110
PI-6217-110110
PFS704-729EG
80
70
75% Peak Load
60
50
50% Peak Load
40
25% Peak Load
30
20
20
Peak Load
10
10
45
0
90
135
180
0
Line Conduction Angle (°C)
Figure 8.
45
90
135
180
Line Conduction Angle (°C)
(a) Frequency Variation Over Line Half-Cycle as a Function of Input Voltage (b) Frequency Variation Over Line Half-Cycle as a Function of Load.
~2.5 V
~5 V
PFS704-716
VIN > 170 VAC
PFS704-716
VIN < 140 VAC
VOFF at VE = 0 V
VOFF
~5 V
~1.25 V
PFS704-716
~2.5 V
~0.8 V
PFS723-729
~4.8 V
VE
Figure 9.
~5 V
(full power)
~140 VAC
~170 VAC
VIN
PI-5338-021711
VOFF vs. VE and VOFF vs. Input Voltage.
controlled with respect to the internal error-voltage level (output
power) to allow the converter to maintain output voltage
regulation and relatively flat conversion efficiency between 10%
to 100% of rated load which is essential to meet many efficiency
directives.
The degree of frequency slide is also controlled as a function of
peak input line voltage, at high input line the maximum off-time
voltage reference at zero error-voltage will be approximately 1/2
of the maximum value at low input line conditions.
The lower VOFF slope reduces the average frequency swing for
high input line operation.
Protection Modes
VOLTAGE MONITOR (V) Pin Shutdown
The VOLTAGE MONITOR pin features a shutdown protection
mode which can be used with the VOLTAGE MONITOR pin
resistor or external circuitry to cover system faults. During
start-up (1 V < VFB < 5.8 V) in the event the current through the
VOLTAGE MONITOR pin exceeds the IV(OFF) threshold for a
duration exceeding approximately (1 ms), the IC disables the
internal MOSFET for the entire duration that the V pin current is
above IV(OFF). In normal operation, if the current through the V
pin exceeds the IV(OFF) threshold for a duration exceeding tV(OFF),
the IC will reinitiate the start-up sequence.
Brown-In Protection (IUV+)
The VOLTAGE MONITOR pin features an input line undervoltage
detection to limit the minimum start-up voltage detected
through the V pin. This detection threshold will inhibit the
device from starting at very low input AC voltage.
Brown-Out Protection (IUV-)
The V pin features a brown-out protection mode wherein the
HiperPFS will turn-off when the V pin current is below the Line
UV-threshold for a period exceeding the tREFRESH time period. In
the event a single half-line cycle is missing (normal operating
line frequency is 47 to 63 Hz) the brown-out protection will not
be activated. The HiperPFS shutdown in effect gradually
reduces the internal error-voltage to zero volts at rate of 1 V/ms
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Rev. D 12/11
PFS704-729EG
IV < 48 µA
PFS704-716
IOCP
to decay the power MOSFET on-time to zero. At peak power
(VE ~5 V) the shutdown time will be approximately 5 ms. The
internal error-voltage is held at 0 V for as long as the input peak
voltage is below the brown-in (IUV+) threshold. The internal
error-voltage controlled slew to 0 V gradually reduces the switch
on-time to zero to deplete energy stored in the boost choke as
well as input EMI filter for power-down. Once the error-voltage
reaches zero volts the controller is effectively in an off-state
(gated by 5 ms timer) and will restart once all the conditions of
soft-start are satisfied.
IV > 59 µA
VIN
The brown-out threshold is reduced to IUV-SS during start-up until
the FEEDBACK pin exceeds approximately 5.8 V. Temporarily
reducing the brown-out threshold prevents false turn-off at high
power start-up when the voltage drop across the input bridge
rectifier and filter stage may cause the rectified input to sag
below the brown-out threshold.
Fast Output Voltage Overvoltage Protection (FBOV )
The FEEDBACK pin features a means to detect an output
overvoltage condition through the FEEDBACK pin and disables
the power MOSFET until the sensed output voltage falls below
the FBOV threshold. A deglitch filter (~2 ms) is used to prevent
the controller from falsely triggering this mode. An FBOV event in
excess of the 2 ms delay will terminate the switch cycle immediately.
This detection circuit also includes some hysteresis.
Output Voltage Undervoltage Protection (FBUV )
The FEEDBACK pin features an undervoltage detection to
detect an output overload or a broken feedback loop. If the IC
detects the falling edge on the FEEDBACK pin that has fallen
below FBUV threshold, it will turn-off the internal power MOSFET
and reinitiate the start-up sequence. Similar to the FBOV
detection, this mode has a deglitch filter of approximately 100 ms.
VCC Undervoltage Protection (UVLO)
The BIAS POWER (VCC) pin has an undervoltage lock-out
protection which inhibits the IC from starting unless the applied
VCC voltage is above the VCC+ threshold. The IC initiates a
soft-start once the VCC pin voltage exceeds the VCC+ threshold.
After start-up the IC will continue to operate until the VCC pin
voltage has fallen below VCC- level. The absolute maximum
voltage of the VCC pin is 13.4 V which must be externally limited
to prevent damage to the IC.
Over-Current Protection
The device includes a cycle-by-cycle over-current-protection
(OCP) mode which protects the device in the event of a
catastrophic fault. The OCP mode in the PFS704-716 is input
line dependent as shown in Figure 10. The intention of OCP in
this device is strictly protection of the internal power MOSFET
and is not intended to protect the converter from output
short-circuit or overload fault conditions.
The PFS704-716 controller latches the high line OCP for a 1/2
line cycle and updates the OCP status after the expiration of a
5 ms block-out timer. This feature has particular benefit for
hard-start after an AC line cycle drop where the peak detector
may falsely detect a low input line condition even though the
input is at high input line.
~140 VAC
~170 VAC
PI-5470-110810
Figure 10. Line Dependant OCP.
The leading edge blanking circuit inhibits the current limit
comparator for a short time (tLEB) after the power MOSFET is
turned on. This leading edge blanking time must be set so that
current spikes caused by capacitance and rectifier reverse
recovery time will not cause premature termination of the
MOSFET conduction.
Safe Operating Range (SOA) Mode
Since the cycle-by-cycle OCP mechanism described above
does not prevent the possibility of inductor current “staircasing”, an SOA mode is required. Rapid build up of the device
current can occur in event of inductor saturation or when the
input and output voltages are equal (non or very short
inductor reset time).
The SOA mode is triggered whenever the device reaches
current limit (IOCP) and the on-time is less than tSOA.
The SOA mode forces an off-time equal to tOCP and pulls the
internal error-voltage (VE) down to approximately 1/2 of its set
value.
Open FEEDBACK Pin Protection
The FEEDBACK pin also features a static current of IFB that is
continuously sourced out of the pin to protect against a fault
related to an open FEEDBACK pin. The internal current source
introduces a static offset to the output regulation which must be
accounted for in selecting the output feedback regulation
components.
Hysteretic Thermal Shutdown
The thermal shutdown circuitry senses the controller die
temperature. The threshold is set at 118 °C typical with a 50 °C
hysteresis. When the die temperature rises above this threshold
(118 °C +8/-7 °C), the power MOSFET switching is disabled and
remains disabled until the die temperature falls by ~50 °C, at
which point the device will reinitiate a soft-start and start-up
sequence.
8
Rev. D 12/11
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PFS704-729EG
Output Power Table1
Product
Maximum Continuous
Output Power Rating at
90 VAC2
Minimum3
Peak Output Power
Rating at 90 VAC5
Product
Maximum
Maximum Continuous
Output Power Rating at
180 VAC4
Peak Output Power
Rating at 180 VAC5
PFS704EG
85 W
110 W
120 W
PFS723EG
255 W
280 W
PFS706EG
105 W
140 W
150 W
PFS724EG
315 W
350 W
PFS708EG
140 W
190 W
205 W
PFS725EG
435 W
480 W
PFS710EG
180 W
240 W
260 W
PFS726EG
540 W
600 W
PFS712EG
225 W
300 W
320 W
PFS727EG
675 W
750 W
PFS714EG
265 W
350 W
385 W
PFS728EG
810 W
900 W
PFS716EG
295 W
388 W
425 W
PFS729EG
900 W
1000 W
Table 2. Output Power Table.
Notes:
1. See Key Application considerations.
2. Maximum practical continuous power at 90 VAC in an open-frame design with adequate heat sinking, measured at 50 °C ambient.
3. Recommended lower range of maximum continuous power for best light load efficiency; HiperPFS will operate and perform below this level.
4. Maximum practical continuous power at 180 VAC in an open-frame design with adequate heat sinking, measured at 50 °C ambient.
5. Internal output power limit.
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PFS704-729EG
Application Example
A High Efficiency, 347 W, 380 VDC Universal Input PFC
The circuit shown in Figure 11 is designed using a PFS714EG
device from the HiperPFS family of integrated PFC controllers.
This design is rated for a continuous output power of 347 W
and provides a regulated output voltage of 380 VDC nominal
maintaining a high input power factor and overall efficiency from
light load to full load.
Fuse F1 provides protection to the circuit and isolates it from the
AC supply in case of a fault. Diode bridge BR1 rectifies the AC
input. Capacitors C3, C4, C5, C6 and C19 together with
inductors L1, L2, L3 and L4 form the EMI filter reducing the
common mode and differential mode noise. Resistors R1, R3
and CAPZero, IC U2 are required to discharge the EMI filter
capacitors once the circuit is disconnected. CAPZero
eliminates static losses in R1 and R2 by only connecting these
components across the input when AC is removed.
The boost converter stage consists of inductor L5, diode rectifier
D2 and the HiperPFS IC U1. This converter stage works as a
boost converter and controls the input current of the power
supply while simultaneously regulating the output DC voltage.
Diode D1 prevents a resonant build up of output voltage at startup by bypassing inductor L5 while simultaneously charging
output capacitor C15. Thermistor RT1 limits the inrush input
current of the circuit at start-up and prevents saturation of L5.
In most high-performance designs, a relay will be used to
bypass the thermistor after start-up to improve power supply
efficiency. Therefore efficiency measurement, that represents
the high performance configuration, the thermistors should be
shorted. Capacitors C14 and C21 are used for reducing the
loop length and area of the output circuit to reduce EMI and
overshoot of voltage across the drain and source of the
MOSFET inside U1 at each switching instant.
The PFS714EG IC requires a regulated supply of 12 V for
operation and must not exceed 13.4 V. Resistors R6, R16, R17,
Zener diode VR1, and transistor Q3 form a shunt regulator that
prevents the supply voltage to IC U1 from exceeding 12 V.
Capacitors C8, C18 and C20 filter the supply voltage and
provide decoupling to ensure reliable operation of IC U1. Diode
D5 prevents destruction of U1 if the auxiliary input is inadvertently
connected reverse polarity.
The rectified AC input voltage of the power supply is sensed by
IC U1 using resistors R4, R5 and R19. The capacitor C12 filters
any noise on this signal.
Divider network comprising of resistors R9, R10, R11, R12, R13,
and R14 are used to scale the output voltage and provide
feedback to IC U1. The circuit comprising of diode D4,
transistor Q1, Q2 and the resistors R12 and R13 form a nonlinear feedback circuit which improves the load transient
response by improving the response time of the PFC circuit.
Resistor R7, R8, R15, and capacitors C13 and C17 are required
for shaping the loop response of the feedback network. The
combination of resistor R8 and capacitor C13 provide a low
frequency zero and the resistor R15 and capacitor C13 form a
low frequency pole.
D1
1N5408
L2
100 µH
F1
6.3 A
L
380 VDC
BR1
RT1 GBU806
10 Ω 600 V
L5
1.38 mH
t
O
D1
CAPZero
U2
CAP006DG
C3
680 nF
275 VAC
C4
680 pF
250 VAC
L1
14 mH
C19
1 µF
310 V
RV1
320 VAC
E
D2
R2
220 kΩ
R18
10 Ω
2W
C6
100 nF
275 VAC
R4
1.5 MΩ
1%
R9
1.5 MΩ
1%
R19
1.5 MΩ
1%
R11
732 kΩ
1%
R5
1 MΩ
1%
R10
1.6 MΩ
1%
C16
100 nF
200 V
C5
680 pF
250 VAC
N
L3
100 µH
L4
Ferrite Bead
R6
100 Ω
+
R16
100 Ω
*Optional Component
D5
DL4001
D
VR1
BZX84C12LT1G
C8
47 µF
50 V
C14
10 nF
1 kV
C15
270 µF DC
450 V OUT
Q1
MMBT4401
R17
3.01 kΩ
1%
Auxiliary
Power
Supply
C21
10 nF
1 kV
D4
1N4148
Q3
MMBT4401LT1G
C20
100 nF
50 V
S
C12
100 nF
50 V
VCC
CONTROL
HiperPFS
U1
PFS714EG
C7
1 µF
400 V
V
FB
D3
BAV116
130 V
G
C11
10 nF
50 V
R15
160 kΩ
R7
2 kΩ
C18
1 µF
25 V
R8
3.01 kΩ
1%
C13
4.7 µF
25 V
Q2
MMBT4403
R1
220 kΩ
+
D2
STTH8S06D
R13
2.21 kΩ
1%
R14
57.6 kΩ
1%
R12
2.21 kΩ
1%
C17
470 pF
100 V
PI-6197-111110
Figure 11. 347 W PFC using PFS714EG.
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PFS704-729EG
D1
1N5408
L2
100 µH
F1
3.15 A
BR1
3KBP06M
600 V
RT1
10 Ω
L
L5
1.7 mH
t
O
R1
750 kΩ
D1
C3
220 nF
275 VAC
L1
10 mH
CAPZero
U2
CAP002DG
C19
220 nF
275 VAC
RV1
320 VAC
E
C4
100 pF
250 VAC
+
D2
STTH3R06U
R4
1.5 MΩ
1%
R9
1.5 MΩ
1%
R19
1.5 MΩ
1%
R11
732 kΩ
1%
R5
1 MΩ
1%
R10
1.6 MΩ
1%
C16
100 nF
200 V
C5
100 pF
250 VAC
D2
R2
750 kΩ
N
C14
10 nF
1 kV
C15
150 µF DC
450 V OUT
D4
1N4148
+
Q1
MMBT4401
12 V
Auxiliary
Power
Supply
C20
47 µF
25 V
VCC
CONTROL
HiperPFS
U1
PFS708EG
C7
470 nF
400 V
V
S
FB
D3
BAV116
130 V
G
C12
100 nF
50 V
C11
10 nF
50 V
R15
160 kΩ
R7
2 kΩ
C18
1 µF
25 V
R8
3.01 kΩ
1%
C13
4.7 µF
25 V
Q2
MMBT4403
D
R13
2.21 kΩ
1%
R14
57.6 kΩ
1%
R12
2.21 kΩ
1%
C17
470 pF
100 V
PI-6229-110210
Figure 12. 180 W PFC using PFS708EG.
D1
1N5408
L2
100 µH
F1
8A
BR1
GBU10J
600 V
RT1
10 Ω
L
L5
2.04 mH
t
O
D1
CAPZero
U2
CAP006DG
C3
680 nF
275 VAC
L1
14 mH
C19
1 µF
275 VAC
RV1
320 VAC
E
D2
R2
220 kΩ
R18
10 Ω
2W
C4
680 pF
250 VAC
C6
100 nF
275 VAC
R4
3 MΩ
1%
R9
1.5 MΩ
1%
R19
3 MΩ
1%
R11
732 kΩ
1%
R5
3 MΩ
1%
R10
1.6 MΩ
1%
C16
100 nF
200 V
C5
680 pF
250 VAC
N
L3
100 µH
L4
Ferrite Bead
R6
100 Ω
+
R16
100 Ω
D5
DL4001
D
VR1
BZX84C12LT1G
C8
47 µF
50 V
C14
10 nF
1 kV
C15
820 µF DC
450 V OUT
Q1
MMBT4401
R17
3.01 kΩ
1%
15 V
Auxiliary
Power
Supply
C21
10 nF
1 kV
D4
1N4148
Q3
MMBT4401LT1G
C20
100 nF
25 V
S
C12
47 nF
50 V
VCC
CONTROL
HiperPFS
U1
PFS729EG
C7
1.5 µF
400 V
V
FB
D3
BAV116
130 V
G
C11
10 nF
50 V
R15
160 kΩ
R7
2 kΩ
C18
1 µF
25 V
R8
3.01 kΩ
1%
C13
4.7 µF
25 V
Q2
MMBT4403
R1
220 kΩ
+
D2
STTH12R06
R13
2.21 kΩ
1%
R14
57.6 kΩ
1%
R12
2.21 kΩ
1%
C17
470 pF
100 V
PI-6230-111110
Figure 13. 900 W PFC using PFS729EG.
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PFS704-729EG
Design, Assembly, and Layout Considerations
Power Table
The data sheet power table as shown in Table 2 represents the
maximum practical continuous output power based on the
following conditions:
For the universal input devices (PFS704-716):
1. An input voltage range of 90 VAC to 264 VAC
2. Overall efficiency of at least 93% at the lowest operating
voltage
3. Use of ultrafast recovery diode or high performance diode for
PFC output.
4. Sufficient heat sinking to keep device temperature ≤100 ºC
5. 380 V to 385 V nominal output
For the 230 V only devices (PFS723-729):
1. An input voltage range of 180 VAC to 264 VAC
2. Overall efficiency of at least 96% at the lowest operating
voltage
3. Use of ultrafast recovery diode or high performance diode
for PFC output.
4. Sufficient heat sinking to keep device temperature ≤100 ºC
5. 380 V to 385 V nominal output
Operation beyond the limits stated above will require derating.
Use of a nominal output voltage higher than 390 V is not
recommended for HiperPFS based designs. Operation at
voltages higher than 390 V can result in higher than expected
drain-source voltage during line and load transients.
HiperPFS Selection
Selection of the optimum HiperPFS part depends on required
maximum output power, PFC efficiency and overall system
efficiency (when used with a second stage DC-DC converter),
heat sinking constraints, system requirements and cost goals.
The HiperPFS part used in a design can be easily replaced with
the next higher or lower part in the power table to optimize
performance, improve efficiency or for applications where there
are thermal design constraints. Minor adjustments to the
inductance value and EMI filter components may be necessary
in some designs when the next higher or the next lower
HiperPFS part is used in an existing design for performance
optimization.
Every HiperPFS family part has an optimal load level where it
offers the most value. Operating frequency of a part will change
depending on load level. Change of frequency will result in
change in peak to peak current ripple in the inductance used.
Change in current ripple will affect input PF and total harmonic
distortion of input current.
peak of the applied voltage. The charging current is only limited
by any inrush limiting thermistors, impedance of the EMI filter
inductors and the forward resistance of the input rectifier
diodes.
A MOV will typically be required to protect the PFC from line
surges. Selection of the MOV rating will depend on the energy
level (EN1000-4-5 Class level) to which the PFC is required to
withstand.
Input EMI Filter
The variable switching frequency of the HiperPFS effectively
modulates the switching frequency and reduces conducted EMI
peaks associated with the harmonics of the fundamental
switching frequency. This is particularly beneficial for the
average detection mode used in EMI measurements.
The PFC is a switching converter and will need an EMI filter at
the input in order to meet the requirements of most safety
agency standards for conducted and radiated EMI. Typically a
common mode filter with X capacitors connected across the
line will provide the required attenuation of high frequency
components of input current to an acceptable level. The
leakage reactance of the common mode filter inductor and the
X capacitors form a low pass filter. In some designs, additional
differential filter inductors may have to be used to supplement
the differential inductance of the common mode choke.
A filter capacitor with low ESR and high ripple current capability
should be connected at the output of the input bridge rectifier.
This capacitor reduces the generation of the switching frequency
components of the input current ripple and simplifies EMI filter
design. Typically, 0.33 mF per 100 W should be used for
universal input designs and 0.15 mF per 100 W of output power
should be used for 230 VAC only designs.
It is often possible to use a higher value of capacitance after the
bridge rectifier and reduce the X capacitance in the EMI filter.
Regulatory requirements require use of a discharge resistor to
be connected across the input (X) capacitance on the AC side
of the bridge rectifier. This is to ensure that residual charge is
dissipated after the input voltage is removed when the
capacitance is higher than 0.1 mF. Use of CAPZero integrated
circuits from Power Integrations, helps eliminate the steady
state losses associated with the use of discharge resistors
connected permanently across the X capacitors.
Input Fuse and Protection Circuit
The input fuse should be rated for a continuous current above
the input current at which the PFC turns-off due to input under
voltage. This voltage is referred to as the brown-out voltage.
Inductor Design
It is recommended that the inductor be designed with the
maximum operating flux density less than 0.3 T and a peak flux
density less than 0.42 T at maximum current limit when a ferrite
core is used. If a core made from Sendust or MPP is used, the
flux density should not exceed 1 T. A powder core inductor will
have a significant drop in inductance when the flux density
approaches 1 T.
The fuse should also have sufficient I2t rating in order to avoid
nuisance failures during start-up. At start a large current is
drawn from the input as the output capacitor charges to the
For high-line only designs, the value of KP (the ratio of peak to
ripple current) of the drain current at the peak of the input
voltage waveform should be kept below 0.5 for ferrite core and
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PFS704-729EG
0.675 for powder core designs respectively. For universal input
designs, KP should be kept below 0.25 for ferrite core and 0.625
for powder core respectively. For high performance designs,
use of Litz wire is recommended to reduce copper loss due to
skin effect and proximity effect. For toroidal inductors the
numbers of layers should be less than 3 and for bobbin wound
inductors, inter layer insulation should be used to minimize inter
layer capacitance.
Output Diode
For a 385 V nominal PFC output voltage, use of a diode with
600 V or higher PIV rating is recommended. CCM operation
with hard switching demands that diodes with low reverse
recovery time and reverse recovery charge should be used. The
variable frequency CCM operation of HiperPFS reduces diode
switching losses as compared to fixed frequency solutions and
enables use of easily available high frequency diodes such as
the Turbo-2 series from STMicroelectronics. Diodes with soft
recovery characteristics that result in a reduced EMI are available
from a number of manufacturers. For highly demanding
applications such as 80 PLUS Gold power supplies, use of
Silicon Carbide diodes may be considered. These uses will
typically provide further full load improvement in efficiency.
The diodes will be required to have a forward continuous current
rating of at least 1.2 A to 1.5 A for every 100 W of output power.
Output Capacitor
For a 385 V nominal PFC, use of a electrolytic capacitor with
450 V or higher continuous rating is recommended. The
capacitance required is dependent on the acceptable level of
output ripple and any hold up time requirements. The equations
below provide an easy way to determine the required capacitance
in order to meet the hold up time requirement and also to meet
the output ripple requirements. The higher of the two values
would be required to be used:
Capacitance required for meeting the hold up requirement is
calculated using the equation:
CO =
CO
PO
tHOLD-UP
VOUT
VOUT(MIN)
2 # POUT # tHOLD_UP
VOUT2 - VOUT(MIN)2
PFC output capacitance in F.
PFC output power in watts.
Hold-up time specification for the power supply in seconds.
Lowest nominal output voltage of the PFC in volts.
Lowest permissible output voltage of the PFC at the end of hold-up time in volts.
Capacitance required for meeting the low frequency ripple
specification is calculated using the equation:
CO =
fL
ΔVO
ηPFC
IO(MAX)
IO(MAX)
2 # r # fL # DVO # hPFC
Input frequency in Hz
Peak-peak output voltage ripple in volts
PFC operating efficiency
Maximum output current in amps
Capacitance calculated using the above method should be
appropriately increased to account for ageing and tolerances.
Power Supply for the IC
A 12 V regulated supply should be used for the HiperPFS. If the
VCC exceeds 13.4 V, the HiperPFS may be damaged. In most
applications a simple series pass linear regulator made using an
NPN transistor and Zener diode is adequate since the HiperPFS
only requires approximately 3.4 mA maximum for its operation.
It is recommended that a 1 mF or higher, low ESR ceramic
capacitor be used to decouple the VCC supply. This capacitor
should be placed directly at the IC on the circuit board.
Line-Sense Network
The line-sense network connected to the V pin provides input
voltage information to the HiperPFS. The value of this resistance
sets the brown-in and brown-out threshold for the part. A value
of 4 MW is recommended for use with the universal input parts
and a value of 9 MW is recommended for the 230 VAC only
parts. Only 1% tolerance resistors are recommended. This
resistance value may be modified to adjust the brown-in
threshold if required however change of this value will affect the
maximum power delivered by the part.
A decoupling capacitor of 0.1 mF is required to be connected
from the VOLTAGE MONITOR pin to the GROUND pin of the
HiperPFS for the universal input parts and a decoupling
capacitor of 0.047 mF is required for the 230 VAC only parts.
This capacitor should be placed directly at the part on the
circuit board.
Feedback Network
A resistor divider network that provides 6 V at the feedback pin
at the rated output voltage should be used. The compensation
elements are included with the feedback divider network since
the HiperPFS does not have a separate pin for compensation.
The HiperPFS based PFC has two loops in its feedback. It has
an inner current loop and a low bandwidth outer voltage loop
which ensures high input power factor. The compensation RC
circuit included with the feedback network reduces the response
time of the HiperPFS to fast changes in output voltage resulting
from transient loads. The feedback circuit recommended for
use with the HiperPFS includes a pair of transistors that are
biased in a way that the transistors are in cutoff during normal
operation. When a rapid change occurs in the output voltage,
these transistors conduct momentarily to correct the feedback
pin voltage rapidly thereby helping the HiperPFS to respond to
the changes in output voltage without the delay associated with
a low bandwidth feedback loop.
The recommended circuit and the associated component
values are shown in Figure 14.
Resistors, R1 to R5 comprise of the main output voltage divider
network. The sum of resistors R1, R2 and R3 is the upper
divider resistor and the lower feedback resistor is comprised of
the sum of resistors R4 and R5. Capacitor C1 is a soft-finish
capacitor that reduces output voltage overshoot at start-up.
Resistor R8 and capacitor C3 form a low pass filter to filter any
switching noise from coupling into the FEEDBACK pin. Resistor
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PFS704-729EG
When the above component values are used, the value of
resistor R1 can be calculated using the equation below:
B+
VCC
R1
R1 =
D2
C1
R2
Q1
D
V
VCC
CONTROL
HiperPFS
S
FB
G
D1
R3
R6
R8
R7
R4
Since the total voltage across resistor R1 is approximately
301 V, resistor R1 may have to be divided into two or more
resistors to distribute the voltage stress below the voltage
ratings of the resistor used.
The value of resistor R7 will have to be adjusted in some
designs and as a guideline the value from the following
calculation can be used:
R7 = R Z =
Q2
C3
C2
VO - 79
100 # 10 - 6
R5
PI-6228-111110
Figure 14. Recommended Feedback Circuit.
R7 and capacitor C2 is the loop compensation network which
introduces a low frequency zero required to tailor the loop
response to ensure low cross-over frequency and sufficient
phase margin. Resistor R6 isolates the fast portion (resistor
voltage divider network comprising of resistors R1 to R5) and
the slow feedback loop compensator circuit (resistor R7 and
capacitor C2). Transistors Q1 and Q2, biased with resistors R3
and R4 respectively, detect output voltage transient conditions
and provide the FEEDBACK pin with “fast” information to
increase the loop response of the system. Diode D1 is included
to cover a single point fault condition wherein capacitor C2 is
shorted. In the event C2 is short-circuited, the FEEDBACK pin
is forced below the FBOFF threshold through diode D1 and
subsequently turns the HiperPFS off. Only a standard recovery
diode should be used for D1. Use of ultrafast or fast recovery
diode is not recommended including small signal diodes (e.g.
1N4148) which are typically also fast recovery.
The recommended values for the components used are as
follows:
R5 = 57.6 kΩ
R3, R4 = 2.2 kΩ
R2 = 732 kΩ
C1 = 0.1 mF, 100 V X7R/NPO
R6 = 160 kΩ
R7 = 3 kΩ
R8 = 2 kΩ
C2 = 4.7 mF
C3 = 10 nF (For layouts that result in excessive noise on the
feedback signal, a 20 nF capacitor may be used).
D1 = BAV116 W or 1N4007 (A general purpose standard
recovery diode should only be used).
Q1, Q2 = Small signal transistors equivalent to 2N4401 and
2N4403.
PO
VO
CO
PO
^ kX h
4 # VO2 # CO
Maximum continuous output power in watts
Nominal PFC output voltage in volts
PFC output capacitance in farads
Improvement in low frequency phase margin can be achieved by
increasing the value of the capacitor C2 however increase in value
of capacitor C2 will result in some increase in overshoot at the
output of the PFC during transient loading and should be verified.
Diode D2 connected in series with the collector of the NPN
transistor Q1 is to prevent loading of the feedback circuit when
the VCC is absent. Presence of this diode ensures that there is
no start-up delay when the VCC is applied to the HiperPFS, the
feedback circuit, and transistor.
Heat Sinking and Thermal Design
The exposed pad on the HiperPFS eSIP package is internally
connected to the drain of the MOSFET. Due to the significant
amount of power dissipated in the part, the HiperPFS should be
mounted on a rectangular heat spreader made of thermally
conductive material such as Aluminum or Copper. Figure 15
shows an example of the recommended assembly for the
HiperPFS. In this assembly shown, a 0.76 mm thick aluminum
heat spreader is used. A thermally conductive sil pad should be
used to separate the heat spreader from the heat sink. A thin
film of thermally conductive silicone grease should be applied to
the rear surface of the HiperPFS to ensure low thermal
resistance contact between the package of the HiperPFS and
the heat spreader.
For universal input applications up to 150 W and 230 VAC only
applications up to 300 W, the heat spreader is not essential.
Use of heat spreader in these applications will help reduce
temperature of the part and heat spreaders can be used if
necessary. Figure 17 shows an example of the recommended
assembly for lower power designs that do not need a heat
spreader.
The HiperPFS is electrically connected to the heat spreader and
the heat sink is required to be connected to the source in order
to reduce EMI. The voltage between the heat spreader and
heat sink can easily exceed 400 V during transient conditions.
Attention should be placed on creepage and clearance based
on applicable safety specification.
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PFS704-729EG
1.SCREW
2. SHOULDER WASHER
3. EDGE CLIP
4.HiperPFS
5. THERMALLY CONDUCTIVE
SILICONE GREASE
6. FIBER WASHER
7. CUSTOM ALUMINUM
HEATSPREADER
8. KAPTON SILPAD INSULATOR
TO-247
9. HEAT SINK
10. FLAT WASHER
11. LOCK WASHER
12.NUT
Figure 15. Heat Sink Assembly Example – High Power Designs.
Figure 16. Heat Sink Assembly – High Power Designs.
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1.SCREW
2. EDGE CLIP
3.HiperPFS
4. KAPTON SILPAD
INSULATOR
5. HEAT SINK
6. FLAT WASHER
7. LOCK WASHER
8.NUT
Figure 17. Heat Sink Assembly Example – Low Power Designs.
Figure 18. Heat Sink Assembly – Low Power Designs.
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PFS704-729EG
PCB Design Guidelines and Design Example
The line-sense network and the feedback circuit use large
resistance values in order to minimize power dissipation in the
feedback network and the line-sense network. Care should be
taken to place the feedback circuit and the line-sense network
components away from the high voltage and high current nodes
to minimize any interference. Any noise injected in the feedback
network or the line-sense network will typically manifest as
degradation of power factor. Excessive noise injection can lead
to waveform instability or dissymmetry.
The EMI filter components should be clustered together to
improve filter effectiveness. The placement of the EMI filter
components on the circuit board should be such that the input
circuit is located away from the drain node of the HiperPFS, the
output diode of the PFC or the PFC inductor.
A filter or decoupling capacitor should be placed at the output
of the bridge rectifier. This capacitor together with the
X capacitance in the EMI filter and the differential inductance of
the EMI filter section and the source impedance, works as a
filter to reduce the switching frequency current ripple in the
input current. This capacitor also helps to minimize the loop
area of the switching frequency current loop thereby reducing
EMI.
The connection between the HiperPFS drain node, output
diode drain terminal and the PFC inductor should be kept as
small as possible.
A low loss ceramic dielectric capacitor should be connected
between the cathode of the PFC output diode and the source
terminal of the HiperPFS. This ensures that the loop area of the
loop carrying high frequency currents at the transition of
switch-off of the MOSFET small and helps to reduce radiated
EMI due to high frequency pulsating nature of the diode current
traversing through the loop.
During placement of components on the board, it is best to
place the VOLTAGE MONITOR pin, FEEDBACK pin and VCC
pin decoupling capacitors close to the HiperPFS before the
other components are placed and routed. Power supply return
trace from the GROUND pin should be separate from the trace
connecting the feedback circuit components to the GROUND pin.
PFC Output
Capacitor
PFC
Output
Second Stage
Converter
HiperPFS
PFC
Inductor
Auxiliary Supply for PFC –
from Standby Power Supply
Input
Capacitor
(CIN)
Bridge
Rectifier
Thermistor
Shorting Relay
EMI Filter
AC Input
PI-6238-012611
Figure 19. PCB Layout Example for System Power Supply consisting of a PFC and a Second Stage Converter.
17
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Rev. D 12/11
PFS704-729EG
To minimize effect of trace impedance affecting regulation,
output feedback should be taken directly from the output
capacitor positive terminal. The upper end of the line-sense
resistors should be connected to the high frequency filter
capacitor connected at the output of the bridge rectifier.
Quick Design Checklist
As with any power supply design, all HiperPFS designs should
be verified on the bench to make sure that component
specifications are not exceeded under worst-case conditions.
The following minimum set of tests is strongly recommended:
1. Maximum drain voltage – verify that peak VDS does not
exceed 530 V at lowest input voltage and maximum overload
output power. Maximum overload output power occurs
when the output is overloaded to a level just above the
highest rated load or before the power supply output voltage
starts falling out of regulation. Additional external snubbers
should be used if this voltage is exceeded. In most designs,
addition of a ceramic capacitor in the range of 33 pF and
100 pF connected across the PFC output diode will reduce
the maximum drain-source voltage to a level below the BVDSS
rating. When measuring drain-source voltage of the MOSFET,
a high voltage probe should be used. When the probe tip is
removed, a silver ring in the vicinity of the probe tip can be
seen. This ring is at ground potential and the best ground
connection point for making noise free measurements.
Wrapping stiff wire around the ground ring and then
connecting that ground wire into the circuit with the shortest
possible wire length, and connecting the probe tip to the
point being measured, ensures error free measurement.
2. Maximum drain current – at maximum ambient temperature,
minimum input voltage and maximum output load, verify
drain current waveforms at start-up for any signs of inductor
saturation and excessive leading edge current spikes.
HiperPFS has a leading edge blanking time of 220 ns to
prevent premature termination of the ON-cycle. Verify that
the leading edge current spike is below the allowed current
limit for the drain current waveform at the end of the 220 ns
blanking period. If a wire loop is inserted in series with the
drain, it forms a small stray inductance in series with the
drain. This stray inductance will add to the leading edge
voltage spike on the drain source waveform. The drainsource voltage waveform should therefore never be measured
with this loop. An alternate measurement that can provide
drain current level and information regarding slope of the
inductor current can be obtained by monitoring the inductor
current instead. A wire loop can be added in series with the
PFC inductor connection that connects the inductor to the
input rectifier for the purpose of measurement.
3. Thermal check – at maximum output power, minimum input
voltage and maximum ambient temperature; verify that
temperature specifications are not exceeded for the HiperPFS,
PFC inductor, output diodes and output capacitors. Enough
thermal margin should be allowed for the part-to-part
variation of the RDS(ON) of HiperPFS, as specified in the data
sheet. A maximum package temperature of 100 °C is
recommended to allow for these variations.
4. Input PF should improve with load, if performance is found to
progressively deteriorate with loading then that is a sign of
possible noise pickup by the VOLTAGE MONITOR pin circuit
or the feedback divider network and the compensation
circuit.
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Rev. D 12/11
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PFS704-729EG
Absolute Maximum Ratings
DRAIN Pin Peak Current: PFS704 ............................................7.5 A
PFS706.......................................9.0 A
PFS708..................................... 11.3 A
PFS710.....................................13.5 A
PFS712.....................................15.8 A
PFS714.....................................18.0 A
PFS716.....................................21.0 A
PFS723.......................................7.5 A
PFS724.......................................9.0 A
PFS725..................................... 11.3 A
PFS726.....................................13.5 A
PFS727.....................................15.8 A
PFS728.....................................18.0 A
PFS729.....................................21.0 A
DRAIN Pin Voltage .....................................................-0.3 V to 530 V
VCC Pin Voltage ................................................... -0.3 V to 13.4 V
VCC Pin Current............................................................... 25 mA
VOLTAGE MONITOR Pin Voltage ................................-0.3 V to 9 V
FEEDBACK Pin Voltage........................................... -0.3 V to 9 V
Storage Temperature ............................................ -65 °C to 150 °C
Operating Junction Temperature(2).....................-40 °C to 150 °C
Lead Temperature(3) .........................................................260 °C
Notes:
1. All voltages referenced to SOURCE, TA = 25 °C.
2. Normally limited by internal circuitry.
3. 1/16 in. from case for 5 seconds.
Thermal Resistance
Thermal Resistance: e Package:
(qJA)(1) ....................................................103 °C/W
(qJC).................................................. (see Figure 20)
Notes:
1. MOSFET only – controller junction temperature (TC) may be less than the power MOSFET junction temperature (TM).
Symbol
Conditions
SOURCE = 0 V; TC = -40 °C to 125 °C
(Note D) (Unless Otherwise Specified)
Min
Typ
Max
Maximum Operating
ON-time
tON(MAX)
0 °C < TC < 100 °C
30
40
50
Minimum Operating
ON-time
tON(MIN)
See Note A
0 °C < TC < 100 °C
0
Maximum Operating
OFF-time
tOFF(MAX)
0 °C < TC < 100 °C
30
Minimum Operating
OFF-time
tOFF(MIN)
0 °C < TC < 100 °C
1
Internal Feedback
Voltage Reference
VREF
TC = 25 °C
See Note A
5.955
6.00
6.045
V
FEEDBACK Pin
Voltage
VFB
0 °C < TC < 100 °C
(In Regulation)
5.82
6.00
6.18
V
FEEDBACK Pin
Current
IFB
TC = 25 °C
340
500
640
nA
Soft-Start Time
tSOFT
TC = 25 °C
12
Internal Compensation
Frequency
fCOMP
See Note A
Pole (fp)
1
kHz
Av
See Note A
100
-
Parameter
Units
Control Functions
Error-Amplifier Gain
1
ms
40
50
3
ms
19
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Rev. D 12/11
PFS704-729EG
Parameter
Symbol
Conditions
SOURCE = 0 V; TC = -40 °C to 125 °C
(Note D) (Unless Otherwise Specified)
Min
Typ
Max
Units
27.50
28.88
mA
Line-Sense/Peak Detector
Brown-In
Threshold Current
IUV+
0 °C < TC < 100 °C
Brown-Out
Threshold Current
IUV-
0 °C < TC < 100 °C
22.52
IUV(HYST)
TC = 25 °C
1
Soft-Start Brown-Out
Threshold Current
IUV-SS
TC = 25 °C
20.5
VOLTAGE MONITOR
Pin Voltage Threshold
VV(THR)
0 °C < TC < 100 °C
IV = IUV+
2.3
V
VOLTAGE MONITOR
Pin Short-Circuit
Current
IV(SC)
0 °C < TC < 100 °C
VV = 6 V
350
mA
VOLTAGE MONITOR
Pin Pre-Soft-Start
Current
IV(SS)
0 °C < TC < 100 °C
VV = 3 V
6
mA
Maximum Line Sample
Refresh Period
TREFRESH
TC = 25 °C
VOLTAGE MONITOR
Pin Shutdown Current
Threshold
IV(OFF)
0 °C < TC < 100 °C
VOLTAGE MONITOR
Pin Shutdown Delay
tV(OFF)
TC = 25 °C
Brown-In/Out
Hysteresis
24.50
22.5
30
mA
5.5
mA
24.5
mA
60
200
65
110
ms
mA
135
ms
20
Rev. D 12/11
www.powerint.com
PFS704-729EG
Parameter
Symbol
Conditions
SOURCE = 0 V; TC = -40 °C to 125 °C
(Note D) (Unless Otherwise Specified)
Min
Typ
Max
Units
Current Limit/Circuit Protection
Over-Current
Protection
IOCP
PFS704
di/dt = 250 mA/ms
TC = 25 °C
IV < 48 mA
3.8
4.1
4.3
IV > 59 mA
2.5
2.7
2.8
PFS706
di/dt = 300 mA/ms
TC = 25 °C
IV < 48 mA
4.5
4.8
5.1
IV > 59 mA
3.0
3.2
3.4
PFS708
di/dt = 400 mA/ms
TC = 25 °C
IV < 48 mA
5.5
5.9
6.2
IV > 59 mA
3.7
4.0
4.2
PFS710
di/dt = 500 mA/ms
TC = 25 °C
IV < 48 mA
6.8
7.2
7.5
IV > 59 mA
4.6
4.9
5.1
PFS712
di/dt = 650 mA/ms
TC = 25 °C
IV < 48 mA
8.0
8.4
8.8
IV > 59 mA
5.4
5.7
6.0
PFS714
di/dt = 800 mA/ms
TC = 25 °C
IV < 48 mA
9.0
9.5
9.9
IV > 59 mA
6.0
6.3
6.6
PFS716
di/dt = 920 mA/ms
TC = 25 °C
IV < 48 mA
9.5
10.0
10.5
IV > 59 mA
6.3
6.7
7.0
A
PFS723
di/dt = 250 mA/ms
TC = 25 °C
3.8
4.1
4.3
PFS724
di/dt = 300 mA/ms
TC = 25 °C
4.5
4.8
5.1
PFS725
di/dt = 400 mA/ms
TC = 25 °C
5.5
5.9
6.2
PFS726
di/dt = 500 mA/ms
TC = 25 °C
6.8
7.2
7.5
PFS727
di/dt = 650 mA/ms
TC = 25 °C
8.0
8.4
8.8
PFS728
di/dt = 800 mA/ms
TC = 25 °C
9.0
9.5
9.9
PFS729
di/dt = 920 mA/ms
TC = 25 °C
9.7
10.2
10.7
21
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Rev. D 12/11
PFS704-729EG
Parameter
Symbol
Conditions
SOURCE = 0 V; TC = -40 °C to 125 °C
(Note D) (Unless Otherwise Specified)
Min
Typ
Max
Units
200
280
360
ms
1
ms
Current Limit/Circuit Protection (cont.)
SOA Protection
Time-out
tOCP
TC = 25 °C
SOA On-time
tSOA
See Note A
Leading Edge
Blanking Time
tLEB
See Note A
220
ns
Current Limit Delay
tIL(D)
See Note A
100
ns
tLEB + tIL(D) +
tDRIVER
TC = 25 °C
370
470
570
ns
Thermal Shutdown
Temperature
TSHUT
See Note A
111
118
126
°C
Thermal Shutdown
Hysteresis
THYST
See Note A
FEEDBACK Pin
Undervoltage
FBUV
TC = 25 °C
3
3.5
4
V
FEEDBACK Pin
Undervoltage Delay
tFB(UV)
TC = 25 °C
65
110
135
ms
0 °C < TC < 100 °C
Threshold
VFB
+40 mV
VFB
+90 mV
VFB
+160 mV
V
LEB + ILD + Driver Delay
50
°C
FEEDBACK Pin
Overvoltage Threshold
and Hysteresis
FBOV
FEEDBACK Pin
Overvoltage Delay
tFB(OV)
TC = 25 °C
1
2
3
ms
FEEDBACK Pin
Start-Up Threshold
FBOFF
0 °C < TC < 100 °C
0.5
1.2
1.65
V
FEEDBACK Pin
OFF Delay
tFB(OFF)
0 °C < TC < 100 °C
0.5
2
4
ms
Start-Up VCC
(Rising Edge)
VCC+
TC = 25 °C
9.5
10.2
V
Shutdown VCC
(Falling Edge)
VCC-
TC = 25 °C
9.0
9.5
V
VCC Hysteresis
VCC(HYST)
TC = 25 °C
0.2
0.8
V
ICD1
0 °C < TC < 100 °C
Switching
3.5
ICD2
0 °C < TC < 100 °C
Not Switching
1.5
VCC Power-Up
Reset Threshold
VCC(POR)
TC = 25 °C
VCC Power-Up
Reset Current
IVCC(POR)
TC = 25 °C
Supply Current
Characteristics
0 °C < TC < 100 °C
Hysteresis
75
0.5
mV
mA
2.85
3.6
4.25
V
1.5
mA
22
Rev. D 12/11
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PFS704-729EG
Parameter
Symbol
Conditions
SOURCE = 0 V; TC = -40 °C to 125 °C
(Note D) (Unless Otherwise Specified)
Min
Typ
Max
0.61
0.72
Units
Power MOSFET
TM = 25 °C
PFS704
TM = 100 °C
TM = 25 °C
PFS706
TM = 25 °C
TM = 25 °C
TM = 25 °C
TM = 25 °C
TM = 25 °C
ID = IOCP × 0.5
See Note E
PFS724
PFS725
PFS726
PFS727
PFS728
PFS729
0.35
0.30
0.26
0.22
0.58
0.49
0.39
0.33
TM = 100 °C
0.46
0.39
0.62
0.28
0.33
0.52
0.25
TM = 100 °C
TM = 25 °C
0.58
0.73
TM = 100 °C
TM = 25 °C
W
0.92
TM = 100 °C
TM = 25 °C
0.69
1.10
TM = 100 °C
TM = 25 °C
0.26
0.42
TM = 100 °C
TM = 25 °C
0.31
0.48
TM = 100 °C
TM = 25 °C
0.35
0.55
TM = 100 °C
TM = 25 °C
0.41
0.65
TM = 100 °C
PFS716
0.48
0.77
TM = 100 °C
PFS714
PFS723
0.41
TM = 100 °C
PFS712
0.61
0.97
TM = 100 °C
PFS710
RDS(ON)
0.52
TM = 100 °C
PFS708
ON-State Resistance
1.16
0.29
0.46
0.21
0.25
0.40
23
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Rev. D 12/11
PFS704-729EG
Parameter
Symbol
Conditions
SOURCE = 0 V; TC = -40 °C to 125 °C
(Note D) (Unless Otherwise Specified)
Min
Typ
Max
Units
Power MOSFET (cont.)
Effective Output
Capacitance
COSS
Breakdown Voltage
BVDSS
Breakdown Voltage
Temperature
Coefficient
BVDSS(TC)
TC = 25 °C,
VGS = 0 V,
VDS = 0 to 80%
VDSS
See Note A
PFS704
176
PFS706
210
PFS708
265
PFS710
312
PFS712
320
PFS714
420
PFS716
487
PFS723
185
PFS724
221
PFS725
278
PFS726
328
PFS727
389
PFS728
441
PFS729
511
TM = 25 °C, VCC = 12 V
ID = 250 mA, VFB = VV = 0 V
530
pF
V
0.048
%/°C
24
Rev. D 12/11
www.powerint.com
PFS704-729EG
Parameter
Symbol
Conditions
SOURCE = 0 V; TC = -40 °C to 125 °C
(Note D) (Unless Otherwise Specified)
Min
Typ
Max
Units
Power MOSFET (cont.)
OFF-State Drain
Current Leakage
IDSS
Turn-Off Voltage
Rise Time
tR
Turn-On Voltage
Fall Time
tF
Start-up Time Delay
TM = 100 °C
VDS = 80% BVDSS
VCC = 12 V
VFB = VV = 0
PFS704
80
PFS706
100
PFS708
120
PFS710
150
PFS712
170
PFS714
200
PFS716
235
PFS723
84
PFS724
105
PFS725
126
PFS726
158
PFS727
179
PFS728
210
PFS729
247
50
See Note A, B, C
tSTART-DELAY
mA
ns
100
0 °C < TC < 100 °C
See Note A, B, C
2
6
10
ms
NOTES:
A. Not a tested parameter. Guaranteed by design.
B. Tested in typical boost PFC application circuit with 0.1 mF capacitor between the V pin and G pin and a 4 MW resistor from
rectified line to the V pin for PFS70x and PFS71x.
C. Tested in typical boost PFC application circuit with 0.047 mF capacitor between the V pin and G pin and a 9 MW resistor from
rectified line to the V pin for PFS72x.
D. Normally limited by internal circuitry.
E. Refer to IOCP with IV <48 mA for PFS704-716.
25
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Rev. D 12/11
PFS704-729EG
Typical Performance Characteristics
PI-6234-110510
Thermal Resistance θJC (°C/W)
3
2.5
2
1.5
1
0.5
0
0
PFS704
PFS723
PFS706
PFS724
PFS708
PFS725
PFS710
PFS726
PFS712
PFS727
PFS714
PFS728
PFS716
PFS729
7
PI-6239-111010
VOLTAGE MONITOR Pin Voltage (V)
Figure 20. Thermal Resistance (θJC ).
6
5
4
3
2
1
0
0
50
100
150
200
250
300
VOLTAGE MONITOR Pin Current (µA)
Figure 21. Typical Characteristic: VOLTAGE MONITOR Pin Voltage vs. Current.
PI-6240-110810
FEEDBACK Pin Current (µA)
20
15
10
5
0
-5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FEEDBACK Pin Voltage (V)
Figure 22. Typical Characteristic: FEEDBACK Pin Current vs. Voltage.
26
Rev. D 12/11
www.powerint.com
PFS704-729EG
Typical Performance Characteristics (cont.)
PI-6241-111010
VCC Pin Current (mA)
1.2
1
0.8
0.6
0.4
0.2
-5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC Pin Voltage (V)
Figure 23. Typical Characteristic: VCC Pin Current vs. Voltage (Device not Switching).
27
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Rev. D 12/11
Rev. D 12/11
END VIEW
0.378 (9.60)
Ref.
10° Ref.
All Around
2
0.403 (10.24)
0.397 (10.08)
FRONT VIEW
0.050 (1.27)
0.060 (1.52)
Ref.
Pin 1 I.D.
0.325 (8.25)
0.320 (8.13)
0.019 (0.48) Ref.
2
B
A
0.048 (1.22)
0.046 (1.17)
0.021 (0.53)
0.019 (0.48)
0.070 (1.78) Ref.
0.016 (0.41) 6×
0.011 (0.28)
0.020 M 0.51 M C
3
0.140 (3.56)
0.120 (3.05)
Detail A
0.081 (2.06)
0.077 (1.96)
0.047 (1.19)
0.118 (3.00)
0.100 (2.54)
0.059 (1.50)
0.100 (2.54)
A
0.100 (2.54)
PIN 7
4
5. Controlling dimensions in inches (mm).
4. Does not include interlead flash or protrusions.
3. Dimensions noted are inclusive of plating thickness.
PI-5711-110810
2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top
and bottom of the plastic body. Maximum mold protrusion is 0.007 (0.18) per side.
3
0.211 (5.36)
Ref.
0.033 (0.84) 6×
0.028 (0.71)
0.010 M 0.25 M C A B
0.059 (1.50)
0.155 (3.93)
0.050 (1.27)
0.050 (1.27)
BACK VIEW
A
0.221 (5.61)
Ref.
MOUNTING HOLE PATTERN (not to scale)
PIN 1
0.207 (5.26)
0.187 (4.75)
0.100 (2.54)
0.519 (13.18)
Ref.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
Detail A
0.027 (0.70)
0.023 (0.58)
0.020 (0.50)
SIDE VIEW
0.290 (7.37)
Ref.
0.016 (0.41)
Ref.
C
eSIP-7G (E Package)
PFS704-729EG
28
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PFS704-729EG
Part Ordering Information
Part Number
Option
Quantity
PFS704EG
Tube
48
PFS706EG
Tube
48
PFS708EG
Tube
48
PFS710EG
Tube
48
PFS712EG
Tube
48
PFS714EG
Tube
48
PFS716EG
Tube
48
PFS723EG
Tube
48
PFS724EG
Tube
48
PFS725EG
Tube
48
PFS726EG
Tube
48
PFS727EG
Tube
48
PFS728EG
Tube
48
PFS729EG
Tube
48
Part Marking Information
• HiperPFS Product Family
• PFS Series Number
• Package Identifier
E
Plastic eSIP-7G
• Pin Finish
G
PFS 704
Halogen Free and RoHS Compliant
E G
29
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Rev. D 12/11
Revision
Notes
Date
A
Initial Release.
B
Updated Figure 9 and deleted sentence on page 7.
11/09/10
02/11
C
Updated FEEDBACK pin voltage rating in Absolute Maximum Rating table.
02/11
D
Updated Inductor Design paragraph on page 12 and BVDSS(TC).
12/11
For the latest updates, visit our website: www.powerint.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered
by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A
complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under
certain patent rights as set forth at http://www.powerint.com/ip.htm.
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POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)
whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant
injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, HiperLCS,
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trademarks are property of their respective companies. ©2011, Power Integrations, Inc.
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World Headquarters
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Kerry Everbright City
No. 218 Tianmu Road West,
Shanghai, P.R.C. 200070
Phone: +86-21-6354-6323
Fax: +86-21-6354-6325
e-mail: [email protected]
China (ShenZhen)
3rd Floor, Block A,
Zhongtou International Business
Center, No. 1061, Xiang Mei Rd,
FuTian District, ShenZhen,
China, 518040
Phone: +86-755-8379-3243
Fax: +86-755-8379-5828
e-mail: [email protected]
Germany
Rueckertstrasse 3
D-80336, Munich
Germany
Phone: +49-89-5527-3910
Fax: +49-89-5527-3920
e-mail: [email protected]
India
#1, 14th Main Road
Vasanthanagar
Bangalore-560052 India
Phone: +91-80-4113-8020
Fax: +91-80-4113-8023
e-mail: [email protected]
Italy
Via De Amicis 2
20091 Bresso MI
Italy
Phone: +39-028-928-6000
Fax: +39-028-928-6009
e-mail: [email protected]
Japan
Kosei Dai-3 Bldg.
2-12-11, Shin-Yokomana,
Kohoku-ku
Yokohama-shi Kanagwan
222-0033 Japan
Phone: +81-45-471-1021
Fax: +81-45-471-3717
e-mail: [email protected]
Korea
RM 602, 6FL
Korea City Air Terminal B/D, 159-6
Samsung-Dong, Kangnam-Gu,
Seoul, 135-728, Korea
Phone: +82-2-2016-6610
Fax: +82-2-2016-6630
e-mail: [email protected]
Taiwan
5F, No. 318, Nei Hu Rd., Sec. 1
Nei Hu Dist.
Taipei, Taiwan 114, R.O.C.
Phone: +886-2-2659-4570
Fax: +886-2-2659-4550
e-mail: [email protected]
Europe HQ
1st Floor, St. James’s House
East Street, Farnham
Surrey GU9 7TJ
United Kingdom
Phone: +44 (0) 1252-730-141
Fax: +44 (0) 1252-727-689
e-mail: [email protected]
Applications Hotline
World Wide +1-408-414-9660
Singapore
51 Newton Road
Applications Fax
#15-08/10 Goldhill Plaza
World Wide +1-408-414-9760
Singapore, 308900
Phone: +65-6358-2160
Fax: +65-6358-2015
e-mail: [email protected]