STM32W108xx datasheet bit and register naming migration

AN4142
Application note
STM32W108xx datasheet bit and register naming migration
Introduction
The purpose of this application note is to explain the compatibility guideline between
revisions 13 and 14 of datasheet STM32W108xx. To that aim, this document does not
provide detailed information on the two datasheet versions, but it highlights for each
peripheral the bit and register naming between them.
Regarding the hardware, revisions 13 and 14 of the STM32W108xx datasheet are identical.
Revision 14 differs from revision 13 version in terms of documentation level.
However, the details of the migration guideline between the HAL and StdLib are
documented in separate documents. Please refer to AN4141 Migration and compatibility
guideline for STM32W108xx microcontroller applications based on the HAL.
This application note applies to the products listed in Table 1.
Table 1.
Applicable products
Type
Part numbers
Microcontrollers
STM32W108xx
Table 2.
Color coding
Color
Meaning
Old name
New name
Reserved
New register added
Register removed
August 2012
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www.st.com
Contents
AN4142
Contents
1
Why migrate from revision 13 to revision 14 of
datasheet STM32W108xx? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.1
2.2
Memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1
3
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1
3.2
3.3
3.4
3.2.1
STM32W108xx CLK oscillators overview . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.2
STM32W108xx CLK bits and registers overview . . . . . . . . . . . . . . . . . . 10
System timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.1
STM32W108xx watchdog timer overview . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.2
STM32W108xx Sleep timer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.3
STM32W108xx MAC Timer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Standard General-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.1
4.2
4.3
STM32W108xx GPIO Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
External interupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.1
STM32W108xx EXTI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.1
STM32W108xx DBG Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
2/38
STM32W108xx Power Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
General-purpose input/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1
6
STM32W108xx RST bits and registers overview . . . . . . . . . . . . . . . . . . . 9
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.1
5
STM32W108xx MEM bits and registers overview . . . . . . . . . . . . . . . . . . 8
System modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
4
STM32W108xx FLASH bit and register overview . . . . . . . . . . . . . . . . . . 6
STM32W108xx Serial control Overview . . . . . . . . . . . . . . . . . . . . . . . . . 22
General-purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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AN4142
Contents
6.1
7
Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1
8
9
STM32W108xx Timers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM32W108xx ADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1
STM32W108xx NVIC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.2
Management interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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List of tables
AN4142
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
4/38
Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Color coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FLASH memory bits and registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory controller bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
RST bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CLK bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WDG bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SLPTMR bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WDG bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
GPIO bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
EXTI bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
WDG bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SC bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TIM bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ADC bits and registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
NVIC bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
MGMT bits and registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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AN4142
1
Why migrate from revision 13 to revision 14 of datasheet STM32W108xx?
Why migrate from revision 13 to revision 14 of
datasheet STM32W108xx?
The revision 14 of the STM32W108xx datasheet is an updated version of revision 13 of the
datasheet that supports the standard naming (clocks oscillators, bits, registers...) used
inside the STM32Fxx standard microcontrollers documentations.
This revision 14 of the STM32W108xx is an aligned version with the available firmware
STM32W108xx_StdPeriph_Lib_V1.0.0.
In this version, the missing registers that are used in the old HAL and not documented in the
revision 13 of the datasheet are added. In addition the structures for the available registers
are re-organized to be compatible with the StdLib and the memory mapping is added for
each peripheral.
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Embedded memory
This section describes the embedded memory peripherals (FLASH, MEM) bits and registers migration from revision 13 to revision
14 of the STM32W108xx datasheet.
2.1
Flash memory
Embedded memory
6/38
2
The Flash memory interface is the same IP on STM32F microcontrollers families, so almost all of the bits and registers are already
aligned with the standard naming except for the FLASH control registers (FPEC_CLK_REQ and FPEC_CLK_STAT registers).
2.1.1
STM32W108xx FLASH bit and register overview
Table 3 gives the list of the changes (renaming) made in the FLASH bits and registers.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 15
Bit 14
Bit 13
Bit[31:16]
Register
Offset
0x8000
0x8004
0x8008
FLASH memory bits and registers overview
STM32W108xx FLASH bits/registers naming overview
FLASH_
ACR
Reserved
PRFTBS
PRFTBE
HLFCYA
LATENCY
FLASH_
ACR
Reserved
PRFTBS
PRFTBE
HLFCYA
LATENCY
FLASH_
KEYR
FKEYR[31:16]
FKEYR[15:0]
FLASH_
KEYR
FKEYR[31:16]
FKEYR[15:0]
FLASH_
OPTKEYR
OPTKEYR[31:16]
OPTKEYR[15:0]
FLASH_
OPTKEYR
OPTKEYR[31:16]
OPTKEYR[15:0]
FLASH_SR
Reserved
EOP
WRPRTERR
Res.
PGERR
Res.
BSY
FLASH_SR
Reserved
EOP
WRPRTERR
Res.
PGERR
Res.
BSY
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0x800C
Doc ID 023458 Rev 1
Table 3.
Bit 3
Bit 2
Bit 1
Bit 0
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 15
Bit 14
Bit 13
Bit[31:16]
FLASH_CR
Reserved
EOPIE Res ERRIE OPTWRE Res LOCK STRT OPTER
OPTPG
Res.
MER
PER
PG
FLASH_CR
Reserved
EOPIE Res ERRIE OPTWRE Res LOCK STRT OPTER
OPTPG
Res.
MER
PER
PG
Register
Offset
0x8014 0x8010
0x801C
0x8020
0x402C
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0x4030
FLASH memory bits and registers overview (continued)
AN4142
Table 3.
STM32W108xx FLASH bits/registers naming overview
FLASH_AR
FAR[31:16]
FAR[15:0]
FLASH_AR
FAR[31:16]
FAR[15:0]
FLASH_
OBR
Reserved
RDPRT
OPTE
RR
FLASH_
OBR
Reserved
RDPRT
OPTE
RR
FLASH_
WRPR
WRP[31:16]
WRP[15:0]
FLASH_
WRPR
WRP[31:16]
WRP[15:0]
FPEC_
CLK_REQ
Reserved
FPEC
_CLK_
REQ
FLASH_
CLKER
Reserved
EN
FPEC_
CLK_STAT
Reserved
FLASH_
CLKSR
Reserved
FPEC
FPEC_
_CLK_
BSY
ACK
BSY
ACK
Embedded memory
7/38
Memory controller
The memory controller is a set of registers to control the RAM and DMA memories, these registers are required for low power
mode, however before entering in low power modes the user needs to save the context for all the memory controller registers and
restore these configurations after the wake up from the low power modes. In revision 13 of the datasheet, the memory controller is
not documented.
2.2.1
STM32W108xx MEM bits and registers overview
Embedded memory
8/38
2.2
Table 4 gives the memory controller bits and registers naming.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Register
Bit15
Memory controller bits and registers overview
Bit 31-16
Doc ID 023458 Rev 1
Offset
Table 4.
STM32W108xx MEM Controller bits/registers naming overview
0x5000
RAM_PROTR1
[31:0]
0x5004
RAM_PROTR2
[31:0]
0x5008
RAM_PROTR3
[31:0]
0x500C
RAM_PROTR4
[31:0]
0x5010
RAM_PROTR5
[31:0]
0x5014
RAM_PROTR6
[31:0]
0x5018
RAM_PROTR7
[31:0]
0x501C
RAM_PROTR8
[31:0]
0x5020
DMA_PROTR1
0x5024
DMA_PROTR2
Reserved
0x5028
RAM_CR
Reserved
OFFSET
ADDRESS
CHANNEL
WEN
Reserved
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System modules
This section describes the system module peripherals (RST, CLK, System timers, PWR) bits and registers migration from revision
13 to revision 14 of the STM32W108xx datasheet.
3.1
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3
Resets
For the RST IP, there are no updates in term for structure but the only updates are related to the bits and registers naming.
3.1.1
STM32W108xx RST bits and registers overview
Table 5 gives the list of the changes (renaming) made in the RST bits and registers.
Bit 2
Bit 1
Bit 0
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 9
Bit 8
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit[31:16]
RST bits and registers overview
Register
Offset
Doc ID 023458 Rev 1
Table 5.
CPU_
LOCKUP
OPT_BYTE
_FAIL
WAKE_UP_
DSLEEP
SW_
RST
W_
DOG
RSTB_
PIN
POWER_
LV
POWER_
HV
LKUP
OBFAIL
WKUP
SWRST
WDG
PIN
PWRLV
PWRHV
STM32W108xx RST bits/registers naming overview
0X002C
RESET_
EVENT
RST_SR
Reserved
System modules
9/38
System modules
3.2
AN4142
Clocks
The clock IP is completely updated in term of clock oscillators naming and in term of bits
and registers naming.
3.2.1
STM32W108xx CLK oscillators overview
The STM32W108xx integrates four oscillators and to be in line with STM32F families the
clocks oscillators naming convention is updated as follows:
●
The High frequency RC oscillator (12MHz RC) is renamed by the High Speed Internal
clock (HSI).
●
The 24 MHz crystal oscillator (24MHz XTAL) is renamed by the High Speed External
clock (HSE)
●
The 10 KHz RC oscillator (10kHz RC) is renamed by the Low Speed Internal 10 KHz
clock (LSI10K)
●
The 32.768 KHz crystal oscillator(32kHz XTAL) is renamed by the Low Speed External
clock (LSE)
Note:
The CLK1K clock is generated from the 10 KHz RC oscillator, so this clock is renamed by
Low Speed Internal 1 KHz clock (LSI1K).
3.2.2
STM32W108xx CLK bits and registers overview
In the revision 13 of the STM32W108xx datasheet, the clock peripheral is not fully
documented:
●
The LSI10KCR, LSI1KCR, HSICR, PERIODCR and PERIODSR registers are required
to calibrate the internal clocks (HSI and LSI) are missing.
●
The HSECR1 register is required to configure the bias trim, the value should be reset to
full bias at power up.
●
The HSECOMPR register is required to check the 24MHz oscillator comparator outputs
status.
●
The DITHERCR register is required to enable disable the clock dither.
●
The PCTRACECR register is required to select the PC_TRACE source.
●
The new name for the SLEEPTMR_CLKEN register is SLEEPCR register; this register
is removed from the sleep timer section and added in the clock section.
Table 6 gives the list of the changes made in the CLK bits and registers naming.
10/38
Doc ID 023458 Rev 1
Bit 1
Bit 0
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 31-16
SLEEPTMR_
CLKEN
Reserved
SLEEPTMR_
CLK10KEN
SLEEPTMR_
CLK32KEN
CLK_SLEEPCR
Reserved
LSI10KEN
LSEEN
Register
Offset
CLK bits and registers overview
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Table 6.
STM32W108xx CLK bits/registers naming overview
0x0008
0x000C
CLK_LSI10KCR
0x0010
CLK_LSI1KCR
Reserved
Res.
TUNE
CALINT
CLKFRAC
Doc ID 023458 Rev 1
0x0014 0x4000
Reserved
0x4004
CLK_HSECR1
Reserved
0x4008
CLK_HSICR
0x400C
CLK_
HSECOMPR
Reserved
0x4010
CLK_PERIODCR
Reserved
0x4014
CLK_PERIODSR
0x4018
CLK_DITHERCR
BIASTRIM
Reserved
TUNE
HLEVEL
LLEVEL
MODE
Res.
PERIOD
Reserved
DIS
OSC24M_CTRL
Reserved
OSC24M_EN
OSC24M_SEL
CLK_HSECR2
Reserved
EN
SW1
0x401C
CPU_CLK_SEL
Reserved
CPU_CLK_SEL
CLK_CPUCR
Reserved
SW2
0x4020
System modules
11/38
System timers
This sub-section describes the System Timers peripherals (WDG, SLPTMR, MACTMR) bits and registers migration from revision
13 to revision 14 of the STM32W108xx datasheet.
3.3.1
STM32W108xx watchdog timer overview
System modules
12/38
3.3
There are no major updates on the WDG IP. The only updates are related to the bit and register naming.Table 7 gives the list of the
changes made in the WDG bits and registers naming.
Bit 1
Bit 0
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Reserved
WDOG_DIS
WDOG_EN
WDG_CR
Reserved
WDGDIS
WDGEN
Register
Bit 8
WDOG_CFG
Offset
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
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Bit 15
WDG bits and registers overview
Bit[31:16]
Table 7.
STM32W108xx WDG bits/registers naming overview
0x6000
WDOG_CTRL
Reserved
WDOG_CTRL
WDG_KR
Reserved
KEY[15:0]
WDOG_RESTART
Reserved
WDOG_RESTART
WDG_KICKSR
Reserved
KS[15:0]
0x6004
0x6008
3.3.2
STM32W108xx Sleep timer Overview
The sleep Timer IP has two levels of changes: the first one is related to the IP structure and to the low power modes requirement
and the second one is related to the bits and registers naming.
The sleep timer force register SLPTMR_IFR is required in low power modes: if the dedicated sleep timer interrupt (WRAP,
CMPA or CMPB) is enabled and configured as wake event, in this case the interrupt will not be generated when the CPU
AN4142
●
●
The Sleep timer clock enables register SLEEPTMR_CLKEN is renamed by the sleep control register CLK_SLEEPCR and
moved to the clock section.
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wakes up from low power mode, so the user should check in the power wake up status register PWR_WAKESR which flag is
used to wake up the CPU then force the dedicated interrupt in the sleep timer force register SLPTMR_IFR.
Table 8 gives the list of the changes made in the Sleep Timer bits and registers.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Register
Bit 15
Offset
SLPTMR bits and registers overview
Bit[31:16]
Table 8.
STM32W108 SleepTimer bits/registers naming overview
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SLEEPTMR_
CFG
Reserved
SLPTMR_
CR
Reserved
0x600C
SLEEPTMR_
Res.
CNTH
SLEEPT
SLEEPTMR SLEEPTMR
MR_DBG
_REVERSE _ENABLE
PAUSE
REVERSE
EN
DBGP
Res.
SLEEPTMR_
CLKDIV
Reserved
SLEEPTMR_
CLKSEL
Res.
PSC
Reserved
CLKSEL
SLEEPTMR_CNTH
0x6010
SLPTMR_
CNTH
Res.
SLEEPTMR_
Res.
CNTL
CNTH
SLEEPTMR_CNTL
0x6014
SLPTMR_
CNTL
Res.
SLEEPTMR_CMPAH
0x6018
SLPTMR_
CMPAH
Res.
CMPAH
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System modules
SLEEPTMR_
Res.
CMPAH
CNTL
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Register
Bit[31:16]
Offset
SLPTMR bits and registers overview
STM32W108 SleepTimer bits/registers naming overview
SLEEPTMR_
Res.
CMPAL
System modules
14/38
Table 8.
SLEEPTMR_CMPAL
0x601C
SLPTMR_
CMPAL
Res.
CMPAL
SLEEPTMR_
Res.
CMPBH
SLEEPTMR_CMPBH
0x6020
SLPTMR_
CMPBH
Res.
CMPBH
Doc ID 023458 Rev 1
SLEEPTMR_
Res.
CMPBL
SLEEPTMR_CMPBL
0x6024
SLPTMR_
CMPBL
INT_
SLEEPTMRF
LAG
0xA014
0xA020
CMPBL
Reserved
INT_SLEEP INT_SLEEPTM INT_SLEEPTM
TMRCMPB
RCMPA
RWRAP
SLPTMR_
ISR
Reserved
CMPB
CMPA
WRAP
SLPTMR_
IFR
Reserved
CMPB
CMPA
WRAP
INT_
SLEEPTMRC
FG
0xA054
SLPTMR_
IER
0x0008
Res.
Reserved
Reserved
INT_SLEEP INT_SLEEPTM INT_SLEEPTM
TMRCMPB
RCMPA
RWRAP
CMPB
CMPA
WRAP
SLEEPTMR_
CLK10KEN
SLEEPTMR_
CLK32KEN
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SLEEPTMR_
CLKEN
Reserved
STM32W108xx MAC Timer Overview
The MAC Timer IP can be used to measure the timing, this timer is not documented in the revision 13 of datasheet STM32W108xx.
Table 9 gives the MAC timer bits and registers mapping.
Bit 1
Bit 0
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Register
Bit 20
Offset
WDG bits and registers overview
Bit[31:21]
Table 9.
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3.3.3
RST
EN
STM32W108xx MAC Timer bits/registers naming overview
0x2038 MACTMR_CNTR Reserved
Doc ID 023458 Rev 1
0x20402088
0x208C
3.4
CNT[20:0]
Reserved
MACTMR_CR
Reserved
Power management
The Low power IP is used to configure the Low power wake up event sources and to control the wake up status, the registers
descriptions for this IP are missing in the revision 13 of the STM32W108xx datasheet.
3.4.1
STM32W108xx Power Overview
Table 10 gives the list of the power bits and registers mapping.
System modules
15/38
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Register
Bit[31:16]
Offset
Power bits and registers overview
STM32W108xx PWR bits/registers naming overview
0x0004
PWR_DSLEE
PCR1
LVFR
Reserved
EEZE
Reserved
0x0080x0010
Reserved
0x0014
PWR_
DSLEEPCR2
0x0018
PWR_
VREGCR
Reserved
Reserved
1V8EN Res.
1V8TRIM
Doc ID 023458 Rev 1
0x001C
MODE
Res.
1V2EN
Res.
1V2TRIM
Reserved
0x0020
PWR_
WAKECR1
0x0024
PWR_
WAKECR2
0x0028
PWR_
WAKESR
0x002C0x0030
Reserved
CSYSPWR
UPREQ
CPWRR
CORE WRAP
UPREQ
COREWA
KE
Reserved
Reserved
CSYSPWR
UPREQ
COMPB
CPWRR
CORE WRAP
UPREQ
COMPB
COMPA IRQD SC2
SC1
WAKEEN
Reserved
COMPA IRQD SC2
SC1
GPIOPIN
Reserved
PWR_CPWR
UPREQSR
Reserved
REQ
0x0038
PWR_CSYSP
WRUPREQSR
Reserved
REQ
0x003C
PWR_CSYSP
WRUPACKSR
Reserved
ACK
0x0040
PWR_CSYSP
WRUPACKCR
Reserved
INHIBIT
Reserved
AN4142
0x0034
0x0044 0xBC04
System modules
16/38
Table 10.
Bit 3
Bit 2
Bit 1
Bit 0
Bit 4
Bit 5
Bit 6
Bit 7
PWR_
WAKEPAR
Reserved
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
0xBC0C
PWR_
WAKEPBR
Reserved
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0xBC10
PWR_
WAKEPCR
Reserved
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
IRQD SC2
SC1
GPIOPIN
Register
Bit 8
0xBC08
Offset
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit[31:16]
Power bits and registers overview
AN4142
Table 10.
STM32W108xx PWR bits/registers naming overview
0xBC140xBC18
Doc ID 023458 Rev 1
0xBC1C
Reserved
PWR_
WAKEFILTR
Reserved
System modules
17/38
General-purpose input/outputs
The General-purpose input/output IP presented in the revision 13 of the STM32W108xx datasheet is split into three main parts:
●
Standard General-purpose input/output : GPIO
●
External interrupt: EXTI
●
Debug management: DBG
The GPIO_PAWAKE, GPIO_PBWAKE, GPIO_PCWAKE and GPIO_WAKEFILT registers are renamed respectively
PWR_WAKEPAR, PWR_WAKEPBR, PWR_WAKEPCR and PWR_WAKEFILTR registers. These registers are required to manage
the GPIO wake up resources from low power modes and will be presented in the low power mode section.
4.1
General-purpose input/outputs
18/38
4
Standard General-purpose input/output
4.1.1
STM32W108xx GPIO Overview
Table 11 gives the list of the changes (renaming) made in the GPIO bits and registers.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Register
Bit 14
Offset
(GPIOA/
GPIOB/
GPIOC)
GPIO bits and registers overview
Bit 15
Table 11.
Bit[31:16]
Doc ID 023458 Rev 1
This part will contain only the GPIO configurations and status registers.
STM32W108xx GPIO bits/registers naming overview
GPIO_PxCFGL
Res
Px3_CFG
Px2_CFG
Px1_CFG
Px0_CFG
GPIOx_CRL
Res
CNFMODE3[3:0]
CNFMODE2[3:0]
CNFMODE1[3:0]
CNFMODE0[3:0]
GPIO_PxCFGH
Res
Px7_CFG
Px6_CFG
Px5_CFG
Px4_CFG
GPIOx_CRH
Res
CNFMODE7[3:0]
CNFMODE6[3:0]
CNFMODE5[3:0]
CNFMODE4[3:0]
0x00
0x04
Reserved
Px7
Px6
Px5
Px4
Px3
Px2
Px1
Px0
GPIOx_IDR
Reserved
IDR7
IDR6
IDR5
IDR4
IDR3
IDR2
IDR1
IDR0
AN4142
GPIO_PxIN
0x08
Bit 3
Bit 2
Bit 1
Bit 0
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Register
Bit[31:16]
Offset
(GPIOA/
GPIOB/
GPIOC)
GPIO bits and registers overview
Px4
Px3
Px2
Px1
Px0
ODR4
ODR3
ODR2
ODR1
ODR0
Px5
Px4
Px3
Px2
Px1
Px0
BS6
BS5
BS4
BS3
BS2
BS1
BS0
Px7
Px6
Px5
Px4
Px3
Px2
Px1
Px0
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
AN4142
Table 11.
STM32W108xx GPIO bits/registers naming overview
GPIO_PxOUT
Reserved
GPIOx_ODR
Reserved
GPIO_PxSET
Reserved
Px7
Px6
GPIOx_BSR
Reserved
BS7
GPIO_PxCLR
Reserved
GPIOx_BRR
Reserved
Px7
Px6
Px5
0x0C
ODR7 ODR6 ODR5
0x10
0x14
Doc ID 023458 Rev 1
4.2
External interupt
This part will contain the GPIO external interrupts configurations and status registers.
4.2.1
STM32W108xx EXTI Overview
Table 12 gives the list of the changes (renaming) made in the EXTI bits and registers.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Register
STM32W108xx EXTI bits/registers naming overview
INT_GPIOFLAG
Reserved
EXTI_PR
Reserved
INT_
INT_
INT_
INT_
IRQDFLAG IRQCFLAG IRQBFLAG IRQAFLAG
0xA814
19/38
0xA8180xA85C
IRQDP
Reserved
IRQCP
IRQBP
IRQAP
General-purpose input/outputs
Offset
EXTI bits and registers overview
Bit[31:16]
Table 12.
STM32W108xx EXTI bits/registers naming overview
GPIO_INTCFGA
Reserved
EXTIA_TSR
Reserved
GPIO_INTCFGB
Reserved
EXTIB_TSR
Reserved
GPIO_INTCFGC
Reserved
EXTIC_TSR
Reserved
GPIO_INTCFGD
Reserved
EXTID_TSR
Reserved
GPIO_INTFILT GPIO_INTMOD
Reserved
0xA860
FILTEN
INTMOD
GPIO_INTFILT GPIO_INTMOD
Reserved
Reserved
0xA864
FILTEN
INTMOD
GPIO_INTFILT GPIO_INTMOD
Reserved
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Register
Bit[31:16]
Offset
EXTI bits and registers overview
General-purpose input/outputs
20/38
Table 12.
Reserved
0xA868
FILTEN
INTMOD
Doc ID 023458 Rev 1
GPIO_INTFILT GPIO_INTMOD
Reserved
Reserved
0xA86C
FILTEN
0xA8700xBC10
INTMOD
Reserved
Reserved
GPIO_IRQCSEL
Reserved
GPIO_SEL
0xBC18
EXTIC_CR
res
GPIO_IRQDSEL
Reserved
Reserved
GPIO_SEL[4:0]
GPIO_SEL
0xBC14
EXTID_CR
res
Reserved
GPIO_SEL[4:0]
AN4142
Debug management
AN4142
4.3
This part will contain the required registers for the debug mode.
4.3.1
STM32W108xx DBG Overview
The GPIO PC trace control register GPIO_PCTRACECR is added to selects PC trace source on baseband debug GPIO pins.
Table 13 gives the list of the changes (renaming) made in the DBG bits and registers.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Register
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Address
(DBG)
WDG bits and registers overview
Bit[31:16]
Table 13.
STM32W108xx EXTI bits/registers naming overview
Doc ID 023458 Rev 1
0x4028
GPIO_PCTRACECR
Reserved
0x402C0xBBFC
0xBC00
0xBC04
SEL
Reserved
GPIO_DBGCFG
Reserved
GPIO_DE GPIO_EXT
BUGDIS
REGEN
Reserved
GPIO_DBGCR
Reserved
DBGDIS
Reserved
EXTREGEN
GPIO_DBGSTAT
Reserved
GPIO_
BOOTMODE
Reserved
GPIO_
GPIO_SWEN
FORCEDBG
GPIO_DBGSR
Reserved
BOOTMODE
Reserved
FORCEDBG
SWEN
General-purpose input/outputs
21/38
Serial interfaces
The STM32W108 has two serial controllers: SC1 and SC2, the register organization in the Datasheet Rev 14 for these IP are
presented as following:
5.1
●
Serial Controller common registers
●
Serial peripheral interface registers
●
Inter-Integrated circuit registers
●
Universal Asynchronous Receiver/Transmitter registers (available for SC1 only)
●
Direct memory access registers
Serial interfaces
22/38
5
STM32W108xx Serial control Overview
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Register
Bit 13
Offset
(SC1/
SC2)
SC bits and registers overview
Bit 15
Bit 14
Table 14.
Bit[31:16]
STM32W108xx EXTI bits/registers naming overview
INT_SCCMDFIN
INT_SCTXFIN
INT_SCRXFIN
INT_SCTXUND
INT_SCRXOVF
INT_SCTXIDLE
INT_SCTXFREE
INT_SCRXVAL
PE FE
INT_SCNAK
Res.
NACK
CMDFIN
BTF
BRF
UDR
OVR
IDLE
TXE
RXNE
AN4142
RXULODA INT_SCRXULDA
SCx_ISR
0xA808
0xA80C
RXULODB INT_SCRXULDB
Res.
TXULODA INT_SCTXULDA
INT_
SCxFLAG
TXULODB INT_SCTXULDB
INT_SC1FRMERR
Serial Controller (Common registers)
INT_SC1PARERR
Doc ID 023458 Rev 1
Table 14 gives the list of the changes (renaming) made in the SC bits and registers.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 15
Bit 14
Register
Bit[31:16]
Offset
(SC1/
SC2)
SC bits and registers overview
AN4142
Table 14.
0xC854
0xC054
INT_SCNAK
INT_SCCMDFIN
INT_SCTXFIN
INT_SCRXFIN
INT_SCTXUND
INT_SCRXOVF
INT_SCTXIDLE
INT_SCTXFREE
INT_SCRXVAL
CMDFINIE
FEIE
BRFIE
UDRIE
OVRIE
IDLEIE
TXEIE
RXNEIE
Reserved
SCx_ICR
Reserved
SC_TXIDL SC_TXFRE SC_RXVA
ELEVEL
ELEVEL
LLEVEL
RXNELEV
IDLELEVEL TXELEVEL
EL
SCx_
MODE
Reserved
SC_MODE
SCx_CR
Reserved
MODE[1:0]
Reserved
SC_DATA
Reserved
DR[7:0]
SCx_
RATELIN
Reserved
SC_RATELIN
SCx_CRR1
Reserved
LIN[3:0]
SCx_
RATEEXP
Reserved
SC_RATEEXP
SCx_CRR2
Reserved
EXP[3:0]
Serial Controller (Serial peripheral interface registers)
23/38
0xC840
0xC040
SCx_
SPISTAT
SCx_
SPISR
Reserved
Reserved
SC_SPIT SC_SPITX
SC_
SC_SPIR
XIDLE
FREE
SPIRXVAL XOVF
IDLE
TXE
RXNE
OVF
Serial interfaces
0xC864
0xC064
BTFIE
SCx_
INTMODE
0xC83C SCx_DATA
0xC03C SCx_DR
0xC860
0xC060
NACKIE
Doc ID 023458 Rev 1
0xA854
0xA858
RXULODAIE INT_SCRXULDA
INT_SC1FRMERR
Res.
RXULODBIE INT_SCRXULDB
INT_SC1PARERR
SCx_
IER
0xA848
0xA84C
TXULODAIE INT_SCTXULDA
Res.
TXULODRIE INT_SCTXULDB
INT_
SCxCFG
PEIE
STM32W108xx EXTI bits/registers naming overview
Bit 2
Bit 1
Bit 0
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 15
Bit 14
Register
Bit[31:16]
Offset
(SC1/
SC2)
SC bits and registers overview
SC_
SPIORD
SC_
SPIPHA
AC_
SPIPOL
LSBFIRST
CPHA
CPOL
STM32W108xx EXTI bits/registers naming overview
0xC858
0xC058
SCx_
SPICFG
SCx_
SPICR
Reserved
SC_SPIR SC_
SC_
XDRV SPIMST SPIRPT
Reserved
RXMODE MSTR
RPTEN
Serial interfaces
24/38
Table 14.
Serial Controller (Inter-Integrated circuit registers)
0xC844
0xC044
Doc ID 023458 Rev 1
0xC84C
0xC04C
0xC850
0xC050
SCx_
TWISTAT
Reserved
SCx_I2CSR
Reserved
SCx_
TWICTRL1
SCx_
I2CCR1
SCx_
TWICTRL2
SCx_
I2CCR2
SC1_
0xC848 UARTSTAT
0xC848
SC1_
UARTSR
CMDFIN
Reserved
Reserved
Reserved
Reserved
BRF
BTF
NACK
SC_
SC_
SC_
SC_TWIR
TWISTOP TWISTART TWISEND
ECV
STOP
START
BTE
BRE
Reserved
SC_
TWIACK
Reserved
ACK
SC_UAR SC_UAR SC_UA
SC_
SC_UART
SC_UARTR
SC_
TTXIDL TPARER RTFRM
UARTTXFR
RXOVR
XVAL
UARTCTS
E
R
ERR
EE
IDLE
PE
FE
OVR
TXE
RXNE
CTS
Reserved
SC_
SC_
SC_
SC_
SC_
SC_
SC_
UARTAU UARTFL UARTO
UARTPAR UART2STP UART8BIT UARTRTS
TO
OW
DD
Reserved
AHFCE
HFCE
PS
PCE
STOP
M
nRTS
SC_UARTPER
N[15:0]
AN4142
SC1_
0xC85C UARTCFG
0xC85C
SC1_
UARTCR
SC1_
Res
0xC868 UARTPER
0xC868
SC1_
Res
UARTBRR1
SC_TWIC
SC_
SC_
SC_TWIR
MDFIN TWIRXFIN TWITXFIN
XNAK
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 15
Bit 14
Register
Bit[31:16]
Offset
(SC1/
SC2)
SC bits and registers overview
AN4142
Table 14.
STM32W108xx EXTI bits/registers naming overview
SC1_
0xC86C UARTFRAC
0xC86C
SC1_
UARTBRR2
Reserved
SC_UART
FRAC
Reserved
F
Serial Controller (Direct memory access registers)
0xC800
0xC000
Doc ID 023458 Rev 1
0xC804
0xC004
0xC808
0xC008
0xC80C
0xC00C
Reserved
SC_RXBEGA
Reserved
ADD[12:0]
Reserved
SC_RXENDA
Reserved
ADD[12:0]
Reserved
SC_RXBEGB
Reserved
ADD[12:0]
Reserved
SC_RXENDB
Reserved
ADD[12:0]
Reserved
SC_TXBEGA
Reserved
ADD[12:0]
25/38
Serial interfaces
0xC810
0xC010
SCx_
RXBEGA
SCx_
DMARXBEG
ADDAR
SCx_
RXENDA
SCx_
DMARXEND
ADDAR
SCx_
RXBEGB
SCx_
DMARXBEG
ADDBR
SCx_
RXENDB
SCx_
DMARXEND
ADDBR
SCx_
TXBEGA
SCx_
DMATXBEG
ADDAR
STM32W108xx EXTI bits/registers naming overview
0xC814
0xC014
0xC818
0xC018
Doc ID 023458 Rev 1
0xC81C
0xC01C
0xC820
0xC020
0xC824
0xC024
0xC828
0xC028
Reserved
SC_TXENDA
Reserved
ADD[12:0]
Reserved
SC_TXBEGB
Reserved
ADD[12:0]
Reserved
SC_TXENDB
Reserved
ADD[12:0]
Reserved
SC_RXCNTA
Reserved
CNT[12:0]
Reserved
SC_RXCNTB
Reserved
CNT[12:0]
Reserved
SC_TXCNT
Reserved
CNT[12:0]
AN4142
SCx_
TXENDA
SCx_
DMATXEND
ADDAR
SCx_
TXBEGB
SCx_
DMATXBEG
ADDBR
SCx_
TXENDB
SCx_
DMATXEND
ADDBR
SCx_
RXCNTA
SCx_
DMARXCNT
AR
SCx_
RXCNTB
SCx_
DMARXCNT
BR
SCx_
TXCNT
SCx_
DMATXCNT
R
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 15
Bit 14
Register
Bit[31:16]
Offset
(SC1/
SC2)
SC bits and registers overview
Serial interfaces
26/38
Table 14.
Bit 2
Bit 1
Bit 0
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 15
Bit 14
Register
Bit[31:16]
Offset
(SC1/
SC2)
SC bits and registers overview
SC_
TXACTA
SC_
RXACTB
SC_
RXACTA
TXBACK
TXAACK
RXBACK
RXAACK
SC_
SC_TXD
SC_
RXDMA
MARST
TXLODB
RST
SC_
TXLODA
SC_
RXLODB
SC_
RXLODA
TXLODA
RXLODB
RXLODA
AN4142
Table 14.
STM32W108xx EXTI bits/registers naming overview
0xC82C
0xC02C
0xC830
0xC030
Doc ID 023458 Rev 1
0xC834
0xC034
0xC838
0xC038
0xC870
0xC070
SCx_
DMASTAT
SCx_
DMASR
Reserved
SC_
RXSSEL
Reserved
NSSS
SCx_
DMACTRL
SCx_
DMACR
SCx_
RXERRA
SCx_DMAR
XERRAR
SCx_
RXERRB
SCx_
DMARXERR
BR
SCx_RXCNT
SAVED
SCx_
DMARXCNT
SAVEDR
SC_RX SC_RX
SC_
SC_RXP SC_
SC_RX
SC_
FRMB FRMA RXPARB ARA RXOVRB OVRA TXACTB
FEB
Reserved
Reserved
FEA
PEB
PEA
OVRB
TXRST
OVRA
RXRST TXLODB
Reserved
SC_RXERRA
Reserved
ADD[12:0]
Reserved
SC_RXERRB
Reserved
ADD[12:0]
Reserved
SC_RXCNTSAVED
Reserved
CNT[12:0]
Serial interfaces
27/38
General-purpose timers
In addition to the flash memory interface the timer IP is the same as the one used in the STM32Fxx microcontroller's families, so
almost of the bits and registers are already aligned with the standard naming except the registers that are used to manage the
timer interrupts (INT_TIMxCFG, INT_TIMxFLAG and INT_TIMxMISS registers).
6.1
STM32W108xx Timers Overview
General-purpose timers
28/38
6
0
0xE014
0xF014
Bit 2
Bit 1
Bit 0
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 3
Doc ID 023458 Rev 1
0xE008
0xF008
Bit 13
Reserved
TIM_
ARBE
TIM_
CMS
TIM_
DIR
TIM_
OPM
TIM_
URS
TIM_
UDIS
TIM_
CEN
TIMx_
CR1
Reserved
ARPE
CMS
DIR
OPM
URS
UDIS
CEN
TIMx_
CR2
Reserved
TIM_
TI1S
TIM_MMS
Reserved
TIMx_
CR2
Reserved
TI1S
MMS
Reserved
(TIM1/ Register
TIM2)
0xE004
0xF004
Bit 14
TIMx_
CR1
Offset
0xE000
0xF000
Bit 15
TIM bits and registers overview
Bit[31:16]
Table 15.
STM32W108xx GPTimer bits/registers naming overview
TIM_ TIM_
ETP ECE
TIMx_
SMCR
Res
TIMx_
SMCR
Res ETP ECE
TIM_ETPS
TIM_ETF
TIM_
MSM
TIM_TS
Res.
TIM_SMS
ETPS
ETF
MSM
TS
Res.
SMS
Reserved
TIM_TG
Res
TIM_
CC4G
TIM_
CC3G
TIM_
CC2G
TIM_
CC1G
TIM_
UG
TIMx_
EGR
Reserved
TG
Res
CC4G
CC3G
CC2G
CC1G
UG
AN4142
TIMx_
EGR
0xE018
0xF018
Doc ID 023458 Rev 1
0xE01C
0xF01C
0xE020
0xF020
0xE024
0xF024
29/38
0xE02C
0xF02C
Bit 0
TIM_
OC1FE
Bit 1
Bit 2
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 3
Res.
Res
Res.
TIMx_
CCMR1 Res
TIMx_
CCMR2
TIM_
OC1BE
STM32W108xx GPTimer bits/registers naming overview
Res;
Res
Res.
TIMx_
CCMR2 Res
TIM_OC2M
TIM_IC2F
OC2M
TIM_ TIM_
OC2BE OC2FE
Res.
TIM_OC1M
TIM_CC2S
TIM_IC2PSC
TIM_IC1F
OC2PE OC2FE
Res.
OC1M
OC1PE
OC1FE
CC2S
IC2F
TIM_OC4M
TIM_IC4F
OC4M
CC1S
IC2PSC
TIM_ TIM_
OC4BE OC4FE
IC1F
Res.
TIM_OC3M
TIM_CC4S
TIM_IC4PSC
TIM_IC3F
OC4PE OC4FE
Res.
OC3M
IC1PSC
TIM_
OC3BE
TIM_
OC3FE
TIM_CC3S
TIM_IC3PSC
OC3PE
OC3FE
CC4S
IC4F
TIM_CC1S
TIM_IC1PSC
CC3S
IC4PSC
IC3F
IC3PSC
TIMx_
CCER
Reserved
TIM_ TIM_
CC4P CC4E
Res.
TIM_ TIM_
CC3P CC3E
Res.
TIM_ TIM_
CC2P CC2E
Reserved
TIM_
CC1P
TIM_
CC1E
TIMx_
CCER
Reserved
CC4P CC4E
Res.
CC3P CC3E
Res.
CC2P CC2E
Reserved
CC1P
CC1E
TIMx_
CTN
Res
TIM_CTN
TIMx_
CTN
Res
CTN[15:0]
TIMx_
PSC
Res
TIM_PSC
TIMx_
PSC
Res
PSC[15:0]
TIMx_
ARR
Res
TIM_ARR
TIMx_
ARR
Res
ARR[15:0]
General-purpose timers
0xE028
0xF028
TIMx_
CCMR1
Bit 14
(TIM1/ Register
TIM2)
Bit 15
Offset
Bit[31:16]
TIM bits and registers overview
AN4142
Table 15.
0xE034
0xF034
0xE038
0xF038
Doc ID 023458 Rev 1
0xE03C
0xF03C
0xE040
0xF040
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
(TIM1/ Register
TIM2)
Bit 15
Offset
Bit[31:16]
TIM bits and registers overview
STM32W108xx GPTimer bits/registers naming overview
TIMx_
CCR1
Res
TIM_CCR
TIMx_
CCR1
Res
CCR[15:0]
TIMx_
CCR2
Res
TIM_CCR
TIMx_
CCR2
Res
CCR[15:0]
TIMx_
CCR3
Res
TIM_CCR
TIMx_
CCR3
Res
CCR[15:0]
TIMx_
CCR4
Res
TIM_CCR
TIMx_
CCR4
Res
CCR[15:0]
TIM1_
OR
Reserved
TIM_
TIM_
CLKMSK
ORRSVD
EN
TIM1_
EXTRIGSEL
TIM1_
OR
Reserved
ORRSVD
CLKMSK
EN
EXTRIGSEL
0xE050
Reserved
TIM_
TIM_ TIM_
TIM_
TIM_RE
TIM_
REMAP
REMA REMAP
CLKMSK
MAPC3
ORRSVD
C4
PC2
C1
EN
TIM1_
EXTRIGSEL
TIM2_
OR
Reserved
REMAP REMAPC REMA REMAP
CLKMSK
ORRSVD
C4
3
PC2
C1
EN
EXTRIGSEL
0xF050
AN4142
TIM2_
OR
General-purpose timers
30/38
Table 15.
INT_
INT_ INT_TIM INT_TIM INT_
Res TIMCC4
TIMCC3IF CC2IF CC1IF TIMUIF
IF
Doc ID 023458 Rev 1
INT_TIM
xCFG
Reserved
INT_
TIMTIF
0xA844
TIMx_
IER
Reserved
TIE
0xA800
INT_TIM
xFLAG
Reserved
INT_TIMRSVD
Res.
INT_
TIMTIF
0xA804
TIMx_
ISR
Reserved
RSVD
Res.
TIP
Reserved
INT_ INT_
INT_
INT_
TIMMI TIMMI
TIMMIS
TIMMIS
SSCC3 SSCC2
SCC4IF
SCC1IF
IF
IF
Res.
INT_TIMMISSRSVD
Reserved
CC4IM CC3IM CC2IM CC1IM
Res.
RSVD
0xA81C
TIMx_
MISSR
Bit 0
STM32W108xx GPTimer bits/registers naming overview
0xA840
INT_TIM
0xA818
xMISS
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
(TIM1/ Register
TIM2)
Bit 15
Offset
Bit[31:16]
TIM bits and registers overview
AN4142
Table 15.
Res
CC4IE
CC3IE
CC2IE
CC1IE
UIE
INT_
INT_ INT_TIM INT_TIM INT_
Res TIMCC4
TIMCC3IF CC2IF CC1IF TIMUIF
IF
Res
CC4IP
CC3IP
CC2IP
CC1IP
UIP
General-purpose timers
31/38
Analog-to-digital converter
Analog-to-digital converter
32/38
7
For the ADC IP, there are no updates in term for structure but the only updates are related to the bits and registers naming.
7.1
STM32W108xx ADC Overview
Table 16 gives the list of the changes (renaming) made in the ADC bits and registers.
Bit 0
Bit 2
Bit 3
Bit 4
Bit 5
Bit 7
Bit 6
Bit 1
Doc ID 023458 Rev 1
ADC_
ADC_
ADC_
ADC_MUXP
PERIOD HVSELP HVSELN
ADC_MUXN
ADC_
1MHZCLK
Reserved
ADC_
ENABLE
ADC_CR
Res SMP[2:0] HVSELP HVSELN CHSELP[3:0]
CHSELN[3:0]
CLK
Reserved
ADON
ADC_
OFFSET
Res
ADC_OFFSET_FIELD
ADC_
OFFSETR
Res
OFFSET[15:0]
ADC_GAIN
Res
ADC_GAIN_FIELD
ADC_
GAINR
Res
GAIN[15:0]
Register
Bit 8
Bit 10
Bit 9
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Offset
ADC bits and registers overview
Bit[31:16]
Table 16.
STM32W108xx ADC bits/registers naming overview
0xD004
0xD008
0xD00C
0xD010
0xD014
ADC_CFG
Res
ADC_
DMACFG
Reserved
ADC_
DMARST
Reserved
ADC_
DMACR
Reserved
RST
Reserved
ADC_DMAAUT
ADC_
OWRAP
DMALOAD
AUTOWRAP
LOAD
Reserved
ADC_
DMAOVF
ADC_
DMAACT
ADC_
DMASR
Reserved
OVF
ACT
AN4142
ADC_
DMASTAT
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 7
Bit 6
Bit 8
Bit 10
Bit 9
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Register
Bit[31:16]
Offset
ADC bits and registers overview
AN4142
Table 16.
STM32W108xx ADC bits/registers naming overview
0xD018
0xD01C
Doc ID 023458 Rev 1
0xD020
0xD024
0xA810
Reserved
ADC_DMABEG
ADC_
DMAMSAR
Reserved
MSA[13:0]
ADC_
DMASIZE
Reserved
ADC_DMASIZE_FIELD
ADC_
DMANDTR
Reserved
NDT[12:0]
ADC_
DMACUR
Reserved
ADC_DMACUR_FIELD
Reserved
ADC_
DMAMNAR
Reserved
MNA[13:0]
Reserved
ADC_
DMACNT
Reserved
ADC_DMACNT_FIELD
ADC_
DMACNDTR
Reserved
CNDT[12:0]
INT_
ADCFLAG
Reserved
INT_
ADCOVF
ADC_ISR
Reserved
DMAOVF
INT_
ADCCFG
Reserved
INT_
ADCOVF
ADC_IER
Reserved
DMAOVFIE
INT_
INT_
INT_
ADCSAT ADCULDFULL ADCULDHALF
SAT
DMABF
INT_
INT_
INT_
ADCSAT ADCULDFULL ADCULDHALF
SATIE
DMABFIE
Reserved
Reserved
Reserved
Reserved
33/38
Analog-to-digital converter
0xA850
ADC_
DMABEG
Interrupts
The STM32W108xx microcontrollers are based on the core Cortex-M3, so the nested vectored interrupt controller (NVIC) registers
section is removed from the datasheet and a reference to the Cortex-M3 programming manual.pdf (PM0056) is added to make the
library compliant with the Cortex™ microcontroller software interface standard (CMSIS)
8.1
Interrupts
34/38
8
STM32W108xx NVIC Overview
Table 17 gives the compatibility guideline between the NVIC registers section presented in datasheet Rev13 and the equivalent
one in the Cortex-M3 programming manual.
The bits and registers definitions for the Cortex-M3 Core Peripheral Access Layer are provided in the CMSIS library under:
CMSIS\Include\core_cm3.h file
Doc ID 023458 Rev 1
Table 17.
Offset
Register
NVIC bits and registers overview
0xA820
INT_
MISS
0xE100
INT_
CFGSET
NVIC_
ISER
0xE180
INT_CFG
CLR
NVIC_
ICER
Bit 31-17 Reserved
0xE200
INT_PEN
DSET
NVIC_
ISPR
0xE280
0xE300
INT_PEN
DCLR
NVIC_
ICPR
INT_
ACTIVE
NVIC_
IABR
0xED3C
SCS_
AFSR
SCB_
AFSR
Reserved
INT_
DEBUG
INT_
DEBUG
DEBUG
INT_
DEBUG
DEBUG
INT_
DEBUG
DEBUG
INT_
DEBUG
DEBUG
INT_
DEBUG
DEBUG
Bit 15
INT_
IRQD
INT_
IRQD
IRQD
INT_
IRQD
IRQD
INT_
IRQD
IRQD
INT_
IRQD
IRQD
INT_
IRQD
IRQD
Bit 14
INT_
IRQC
INT_
IRQC
IRQC
INT_
IRQC
IRQC
INT_
IRQC
IRQC
INT_
IRQC
IRQC
INT_
IRQC
IRQC
Bit 13
INT_
IRQB
INT_
IRQB
IRQB
INT_
IRQB
IRQB
INT_
IRQB
IRQB
INT_
IRQB
IRQB
INT_
IRQB
IRQB
Bit 12
INT_
IRQA
INT_
IRQA
IRQA
INT_
IRQA
IRQA
INT_
IRQA
IRQA
INT_IRQA
IRQA
INT_I
RQA
IRQA
Bit 11
INT_ADC
INT_
ADC
ADC
INT_
ADC
ADC
INT_
ADC
ADC
INT_
ADC
ADC
INT_ADC
ADC
Res
Reserved
AN4142
Bit 16
Bit 10
NVIC bits and registers overview
INT_
MACRX
INT_
MACRX
INT_
MACRX
Res.
INT_
MACTX
INT_
MACRX
Res.
INT_
MACTX
INT_
MACRX
Res.
INT_
MACTX
Res.
INT_
MACTX
INT_
MACRX
AN4142
Table 17.
Res.
Doc ID 023458 Rev 1
Bit 9
INT_
MACTX
Bit 8
INT_
MACTMR
Bit 7
INT_SEC
INT_
SEC
Res.
INT_
SEC
Res.
INT_
SEC
Res.
INT_
SEC
Res.
INT_SEC
Res.
Bit 6
INT_SC2
INT_
SC2
SC2
INT_SC2
SC2
INT_SC2
SC2
INT_SC2
SC2
INT_SC2
SC2
Bit 5
INT_SC1 Res
INT_
SC1
SC1
INT_SC1
SC1
INT_SC1
SC1
INT_SC1
SC1
INT_SC1
SC1
Bit 4
INT_SLEE
PTMR
Bit 3
INT_BB
INT_BB
Res
INT_BB
Res
INT_BB
Res
INT_BB
Res
INT_BB
Res
WRONGS WRONGS
IZE
IZE
Bit 2
INT_
MGMT
INT_
MGMT
MGMT
INT_
MGMT
MGMT
INT_
MGMT
MGMT
INT_
MGMT
MGMT
INT_
MGMT
MGMT
PROTEC PROTEC
TED
TED
Bit 1
INT_TIM2
INT_
TIM2
TIM2
INT_
TIM2
TIM2
INT_
TIM2
TIM2
INT_
TIM2
TIM2
INT_TIM2
TIM2
Reserved
Bit 0
INT_TIM1
INT_
TIM1
TIM1
INT_
TIM1
TIM1
INT_
TIM1
TIM1
INT_
TIM1
TIM1
INT_TIM1
TIM1
MISSED MISSED
INT_MAC
INT_MAC
INT_MAC
INT_MAC
INT_
MACTMR
MACTMR
MACTMR
MACTMR
MACTMR
TMR
TMR
TMR
TMR
MACTMR
Res.
INT_SLEE SLEEPTM INT_SLEE SLEEPT INT_SLEE SLEEPT INT_SLEE SLEEPT INT_SLEE SLEEPTM
PTMR
R
PTMR
MR
PTMR
MR
PTMR
MR
PTMR
R
Interrupts
35/38
Management interrupt
The HSE COMP high level and HSE COMP low level interrupts can be managed separately using the management interrupt IP .
Table 18 gives the MGMT bits and registers mapping.
Bit 1
Bit 0
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Register
Bit 15
Offset
MGMT bits and registers overview
Bit[31:16]
Table 18.
Interrupts
36/38
8.2
HSECOMPHLIF
HSECOMPLLIF
HSECOMPHLIE
HSECOMPLLIE
STM32W108xx PWR bits/registers naming overview
Doc ID 023458 Rev 1
0xA018
MGMT_ISR
Reserved
0xA01C
-0xA054
0xA058
Reserved
MGMT_IER
Reserved
AN4142
AN4142
9
Revision history
Revision history
Table 19.
Document revision history
Date
Revision
23-Aug-2012
1
Changes
Initial release.
Doc ID 023458 Rev 1
37/38
AN4142
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