AGS04
4-Channel Differential Calibration Capacitive Touch Sensor
SPECIFICATION
Preliminary
February 2010
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AGS04 (4-CH Differential Sensitivity Calibration Capacitive Touch Sensor)
1 Specification
1.1 General Feature
4-Channel capacitive sensor with differential sensitivity calibration
2
I C serial interface
Selectable output operation mode (Single output /Multi output)
Independently adjustable in 128 steps sensitivity
Adjustable response time by the control registers
Programmable wake up sequence from SLEEP mode
Almost no external component needed
Very low current consumption
Embedded common and normal noise elimination circuit
RoHS compliant 12QFN package
1.2
Application
Mobile application (mobile phone / PDA / PMP / MP3 etc)
Membrane switch replacement
Sealed control panels, keypads
1.3 Package (12 QFN)
AGS04 12QFN (Drawings not to scale)
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2 Pin Description (12QFN)
PIN No.
Name
I/O
Description
1
GND
Ground
Supply ground
VDD
2
N.C.
-
No Connection
-
3
N.C.
-
No Connection
-
4
VDD
Power
5
INT
Digital Output
Interrupt output (Open drain)
6
SDA
Digital
Input/Output
I C data input-output
Open drain NMOS structure
7
SCL
Digital Input
I C clock input
VDD/GND
8
CS4
Analog Input
Capacitive sensor input4
VDD/GND
9
CS3
Analog Input
Capacitive sensor input3
VDD/GND
10
CS2
Analog Input
Capacitive sensor input2
VDD/GND
11
CS1
Analog Input
Capacitive sensor input1
VDD/GND
12
R.N.D.
Analog Input
Radio frequency Noise Detection pin
VDD/GND
Power (1.8V~3.3V)
Protection
GND
VDD/GND
2
2
VDD/GND
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3 Absolute Maximum Rating
Battery supply voltage
3.3V
Maximum voltage on any pin VDD+0.3
Maximum current on any PAD 100mA
Power Dissipation
800mW
Storage Temperature
-50 ~ 150℃
Operating Temperature
-20 ~ 75℃
Junction Temperature
150℃
Note : Unless any other command is noted, all above are operated in normal temperature.
4 ESD & Latch-up Characteristics
4.1 ESD Characteristics
Mode
Polarity
H.B.M
Pos / Neg
M.M
Pos / Neg
C.D.M
-
Max
Reference
Max
Reference
4.2 Latch-up Characteristics
Mode
Polarity
Positive
I Test
Negative
V supply over 5.0V
JESD78A
Positive
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5 Electrical Characteristics
▪ Note : VDD=3.3V, Typical system frequency (Unless otherwise noted), TA = 25℃
Characteristics
Symbol
Test Condition
Min
Power supply requirement and current consumption
Operating voltage
VDD
1.8
Current consumption
Reset and input level
Internal reset voltage
Self calibration time after
system reset
Touch sensing performance
Minimum detective
capacitance difference
Sense input
1
capacitance range
Output impedance
(open drain)
System performance
2
Sensitivity control
2
Max. I C SCL clock speed
Touch expired time
Typ
Max
Units
3.3
V
IDD
VDD = 1.8V
-
-
30
㎂
VDD_RST
TA = 25℃
-
-
1.2
V
-
80
-
ΔCMIN
0.1
-
-
㎊
CS
-
-
50
㎊
-
12
30M
-
Ω
-
128
30
1
-
step
MHz
sec
Zo
fSCL_MAX
TEX
ΔC > ΔCMIN
ΔC < ΔCMIN
2
Maximum internal I C clock
Normal calibration speed
1
The sensitivity can be decreased with higher parallel capacitance of CS pin including parasitic capacitance made by
neighbor GND or other pattern. The series resistor(under 1kΩ) of CS can be used in noisy condition to avoid mal-function
from external surge and ESD.
2
Refer to the chapter 8.2.5. Sensitivity register
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6 AGS04 Implementation
6.1 Typical current consumption
AGS04 uses internal bias circuit, so internal clock frequency and current consumption is fixed
and no external bias circuit is needed. The typical current consumption curve of AGS04 is
represented in accordance with VDD voltage as below.
Internal bias circuit can make the circuit design simple and reduce external components.
Typical current consumption curve of AGS04
6.2 R.N.D
Radio frequency Noise Detection pin. Normally, R.N.D pin does not connect to anywhere.
But, in radio frequency noise environment, this pin must form a pattern line on PCB.
6.3 CS implementation
AGS04 has 128 step selections of sensitivity and internal surge protection resister. Sensitivity of
each sensing channel (CS) can be independently controlled on others. External components of
CS pin such as series resistor or parallel capacitor isn’t necessary. The parallel parasitic
capacitance of CS pins caused by touch line, touch pad and neighbor GND or other pattern
may affect sensitivity. The sensitivity will be decreased when bigger parallel parasitic
capacitance of CS pin is added.
Parallel capacitor (CS1~S4) of CS pin is useful in case of detail sensitivity mediation is required
such as for complementation sensitivity difference between channels. Same as above parallel
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parasitic capacitance, sensitivity will be decreased when a big value of parallel capacitor
(CS1~S4) is used. Under 50pF capacitor can be used as sensitivity meditation capacitor and a
few pF is usually used. The RS, serial connection resistor of CS pins, may be used to avoid
mal-function from external surge and ESD. (It might be optional.) From 200Ω to 1kΩ is
recommended for RS. Refer to below CS pins application figure.
RS4
CS4<<
Touch PAD4
CS4
RS1
CS1<<
Touch PAD1
CS1
The AGS04 has eight independent touch sensor input from CS1 to CS4. The internal touch
decision process of each channel is separated from others. Therefore eight channel touch key
board application can be designed by using only one AGS04 without coupling problems.
The size and shape of PAD might have influence on the sensitivity. The sensitivity will be optimal
when the size of PAD is approximately an half of the first knuckle (it’s about 10mmx7mm). The
connection line of CS to touch PAD is recommended to be routed as short as possible to
prevent from abnormal touch detect caused by connection line. The unused CS pin must be
connected with the ground to prevent the unpredictable mal-function that occurred in the
floating CS pin.
6.4 INT (Interrupt output)
Special function of INT is for the touch sensing interrupt output. Functions of INT can be
3
controlled by ‘Interrupt mode’ register setting. There are two interrupt operation is possible and
can be selected by ‘int_sel’ bit of ‘interrupt mode’ register setting.
6.4.1
Normal interrupt operation
The interrupt operation act as normal if the ‘int_sel’ bit is ‘0’. There are two state of interrupt
output in the normal interrupt operation. In first interrupt operation case, the interrupt pulse is
generated only during short period of every each channel touch start points and touch end point.
3
Refer to the chapter 8.2.4. Interrupt mode.
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In other interrupt operation case, the interrupt pulse is generated during every each channel
touch duration. Interrupt pulse has logical low level in both two interrupt modes. Pull-up resister
about a few kΩ is required for interrupt output.
6.4.2
Pattern SleepTM interrupt operation
The purpose of pattern sleep is to replace power key or unlock key in the application. For
example, many mal-functions could happen if the mobile product is in the pocket. But thanks
to the pattern sleep, the MCU would be awaked from SLEEP mode with a proper touch input
only.
The AGS04 triggers the interrupt when it is in the normal operation. But the interrupt would be
used when the touch inputs correspond with the reserved sequence in pattern sleep mode if the
‘int_sel’ bit is ‘1’. And all the touch inputs should arrive within the expiration time that is
controllable by the dedicated register. As already mentioned, there is an advantage for the
material cost as it will accordingly replace the unlock tact switch.
4
** Pattern sleep setting up **
- Two pattern sleep sequence is possible. If user wants to use pattern 1, set the pattern 1
5
enable bit ‘patt1_en’ . And if user wants to use pattern 2, set the pattern 2 enable bit ‘patt2_en’.
- Two types of pattern sleep mode could be provided.
Pattern sleep mode type
Description
Slide type
When the touch input sequence is coming by sliding touch.
6
“pattx_mode” = “00”, (x means 1 or 2)
Touch to touch type
When the touch input sequence is coming by touch on / off
“pattx_mode” = “01”, (x means 1 or 2)
4
5
6
Refer to the chapter 8.2.11 ~ 8.2.18, Pattern sleep interrupt operation registers
Refer to the chapter 8.2.11, Pattern sleep control register
Refer to the chapter 8.2.11, Pattern sleep control register
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7
- Expiration time is available to control with “pattx_expire_time” register. (See Register
Description)
8
- Pattern sequence number is available to control with “pattx_num” register. (See Register
Description)
9
- It is possible to recognize one pad from 1, 2, 3 or 4 pad. If user set the “pattx_pairn” (n
means 1 or 2, to make two pairs) with the value “1100”, the pad 4 and pad 3 are regard to one
pad.
- User defined pattern sequence
10
The interrupt generation is done by the OR operation between “pattxa_datan” (n means 1 to 15)
and “pattxb_datan”(n means 1 to 15) in the slide type and the interrupt generation is done by
the only “pattxa_datan”(n means 1 to 15) in the touch to touch type. The pattern is available to
extend up to 15 steps.
- Application support idea
With our unique sleep pattern set up, it allows mobile phones, MP3 players and other devices to
be in IDLE mode and then back to active mode using just a few easy steps. A mobile phone,
for example, normally will be in left unattended in our pockets, tables, etc. Using our set up,
mobile phones will automatically be in Idle mode without pressing any special keys. Sleep time
(length of time before it goes to sleep) will vary depending on the time you input in the system.
This will help prevent unnecessary dialed numbers or unwanted calls. Our sleep pattern set up
will eliminate the use of special keys (e.g unlock key button) and instead it uses a touch sensors
to activate and unlock the phone.
6.5 RST implementation
The AGS04 has stable internal reset circuit to offer reset pulse to digital block. The supply
voltage for a system start or restart should be under 1.2V. No external components required for
AGS04 power reset, that helps simple circuit design and to realize the low cost application.
6.6 SCL, SDA implementation
2
2
SCL is I C clock input and SDA is I C data input-output. SCL has Schmitt trigger input structure
2
to prevent clock signal from being broken. Maximum supported I C clock frequency is 1MHz.
SDA has NMOS open drain. So, according to communication speed a few kΩ resister must be
used as pull-up resister for proper data pulse rising time. For more details refer to ‘Chapter 7.
2
I C Interface’.
7
8
9
Refer to the chapter 8.2.13, Pattern sleep expiration counter register.
Refer to the chapter 8.2.14, Pattern sleep sequence number.
Refer to the chapter 8.2.11, 8.2.12, Pattern sleep channel pair1, pair2.
10
Refer to the chapter 8.2.17, 8.2.18, Pattern sleep data A, B.
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7 I2C Interface
7.1 I2C Enable / Disable
2
If the SDA or SCL signal goes to low, I C control block is enabled automatically. And if the SDA
2
and SCL signal maintain high during about 2us, I C control block is disabled automatically also.
7.2 Start & stop condition
Start Condition (S)
Stop Condition (P)
Repeated Start (Sr)
7.3 Data validity
The SDA should be stable when the SCL is high and the SDA can be changed when the SCL is
low.
7.4 Byte format
The byte structure is composed with 8Bit data and an acknowledge signal.
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7.5 Acknowledge
It is a check bit whether the receiver gets the data from the transmitter without error or not. The
receiver will write ‘0’ when it received the data successfully and ‘1’ if not.
7.6 First byte
7.6.1
Slave address
It is the first byte from the start condition. It is used to access the slave device. The initial chip
address of AGS04 is ‘D4’ hex number. If user uses 7-bit slave address protocol, use ‘6A’ for
AGS04 chip address.
7.6.2
─
R/W
The direction of data is decided by the bit and it follows the address data.
MSB
Address
LSB
R/W
7 bit
1bit
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7.7 Transferring data
7.7.1
The
1.
2.
3.
4.
5.
Write operation
byte sequence is as follows:
The first byte gives the device address plus the direction bit (R/W = 0).
The second byte contains the internal address of the first register to be accessed.
The next byte is written in the internal register. Following bytes are written in successive
internal registers.
The transfer lasts until stop conditions are encountered.
The AGS04 acknowledges every byte transfer.
7.7.2
Read operation
The address of the first register to read is programmed in a write operation without data, and
terminated by the stop condition. Then, another start is followed by the device address and
R/W= 1. All following bytes are now data to be read at successive positions starting from the
initial address.
7.7.3
Read/Write Operation
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7.8 I2C write and read operations in normal mode
2
The following figure represents the I C normal mode write and read registers.
☞ Write register 0x01 to 0x02 with data AA and BB
Start
Device
Address 0xD4
ACK
Register
Address 0x01
ACK
Data AA
ACK
Data BB
ACK
Stop
Read register 0x01 and 0x02
Start
Device
Address 0xD4
ACK
Register
Address 0x01
ACK
Start
Device
Address 0xD5
ACK
Data Read AA
ACK
From Master to Slave
Stop
Data Read BB
ACK
Stop
From Slave to Master
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8 AGS04 Control Register List
2
Note: The unused bits (defined as reserved) in I C registers must be kept to zero.
8.1 I2C Register Map
Name
Addr.
(Hex)
Reset
Bit name of each bytes
Value
(Bin)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
read only
-
-
-
-
o_ch4
o_ch3
o_ch2
o_ch1
ch4_en
ch3_en
ch2_en
ch1_en
-100 1100
-
mode_sel
cal_pause
--10 --00
-
-
output
00H
ch_enable
01H
---- 1111
global_ctrl1
02H
interrupt mode 03H
reseponse_ctrl
sen_ctrl
-
-
clk_off
sw_rst
int_mode
int_sel
sensitivity1
04H
-000 1001
-
sensitivity1
sensitivity1
05H
-000 1001
-
sensitivity2
sensitivity3
06H
-000 1001
-
sensitivity3
sensitivity4
07H
-000 1001
-
sen_limit1
08H
--11 1111
-
-
sen_limit1
sen_limit2
09H
--11 1111
-
-
sen_limit2
sen_limit3
0AH
--11 1111
-
-
sen_limit3
sen_limit4
0BH
--11 1111
-
-
cal. speed
0CH
-010 -011
-
cal_speed_up
-
cal_speed_down
dmCal. speed
0DH
-010 -011
-
dum_cal_speed_up
-
dum_cal_speed_down
out expiration
0EH
--00 0000
-
variable fduty1
10H
-100 -100
-
dummy_fduty1
-
sense_fduty1
variable fduty2
11H
-100 -100
-
dummy_fduty2
-
sense_fduty2
variable fduty3
12H
-100 -100
-
dummy_fduty3
-
sense_fduty3
variable fduty4
13H
-100 -100
-
dummy_fduty4
-
sense_fduty4
variable fduty5
14H
-100 -100
-
dummy_fduty5
-
sense_fduty5
variable fduty6
15H
-100 -100
-
dummy_fduty6
-
variable period
16H
---0 1001
-
pattern ctrl
1AH
-000 0000
-
pattern cnt1
1BH
0000 0000
patt2_inner_time
patt1_inner_time
patt1_expire_time
sensitivity4
sen_limit4
-
exp_time
-
patt1_mode
exp_mode
exp_en
sense_fduty6
var_period
patt1_en
patt1_mode
pattern cnt2
1CH
0000 0000
patt2_expire_time
pattern num.
1DH
0000 0000
patt2_num
patt1_num
pattern pair1
1EH
0000 0000
patt2_pair1
patt1_pair1
pattern pair2
1FH
0000 0000
patt2_pair2
patt1_pair2
patt A data1
20H
0000 0000
patt2a_data1
patt1a_data1
patt A data2
21H
0000 0000
patt2a_data2
patt1a_data2
patt A data3
22H
0000 0000
patt2a_data3
patt1a_data3
patt A data4
23H
0000 0000
patt2a_data4
patt1a_data4
patt A data5
24H
0000 0000
patt2a_data5
patt1a_data5
patt A data6
25H
0000 0000
patt2a_data6
patt1a_data6
patt A data7
26H
0000 0000
patt2a_data7
patt1a_data7
patt A data8
27H
0000 0000
patt2a_data8
patt1a_data8
patt A data9
28H
0000 0000
patt2a_data9
patt1a_data9
patt A data10
29H
0000 0000
patt2a_data10
patt1a_data10
patt A data11
2AH
0000 0000
patt2a_data11
patt1a_data11
patt A data12
2BH
0000 0000
patt2a_data12
patt1a_data12
patt A data13
2CH
0000 0000
patt2a_data13
patt1a_data13
patt A data14
2DH
0000 0000
patt2a_data14
patt1a_data14
patt A data15
2EH
0000 0000
patt2a_data15
patt1a_data15
patt1_en
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Name
Addr.
(Hex)
Reset
Bit name of each bytes
Value
(Bin)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
patt B data1
30H
0000 0000
patt2b_data1
patt1b_data1
patt B data2
31H
0000 0000
patt2b_data2
patt1b_data2
patt B data3
32H
0000 0000
patt2b_data3
patt1b_data3
patt B data4
33H
0000 0000
patt2b_data4
patt1b_data4
patt B data5
34H
0000 0000
patt2b_data5
patt1b_data5
patt B data6
35H
0000 0000
patt2b_data6
patt1b_data6
patt B data7
36H
0000 0000
patt2b_data7
patt1b_data7
patt B data8
37H
0000 0000
patt2b_data8
patt1b_data8
patt B data9
38H
0000 0000
patt2b_data9
patt1b_data9
patt B data10
39H
0000 0000
patt2b_data10
patt1b_data10
patt B data11
3AH
0000 0000
patt2b_data11
patt1b_data11
patt B data12
3BH
0000 0000
patt2b_data12
patt1b_data12
patt B data13
3CH
0000 0000
patt2b_data13
patt1b_data13
patt B data14
3DH
0000 0000
patt2b_data14
patt1b_data14
patt B data15
3EH
0000 0000
patt2b_data15
read CH head
40H
read only
-
-
sen_H
41H
read only
-
-
sen_L
42H
read only
ref_H
43H
read only
ref_L
44H
read only
read CH tail
45H
read only
Bit0
patt1b_data15
-
ch_head
ref_data[13:8]
ref_data[7:0]
-
sense_data[14:8]
sense_data[7:0]
-
-
-
ch_tail
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8.2 Details
8.2.1
Output data
Type: R
Address
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00H
output
-
-
-
-
o_ch4
o_ch3
o_ch2
o_ch1
Description
The output data register from channel 1 to channel 4.
Bit name
Reset value
o_chx
0
8.2.2
Function
o_chx is output bit for CSx channel
0 : No touch detected
1 : Touch detected
Channel enable / reset register
Type: R/W
Address
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
01H
ch_enable
-
-
-
-
ch4_en
ch3_en
ch2_en
ch1_en
Description
Enable, disable and reset of each channel control register.
Bit name
Reset value
chx_en
1
Function
Channel enable / disable and Channel reset (chx_en is control bit for CSx channel)
0 : Channel disable and sensing channel reset
1 : Channel enable
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8.2.3
Global option control register 1
Type: R/W
Address
Register Name
Bit7
Bit6
Bit5
Bit4
03h
global_ctrl1
-
mode_sel
cal_pause
Bit3
Bit2
response_ctrl
Bit1
Bit0
clk_off
sw_rst
Description
This register controls the global options of AGS04
Bit name
Reset value
Function
sw_rst
0
Software reset control bit.
0 : Not reset
1 : Reset
clk_off
0
System clock off control bit.
0 : Not clock off
1 : Clock off
Numbers of continuous touch detections for touch decision.
Response ctrl[2:0] + 1 (Maximum time : 7)
response_ctrl
011
cal_pause
0
Holding calibration for a while after touch off (about 200ms).
0 : Holding calibration disable
1 : Holding calibration enable
mode_sel
1
Single/Multi output operation mode selection bit.
0 : Single output mode
1 : Multi output mode
8.2.4
Interrupt mode
Type: R/W
Address
Register Name
Bit7
Bit6
03h
interrupt mode
-
-
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
int_mode
int_sel
sen_ctrl
Description
Using this register, select the interrupt mode between normal interrupt mode and pattern interrupt mode, And
this register controls sense frequency speed.
Bit name
Reset value
int_sel
0
Select interrupt operation mode
0 : Normal operation mode
1 : Pattern Sleep operation mode
int_mode
0
Interrupt output shape selection.
0 : Pulse mode (Interrupt mode A)
1 : Level mode (Interrupt mode B)
10
Sense frequency speed selection
00 : Fastest
01 : Fast
10 : Normal
11 : Slow
sen_ctrl
Function
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8.2.5
Sensitivity
Type: R/W
Address
Register Name
Bit7
04H~07H
Sensitivity1 ~
sensitivity4
-
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
sensitivity1 ~ sensitivity4
Description
AGS04 can control the sensitivities of all channels independently.
Bit name
Reset value
sensitivity1 ~
sensitivity4
0001001
8.2.6
Function
Sensitivities of each channel.
Sensitivity of CSx channel: {(sensitivityx[6:0] * 0.1) + 0.05} (%)
Sensitivity Limit
Type: R/W
Address
Register Name
Bit7
Bit6
08H~0BH
sen_limit1 ~
sen_limit4
-
-
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
sen_limit1 ~ sen_limit4
Description
AGS04 can control the sensitivity limit of all channels independently. The output data can be appeared when
the touch sensitivity is in between sensitivity and sensitivity limit. It is possible to make removing mal-function
in strong noisy environment.
Bit name
Reset value
sen_limit1 ~
sen_limit4
111111
Function
Sensitivity limit of each channel.
Sensitivity limit of CSx channel: {(sen_limitx[5:0] * 0.2) + 0.15} (%)
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8.2.7
Calibration speed control register of sense channel
Type: R/W
Address
Register Name
Bit7
0CH
cal. speed
-
Bit6
Bit5
Bit4
Bit3
cal_speed_up
Bit2
-
Bit1
Bit0
cal_speed_down
Description
Calibration speed of sense channels can be controlled by this „cal. speed‟ register. And if any calibration control
bits are set by “111”, the reference sense percent is updated immediately with the present sense percent.
Bit name
Reset value
Function
Down calibration speed of sense channels.
cal_speed_down
000 : Fastest
001 : Faster
010 : Fast
011 : Normal
011
100 : Slow
101 : Slower
110 : Slowest
111 : ref. percent present percent
Down calibration speed of sense channels.
cal_speed_down
8.2.8
000 : Fastest
001 : Faster
010 : Fast
011 : Normal
010
100 : Slow
101 : Slower
110 : Slowest
111 : ref. percent present percent
Calibration speed control register of dummy channel
Type: R/W
Address
Register Name
Bit7
0DH
dmCal. speed
-
Bit6
Bit5
dum_cal_speed_up
Bit4
Bit3
-
Bit2
Bit1
Bit0
dum_cal_speed_down
Description
Calibration speed of dummy channel can be controlled by this „dmCal. speed‟ register. And if any calibration
control bits are set by “111”, the reference dummy count is updated immediately with the present dummy count.
Bit name
Reset value
Function
Down calibration speed of dummy channel.
dum_cal_speed_down
011
000 : Fastest
001 : Faster
010 : Fast
011 : Normal
100 : Slow
101 : Slower
110 : Slowest
111 : ref. count present count
Down calibration speed of dummy channel.
dum_cal_speed_down
010
000 : Fastest
001 : Faster
010 : Fast
011 : Normal
100 : Slow
101 : Slower
110 : Slowest
111 : ref. count present count
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AGS04 (4-CH Differential Sensitivity Calibration Capacitive Touch Sensor)
8.2.9
Out Expiration
Type: R/W
Address
Register Name
Bit7
Bit6
0EH
out expiration
-
-
Bit5
Bit4
Bit3
Bit2
exp_time
Bit1
Bit0
exp_mode
exp_en
Description
This register controls expiration mode option of AGS04.
Bit name
Reset value
Function
exp_en
0
Output expiration enable control bit.
0 : Don‟t use output expiration
1 : Use output expiration
exp_mode
0
Output expiration time count mode selection bit.
0 : Expiration time counter is reset when any touch output is not appeared.
1 : Expiration time counter is reset when any output state is changed.
exp_time
0000
Output expiration Time control.
exp_time[3:0] x 4 ( seconds)
8.2.10 Variable period
Type: R/W
Address
Register Name
Bit7
Bit6
Bit5
16H
variable period
-
-
-
Bit4
Bit3
Bit2
Bit1
Bit0
var_period
Description
This register controls the sensing burst period.
Bit name
Reset value
var_period
01001
Function
Controls the sensing burst period
{(var_period[4:0] * 3.2) + 11.2} (ms)
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AGS04 (4-CH Differential Sensitivity Calibration Capacitive Touch Sensor)
8.2.11 Pattern sleep control register
Type: R/W
Address
Register Name
Bit7
1AH
pattern ctrl
-
Bit6
Bit5
patt2_mode
Bit4
Bit3
patt2_en
-
Bit2
Bit1
patt1_mode
Bit0
patt1_en
Description
This register controls the enable, disable and mode of pattern sleep. And AGS04 provides 2 pattern sleep.
Bit name
Reset value
Function
patt1_en
0
Enable pattern 1 sleep interrupt operation.
0 : Disable
1 : Enable
patt1_mode
00
Controls pattern 1 sleep interrupt mode.
00 : Slide type
01 : Touch to touch type
patt2_en
0
Enable pattern 2 sleep interrupt operation.
0 : Disable
1 : Enable
patt2_mode
00
Controls pattern 2 sleep interrupt mode.
00 : Slide type
01 : Touch to touch type
8.2.12 Pattern sleep inner counter register
Type: R/W
Address
Register Name
1BH
pattern cnt1
Bit7
Bit6
Bit5
Bit4
Bit3
patt2_inner_time
Bit2
Bit1
Bit0
patt1_inner_time
Description
This register controls the waiting time for coming next matched output data. If mismatched output data
appeared within waiting time or the time is to be same with the set value of “pattx_inner_time”, the pattern
sequence is expired and initialized the whole sequence factors. And this registers is valid for touch to touch
mode pattern sleep.
Bit name
Reset value
Function
patt1_inner_time
0000
Controls waiting time for next matched output data.
pattx_inner_time[3:0] * 40ms(1 sensing burst period)
patt2_inner_time
0000
Controls waiting time for next matched output data.
pattx_inner_time[3:0] * 40ms(1 sensing burst period)
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AGS04 (4-CH Differential Sensitivity Calibration Capacitive Touch Sensor)
8.2.13 Pattern sleep expiration counter register
Type: R
Address
Register Name
1CH
pattern cnt2
Bit7
Bit6
Bit5
Bit4
Bit3
patt2_expire_time
Bit2
Bit1
Bit0
patt1_expire_time
Description
This register controls the maximum time for finishing pattern sleep sequence. Pattern sleep sequence must be
done within the time of “pattx_expire_time”. If pattern sleep sequence is not done, the pattern sequence is
expired and initialized the whole sequence factors.
Bit name
Reset value
Function
patt1_expire_time
0000
Controls total time for pattern sleep sequence.
pattx_expire_time[3:0] * 320ms(8 sensing burst period)
patt2_expire_time
0000
Controls total time for pattern sleep sequence.
pattx_expire_time[3:0] * 320ms(8 sensing burst period)
8.2.14 Pattern sleep sequence number
Type: R
Address
Register Name
1DH
pattern num
Bit7
Bit6
Bit5
Bit4
Bit3
patt2_num
Bit2
Bit1
Bit0
patt1_num
Description
This register controls the pattern sleep sequence number.
Bit name
Reset value
Function
patt1_num
0000
Controls pattern sequence number
patt1_num[3:0]
patt2_num
0000
Controls pattern sequence number
patt2_num[3:0]
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AGS04 (4-CH Differential Sensitivity Calibration Capacitive Touch Sensor)
8.2.15 Pattern sleep channel pair 1
Type: R/W
Address
Register Name
1EH
pattern pair1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
patt2_pair1
Bit1
Bit0
patt1_pair1
Description
This register controls channel pairs. If the registers set „1‟, set channels become one. If one of set channels is
touched, it seems that all set channels are touched. For example, let the value of “patt1_pair1” “1100”. If the
touch output data is “1000” or “0100”, the output data is regarded “1100” in the pattern sleep operation. One
more example, if the generated touch output data is “1010” or “0110”, that output data is regarded “1110” in
the pattern sleep operation.
Bit name
patt1_pair1
patt2_pair1
Reset value
Function
0000
Controls channel pairs for pattern 1 sleep operation.
patt1_pair1[3] : CS4
patt1_pair1[2] : CS3
patt1_pair1[1] : CS2
patt1_pair1[0] : CS1
0000
Controls channel pairs for pattern 2 sleep operation.
patt2_pair1[3] : CS4
patt2_pair1[2] : CS3
patt2_pair1[1] : CS2
patt2_pair1[0] : CS1
8.2.16 Pattern sleep channel pair 2
Type: R/W
Address
Register Name
1FH
pattern pair2
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
patt2_pair2
Bit1
Bit0
patt1_pair2
Description
Same as pattern sleep channel pair 1. This register is possible to make 2 of channel pair
Bit name
patt1_pair2
patt2_pair2
Reset value
Function
0000
Controls channel pairs for pattern 1 sleep operation.
patt1_pair2[3] : CS4
patt1_pair2[2] : CS3
patt1_pair2[1] : CS2
patt1_pair2[0] : CS1
0000
Controls channel pairs for pattern 2 sleep operation.
patt2_pair2[3] : CS4
patt2_pair2[2] : CS3
patt2_pair2[1] : CS2
patt2_pair2[0] : CS1
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AGS04 (4-CH Differential Sensitivity Calibration Capacitive Touch Sensor)
8.2.17 Pattern sleep data A
Type: R/W
Address
Register Name
20H ~ 2EH
pattern A data1~
pattern A data15
Bit7
Bit6
Bit5
Bit4
Bit3
patt2a_data1 ~
patt2a_data15
Bit2
Bit1
Bit0
patt1a_data1 ~
patt1a_data15
Description
This register controls pattern sleep data. The pattern data is possible to extend up to 15.
Bit name
Reset value
patt1a_data1
~ patt1a_data15
patt2a_data1
~ patt2a_data15
Function
0000
Controls pattern sleep data.
patt1a_datax[3] : Output[3]
patt1a_datax[2] : Output[2]
patt1a_datax[1] : Output[1]
patt1a_datax[0] : Output[0]
0000
Controls channel pairs for pattern 2 sleep operation.
patt2a_datax[3] : Output[3]
patt2a_datax[2] : Output[2]
patt2a_datax[1] : Output[1]
patt2a_datax[0] : Output[0]
8.2.18 Pattern sleep data B
Type: R/W
Address
Register Name
30H ~ 3EH
pattern B data1~
pattern B data15
Bit7
Bit6
Bit5
Bit4
Bit3
patt2b_data1 ~
patt2b_data15
Bit2
Bit1
Bit0
patt1b_data1 ~
patt1b_data15
Description
This register controls pattern sleep data. The pattern data is possible to extend up to 15.
Bit name
patt1b_data1
~ patt1b_data15
patt2b_data1
~ patt2b_data15
Reset value
Function
0000
Controls pattern sleep data.
patt1b_datax[3] : Output[3]
patt1b_datax[2] : Output[2]
patt1b_datax[1] : Output[1]
patt1b_datax[0] : Output[0]
0000
Controls channel pairs for pattern 2 sleep operation.
patt2b_datax[3] : Output[3]
patt2b_datax[2] : Output[2]
patt2b_datax[1] : Output[1]
patt2b_datax[0] : Output[0]
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AGS04 (4-CH Differential Sensitivity Calibration Capacitive Touch Sensor)
8.2.19 Count, percent read register
Type: R
Address
Register Name
Bit7
Bit6
Bit5
40H
read CH head
-
-
-
41H
sen_H
-
-
42H
sen_L
43H
ref_H
44H
ref_L
45H
read CH tail
Bit4
Bit3
Bit2
Bit1
Bit0
ch_head
ref_data[13:8]
ref_data[7:0]
-
sense_data[14:8]
sense_data[7:0]
-
-
-
ch_tail
Description
AGS04 provides the special function to read sense count/percent or reference count/percent.
Bit name
Reset value
Function
ch_head
Read only
Read channel indication register.
00001 : R.N.D channel
00010 : CS1 channel
00100 : CS2 channel
01000 : CS3 channel
10000 : CS4 channel
ref_data[13:8]
Read only
Reference data of R.N.D, sense channels.
Reference count [13:8] at R.N.D channel.
Reference percent [8] at sense channels, ignore ref_data[13:9].
ref_data[7:0]
Read only
Reference data of R.N.D, sense channels.
R.N.D reference count [7:0] at R.N.D channel.
Sense reference percent [7:0] at sense channels.
sense_data[14:8]
Read only
Present data of R.N.D, sense channels.
R.N.D present count [13:8] at R.N.D channel, ignore sense_data[14].
Sense present count [14:8] at sense channels. sense_data[14] is sign bit.
sense_data[7:0]
Read only
Present data of R.N.D, sense channels.
R.N.D present count [7:0] at R.N.D channel.
Sense present count [7:0] at sense channels.
Read only
Read channel indication register.
00001 : R.N.D channel
00010 : CS1 channel
00100 : CS2 channel
01000 : CS3 channel
10000 : CS4 channel
ch_tail
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AGS04 (4-CH Differential Sensitivity Calibration Capacitive Touch Sensor)
9 Recommended Circuit Diagram
9.1 Application Example in clean power environment
AGS04 Application Example Circuit (Clean power environment)
The CS patterns also should be routed as short as possible and the width of line might be
about 0.25mm (or narrower line).
The capacitor that is between VDD and GND is an obligation. It should be located as close as
possible from AGS04.
The CS pattern routing should be formed by bottom metal (opposite metal of touch PAD).
The empty space of PCB must be filled with GND pattern to strengthen GND pattern and to
prevent external noise from interfere with sensing frequency.
The AGS04 is reset when power rise from 0V to proper VDD
The GND should be short in the system and the lines are recommended to be split from the
most low impedance ground point to avoid ground bouncing problems.
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9.2 Application Example in noisy environment
TS06 Application Example Circuit (Noisy environment)
The VDD periodic voltage ripple over 50mV and the ripple frequency is lower than 10 kHz can
cause wrong sensitivity calibration. To prevent above problem, power (VDD, GND) line of touch
circuit should be separated from other circuit. Especially LED driver power line or digital
switching circuit power line certainly should be treated to be separated from touch circuit.
Thanks to the RRND, RS1, RS2, RS3, RS4, CCS00, CCS01, CCS02, CCS03, CCS04, CCS10,
CCS11, CCS12, CCS13 and CCS14, the noise immunity could be improved.
CCS00 ~ CCS14 is required to control the parasitic capacitance of each channels.
The GND should be short in the system and the lines are recommended to be split from the
most low impedance ground point to avoid ground bouncing problems
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9.3 Example – Power Line Split Strategy PCB Layout
A. Not split power line (Bad power line design)
The noise that is generated by AC load or relay can be loaded at 5V power line.
A big inductance might be appeared in case of the connection line between main board and
display board is too long, moreover the voltage ripple could be generated by LED (LCD)
display driver at VDD (5V).
B. Split power line (One 5V regulator used) – Recommended
C. Split power line (Separated 5V regulator used) – Strongly recommended
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AGS04 (4-CH Differential Sensitivity Calibration Capacitive Touch Sensor)
10 MECHANICAL DRAWING
NOTE: Dimensions are in millimeters
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11 MARKING DESCRIPTION
Device Code
: AGS 4
Channel Number
Touch Switch Group
Weekly Code
: YY WW
Manufacturing Year
Manufacturing Week
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NOTES:
LIFE SUPPORT POLICY
AD SEMICONDUCTOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN
LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE
PRESIDENT AND GENERAL COUNSEL OF AD SEMICONDUCTOR CORPORATION
The ADS logo is a registered trademark of ADSemiconductor
ⓒ 2006 ADSemiconductor – All Rights Reserved
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