8-bit MCU for automotive, 16 Kbyte Flash/ROM, 10

ST7232AK1-Auto ST7232AK2-Auto
ST7232AJ1-Auto ST7232AJ2-Auto
8-bit MCU for automotive, 16 Kbyte Flash/ROM,
10-bit ADC, 4 timers, SPI, SCI
Features
■
■
■
■
■
Memories
– 8K dual voltage high density Flash
(HDFlash) or ROM with read-out protection
capability. In-application programming and
in-circuit programming for HDFlash devices
– 384 bytes RAM
– HDFlash endurance: 100 cycles, data
retention: 20 years at 55°C
Clock, reset and supply management
– Clock sources: crystal/ceramic resonator
oscillators and bypass for external clock
– PLL for 2x frequency multiplication
– Four power saving modes: halt, active halt,
wait and slow
Interrupt management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and reset
– 6 external interrupt lines (on 4 vectors)
Table 1.
– Main clock controller with: real time base,
beep and clock-out capabilities
– Configurable watchdog timer
– Two 16-bit timers with: 2 input captures, 2
output compares, PWM and pulse
generator modes
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2 communications interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface
■
1 analog peripheral (low current coupling)
– 10-bit ADC with up to 12 robust input ports
■
Instruction set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
■
Development tools
– Full hardware/software development
package
– In-circuit testing capability
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4 timers
LQFP44 10 x 10
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Up to 32 I/O ports
– 32/24 multifunctional bidirectional I/O lines
– 22/17 alternate function lines
– 12/10 high sink outputs
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LQFP32 7 x 7
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Device summary
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Program memory - bytes RAM (stack) - bytes Operating volt. Temp. range Package
ST72F32AK1-Auto
Flash 4K
ST72F32AK2-Auto
Flash 8K
ST72F32AJ1-Auto
Flash 4K
ST72F32AJ2-Auto
Flash 8K
ST7232AK1-Auto
ROM 4K
ST7232AK2-Auto
ROM 8K
ST7232AJ1-Auto
ROM 4K
ST7232AJ2-Auto
ROM 8K
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LQFP32
LQFP44
384 (256)
3.8V to 5.5V
-40°C to
+125°C
LQFP32
LQFP44
January 2008
Rev 1
1/201
www.st.com
1
Contents
ST7232Axx-Auto
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2
Differences between ST7232A-Auto and ST7232A datasheets . . . . . . . . 15
1.2.1
Principal differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2.2
Minor content differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2.3
Editing and formatting differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.5
In-Circuit Programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.6
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.7
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1
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CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3
Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4
Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.1
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4.2
Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
ST7232Axx-Auto
6.5
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.6
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6.5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5.2
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.5.3
External power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.5.4
Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
System integrity management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2
Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.1
Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.2
Different interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.3
Non-maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2.4
Maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.4
Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5
Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.6
Interrupt related instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.7
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.8
External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.9
Nested interrupts register map and reset value . . . . . . . . . . . . . . . . . . . . 53
7.10
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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8.2
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Active halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.4.1
Active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.4.2
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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ST7232Axx-Auto
9.2.1
Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2.2
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.2.3
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.3
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1
Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.1.4
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.1.5
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.1.6
Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.1.7
Using halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 72
10.1.8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.1.9
Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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10.1.10 Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . 73
10.2
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Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 73
10.2.1
Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.2.2
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.3
Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.4
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.2.6
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Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.2.7
MCC/RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.2.8
MCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.3.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.3.6
Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.3.7
16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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10.3
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16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ST7232Axx-Auto
Contents
10.4
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.5
10.6
11
10.4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.4.4
Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
10.4.5
Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.4.6
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
10.4.7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
10.4.8
SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.5.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.5.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10.5.4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10.5.5
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.5.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.5.7
SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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10.6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.6.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.6.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.6.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.6.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.6.6
10-bit ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
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11.1.1
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Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.1.2
Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.1.3
Direct instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.1.4
Indexed instructions (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . 147
11.1.5
Indirect instructions (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.1.6
Indirect indexed instructions (short, long) . . . . . . . . . . . . . . . . . . . . . . 148
11.1.7
Relative mode instructions (direct, indirect) . . . . . . . . . . . . . . . . . . . . . 149
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CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.2
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
11.3
Using a pre-byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
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ST7232Axx-Auto
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1
12.2
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.2.1
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.2.2
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.2.3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.5
12.6
12.7
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.4.2
Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.4.3
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
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Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
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General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.5.2
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.5.3
Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 162
12.5.4
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
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Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
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RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.6.2
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
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12.4.1
12.7.1
Functional electromagnetic susceptibility (EMS) . . . . . . . . . . . . . . . . . 165
12.7.2
Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.7.3
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 167
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.8.1
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.8.2
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.9.1
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.9.2
ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.10 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.10.1 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
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Contents
12.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 175
12.11.1 SPI (serial peripheral interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
12.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.12.1 Analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 179
12.12.2 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
12.12.3 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
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Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
13.3
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
14.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.2
Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
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Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.2.2
Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
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ROM device ordering information and transfer of customer code . . . . . 188
14.4
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.2
Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.3
Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.4
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4.5
Socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 193
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ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
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Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
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Device configuration and ordering information . . . . . . . . . . . . . . . . . 185
All Flash and ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.1
Safe connection of OSC1/OSC2 pins . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.2
External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.3
Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
15.1.4
Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 196
15.1.5
16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
15.1.6
TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 197
15.1.7
SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
15.1.8
39-pulse ICC entry mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
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Contents
ST7232Axx-Auto
15.2
16
ROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.2.1
I/O port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.2.2
External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
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ST7232Axx-Auto
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ST7 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CPU CC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ISPRx interrupt vector correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
EICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Active halt and halt power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DR register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I/O Port Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Port register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
I/O interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Effect of low power modes on watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
WDGCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Effect of low power modes on MCC/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
MCC/RTC interrupt control/wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
MCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
MCCBCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
16-bit timer interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
CR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
CR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
CSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
SPI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SPICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SPICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SCI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SCISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SCICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
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List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
ST7232Axx-Auto
SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
SCIBRR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SCIERPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SCIETPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Effect of low power modes on 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
ADCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
ADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
ADCDRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
CPU addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 148
Short instructions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Relative mode instructions (direct and indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Supply current of clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Oscillator parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Examples of typical resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Characteristics of dual VOLTAGE HDFlash MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Electromagnetic test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Latch up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
I/O general port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
ICCSEL/VPP pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
ADC accuracy with VDD = 5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
32-pin LQFP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
44-pin LQFP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . 184
Flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Option byte 0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
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Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
List of tables
Option byte 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Package selection (OPT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Flash user programmable device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
FASTROM factory coded device types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
ROM factory coded device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
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List of figures
ST7232Axx-Auto
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
32-pin LQFP 7x7 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
44-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory map and sector addresses of the ST7232X family . . . . . . . . . . . . . . . . . . . . . . . . 28
Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Wait mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Active halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Active halt Mode Flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Halt mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Exact timeout duration (tmin and tmax). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Output compare block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Output compare timing diagram, fTIMER = fCPU/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
One pulse mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Pulse width modulation mode timing example with 2 output compare functions . . . . . . . . 91
Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Generic SS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
List of figures
Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 111
Single master/multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
fCPU max versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Typical IDD in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Typical IDD in slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Typical IDD in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Typ. IDD in slow wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Integrated PLL jitter vs signal frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Unused I/O pins configured as input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Typical IPU vs. VDD with VIN = VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Typical VOL at VDD = 5V (std. ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Typ. VOL at VDD = 5V (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Typical VOH at VDD = 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Typical VOL vs. VDD (std. ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Typical VOL vs. VDD (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Typical VOH vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
RESET pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Two typical applications with ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
SPI slave timing diagram with CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
SPI slave timing diagram with CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
RAIN max. vs fADC with CAIN = 0pF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Recommended CAIN and RAIN values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
32-pin LQFP outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
44-pin LQFP outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Flash commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
FASTROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
ROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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Introduction
ST7232Axx-Auto
1
Introduction
1.1
Description
The ST7232AK1-Auto, ST7232AK2-Auto, ST7232AJ1-Auto, and ST7232AJ2-Auto devices
are members of the ST7 microcontroller family designed for the 5V operating range.
The 32 and 44-pin devices are designed for mid-range applications
All devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set and are available with Flash or ROM program memory.
Under software control, all devices can be placed in wait, slow, active halt or halt mode,
reducing power consumption when the application is in idle or stand-by state.
The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8 x 8 unsigned multiplication and indirect addressing modes.
Figure 1.
Device block diagram
8-bit core
ALU
RESET
VPP
OSC1
OSC
OSC2
e
t
le
u
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P
e
PORT F
Timer A
ADDRESS AND DATA BUS
)
s
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o
s
b
O
-
MCC/RTC/beep
t
e
l
o
Program
memory
(8K bytes)
Control
VSS
VDD
o
r
P
RAM
(384 bytes)
Watchdog
Port A
Port B
Beep
Port E
bs
Port C
SCI
O
Timer B
Port D
SPI
10-bit ADC
VAREF
VSSA
14/201
c
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ST7232Axx-Auto
1.2
Introduction
Differences between ST7232A-Auto and ST7232A datasheets
The differences between the ST7232A-Auto datasheet, version 1, released in January 2008
and the ST7232A datasheet, version 2, released in December 2005 are listed below.
Differences are categorised as follows:
1.2.1
●
Principal differences
●
Minor content differences
●
Editing and formatting differences
Principal differences
1.
Changed root part number from ST7232A to ST7232AK1-Auto, ST7232AK2-Auto,
ST7232AJ1-Auto, and ST7232AJ2-Auto throughout document
2.
Changed document title on page 1
3.
Removed 1 and 5 suffix version temperatures ranges throughout the document
4.
Features on page 1: Changed minimum value of data retention time (tRET) to 20 years
and changed the condition to TA = 55°C
5.
Table 2: Device pin description on page 21: Added footnote (5)
6.
Section 6.3: Phase locked loop (PLL) on page 36: Added caution regarding use of PLL
with an external clock
7.
Reset vector fetch on page 38: Added a ‘caution’ about the reset vector when it is not
programmed
8.
Section 9.2.1: Input modes on page 62: Amended note3 of this section
9.
Section 9.3: I/O port implementation on page 66: Deleted I/O port implementation
tables
c
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10. Output compare on page 85: Amended text in note 3
11. Figure 41: Output compare timing diagram, fTIMER = fCPU/4 on page 88: Removed
compare register i Latch from diagram
)
s
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12. Section 10.6: 10-bit A/D converter (ADC) on page 139: Amended text concerning the
EOC bit in Starting the conversion
13. Table 70: Current characteristics on page 155:
u
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–
Added data for the LQFP44 package to IVDD and IVSS
–
Updated max IIO values for standard I/O and high sink I/O
r
P
e
14. Table 72: General operating conditions on page 156: Updated temperature ranges in
the ‘conditions’ column
t
e
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o
15. Table 82: Characteristics of dual VOLTAGE HDFlash MEMORY on page 164:
O
bs
–
Changed typical value of supply current (IDD) to < 10µA
–
Changed minimum value of data retention time (tRET) to 20 years and changed the
condition to TA = 55°C
–
Changed the condition of write erase cycle (NRW) to TA = 85°C
16. Section 12.7.3: Absolute maximum ratings (electrical sensitivity) on page 167:
Removed text concerning dynamic latch-up
17. Electro-static discharge (ESD) on page 167: Replaced JESD22-A114A/A115A
standard with AEC-Q100-002/003/011 standard
15/201
Introduction
ST7232Axx-Auto
18. Table 85: ESD absolute maximum ratings on page 167:
–
Added test standards to conditions column
–
Changed max value of CDM from 250 V to: > 500 V to ≤ 750 V with corner pins >
750 V
–
Added ‘class’ information
19. Static latch-up on page 167: Added ‘AEC-Q100/004’ standard
20. Table 86: Latch up results on page 167:
–
Removed TA = +25°C, +85°C and +105°C from latch-up conditions
–
Added AEC-Q100/004 test standard
–
Removed dynamic latch-up results
–
Changed ‘class’ information
–
Removed footnote 1 pertaining to class descriptions and JEDEC standards
21. Table 87: I/O general port pin characteristics on page 168:
–
Added footnote (3) and (5)
–
Amended footnote (4)
)
s
t(
22. Figure 76: RESET pin protection on page 173: Removed EMC protective circuitry
(device works correctly without these components)
c
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23. Table 92: SPI characteristics on page 175:
(1)
(2)
o
r
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–
Added footnote
–
Updated max and unit information of tv(MO)
–
Updated min values of th(MO)
–
Updated min and max values for ‘data output valid’ and ‘data output hold’ times
and
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24. Figure 80: SPI master timing diagram on page 177: Modified figure to reflect changes
made in Table 92: SPI characteristics concerning tv(MO) and th(MO)
25. Table 93: 10-bit ADC characteristics on page 178:
–
Removed word ‘positive’ from explanation of Ilkg parameter
–
Updated footnote (2)
)
s
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26. Figure 83: Typical A/D converter application on page 179: Changed IL ± 1µA to Ilkg
27. Table 94: ADC accuracy with VDD = 5.0V on page 181:
–
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Made the ‘conditions’ applicable for all parameters
r
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e
–
Updated footnote (2)
28. Table 97: Thermal characteristics on page 184:
t
e
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O
–
Amended footnotes (1) and (2)
–
Added a value for LQFP44
29. Table 99: Flash option bytes on page 185:
–
Changed bits 4 and 3 of option byte 0 to a default value of ‘1’
–
Changed the OSCRANGE bits [2:0] of option byte 1 from 111 to 011
–
Added footnote 1 concerning package selection
30. Updated Table 100: Option byte 0 description on page 186
31. Updated Table 101: Option byte 1 description on page 186
32. Added Table 102: Package selection (OPT7) on page 187
33. Section 15.1.2: External interrupt missed on page 194: Added section on ‘external
interrupt missed’ bug
16/201
ST7232Axx-Auto
Introduction
34. Section 15.1.6: TIMD set simultaneously with OC interrupt on page 197:
1.2.2
–
Added section concerning limitation of the 16-bit timer
–
Added ‘TBCR1’, ‘TBCSR I’ and ‘TBCSR &’ to the workaround subsection
Minor content differences
1.
Removed all references to the SDIP32 and SDIP42 packages (which are unavailable in
automotive) thoughout document
2.
Replaced TQFP by LQFP throughout document
3.
Table 3: Hardware register map on page 25: Replaced ‘h’ with ‘b’ in the reset status
column for the SCICR1 register
4.
System integrity control/status register (SICSR) on page 41: Replaced ‘h’ with ‘b’ in the
reset value cell of the SICSR register
5.
Table 43: SPI register map and reset values on page 117: Changed the name of bit 5 in
the SPICSR register from OR to OVR
6.
Break character on page 123: SPI replaced by SCI
7.
Control register 1 (SCICR1) on page 133: Replaced ‘h’ with ‘b’ in the reset value cell of
the SCICR1 register
8.
Changed IL to Ilkg in Table 77: External clock source on page 161, Figure 65: Typical
application with an external clock source on page 161 and Table 90: ICCSEL/VPP pin
characteristics on page 174
9.
Table 95: 32-pin LQFP mechanical data on page 182 and Table 96: 44-pin LQFP
mechanical data on page 183: Altered ‘inches’ data to four decimal places
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10. Section 13.3: Soldering information on page 184:
o
s
b
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-
–
Updated environmental information regarding ‘ECOPACK®’ packages
–
Replaced ECOPACKTM with ECOPACK® throughout the document
–
Updated section on ECOPACK® soldering compatability
11. Table 98: Soldering compatibility (wave and reflow soldering process) on page 184:
Removed footnote on Pb package maximum temperature
)
s
(
ct
12. Updated Table 103: Flash user programmable device types on page 187
13. Added Figure 88: Flash commercial product code structure on page 188
u
d
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14. Updated Section 14.3: ROM device ordering information and transfer of customer code
on page 188
r
P
e
15. Added Table 104: FASTROM factory coded device types on page 189
16. Added Figure 89: FASTROM commercial product code structure on page 189
t
e
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o
17. Added Table 105: ROM factory coded device types on page 190
s
b
O
18. Updated Figure 90: ROM commercial product code structure on page 190
19. Updated ST72P32A/ST7232A (3.8 to 5.5V) microcontroller option list on page 191
20. Updated Table 106: STMicroelectronics development tools on page 193
21. Section 14.4: Development tools on page 192:
–
Updated Introduction and Programming tools
–
Deleted Emulators and In-circuit debugging kit
–
Added Evaluation tools and starter kits and Development and debugging tools
22. Section 14.5: ST7 application notes on page 193: Removed list of ST7 application
notes
17/201
Introduction
1.2.3
ST7232Axx-Auto
Editing and formatting differences
1.
Reformatted document
2.
Converted register and bit decriptions to table format
3.
Edited English throughout document
4.
Correctly aligned footnotes of tables throughout document
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18/201
o
s
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O
-
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)
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ST7232Axx-Auto
2
Pin description
Pin description
32-pin LQFP 7x7 package pinout
PD1/AIN1
PD0/AIN0
PB4 (HS)
PB3
PB0
PE1/RDI
PE0/TDO
VDD_2
Figure 2.
VAREF
VSSA
OSC1
OSC2
VSS_2
RESET
VPP/ICCSEL
PA7 (HS)
PA6 (HS)
PA4 (HS)
AIN13/OCMP1_B/PC1
ICAP2_B/(HS) PC2
ICAP1_B/(HS) PC3
ICCDATA/MISO/PC4
AIN14/MOSI/PC5
ICCCLK/SCK/PC6
AIN15/SS/PC7
(HS) PA3
MCO/AIN8/PF0
Beep/(HS) PF1
OCMP1_A/AIN10/PF4
ICAP1_A/(HS) PF6
EXTCLK_A/(HS) PF7
AIN12/OCMP2_B/PC0
32 31 30 29 28 27 26 25
24
1
ei3 ei2
23
2
22
3
ei1
21
4
20
5
19
6
18
7
ei0 17
8
9 10 11 12 13 14 1516
e
t
le
c
u
d
)
s
t(
o
r
P
o
s
b
O
-
1. Legend: (HS) = 20mA high sink capability; eix = associated external interrupt vector
)
s
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19/201
Pin description
ST7232Axx-Auto
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
ei0 31
ei2
4
30
5
29
6 ei3
28
7
27
8
26
9
25
ei1
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
VSS_1
VDD_1
PA3 (HS)
PC7/SS/AIN15
PC6/SCK/ICCCLK
PC5/MOSI/AIN14
PC4/MISO/ICCDATA
PC3 (HS)/ICAP1_B
PC2 (HS)/ICAP2_B
PC1/OCMP1_B/AIN13
PC0/OCMP2_B/AIN12
AIN5/PD5
VAREF
VSSA
MCO/AIN8/PF0
Beep/(HS) PF1
(HS) PF2
OCMP1_A/AIN10/PF4
ICAP1_A/(HS) PF6
EXTCLK_A/(HS) PF7
VDD_0
VSS_0
RDI/PE1
PB0
PB1
PB2
PB3
(HS) PB4
AIN0/PD0
AIN1/PD1
AIN2/PD2
AIN3/PD3
AIN4/PD4
VPP/ICCSEL
PA7 (HS)
PA6 (HS)
PA5 (HS)
PA4 (HS)
44-pin LQFP package pinout
PE0/TDO
VDD_2
OSC1
OSC2
VSS_2
RESET
Figure 3.
e
t
le
c
u
d
)
s
t(
o
r
P
1. Legend: (HS) = 20mA high sink capability; eix = associated external interrupt vector
o
s
b
O
-
For external pin connection guidelines, refer to Section 12: Electrical characteristics on
page 153.
In Table 2: Device pin description below, refer to Section 9: I/O ports on page 62 for more
details on the software configuration of the I/O ports. The RESET configuration of each pin
is shown in bold. This configuration is valid as long as the device is in reset state. For
external pin connection guidelines refer to Section 12: Electrical characteristics on
page 153.
)
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20/201
ST7232Axx-Auto
Table 2.
Pin description
Device pin description(1)
Pin
no.
Port
30 PB4 (HS)
I/O CT HS
X
7
31 PD0/AIN0
I/O CT
X
X
8
32 PD1/AIN1
I/O CT
X
9
(4)
-
PD2/AIN2
I/O CT
10
-(4)
PD3/AIN3
(4)
Alternate function
X
X
X
Port D0
ADC analog input 0
X
X
X
X
Port D1
ADC analog input 1
X
X
X
X
X
Port D2
ADC analog Input 2
I/O CT
X
X
X
X
X
Port D3
ADC analog Input 3
PD4/AIN4
I/O CT
X
X
X
X
X
Port D4
ADC analog Input 4
12 -(4) PD5/AIN5
I/O CT
X
X
X
X
X
Port D5
ADC analog Input 5
11 -
13
1
VAREF(5)
(5)
ei3
)
s
t(
S
Analog reference voltage for ADC
S
Analog ground voltage
14
2
VSSA
15
3
PF0/MCO/AIN8
I/O CT
X
ei1
16
4
PF1 (HS)/Beep
I/O CT HS
X
ei1
I/O CT HS
X
I/O CT
X
X
17 -(4) PF2 (HS)
ana
Port B4
int(2)
X
wpu
X
float
PP
Output
Main
function
(after
reset)
OD(3)
Output
6
Input
LQFP32
Input
LQFP44
Pin name
Type
Level
X
ei1
c
u
d
Main clock
out (fCPU)
ADC analog
input 8
X
X
Port F0
X
X
Port F1
X
X
Port F2
X
X
Port F4
Timer A output ADC analog
compare 1
input 10
X
X
Port F6
Timer A input capture 1
X
X
Port F7
Timer A external clock source
e
t
le
o
r
P
Beep signal output
18
5
PF4/OCMP1_A/
AIN10
19
6
PF6 (HS)/ICAP1_A I/O CT HS
X
X
20
7
PF7
(HS)/EXTCLK_A
X
X
21
-
VDD_0(5)
S
22
-
VSS_0
(5)
S
23
8
PC0/OCMP2_B/
AIN12
I/O CT
X
X
X
X
X
Port C0
Timer B output ADC analog
compare 2
input 12
24
9
PC1/OCMP1_B/
AIN13
I/O CT
X
X
X
X
X
Port C1
Timer B output ADC analog
compare 1
input 13
PC2
(HS)/ICAP2_B
I/O CT HS
X
X
X
X
Port C2
Timer B input capture 2
PC3
(HS)/ICAP1_B
I/O CT HS
X
X
X
X
Port C3
Timer B input capture 1
PC4/MISO/
ICCDATA
I/O CT
X
X
X
X
Port C4
SPI master in/ ICC data
slave out data input
28 13 PC5/MOSI/AIN14
I/O CT
X
X
X
X
Port C5
SPI master out ADC analog
/slave in data input 14
29 14 PC6/SCK/ICCCLK
I/O CT
X
X
X
X
Port C6
SPI serial
clock
bs
26 11
O
27 12
o
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P
e
t
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25 10
I/O CT HS
c
u
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(t s)
X
o
s
b
O
-
Digital main supply voltage
Digital ground voltage
X
ICC clock
output
21/201
Pin description
ST7232Axx-Auto
Device pin description(1) (continued)
Port
X
X
31 16 PA3 (HS)
I/O CT HS
X
32
33
ei0
PP
wpu
I/O CT
Output
Main
function
(after
reset)
OD(3)
float
30 15 PC7/SS/AIN15
int(2)
Input
Output
Input
Pin name
Type
Level
LQFP32
LQFP44
Pin
no.
ana
Table 2.
X
X
X
Port C7
X
X
Port A3
Alternate function
SPI slave
select (active
low)
-
VDD_1(5)
S
Digital main supply voltage
-
(5)
S
Digital ground voltage
VSS_1
I/O CT HS
X
X
X
X
Port A4
PA5 (HS)
I/O CT HS
X
X
X
X
Port A5
36 18 PA6 (HS)
I/O CT HS
X
T
Port A6
37 19 PA7 (HS)
I/O CT HS
X
T
Port A7
34 17 PA4 (HS)
(4)
35 -
38 20 VPP/ICCSEL
S
41 23 OSC2(6)
O
42 24 OSC1(6)
I
43 25 VDD_2(5)
S
40 22 VSS_2
e
t
le
so
I/O CT
(5)
r
P
e
(s)
t
c
u
od
44 26 PE0/TDO
b
O
-
Digital ground voltage
Resonator oscillator inverter output
External clock input or resonator
oscillator inverter input
Digital main supply voltage
I/O CT
X
X
X
X
Port E0
SCI transmit data out
I/O CT
X
X
X
X
Port E1
SCI receive data in
I/O CT
X
ei2
X
X
Port B0
Caution: Negative current
injection not allowed on this
pin(7)
27 PE1/RDI
2
28 PB0
3
-(4) PB1
I/O CT
X
ei2
X
X
Port B1
4
-(4) PB2
I/O CT
X
ei2
X
X
Port B2
5
29 PB3
I/O CT
X
X
X
Port B3
s
b
O
o
r
P
Top priority non maskable interrupt.
1
t
e
l
o
c
u
d
)
s
t(
Must be tied low. In the Flash
programming mode, this pin acts as the
programming voltage input VPP. See
Section 12.9.2 for more details. High
voltage must not be applied to ROM
devices.
I
39 21 RESET
ADC analog
input 15
ei2
1. Legend/abbreviations for Table 2:
Type: I = input, O = output, S = supply
Input level: CT = CMOS 0.3VDD/0.7VDD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration inputs: float = floating, wpu = weak pull-up, int = interrupt, ana = analog ports
Port and control configuration outputs: OD = open drain, PP = push-pull
2. ‘eiX’ defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column
(int), then the I/O configuration is pull-up interrupt input; otherwise the configuration is floating interrupt input
22/201
ST7232Axx-Auto
Pin description
3. ‘T’ defines a true open drain I/O (P-buffer and protection diode to VDD are not implemented). See Section 9: I/O ports on
page 62 and Section 12.8: I/O port pin characteristics for more details
4. Each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The
configuration of these pads must be kept at reset state to avoid added current consumption.
5. It is mandatory to connect all available VDD and VAREF pins to the supply voltage and all VSS and VSSA pins to ground
6. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1:
Introduction and Section 12.5: Clock and timing characteristics for more details
7. For details refer to Section 12.8.1: General characteristics on page 168
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Register and memory map
3
ST7232Axx-Auto
Register and memory map
As shown in <Blue HT>Figure 4, the MCU is capable of addressing 64K bytes of memories
and I/O registers.
The available memory locations consist of 128 bytes of register locations, up to 384 bytes of
RAM and up to 8 Kbytes of user program memory. The RAM space includes up to 256 bytes
for the stack from 0100h to 01FFh.
The highest address bytes contain the user reset and interrupt vectors.
Caution:
Memory locations marked as ‘reserved’ must never be accessed. Accessing a reserved
area can have unpredictable effects on the device.
Figure 4.
Memory map
0080h
0000h
Short addressing
RAM (zero page)
HW registers
(see Table 3)
007Fh
0080h
00FFh
0100h
01FFh
0200h
027Fh
or 047Fh
Reserved
e
t
le
E000h
Program memory
(4K or 8K)
(see Table 15)
)
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o
s
b
O
-
Interrupt and reset vectors
FFFFh
r
P
e
o
r
P
Reserved
047Fh
0480h
FFDFh
FFE0h
c
u
d
256 bytes stack
RAM
(384 bytes)
E000h
8 Kbytes
F000h
FFFFh
4 Kbytes
)
s
t(
ST7232Axx-Auto
Table 3.
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
Register and memory map
Hardware register map
Block
Register label
(3)
PADR
PADDR
PAOR
Port A data register
Port A data direction register
Port A option register
00h(4)
00h
00h
R/W
R/W
R/W
(3)
PBDR
PBDDR
PBOR
Port B data register
Port B data direction register
Port B option register
00h(4)
00h
00h
R/W
R/W
R/W
PCDR
PCDDR
PCOR
Port C data register
Port C data direction register
Port C option register
00h(4)
00h
00h
R/W
R/W
R/W
(3)
PDADR
PDDDR
PDOR
Port D data register
Port D data direction register
Port D option register
00h(4)
00h
00h
R/W
R/W
R/W
(3)
PEDR
PEDDR
PEOR
Port E data register
Port E data direction register
Port E option register
00h(4)
00h
00h
R/W
R/W(3)
R/W(3)
(3)
PFDR
PFDDR
PFOR
Port F data register
Port F data direction register
Port F option register
00h(4)
00h
00h
R/W
R/W
R/W
Port A
Port B
Port C
Port D
Port E
Port F
0012h to
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
Reserved area (15 bytes)
SPI
ITC
0028h
0029h
002Ah
Flash
SPIDR
SPICR
SPICSR
SPI data I/O register
SPI control register
SPI control/status register
ISPR0
ISPR1
ISPR2
ISPR3
002Eh to
0030h
Interrupt software priority register 0
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
EICR
External interrupt control register
00h
R/W
FCSR
Flash control/status register
00h
R/W
7Fh
R/W
00h
00h
R/W
R/W
(s)
ct
e
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o
s
b
O
-
Watchdog control register
du
MCCSR
MCCBCR
o
r
P
e
t
e
l
o
o
r
P
R/W
R/W
R/W
Watchdog WDGCR
MCC
c
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)
s
t(
xxh
0xh
00h
002Bh
002Ch
002Dh
Reset status(1) Remarks(2)
Register name
Reserved area (1 byte)
Main clock control/status register
Main clock controller: beep control register
Reserved area (3 bytes)
s
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25/201
Register and memory map
Table 3.
Address
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
ST7232Axx-Auto
Hardware register map (continued)
Block
Timer A
Register label
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A control register 2
Timer A control register 1
Timer A control/status register
Timer A input capture 1 high register
Timer A input capture 1 low register
Timer A output compare 1 high register
Timer A output compare 1 low register
Timer A counter high register
Timer A counter low register
Timer A alternate counter high register
Timer A alternate counter low register
Timer A input capture 2 high register
Timer A input capture 2 low register
Timer A output compare 2 high register
Timer A output compare 2 low register
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
Timer B
SCI
O
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B control register 2
Timer B control register 1
Timer B control/status register
Timer B input capture 1 high register
Timer B input capture 1 low register
Timer B output compare 1 high register
Timer B output compare 1 low register
Timer B counter high register
Timer B counter low register
Timer B alternate counter high register
Timer B alternate counter low register
Timer B input capture 2 high register
Timer B input capture 2 low register
Timer B output compare 2 high register
Timer B output compare 2 low register
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCI status register
SCI data register
SCI baud rate register
SCI control register 1
SCI control register 2
SCI extended receive prescaler register
Reserved area
SCI extended transmit prescaler register
o
r
P
e
t
e
l
o
bs
00h
00h
xxxx x0xxb
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W
00h
00h
xxxx x0xxb
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W
C0h
xxh
00h
x000 0000b
00h
00h
Read only
R/W
R/W
R/W
R/W
R/W
Reserved area (1 byte)
0058h to
006Fh
0070h
0071h
0072h
Reset status(1) Remarks(2)
Register name
ADC
0073h
007Fh
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SCIETPR
ADCCSR
ADCDRH
ADCDRL
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(t s)
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)
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00h
R/W
00h
00h
00h
R/W
Read only
Read only
Reserved area (24 bytes)
Control/status register
Data high register
Data low register
Reserved area (13 bytes)
1. x = undefined
2. R/W = read/write
3. The bits associated with unavailable pins must always keep their reset value
4. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents
26/201
ST7232Axx-Auto
Flash program memory
4
Flash program memory
4.1
Introduction
The ST7 dual voltage high density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external VPP supply.
The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).
The array matrix organisation allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
Main features
●
4.3
Three Flash programming modes:
)
s
t(
–
Insertion in a programming tool. In this mode, all sectors including option bytes
can be programmed or erased
–
ICP (in-circuit programming). In this mode, all sectors including option bytes can
be programmed or erased without removing the device from the application board
–
IAP (in-application programming) In this mode, all sectors except sector 0, can be
programmed or erased without removing the device from the application board
and while the application is running
c
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●
ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
●
Read-out protection
●
Register access security system (RASS) to prevent accidental programming or erasing
)
s
(
ct
Structure
o
s
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O
-
u
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o
The Flash memory is organised in sectors and can be used for both code and data storage.
Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (see Table 4). Each of these sectors can be erased independently to
avoid unnecessary erasing of the whole Flash memory when only a partial erasing is
required.
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The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
sector 0 (F000h-FFFFh).
Table 4.
Sectors available in Flash devices
Flash size (bytes)
Available sectors
4K
Sector 0
8K
Sectors 0,1
27/201
Flash program memory
4.3.1
ST7232Axx-Auto
Read-out protection
Read-out protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the
entire program memory is first automatically erased and the device can be reprogrammed.
Read-out protection selection depends on the device type:
●
In Flash devices it is enabled and removed through the FMP_R bit in the option byte
●
In ROM devices it is enabled by mask option specified in the option list
Figure 5.
Memory map and sector addresses of the ST7232X family
4K
8K
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
10K
16K
24K
32K
48K
Flash memory size
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Sector 2
2 Kbytes
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8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes
4 Kbytes
4 Kbytes
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4.4
60K
ICC interface
Sector 1
Sector 0
o
s
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O
-
ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see
Figure 6). These pins are:
)
s
(
ct
●
RESET: device reset
●
VSS: device power supply ground
●
ICCCLK: ICC output serial clock pin
●
ICCDATA: ICC input/output serial data pin
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28/201
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ICCSEL/VPP: programming voltage
OSC1(or OSCIN): main clock input for external source (optional)
VDD: application board power supply (optional, see Figure 6, footnote 3)
ST7232Axx-Auto
Figure 6.
Flash program memory
Typical ICC interface
Programming tool
ICC connector
ICC cable
Application board
(3)
(See ‘caution’)
9
7
5
3
1
10
8
6
4
2
ICC connector
HE10 connector type
Application reset source(2)
10kΩ
ICCCLK
ICCDATA
ST7
RESET
Application I/O(1)
ICCSEL/VPP
OSC1
CL1
OSC2
VDD
CL2
VSS
Application
power supply
c
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)
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1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is
necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in
progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by
the application, isolation such as a serial resistor has to implemented in case another device forces the
signal. Refer to the programming tool documentation for recommended resistor values.
e
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2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts
between the programming tool and the application reset circuit if it drives more than 5mA at high level
(push pull output or pull-up resistor < 1K). A schottky diode can be used to isolate the application reset
circuit in this case. When using a classical RC network with R > 1K or a reset management IC with open
drain output and pull-up resistor > 1K, no additional components are needed. In all cases the user must
ensure that no external reset is generated by the application during the ICC session.
o
s
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O
-
3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be
connected when using most ST programming tools (it is used to monitor the application power supply).
Please refer to the programming tool manual.
Caution:
4.5
b
O
l
o
s
)
s
(
ct
External clock ICC entry mode is mandatory. Pin 9 must be connected to the OSC1 or
OSCIN pin of the ST7 and OSC2 must be grounded.
u
d
In-circuitro
programming (ICP)
P
ete
To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM, Flash memory programming can be fully
customized (number of bytes to program, program locations, or selection serial
communication interface for downloading).
When using an STMicroelectronics or third-party programming tool that supports ICP and
the specific microcontroller device, the user needs only to implement the ICP hardware
interface on the application board (see Figure 6). For more details on the pin locations, refer
to the device pinout description.
29/201
Flash program memory
4.6
ST7232Axx-Auto
In-application programming (IAP)
This mode uses a Bootloader program previously stored in sector 0 by the user (in ICP
mode or by plugging the device in a programming tool).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored, ...). For example, it is possible
to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash sectors except sector 0, which is write/erase
protected to allow recovery in case errors occur during the programming operation.
4.7
Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash programming
reference manual and to the ST7 ICC protocol reference manual.
Flash control/status register (FCSR)
FCSR
c
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)
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Reset value: 0000 0000 (00h)
7
6
5
4
3
2
0
R/W
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1
0
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This register is reserved for use by programming tool software. It controls the Flash
programming and erasing operations.
Table 5.
Address (Hex.)
Register label
0029h
FCSR
Reset value
)
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30/201
o
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-
Flash control/status register address and reset value
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
ST7232Axx-Auto
Central processing unit
5
Central processing unit
5.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient
8-bit data manipulation.
5.2
5.3
Main features
●
Enable executing 63 basic instructions
●
Fast 8-bit by 8-bit multiply
●
17 main addressing modes (with indirect addressing mode)
●
Two 8-bit index registers
●
16-bit stack pointer
●
Low power halt and wait modes
●
Priority maskable hardware interrupts
●
Non-maskable software/hardware interrupts
c
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CPU registers
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)
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The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are
accessed by specific instructions.
Figure 7.
CPU registers
7
)
s
(
ct
o
s
b
O
0
Accumulator
Reset value = XXh
7
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15
PCH
0
X index register
Reset value = XXh
7
0
Y index register
Reset value = XXh
8 7
PCL
0
Program counter
Reset value = reset vector @ FFFEh-FFFFh
7
0
1 1 I1 H I0 N Z C
Condition code register
Reset value = 1 1 1 X 1 X X X
15
8
7
0
Stack pointer
Reset value = stack higher address
1.
X = undefined value
31/201
Central processing unit
ST7232Axx-Auto
Accumulator (A)
The accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
Index registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas
for data manipulation. (The cross-assembler generates a precede instruction (PRE) to
indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is
the LSB) and PCH (program counter high which is the MSB).
Condition code register (CC)
CC
c
u
d
)
s
t(
Reset value: 111x 1xxx
7
6
5
4
3
2
1
I1
H
I0
N
R/W
R/W
R/W
R/W
1
P
e
let
ro
R/W
0
Z
C
R/W
R/W
The 8-bit condition code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
o
s
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-
These bits can be individually tested and/or controlled by specific instructions.
)
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32/201
ST7232Axx-Auto
Central processing unit
Table 6.
CC register description
Bit
5,3
Bit name
Function
I1, I0
Interrupt management bits - interrupt
The combination of the I1 and I0 bits gives the current interrupt
software priority:
10: Interrupt software priority = level 0 (main)
01: Interrupt software priority = level 1
00: Interrupt software priority = level 2
11: Interrupt software priority = level 3 (= interrupt disable)
These two bits are set/cleared by hardware when entering in
interrupt. The loaded value is given by the corresponding bits in the
interrupt software priority registers (IxSPR). They can be also
set/cleared by software with the RIM, SIM, IRET, HALT, WFI and
PUSH/POP instructions. See Section 7: Interrupts for more details.
Arithmetic management bit - Half carry
4
H
This bit is set by hardware when a carry occurs between bits 3 and 4
of the ALU during an ADD or ADC instructions. It is reset by
hardware during the same instructions.
0: No half carry has occurred
1: A half carry has occurred
This bit is tested using the JRH or JRNH instruction. The H bit is
useful in BCD arithmetic subroutines.
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2
1
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0
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N
Arithmetic management bit - Negative
This bit is set and cleared by hardware. It is representative of the
result sign of the last arithmetic, logical or data manipulation. It’s a
copy of the result 7th bit.
0: The result of the last operation is positive or null
1: The result of the last operation is negative (i.e. the most significant
bit is a logic 1)
This bit is accessed by the JRMI and JRPL instructions.
Z
Arithmetic management bit - Zero
This bit is set and cleared by hardware. This bit indicates that the
result of the last arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero
1: The result of the last operation is zero
This bit is accessed by the JREQ and JRNE test instructions.
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C
o
s
b
O
-
Arithmetic management bit - Carry/borrow
This bit is set and cleared by hardware and software. It indicates an
overflow or an underflow has occurred during the last arithmetic
operation.
0: No overflow or underflow has occurred
1: An overflow or underflow has occurred
This bit is driven by the SCF and RCF instructions and tested by the
JRC and JRNC instructions. It is also affected by the ‘bit test and
branch’, shift and rotate instructions.
33/201
Central processing unit
ST7232Axx-Auto
Stack pointer register (SP)
SP
Reset value: 01 FFh
15
7
14
6
13
5
12
11
10
9
8
0
1
R/W
R/W
4
3
2
1
0
SP[7:0]
R/W
The stack pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 8).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU reset, or after a reset stack pointer instruction (RSP), the stack pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
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s
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The least significant byte of the stack pointer (called S) can be directly accessed by a LD
instruction.
Note:
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When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
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The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 8.
)
s
(
ct
o
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-
●
When an interrupt is received, the SP is decremented and the context is pushed on the
stack
●
On return from interrupt, the SP is incremented and the context is popped from the
stack
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A subroutine call occupies two locations and an interrupt five locations in the stack area.
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34/201
ST7232Axx-Auto
Central processing unit
Figure 8.
Stack manipulation example
Call
subroutine
PUSH Y
Interrupt
event
POP Y
IRET
RET or RSP
@ 0100h
SP
SP
CC
A
A
A
X
X
X
PCH
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
SP
@ 01FFh
SP
Y
CC
CC
SP
SP
1. Legend: stack higher addres = 01FFh; stack lower address = 0100h
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35/201
Supply, reset and clock management
ST7232Axx-Auto
6
Supply, reset and clock management
6.1
Introduction
The device includes a range of utility features for securing the application in critical situations (for
example in case of a power brown-out), and reducing the number of external components. An overview is
shown in Figure 10.
6.2
Main features
●
Optional PLL for multiplying the frequency by 2
●
Reset sequence manager (RSM)
●
Multi-oscillator clock management (MO)
–
5 crystal/ceramic resonator oscillators
6.3
Phase locked loop (PLL)
c
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)
s
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If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the
frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is
disabled, then fOSC2 = fOSC/2.
o
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Caution:
The PLL is not recommended for applications where timing accuracy is required.
Caution:
When the PLL is used with an external clock signal, the clock signal must be available on
the OSCIN pin before the reset signal is released.
Figure 9.
PLL block diagram
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fOSC
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36/201
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O
-
PLL x 2
0
/2
1
PLL option bit
fOSC2
ST7232Axx-Auto
Supply, reset and clock management
Figure 10. Clock, reset and supply block diagram
OSC2
Multi-oscillator
(MO)
OSC1
fOSC
fOSC2
PLL
(option)
Main clock controller fCPU
with real-time clock
(MCC/RTC)
System integrity management
Reset sequence manager
(RSM)
RESET
Watchdog timer
(WDG)
SICSR
0
0
0
0
WDG
RF
VSS
VDD
6.4
Multi-oscillator (MO)
c
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The main clock of the ST7 can be generated by two different source types coming from the
multi-oscillator block:
●
An external source
●
4 crystal or ceramic resonator oscillators
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Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Table 7. Refer to Section 12: Electrical characteristics for more details.
Caution:
o
s
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O
-
The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of failure
mode and effect analysis, it should be noted that if the OSC1 and/or OSC2 pins are left
unconnected, the ST7 main oscillator may start and, in this configuration, could generate an
fOSC clock frequency in excess of the allowed maximum (> 16MHz), putting the ST7 in an
unsafe/undefined state. The product behaviour must therefore be considered undefined
when the OSC pins are left unconnected.
)
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6.4.1
External clock source
r
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In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
t
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6.4.2
O
bs
Crystal/ceramic oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main
clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges
has to be done by option byte in order to reduce consumption (refer to Section 14.2: Flash
devices on page 185 for more details on the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and start-up stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the reset phase to avoid losing time in the oscillator
start-up phase.
37/201
Supply, reset and clock management
Table 7.
ST7232Axx-Auto
ST7 clock source
External clock
Hardware configuration
ST7
OSC1
OSC2
Crystal/ceramic resonators
External source
ST7
OSC1
CL1
OSC2
Load
capacitors
6.5
Reset sequence manager (RSM)
6.5.1
Introduction
CL2
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The reset sequence manager includes two reset sources as shown in Figure 12:
●
External RESET source pulse
●
Internal watchdog reset
)
s
(
ct
These sources act on the RESET pin and it is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
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The basic reset sequence consists of 3 phases as shown in Figure 11:
r
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●
●
t
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o
●
Caution:
s
b
O
Active phase depending on the reset source
256 or 4096 CPU clock cycle delay (selected by option byte)
Reset vector fetch
When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that
recovery has taken place from the reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application.
The reset vector fetch phase duration is 2 clock cycles.
38/201
ST7232Axx-Auto
Supply, reset and clock management
Figure 11. Reset sequence phases
Reset
Active phase
6.5.2
Internal reset
Fetch vector
256 or 4096 CLOCK CYCLES
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Section 12: Electrical
characteristics for more details.
A reset signal originating from an external source must have a duration of at least th(RSTL)in
in order to be recognized (see Figure 13). This detection is asynchronous and therefore the
MCU can enter reset state even in halt mode.
c
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d
Figure 12. Reset block diagram
VDD
e
t
le
RON
o
s
b
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Filter
RESET
(s)
Pulse
generator
)
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P
Internal reset
Watchdog reset
t
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e
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
6.5.3
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o
External power on reset
To start up the microcontroller correctly, the user must ensure by means of an external reset
circuit that the reset signal is held low until VDD is over the minimum level specified for the
selected fOSC frequency.
A proper reset signal for a slow rising VDD supply can generally be provided by an external
RC network connected to the RESET pin.
39/201
Supply, reset and clock management
6.5.4
ST7232Axx-Auto
Internal watchdog reset
The reset sequence generated by a internal watchdog counter overflow is shown in
Figure 13.
Starting from the watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
Figure 13. Reset sequences
Watchdog
reset
External reset
Run
Run
Active
phase
Run
Active
phase
tw(RSTL)out
th(RSTL)in
c
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External
RESET
source
RESET pin
e
t
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Watchdog
reset
o
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P
Watchdog underflow
o
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-
Internal reset (256 or 4096 TCPU)
Vector fetch
)
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ST7232Axx-Auto
6.6
Supply, reset and clock management
System integrity management
System integrity control/status register (SICSR)
SICSR
Reset value: 0000 000x (00b)
7
Table 8.
6
5
4
3
2
1
0
Reserved
WDGRF
-
R/W
SICSR register description
Bit
Bit name
7:1
-
0
Function
Reserved, must be kept cleared
WDGRF
Watchdog reset flag
This bit indicates that the last reset was generated by the watchdog
peripheral. It is set by hardware (watchdog reset) and cleared by
software (writing zero).
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Interrupts
ST7232Axx-Auto
7
Interrupts
7.1
Introduction
The ST7 enhanced interrupt management provides the following features:
●
Hardware interrupts
●
Software interrupt (TRAP)
●
Nested or concurrent interrupt management with flexible interrupt priority and level
management:
–
Up to 4 software programmable nesting levels
–
Up to 16 interrupt vectors fixed by hardware
–
2 non maskable events: reset, TRAP
This interrupt management is based on:
●
Bit 5 and bit 3 of the CPU CC register (I1:0)
●
Interrupt software priority registers (ISPRx)
●
Fixed interrupt vector addresses located at the high addresses of the memory map
(FFE0h to FFFFh) sorted by hardware priority order
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)
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This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.
7.2
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Masking and processing flow
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-
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx
registers which give the interrupt software priority level of each interrupt vector (see
Table 9). The processing flow is shown in Figure 14.
When an interrupt request has to be serviced:
)
s
(
ct
●
Normal processing is suspended at the end of the current instruction execution
●
The PC, X, A and CC registers are saved onto the stack
●
I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx
registers of the serviced interrupt vector
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Note:
42/201
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The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to Table 15: Interrupt
mapping for vector addresses)
The interrupt service routine should end with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
As a consequence of the IRET instruction, the I1 and I0 bits are restored from the stack and
the program in the previous level is resumed.
ST7232Axx-Auto
Table 9.
Interrupts
Interrupt software priority levels
Interrupt software priority
Level
Level 0 (main)
Low
Level 1
Level 2
High
Level 3 (= interrupt disable)
I1
I0
1
0
0
1
0
0
1
1
Figure 14. Interrupt processing flowchart
Pending
interrupt
Reset
Y
TRAP
Interrupt has the same or a
lower software priority
than current one
N
Fetch next
instruction
Y
I1:0
c
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Interrupt has a higher
software priority
than current one
N
Restore PC, X, A, CC
from stack
N
The interrupt
stays pending
‘IRET’
Execute
instruction
Y
)
s
t(
o
r
P
Stack PC, X, A, CC
Load I1:0 from interrupt SW register
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Load PC from interrupt vector
)
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43/201
Interrupts
7.2.1
ST7232Axx-Auto
Servicing pending interrupts
As several interrupts can be pending at the same time, the interrupt to be taken into account
is determined by the following two-step process:
●
the highest software priority interrupt is serviced
●
if several interrupts have the same software priority then the interrupt with the highest
hardware priority is serviced first
Figure 15 describes this decision process.
Figure 15. Priority decision process
Pending
interrupts
Same
Different
Software
priority
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Highest software
priority serviced
Highest hardware
priority serviced
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When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.
Note:
The hardware priority is exclusive while the software one is not. This allows the previous
process to succeed with only one interrupt.
2
Reset and TRAP can be considered as having the highest software priority in the decision
process.
)
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7.2.2
o
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-
1
Different interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (reset, TRAP) and the maskable type (external or from internal peripherals).
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44/201
ST7232Axx-Auto
7.2.3
Interrupts
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see Figure 14). After stacking the PC, X, A and CC registers (except for reset), the
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit halt mode.
●
TRAP (non maskable software interrupt)
This software interrupt is serviced when the TRAP instruction is executed. It is serviced
according to the flowchart in Figure 14.
●
Reset
The reset source has the highest priority in the ST7. This means that the first current routine
has the highest software priority (level 3) and the highest hardware priority. See Section 6.5:
Reset sequence manager (RSM).
7.2.4
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
●
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External interrupts
)
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External interrupts allow the processor to exit from halt low power mode. External
interrupt sensitivity is software selectable through the external interrupt control register
(EICR).
e
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External interrupt triggered on edge is latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
o
s
b
O
-
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these are logically ORed.
●
Peripheral interrupts
)
s
(
ct
Usually the peripheral interrupts cause the MCU to exit from halt mode except those
mentioned in Table 15: Interrupt mapping . A peripheral interrupt occurs when a
specific flag is set in the peripheral status registers and if the corresponding enable bit
is set in the peripheral control register.
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The general sequence for clearing an interrupt is based on an access to the status register
followed by a read or write to an associated register.
Note:
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The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be
serviced) is therefore lost if the clear sequence is executed.
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45/201
Interrupts
7.3
ST7232Axx-Auto
Interrupts and low power modes
All interrupts allow the processor to exit the wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the halt modes (see
column ‘exit from halt’ in Table 15: Interrupt mapping). When several pending interrupts are
present while exiting halt mode, the first one serviced can only be an interrupt with exit from
halt mode capability and it is selected through the same decision process shown in
Figure 15.
Note:
If an interrupt, that is not able to exit from halt mode, is pending with the highest priority
when exiting halt mode, this interrupt is serviced after the first one serviced.
7.4
Concurrent and nested management
Figure 16 and Figure 17 show two different interrupt management modes. The first is called
concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode
in Figure 17. The interrupt hardware priority is given in this order from the lowest to the
highest: MAIN, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt.
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A stack overflow may occur without notifying the software of
the failure.
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IT0
TRAP
IT3
IT4
IT1
IT2
Figure 16. Concurrent interrupt management
o
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Software priority level
Hardware priority
TRAP
ct
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46/201
du
IT2
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RIM
MAIN
11/10
IT1
IT0
IT1
IT3
IT4
MAIN
10
I1
I0
3
1 1
3
1 1
3
1 1
3
1 1
3
1 1
3
1 1
3/0
Used stack = 10 bytes
Warning:
)
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ST7232Axx-Auto
Interrupts
I1
TRAP
Hardware priority
IT0
IT1
IT1
IT2
IT2
IT3
3
1 1
3
1 1
2
0 0
1
0 1
3
1 1
3
1 1
RIM
IT4
IT4
MAIN
11/10
7.5
MAIN
10
3/0
Interrupt registers
CPU CC register interrupt bits
CPU CC
6
5
4
3
1
I1
H
I0
R/W
R/W
R/W
R/W
Table 10.
Bit name
)
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2
1
0
N
Z
C
R/W
R/W
R/W
o
s
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-
e
t
le
CPU CC register description
Bit
5, 3
o
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Reset value: 111x 1010 (xAh)
7
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I0
Used stack = 20 bytes
Software priority level
IT0
TRAP
IT3
IT4
IT1
IT2
Figure 17. Nested interrupt management
I1, I0
Function
Software interrupt priority
These two bits indicate the current interrupt software priority:
10: Interrupt software priority = level 0 (main)
01: Interrupt software priority = level 1
00: Interrupt software priority = level 2
11: Interrupt software priority = level 3 (= interrupt disable(1))
These two bits are set/cleared by hardware when entering in
interrupt. The loaded value is given by the corresponding bits in the
interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT,
WFI, IRET and PUSH/POP instructions (see Table 12: Dedicated
interrupt instruction set).
1. TRAP and reset events can interrupt a level 3 program.
47/201
Interrupts
ST7232Axx-Auto
Interrupt software priority registers (ISPRX)
ISPR0
Reset value: 1111 1111 (FFh)
7
6
5
4
3
2
1
0
I1_3
I0_3
I1_2
I0_2
I1_1
I0_1
I1_0
I0_0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISPR1
Reset value: 1111 1111 (FFh)
7
6
5
4
3
2
1
0
I1_7
I0_7
I1_6
I0_6
I1_5
I0_5
I1_4
I0_4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISPR2
Reset value: 1111 1111 (FFh)
7
6
5
4
3
2
1
I1_11
I0_11
I1_10
I0_10
I1_9
I0_9
I1_8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISPR3
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I0_8
R/W
Reset value: 1111 1111 (FFh)
7
6
5
4
3
1
1
1
1
I1_13
I0_13
R
R
R
R
R/W
R/W
ro
2
P
e
let
1
0
I1_12
I0_12
R/W
R/W
o
s
b
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-
These four registers contain the interrupt software priority of each interrupt vector.
●
Each interrupt vector (except reset and TRAP) has corresponding bits in the ISPRx
registers where its own software priority is stored. This correspondance is shown in
Table 11.
●
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1
and I0 bits in the CC register.
●
Level 0 can not be written (I1_x = 1, I0_x = 0). In this case, the previously stored value
is kept (example, previous = CFh, write = 64h, result = 44h).
)
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Table 11.
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Caution:
48/201
ISPRx interrupt vector correspondence
Vector address
ISPRx bits
FFFBh-FFFAh
I1_0 and I0_0 bits*
FFF9h-FFF8h
I1_1 and I0_1 bits
-
-
FFE1h-FFE0h
I1_13 and I0_13 bits
The reset, and TRAP vectors have no software priorities. When one is serviced, the I1 and
I0 bits of the CC register are both set.
If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour
has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
ST7232Axx-Auto
7.6
Interrupts
Interrupt related instructions
Table 12.
Dedicated interrupt instruction set(1)
Instruction
New description
Function/example
HALT
Entering halt mode
IRET
Interrupt routine return
Pop CC, A, X, PC
JRM
Jump if I1:0 = 11 (level 3)
I1:0 = 11 ?
JRNM
Jump if I1:0 <> 11
I1:0 <> 11 ?
POP CC
Pop CC from the stack
RIM
Enable interrupt (level 0 set)
I1
H
1
I0
N
Z
C
0
I1
H
I0
N
Z
C
Mem => CC
I1
H
I0
N
Z
C
Load 10 in I1:0 of CC
1
0
SIM
Disable interrupt (level 3 set) Load 11 in I1:0 of CC
1
1
TRAP
Software TRAP
1
1
WFI
Wait for interrupt
1
0
Software NMI
)
s
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1. During the execution of an interrupt routine, the HALT, POP CC, RIM, SIM and WFI instructions change
the current software priority up to the next IRET instruction or one of the previously mentioned instructions.
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7.7
External interrupts
7.7.1
I/O port interrupt sensitivity
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The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register (Figure 18). This control allows up to 4 fully independent external interrupt source
sensitivities.
o
s
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-
Each external interrupt source can be generated on four (or five) different events on the pin:
●
Falling edge
●
Rising edge
●
Falling and rising edge
●
Falling edge and low level
●
Rising edge and high level (only for ei0 and ei2)
)
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To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that
interrupts must be disabled before changing sensitivity.
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The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits
of the EICR.
49/201
Interrupts
ST7232Axx-Auto
Figure 18. External interrupt control bits
EICR
Port A3 interrupt
IS20
PAOR.3
PADDR.3
IS21
ei0 interrupt source
Sensitivity
control
PA3
IPA bit
EICR
Port F [2:0] interrupts
IS21
IS20
PFOR.2
PFDDR.2
Sensitivity
control
PF2
IS10
PBOR.3
PBDDR.3
IPB bit
EICR
Port B [7:4] interrupts
IS10
PBOR.7
PBDDR.7
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PB3
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ei2 interrupt source
PB2
PB1
PB0
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-
IS11
Sensitivity
control
PB7
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IS11
Sensitivity
control
PB3
s
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ei1 interrupt source
PF1
PF0
EICR
Port B [3:0] interrupts
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PF2
PB7
PB6
PB5
PB4
ei3 interrupt source
ST7232Axx-Auto
7.8
Interrupts
External interrupt control register (EICR)
EICR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
IS1[1:0]
IPB
IS2[1:0]
IPA
Reserved
R/W
R/W
R/W
R/W
-
Table 13.
EICR register description
Bit
7:6
Bit name
Function
IS1[1:0]
Interrupt sensitivity (ei2 and ei3)
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to
the following external interrupts:
External interrupt ei2 (port B[3:0]):
00: External interrupt sensitivity = falling edge and low level
(IPB bit = 0) and rising edge and high level (IPB bit = 1)
01: External interrupt sensitivity = rising edge only (IPB bit = 0) and
falling edge only (IPB bit = 1)
10: External interrupt sensitivity = falling edge only (IPB bit = 0) and
rising edge only (IPB bit = 1)
11: External interrupt sensitivity = rising and falling edge
(IPB bit = 0 and 1)
External interrupt ei3 (port B[4]):
00: external interrupt sensitivity = falling edge and low level
01: external interrupt sensitivity = rising edge only
10: external interrupt sensitivity = falling edge only
11: external interrupt sensitivity = rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register
are both set to 1 (level 3).
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5
IPB
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-
Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B [3:0] external
interrupts. It can be set and cleared by software only when I1 and I0
of the CC register are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
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Interrupts
ST7232Axx-Auto
Table 13.
EICR register description (continued)
Bit
4:3
Bit name
Function
IS2[1:0]
Interrupt sensitivity (ei0 and ei1)
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to
the following external interrupts:
External interrupt ei0 (port A[3:0]):
00: External interrupt sensitivity = falling edge and low level
(IPA bit = 0) and rising edge and high level (IPA bit = 1)
01: External interrupt sensitivity = rising edge only (IPA bit = 0) and
falling edge only (IPA bit = 1)
10: External interrupt sensitivity = falling edge only (IPA bit = 0) and
rising edge only (IPA bit = 1)
11: External interrupt sensitivity = rising and falling edge
(IPA bit = 0 and 1)
External interrupt ei1 port ([F2:0]):
00: External interrupt sensitivity = falling edge and low level
01: External interrupt sensitivity = rising edge only
10: External interrupt sensitivity = falling edge only
11: External interrupt sensitivity = rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register
are both set to 1 (level 3).
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2
IPA
1:0
-
Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A [3:0] external
interrupts. It can be set and cleared by software only when I1 and I0
of the CC register are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
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b
O
-
Reserved, must always be kept cleared
)
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ST7232Axx-Auto
Interrupts
7.9
Nested interrupts register map and reset value
Table 14.
Nested interrupts register map and reset values
Address (Hex.)
Register label
7
6
5
4
ei1
ISPR0
Reset value
0024h
3
ei0
I1_3
1
I0_3
1
2
ISPR1
Reset value
0026h
ISPR2
Reset value
0027h
0028h
I1_7
1
I1_2
1
I0_2
1
I1_1
1
1
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
SCI
ei2
I0_5
1
I1_4
1
Timer B
I0_4
1
Timer A
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
ISPR3
Reset value
1
1
1
1
I1_13
1
I0_13
1
I1_12
1
I0_12
1
EICR
Reset value
IS11
0
IS10
0
IPB
0
IS21
0
IS20
0
IPA
0
7.10
Interrupt mapping
Table 15.
Interrupt mapping
Source
block
uc
0
)
s
t(
0
d
o
r
P
e
let
Register Priority Exit from
label
order
halt
so
Description
Reset
I0_1
1
ei3
AVD
No.
0
MCC + SI
SPI
0025h
1
Reset
b
O
-
Exit from
active halt
Address vector
Yes
Yes
FFFEh-FFFFh
No
No
FFFCh-FFFDh
N/A
TRAP
Software interrupt
(s)
0
Not used
1
MCC/RTC
2
ei0
3
ei1
4
ei2
ct
Main clock controller time
base interrupt
Yes
FFF8h-FFF9h
Yes
No
FFF6h-FFF7h
Yes
No
FFF4h-FFF5h
External interrupt port B[3:0]
Yes
No
FFF2h-FFF3h
External interrupt port B[7:4]
Yes
No
FFF0h-FFF1h
External interrupt port A[3:0]
r
P
e
External interrupt port F[2:0]
N/A
7
t
e
l
o
SPI peripheral interrupts
8
Timer A
Timer A peripheral interrupts
TASR
9
Timer B
Timer B peripheral interrupts
TBSR
10
SCI
SCI peripheral interrupts
SCISR
5
6
ei3
s
b
O
11
SPI
Higher
priority
Yes
u
d
o
MCCSR
FFFAh-FFFBh
Not used
Not used
SPICSR
Not used
FFEEh-FFEFh
No
FFECh-FFEDh
No
No
FFEAh-FFEBh
No
No
FFE8h-FFE9h
No
No
FFE6h-FFE7h
Yes
Lower
priority
(1)
FFE4h-FFE5h
1. Unexpected exit from halt may occur when SPI is in slave mode.
53/201
Power saving modes
ST7232Axx-Auto
8
Power saving modes
8.1
Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 19): slow, wait (slow
wait), active halt and halt.
After a reset the normal operating mode is selected by default (RUN mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided or multiplied by 2 (fOSC2).
From RUN mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 19. Power saving mode transitions
High
c
u
d
Run
Slow
e
t
le
Wait
)
s
t(
o
r
P
o
s
b
O
Slow wait
Active halt
)
s
(
ct
o
r
P
e
du
Halt
Low
Power consumption
Slow
mode
t
e
ol
8.2
s
b
O
This mode has two targets:
●
To reduce power consumption by decreasing the internal clock in the device
●
To adapt the internal clock frequency (fCPU) to the available supply voltage
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or
disables slow mode and two CPx bits which select the internal slow frequency (fCPU).
In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU
and peripherals are clocked at this lower frequency (fCPU).
Note:
54/201
Slow wait mode is activated when entering the wait mode while the device is already in slow
mode.
ST7232Axx-Auto
Power saving modes
Figure 20. Slow mode clock transitions
fOSC2/2
fOSC2/4
fOSC2
fCPU
MCCSR
fOSC2
00
CP1:0
01
SMS
Normal run mode request
New slow
frequency request
8.3
Wait mode
)
s
t(
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
c
u
d
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During wait mode, the I[1:0] bits of the CC register are forced
to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU
remains in wait mode until an interrupt or reset occurs, whereupon the program counter
branches to the starting address of the interrupt or reset service routine. The MCU remains
in wait mode until a reset or an interrupt occurs, causes it to wake up.
e
t
le
Refer to Figure 21.
)
s
(
ct
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
55/201
Power saving modes
ST7232Axx-Auto
Figure 21. Wait mode flow-chart
WFI instruction
Oscillator
Peripherals
ON
ON
OFF
10
CPU
I[1:0] bits
N
Reset
Y
N
Interrupt
Y
Oscillator
Peripherals
ON
OFF
ON
10
CPU
I[1:0] bits
256 OR 4096 CPU clock
cycle delay
Oscillator
Peripherals
CPU
e
t
le
I[1:0] bits
c
u
d
)
s
t(
o
r
P
ON
ON
ON
XX(1)
o
s
b
O
-
Fetch reset vector or
service interrupt
1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
8.4
)
s
(
t
Active halt and c
halt modes
u
d
o
r
P
e
t
e
ol
Active halt and halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in active
halt or halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR
register).
s
b
O
56/201
Table 16.
MCCSR
OIE bit
Active halt and halt power saving modes
Power saving mode entered when HALT instruction is executed
0
Halt mode
1
Active halt mode
ST7232Axx-Auto
8.4.1
Power saving modes
Active halt mode
Active halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the main clock
controller status register (MCCSR) is set (see Section 10.2: Main clock controller with realtime clock and beeper (MCC/RTC) on page 73 for more details on the MCCSR register).
The MCU can exit active halt mode on reception of either an MCC/RTC interrupt, a specific
interrupt (see Table 15: Interrupt mapping on page 53) or a reset. When exiting active halt
mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes
operation by servicing the interrupt or by fetching the reset vector which woke it up (see
Figure 23).
When entering active halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In active halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
)
s
t(
The safeguard against staying locked in active halt mode is provided by the oscillator
interrupt.
c
u
d
Note:
As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),
entering active halt mode while the watchdog is active does not generate a reset. This
means that the device cannot spend more than a defined delay in this power saving mode.
Caution:
When exiting active halt mode following an interrupt, OIE bit of MCCSR register must not be
cleared before tDELAY after the interrupt occurs (tDELAY = 256 or 4096 tCPU delay depending
on option byte). Otherwise, the ST7 enters halt mode for the remaining tDELAY period.
e
t
le
o
s
b
O
-
o
r
P
Figure 22. Active halt timing overview
Run
t
c
u
(s)
d
o
r
P
e
Active
halt
HALT
instruction
[MCCSR.OIE = 1]
256 OR 4096 CPU
cycle delay(1)
Run
Reset or interrupt
Fetch
vector
t
e
l
o
1. This delay occurs only if the MCU exits active halt mode by means of a reset
s
b
O
57/201
Power saving modes
ST7232Axx-Auto
Figure 23. Active halt mode flow-chart
HALT instruction
(MCCSR.OIE = 1)
Oscillator
Peripherals(1)
CPU
I[1:0] bits
N
N
Reset
Y
Interrupt(2)
Y
ON
OFF
OFF
10
Oscillator
Peripherals
CPU
I[1:0] bits
ON
OFF
ON
XX(3)
256 OR 4096 CPU clock
cycle delay
Oscillator
Peripherals
CPU
I[1:0] bits
ON
ON
ON
XX(3)
o
r
P
Fetch reset vector or
service interrupt
e
t
le
c
u
d
)
s
t(
1. Peripheral clocked with an external clock source can still be active
o
s
b
O
-
2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from active halt mode (such as
external interrupt). Refer to Table 15: Interrupt mapping on page 53 for more details.
3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and restored when the CC register is
popped.
8.4.2
)
s
(
ct
Halt mode
The halt mode is the lowest power consumption mode of the MCU. It is entered by executing
the ‘HALT’ instruction when the OIE bit of the main clock controller status register (MCCSR)
is cleared (see Section 10.2: Main clock controller with real-time clock and beeper
(MCC/RTC) on page 73 for more details on the MCCSR register).
u
d
o
r
P
e
The MCU can exit halt mode on reception of either a specific interrupt (see Table 15:
Interrupt mapping on page 53) or a reset. When exiting halt mode by means of a reset or an
interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is
used to stabilize the oscillator. After the start up delay, the CPU resumes operation by
servicing the interrupt or by fetching the reset vector which woke it up (see Figure 25).
t
e
l
o
s
b
O
When entering halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
58/201
ST7232Axx-Auto
Power saving modes
The compatibility of watchdog operation with halt mode is configured by the ‘WDGHALT’
option bit of the option byte. The HALT instruction when executed while the watchdog
system is enabled, can generate a watchdog reset (see Section 14.2 on page 185) for more
details.
Figure 24. Halt timing overview
Run
Halt
HALT
instruction
[MCCSR.OIE = 1]
256 OR 4096 CPU
cycle delay
Run
Reset or interrupt
Fetch
vector
c
u
d
e
t
le
)
s
(
ct
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
59/201
Power saving modes
ST7232Axx-Auto
Figure 25. Halt mode flow-chart
HALT instruction
(MCCSR.OIE = 0)
Enable
WDGHALT(1)
Watchdog
Disable
0
1
Watchdog reset
Oscillator
Peripherals(2)
CPU
I[1:0] bits
N
OFF
OFF
OFF
10
Reset
Y
N
Interrupt(3)
Y
Oscillator
Peripherals
CPU
I[1:0] bits
e
t
le
c
u
d
ON
)
s
t(
o
r
P
OFF
ON
XX(4)
256 or 4096 CPU clock
cycle delay
o
s
b
O
-
Oscillator
Peripherals
(s)
t
c
u
d
o
r
P
e
CPU
I[1:0] bits
ON
ON
ON
XX(4)
Fetch reset vector or
service interrupt
1. WDGHALT is an option bit. See Section 14.2: Flash devices for more details.
2. Peripheral clocked with an external clock source can still be active.
t
e
l
o
3. Only some specific interrupts can exit the MCU from halt mode (such as external interrupt). Refer to
Table 15: Interrupt mapping on page 53 for more details.
s
b
O
60/201
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
ST7232Axx-Auto
Power saving modes
Halt mode recommendations
●
Make sure that an external event is available to wake up the microcontroller from halt
mode
●
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as ‘input pull-up with interrupt’ before executing the HALT instruction.
The main reason for this is that the I/O may be wrongly configured due to external
interference or by an unforeseen logical condition.
●
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
●
The opcode for the HALT instruction is 0 x 8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
●
As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,
the user may choose to clear all pending interrupt bits before executing the HALT
instruction. This avoids entering other peripheral interrupt routines after executing the
external interrupt routine corresponding to the wake up event (reset or external
interrupt).
c
u
d
e
t
le
)
s
(
ct
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
61/201
I/O ports
ST7232Axx-Auto
9
I/O ports
9.1
Introduction
The I/O ports offer different functional modes:
●
Transfer of data through digital inputs and outputs
For specific pins they offer different functional modes:
●
External interrupt generation
●
Alternate signal input/output for the on-chip peripherals
An I/O port contains up to 8 pins. Each pin can be programmed independently as digital
input (with or without interrupt generation) or digital output.
9.2
Functional description
Each port has 2 main registers:
●
Data register (DR)
●
Data direction register (DDR)
c
u
d
Each port also has one optional register:
●
Option register (OR)
e
t
le
)
s
t(
o
r
P
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers: bit X corresponding to pin X of the port. The same correspondence is used for the
DR register.
o
s
b
O
-
The following description takes into account the OR register, (for specific ports which do not
provide this register refer to Section 9.3: I/O port implementation on page 66). The generic
I/O block diagram is shown in Figure 26.
9.2.1
)
s
(
ct
Input modes
The input configuration is selected by clearing the corresponding DDR register bit. In this
case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Note:
u
d
o
r
P
e
1
Writing the DR register modifies the latch value but does not affect the pin status.
2
When switching from input to output mode, the DR register has to be written first to drive the
correct level on the pin as soon as the port is configured as an output.
3
Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this
might corrupt the DR content for I/Os configured as input."
t
e
l
o
s
b
O
62/201
ST7232Axx-Auto
I/O ports
External interrupt function
When an I/O is configured as input with interrupt, an event on this I/O can generate an
external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the EICR register.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see Section 2:
Pin description and Section 7: Interrupts). If several input pins are selected simultaneously
as interrupt sources, these are first detected according to the sensitivity bits in the EICR
register and then logically ORed.
The external interrupts are hardware interrupts, which means that the request latch (not
accessible directly by the application) is automatically cleared when the corresponding
interrupt vector is fetched. To clear an unwanted pending interrupt by software, the
sensitivity bits in the EICR register must be modified.
9.2.2
Output modes
)
s
t(
The output configuration is selected by setting the corresponding DDR register bit. In this
case, writing the DR register applies this digital value to the I/O pin through the latch. Then
reading the DR register returns the previously stored value.
c
u
d
Two different output modes can be selected by software through the OR register: Output
push-pull and open-drain.
See Table 17 for the DR register value and output pin status.
Table 17.
9.2.3
e
t
le
o
r
P
DR register value and output pin status
DR
Push-pull
0
VSS
1
VDD
)
s
(
ct
b
O
-
so
Open-drain
Vss
Floating
Alternate functions
u
d
o
When an on-chip peripheral is configured to use a pin, the alternate function is automatically
selected. This alternate function takes priority over the standard I/O programming.
r
P
e
When the signal is coming from an on-chip peripheral, the I/O pin is automatically
configured in output mode (push-pull or open drain according to the peripheral).
t
e
l
o
When the signal is going to an on-chip peripheral, the I/O pin must be configured in input
mode. In this case, the pin state is also digitally readable by addressing the DR register.
bs
Note:
O
Input pull-up configuration can cause unexpected value at the input of the alternate
peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to
be configured in input floating mode.
63/201
I/O ports
ST7232Axx-Auto
Figure 26. I/O port general block diagram
Register
access
1
Alternate
output
VDD
P-buffer (see Table below)
0
Pull-up (see Table below)
Alternate
enable
DR
VDD
DDR
Pull-up
condition
Pad
Data bus
OR
If implemented
OR SEL
N-buffer
)
s
t(
Diodes
(see Table below)
c
u
d
DDR SEL
o
r
P
Analog input
CMOS
Schmitt trigger
DR SEL
e
t
le
1
so
0
External interrupt
source (eix)
Table 18.
)
s
(
ct
du
o
r
P
e
Floating with/without interrupt
t
e
l
o
Pull-up with/without interrupt
Push-pull
bs
Output
O
b
O
-
I/O port mode options
Configuration mode
Input
Alternate input
Diodes
Pull-up
to VDD
Off(1)
On(2)
Off(1)
Open drain (logic level)
True open drain
P-buffer
NI(3)
Off(1)
On(2)
On(2)
Off(1)
NI(3)
NI(4)
1. Implemented not activated
2. Implemented and activated
3. Not implemented
4. The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VSS is
implemented to protect the device against positive stress.
64/201
to VSS
On(2)
ST7232Axx-Auto
Table 19.
I/O ports
I/O port configurations
Hardware configuration
Not implemented in
true open drain
I/O ports
DR register access
VDD
RPU
Pull-up condition
W
DR
register
Data bus
Pad
Input(1)
R
Alternate input
External interrupt source (eix)
Interrupt condition
Analog input
Open-drain output(2)
Not implemented in
true open drain
I/O ports
DR register access
VDD
RPU
DR
register
Pad
e
t
le
Alternate
enable
Push-pull output(2)
Not implemented in
true open drain
I/O ports
VDD
(s)
RPU
Pad
d
o
r
P
e
t
c
u
o
s
b
O
-
Alternate
enable
c
u
d
R/W
o
r
P
)
s
t(
Data bus
Alternate
output
DR register access
DR
register
R/W
Data bus
Alternate
output
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR
register reads the alternate function output status.
t
e
l
o
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate
function reads the pin status given by the DR register content.
s
b
O
Caution:
The alternate function must not be activated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious interrupts.
65/201
I/O ports
ST7232Axx-Auto
Analog alternate function
When the pin is used as an ADC input, the I/O must be configured as floating input. The
analog multiplexer (controlled by the ADC registers) switches the analog voltage present on
the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level or loading on any port pin while
conversion is in progress. Furthermore it is recommended not to have clocking pins located
close to a selected analog pin.
Warning:
9.3
The analog input voltage level must be within the limits
stated in the absolute maximum ratings.
I/O port implementation
)
s
t(
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC input or true open drain.
c
u
d
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 27
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation. The I/O port register
configurations are summarized in Table 20 below.
Figure 27. Interrupt I/O port state transitions
01
(s)
Input
floating/pull-up
interrupt
od
t
c
u
r
P
e
t
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s
b
O
66/201
e
t
le
o
s
b
O
-
o
r
P
00
10
11
Input
floating
(reset state)
Output
open-drain
Output
push-pull
XX
= DDR, OR
ST7232Axx-Auto
I/O ports
Table 20.
Port register configurations
Input (DDR = 0)
Port
Output (DDR = 1)
Pin name
OR = 0
OR = 1
PA[7:6]
Port A
OR = 0
Floating
PA[5:4]
OR = 1
True open-drain
Pull-up
PA[3]
Floating interrupt
PB[3]
Port B
PB[4]
PB[2:0]
Port C
PC[7:0]
Port D
PD[5:0]
Port E
PE[1:0]
Pull-up interrupt
Floating
Open drain
Push-pull
Pull-up
PF[7:6]
PF[4]
Port F
9.4
PF[2]
Floating interrupt
PF[1:0]
Pull-up interrupt
Low power modes
Table 21.
e
t
le
o
r
P
Effect of low power modes on I/O ports
o
s
b
O
-
Mode
9.5
c
u
d
)
s
t(
Description
Wait
No effect on I/O ports. External interrupts cause the device to exit from wait mode.
Halt
No effect on I/O ports. External interrupts cause the device to exit from halt mode.
Interrupts
)
s
(
ct
u
d
o
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and the interrupt mask in the CC register is not active
(RIM instruction).
r
P
e
t
e
l
o
Table 22.
s
b
O
I/O interrupt control/wake-up capability
Interrupt event
External interrupt on selected
external event
Event flag Enable control bit
-
DDRx
ORx
Exit from wait
Exit from halt
Yes
67/201
I/O ports
ST7232Axx-Auto
Table 23.
I/O port register map and reset values
Address (Hex.)
Register label
7
6
5
4
3
2
1
0
Reset value of all I/O port registers
0
0
0
0
0
0
0
0
0000h
PADR
0001h
PADDR
0002h
PAOR
0003h
PBDR
0004h
PBDDR
0005h
PBOR
0006h
PCDR
0007h
PCDDR
0008h
PCOR
0009h
PDDR
000Ah
PDDDR
000Bh
PDOR
000Ch
PEDR
000Dh
PEDDR
000Eh
PEOR
000Fh
PFDR
0010h
PFDDR
MSB
0011h
PFOR
b
O
-
)
s
(
ct
u
d
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O
68/201
MSB
LSB
MSB
LSB
MSB
LSB
MSB
c
u
d
MSB
so
e
t
le
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r
P
)
s
t(
LSB
LSB
LSB
ST7232Axx-Auto
On-chip peripherals
10
On-chip peripherals
10.1
Watchdog timer (WDG)
10.1.1
Introduction
The watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before the T6 bit becomes cleared.
10.1.2
10.1.3
Main features
●
Programmable free-running downcounter
●
Programmable reset
●
Reset (if watchdog activated) when the T6 bit reaches zero
●
Optional reset on HALT instruction (configurable by option byte)
●
Hardware watchdog selectable by option byte
Functional description
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The counter value stored in the watchdog control register (WDGCR bits T[6:0]), is
decremented every 16384 fOSC2 cycles (approx.), and the length of the timeout period can
be programmed by the user in 64 increments.
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If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling the reset pin low
for typically 30µs.
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The application program must write in the WDGCR register at regular intervals during
normal operation to prevent an MCU reset. This downcounter is free-running: it counts down
even if the watchdog is disabled. The value to be stored in the WDGCR register must be
between FFh and C0h:
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The WDGA bit is set (watchdog enabled)
The T6 bit is set to prevent generating an immediate reset
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset (see Figure 29: Approximate timeout duration).
The timing varies between a minimum and a maximum value due to the unknown
status of the prescaler when writing to the WDGCR register (see Figure 30).
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the watchdog is activated, the HALT instruction generates a reset.
69/201
On-chip peripherals
ST7232Axx-Auto
Figure 28. Watchdog block diagram
Reset
fOSC2
MCC/RTC
Watchdog control register (WDGCR)
DIV 64
WDGA
T6
T5
T4
T3
T2
T1
T0
6-bit downcounter (CNT)
12-bit MCC
RTC counter
MSB
LSB
0
65
11
10.1.4
WDG prescaler DIV 4
TB[1:0] bits (MCCSR register)
How to program the watchdog timeout
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Figure 29 shows the linear relationship between the 6-bit value to be loaded in the watchdog
counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a
quick calculation without taking the timing variations into account. If more precision is
needed, use the formulae in Figure 30.
Caution:
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When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
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Figure 29. Approximate timeout duration
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30
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CNT value (hex.)
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20
18
10
08
00
1.5
18
34
50
65
Watchdog timeout (ms) @ 8 MHz. fOSC2
70/201
82
98
114
128
ST7232Axx-Auto
On-chip peripherals
Figure 30. Exact timeout duration (tmin and tmax)
Where:
tmin0 = (LSB + 128) x 64 x tOSC2
tmax0 = 16384 x tOSC2
tOSC2 = 125ns if fOSC2 = 8 MHz
CNT = value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register.
TB1 bit (MCCSR reg.)
TB0 bit (MCCSR reg.)
Selected MCCSR timebase
MSB
LSB
0
0
2ms
4
59
0
1
4ms
8
53
1
0
10ms
20
35
1
1
25ms
49
54
To calculate the minimum watchdog timeout (tmin):
If CNT < MSB
------------4
Then t
Else t
min
min
= t
min0
+ 16384 ×
CNT
×
t
osc2
4CNT
= t
+ 16384 × ⎛ CNT – ----------------- ⎞
min0
⎝
MSB ⎠
+ ( 192 + LSB ) ×
4CNT
64 × ----------------MSB
×
To calculate the maximum watchdog timeout (tmax):
If CNT
------------≤ MSB
4
Then t
Else t
max
max
max0
+ 16384 ×
max0
4CNT
+ 16384 × ⎛ CNT – ----------------- ⎞
⎝
MSB ⎠
= t
= t
CNT
×
t
osc2
+ ( 192 + LSB ) ×
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4CNT
64 × ----------------MSB
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×
t
osc2
Note: In the above formulae, division results must be rounded down to the next integer value.
Example: With 2ms timeout selected in MCCSR register
Value of T[5:0] bits in WDGCR register
(Hex.)
Min. watchdog timeout (ms)
tmin
Max. watchdog timeout (ms)
tmax
00
1.496
2.048
128
128.552
3F
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On-chip peripherals
10.1.5
ST7232Axx-Auto
Low power modes
Table 24.
Effect of low power modes on watchdog timer
Mode
Description
Slow
No effect on watchdog.
Wait
No effect on watchdog.
OIE bit in
MCCSR
register
WDGHALT
bit in option
byte
0
0
Halt
0
1
10.1.6
No watchdog reset is generated. The MCU enters halt mode.
The watchdog counter is decremented once and then stops
counting and is no longer able to generate a watchdog reset
until the MCU receives an external interrupt or a reset.
If an external interrupt is received, the watchdog restarts
counting after 256 or 4096 CPU clocks. If a reset is generated,
the watchdog is disabled (reset state) unless hardware
watchdog is selected by option byte. For application
recommendations see Section 10.1.7 below.
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1
A reset is generated
x
No reset is generated. The MCU enters active halt mode. The
watchdog counter is not decremented. It stops counting. When
the MCU receives an oscillator interrupt or external interrupt,
the watchdog restarts counting immediately. When the MCU
receives a reset the watchdog restarts counting after 256 or
4096 CPU clocks.
Hardware watchdog option
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If hardware watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to Section 14.2: Flash devices.
10.1.7
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Using halt mode with the WDG (WDGHALT option)
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The following recommendation applies if halt mode is used when the watchdog is enabled:
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Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected
WDG reset immediately after waking up the microcontroller.
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10.1.8
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Interrupts
None
ST7232Axx-Auto
10.1.9
On-chip peripherals
Control register (WDGCR)
WDGCR
Reset value: 0111 1111 (7Fh)
7
6
5
4
3
2
WDGA
T[6:0]
R/W
R/W
Table 25.
1
0
WDGCR register description
Bit
7
6:0
Bit name
Function
WDGA
Activation bit(1)
This bit is set by software and only cleared by hardware after a reset.
When WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
T[6:0]
7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter. They are
decremented every 16384 fOSC2 cycles (approx.). A reset is
produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
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1. The WDGA bit is not used if the hardware watchdog option is enabled by option byte.
10.1.10
Watchdog timer register map and reset values
Table 26.
Watchdog timer register map and reset values
Address(Hex.)
Register label
002Ah
WDGCR
Reset value
7
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WDGA
0
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10.2
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T6
1
5
T5
1
4
3
2
1
0
T4
1
T3
1
T2
1
T1
1
T0
1
Main clock controller with real-time clock and beeper
(MCC/RTC)
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The main clock controller consists of three different functions:
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10.2.1
A programmable CPU clock prescaler
A clock-out signal to supply external devices
A real-time clock timer with interrupt capability
Each function can be used independently and simultaneously.
Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal
peripherals. It manages slow power saving mode (see Section 8.2: Slow mode for more
details).
The prescaler selects the fCPU main clock frequency and is controlled by three bits in the
MCCSR register: CP[1:0] and SMS.
73/201
On-chip peripherals
10.2.2
ST7232Axx-Auto
Clock-out capability
The clock-out capability is an alternate function of an I/O port pin that outputs a fOSC2 clock
to drive external devices. It is controlled by the MCO bit in the MCCSR register.
Caution:
When selected, the clock out pin suspends the clock during active halt mode.
10.2.3
Real-time clock timer (RTC)
The counter of the real-time clock timer allows an interrupt to be generated based on an
accurate real-time clock. Four different time bases depending directly on fOSC2 are available.
The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and
OIF.
When the RTC interrupt is enabled (OIE bit set), the ST7 enters active halt mode when the
HALT instruction is executed. See Section 8.4: Active halt and halt modes for more details.
10.2.4
Beeper
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The beep function is controlled by the MCCBCR register. It can output three selectable
frequencies on the BEEP pin (I/O port alternate function).
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Figure 31. Main clock controller (MCC/RTC) block diagram
BC1 BC0
MCCBCR
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Beep signal
selection
DIV 64
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DIV 2, 4, 8, 16
1
0
Beep
MCO
To watchdog timer
12-bit MCC RTC
counter
MCO CP1 CP0 SMS TB1
MCCSR
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TB0
OIE
OIF
MCC/RTC interrupt
fCPU
CPU clock
to CPU and
peripherals
ST7232Axx-Auto
10.2.5
On-chip peripherals
Low power modes
Table 27.
Effect of low power modes on MCC/RTC
Mode
10.2.6
Description
Wait
No effect on MCC/RTC peripheral
MCC/RTC interrupt causes the device to exit from wait mode
Active halt
No effect on MCC/RTC counter (OIE bit is set), the registers are frozen
MCC/RTC interrupt causes the device to exit from active halt mode
Halt
MCC/RTC counter and registers are frozen
MCC/RTC operation resumes when the MCU is woken up by an interrupt with
‘exit from halt’ capability
Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is
set and the interrupt mask in the CC register is not active (RIM instruction).
Table 28.
MCC/RTC interrupt control/wake-up capability
Interrupt event
Event flag
Enable control bit
Time base overflow event
OIF
OIE
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Exit from wait
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Exit from halt
No(1)
1. The MCC/RTC interrupt wakes up the MCU from active halt mode, not from halt mode.
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On-chip peripherals
10.2.7
ST7232Axx-Auto
MCC/RTC registers
MCC control/status register (MCCSR)
MCCSR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
MCO
CP[1:0]
SMS
TB[1:0]
OIE
OIF
R/W
R/W
R/W
R/W
R/W
R/W
Table 29.
MCCSR register description
Bit
7
Bit name
Function
MCO
Main clock out selection
This bit enables the MCO alternate function on the PF0 I/O port. It is
set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (fCPU on I/O port)
Note: To reduce power consumption, the MCO function is not active
in active halt mode.
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3:2
TB[1:0]
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Slow mode select
This bit is set and cleared by software.
0: Normal mode, fCPU = fOSC2
1: Slow mode, fCPU is given by CP1, CP0; see Section 8.2: Slow
mode and Section 10.2: Main clock controller with real-time clock
and beeper (MCC/RTC) for more details.
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CPU clock prescaler
These bits select the CPU clock prescaler which is applied in the
different slow modes. Their action is conditioned by the setting of the
SMS bit. These two bits are set and cleared by software.
00: fCPU in slow mode = fOSC2/2
01: fCPU in slow mode = fOSC2/4
10: fCPU in slow mode = fOSC2/8
11: fCPU in slow mode = fOSC2/16
CP[1:0]
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Time base control
These bits select the programmable divider time base. They are set
and cleared by software:
00: Time base (for counter prescaler 16000) = 4ms (fOSC2 = 4MHz)
and 2ms (fOSC2 = 8MHz)
01: Time base (for counter prescaler 32000) = 8ms (fOSC2 = 4MHz)
and 4ms (fOSC2 = 8MHz)
10: Time base (for counter prescaler 80000) = 20ms (fOSC2 = 4MHz)
and 10ms (fOSC2 = 8MHz)
11: Time base (for counter prescaler 200000) = 50ms
(fOSC2 = 4MHz) and 25ms (fOSC2 = 8MHz)
A modification of the time base is taken into account at the end of the
current period (previously set) to avoid an unwanted time shift. This
allows use of this time base as a real-time clock.
ST7232Axx-Auto
On-chip peripherals
Table 29.
MCCSR register description (continued)
Bit
1
Bit name
Function
OIE
Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from active halt mode. When this
bit is set, calling the ST7 software HALT instruction enters the active
halt power saving mode
.
0
Oscillator interrupt flag
This bit is set by hardware and cleared by software reading the
MCCSR register. It indicates when set that the main oscillator has
reached the selected elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
Caution: The BRES and BSET instructions must not be used on the
MCCSR register to avoid unintentionally clearing the OIF bit.
OIF
MCC beep control register (MCCBCR)
MCCBCR
Reset value: 0000 0000 (00h)
7
6
5
4
3
-
Bit
Bit name
7:2
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BC[1:0]
1
0
BC[1:0]
R/W
Function
Reserved, must be kept cleared
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MCCBCR register description
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2
Reserved
Table 30.
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Beep control
These 2 bits select the PF1 pin beep capability:
00: Beep mode (with fOSC2 = 8MHz) = off
01: Beep mode (with fOSC2 = 8MHz) = ~2-KHz (output beep
signal ~ 50% duty cycle)
10: Beep mode (with fOSC2 = 8MHz) = ~1-KHz (output beep
signal ~ 50% duty cycle)
11: beep mode (with fOSC2 = 8MHz) = ~500-Hz (output beep
signal ~ 50% duty cycle)
The beep output signal is available in active halt mode but has to be
disabled to reduce the consumption.
77/201
On-chip peripherals
10.2.8
ST7232Axx-Auto
MCC register map and reset values
Table 31.
Main clock controller register map and reset values
Address(Hex.)
Register label
7
6
5
4
3
2
1
0
002Ch
MCCSR
Reset value
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
002Dh
MCCBCR
Reset value
0
0
0
0
0
0
BC1
0
BC0
0
10.3
16-bit timer
10.3.1
Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
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It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).
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Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.
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Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and
do not share any resources. They are synchronized after a MCU reset as long as the timer
clock frequencies are not modified.
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This description covers one or two 16-bit timers. In ST7 devices with two timers, register
names are prefixed with TA (Timer A) or TB (Timer B).
10.3.2
Main features
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Programmable prescaler: fCPU divided by 2, 4 or 8
●
Overflow status flag and maskable interrupt
●
External clock input (must be at least 4 times slower than the CPU clock speed) with
the choice of active edge
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1 or 2 output compare functions each with:
–
2 dedicated 16-bit registers
–
2 dedicated programmable signals
–
2 dedicated status flags
–
1 dedicated maskable interrupt
1 or 2 input capture functions each with:
–
2 dedicated 16-bit registers
–
2 dedicated active edge selection signals
–
2 dedicated status flags
–
1 dedicated maskable interrupt
●
Pulse width modulation mode (PWM
●
One pulse mode
ST7232Axx-Auto
On-chip peripherals
●
Reduced power mode
●
5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)(a)
The block diagram is shown in Figure 32.
10.3.3
Functional description
Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
Counter register (CR)
●
Counter high register (CHR) is the most significant byte (MS byte)
●
Counter low register (CLR) is the least significant byte (LS byte)
Alternate counter register (ACR)
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Alternate counter high register (ACHR) is the most significant byte (MS byte)
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Alternate counter low register (ACLR) is the least significant byte (LS byte)
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These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the
status register, (SR), (see 16-bit read sequence (from either the counter register or alternate
counter register) on page 81).
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Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value.
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Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and PWM
mode.
The timer clock depends on the clock control bits (bits 3 and 2) of the CR2 register, as
illustrated in Table 36: CR2 register description. The value in the counter register repeats
every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The
timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
Caution:
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In Flash devices, Timer A functionality has the following restrictions:
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TAOC2HR and TAOC2LR registers are write only
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Input capture 2 is not implemented
The corresponding interrupts cannot be used (ICF2, OCF2 forced by hardware to zero)
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a. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pinout
description. When reading an input signal on a non-bonded pin, the value is always ‘1’.
79/201
On-chip peripherals
ST7232Axx-Auto
Figure 32. Timer block diagram
ST7 internal bus
fCPU
MCU-peripheral interface
8 high
8 low
8-bit
buffer
8
High
EXEDG
8
8
Low
High
8
Low
8
High
8
8
Low
High
8
Low
16
1/2
Output
compare
register
1
Counter register
1/4
1/8
EXTCLK
pin
Output
compare
register
2
Input
capture
register
2
Input
capture
register
1
Alternate counter
register
16
16
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CC[1:0]
Timer internal bus
16
Overflow detect
circuit
16
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ICF1 OCF1 TOF ICF2 OCF2 TIMD
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Edge detect circuit 1
ICAP1
pin
Edge detect circuit 2
ICAP2
pin
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ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
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Latch1
OCMP1
pin
Latch2
OCMP2
pin
0
CSR (control/status register)
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CR1 (control register 1)
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
CR2 (control register 2)
(1)
Timer interrupt
1.
If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table 15: Interrupt mapping on page 53).
80/201
ST7232Axx-Auto
On-chip peripherals
16-bit read sequence (from either the counter register or alternate counter register)
Figure 33. 16-bit read sequence
Beginning of the sequence
At t0
Read MS byte
LS byte is buffered
Other
instructions
At t0 +∆t
Read LS byte
Returns buffered LS byte
value at t0
Sequence completed
The user must read the MS byte first, then the LS byte value is buffered automatically.
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This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MS byte several times.
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After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LS byte of the count value at the time of the read.
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Whatever the timer mode used (input capture, output compare, one pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:
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The TOF bit of the SR register is set
●
A timer interrupt is generated if the TOIE bit of the CR1 register is set and the I bit of the
CC register is cleared
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If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
Note:
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1.
Reading the SR register while the TOF bit is set
2.
An access (read or write) to the CLR register
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The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
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The timer is not affected by wait mode.
s
b
O
In halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a reset).
81/201
On-chip peripherals
ST7232Axx-Auto
External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that triggers the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 34. Counter timing diagram, internal clock divided by 2
CPU clock
Internal reset
Timer clock
Counter register
FFFD
FFFE
FFFF
0000
0001
Timer overflow flag (TOF)
0002
0003
c
u
d
)
s
t(
o
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P
Figure 35. Counter timing diagram, internal clock divided by 4
e
t
le
CPU clock
Internal reset
Timer clock
(s)
Counter register
o
s
b
O
-
FFFC
FFFD
0000
0001
t
c
u
Timer overflow flag (TOF)
d
o
r
P
e
Figure 36. Counter timing diagram, internal clock divided by 8
t
e
l
o
s
b
O
CPU clock
Internal reset
Timer clock
Counter register
FFFC
FFFD
0000
Timer overflow flag (TOF)
Note:
82/201
The MCU is in reset state when the internal reset signal is high, when it is low the MCU is
running.
ST7232Axx-Auto
On-chip peripherals
Input capture
In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the
16-bit timer.
The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the
free running counter after a transition is detected on the ICAPi pin (see below).
ICiR
MSB
LSB
ICiHR
ICiLR
ICiR register is a read-only register.
The active transition is software programmable through the IEDGi bit of Control Registers
(CRi).
Timing resolution is one count of the free running counter: (fCPU/CC[1:0]).
Procedure
To use the input capture function select the following in the CR2 register:
)
s
t(
●
The timer clock (CC[1:0]) (see Table 36: CR2 register description)
●
The edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
Select the following in the CR1 register:
e
t
le
c
u
d
o
r
P
●
Set the ICIE bit to generate an interrupt after an input capture coming from either the
ICAP1 pin or the ICAP2 pin.
●
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input or input with pull-up without interrupt if
this configuration is available).
When an input capture occurs:
)
s
(
ct
o
s
b
O
-
●
ICFi bit is set
●
The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see Figure 38).
●
A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
u
d
o
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P
e
Clearing the input capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
t
e
l
o
1.
2.
By reading the SR register while the ICFi bit is set
By accessing (reading or writing) the ICiLR register
s
b
O
83/201
On-chip peripherals
Note:
ST7232Axx-Auto
1
After reading the ICiHR register, transfer of input capture data is inhibited and ICFi is never
set until the ICiLR register is also read.
2
The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
3
The 2 input capture functions can be used together even if the timer also uses the 2 output
compare functions.
4
In one pulse mode and PWM mode only input capture 2 can be used.
5
The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any
transitions on these pins activates the input capture function.
Moreover if one of the ICAPi pins is configured as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR
(see note 1).
6
The TOF bit can be used with interrupt generation in order to measure events that go
beyond the timer range (FFFFh).
7
In Flash devices, the ICAP2 registers (TAIC2HR, TAIC2LR) are not available on Timer A.
The corresponding interrupts cannot be used (ICF2 is forced by hardware to 0).
c
u
d
Figure 37. Input capture block diagram
ICAP1
pin
Edge detect
circuit 2
ICAP2
pin
IC2R register
Edge detect
circuit 1
(s)
16-bit
ct
16-bit free running counter
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84/201
CR1 (control register 1)
ICIE
so
b
O
-
IC1R register
e
t
le
o
r
P
ICF1
)
s
t(
IEDG1
SR (status register)
ICF2
0
0
0
CR2 (control register 2)
CC1
CC0 IEDG2
ST7232Axx-Auto
On-chip peripherals
Figure 38. Input capture timing diagram
Timer clock
FF01
Counter register
FF02
FF03
ICAPi pin
ICAPi flag
FF03
ICAPi register
1.
The rising edge is the active edge.
Output compare
)
s
t(
In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in
the 16-bit timer.
c
u
d
This function can be used to control an output waveform or indicate when a period of time
has elapsed.
o
r
P
When a match is found between the output compare register and the free running counter,
the output compare function:
e
t
le
●
Assigns pins with a programmable value if the OCiE bit is set
●
Sets a flag in the status register
●
Generates an interrupt if enabled
o
s
b
O
-
Two 16-bit registers, output compare register 1 (OC1R) and output compare register 2
(OC2R) contain the value to be compared to the counter register each timer clock cycle (see
below).
u
d
o
)
s
(
ct
OCiR
MSB
LSB
OCiHR
OCiLR
r
P
e
These registers are readable and writable and are not affected by the timer hardware. A
reset event changes the OCiR value to 8000h.
t
e
l
o
Timing resolution is one count of the free running counter: (fCPU/CC[1:0]).
s
b
O
Procedure
To use the output compare function, select the following in the CR2 register:
●
Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
●
Select the timer clock (CC[1:0]) (see Table 36: CR2 register description)
Select the following in the CR1 register:
●
Select the OLVLi bit to applied to the OCMPi pins after the match occurs
●
Set the OCIE bit to generate an interrupt if it is needed
85/201
On-chip peripherals
ST7232Axx-Auto
When a match is found between OCRi register and CR register:
●
OCFi bit is set
●
The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset)
●
A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is
cleared in the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using
the following formula:
∆ OCiR =
∆t * fCPU
PRESC
Where:
∆t
= Output compare period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC
= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 36: CR2
register description)
If the timer clock is an external clock, the formula is:
c
u
d
∆ OCiR = ∆t * fEXT
Where:
∆t
e
t
le
= Output compare period (in seconds)
fEXT = External timer clock frequency (in hertz)
)
s
t(
o
r
P
o
s
b
O
-
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by:
1.
Reading the SR register while the OCFi bit is set
2.
Accessing (reading or writing) the OCiLR register
)
s
(
ct
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OCiR register:
●
Write to the OCiHR register (further compares are inhibited)
●
Read the SR register (first step of the clearance of the OCFi bit, which may be already
set)
●
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86/201
u
d
o
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit)
ST7232Axx-Auto
Note:
On-chip peripherals
1
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
2
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit does not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
3
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see Figure 40 on page 88 for an example with fCPU/2 and
Figure 41 on page 88 for an example with fCPU/4). This behavior is the same in OPM or
PWM mode.
4
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
5
The value in the 16-bit OCiR register and the OLVi bit should be changed after each
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
6
In Flash devices, the TAOC2HR, TAOC2LR registers are ‘write only’ in Timer A. The
corresponding event cannot be generated (OCF2 is forced by hardware to 0).
Forced compare output capability
)
s
t(
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
c
u
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P
The FOLVLi bits have no effect in both one pulse mode and PWM mode.
Figure 39. Output compare block diagram
16 bit free running counter
Output compare circuit
16-bit
c
u
d
16-bit
OC1R register
o
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e
OC2R register
o
s
b
O
-
OC1E OC2E
16-bit
(t s)
e
t
le
OCIE
OCF1
CC1
CC0
CR2 (control register 2)
CR1 (control register 1)
FOLV2 FOLV1 OLVL2
OCF2
0
OLVL1
0
Latch
1
OCMP1
pin
Latch
2
OCMP2
pin
0
SR (status register)
t
e
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s
b
O
87/201
On-chip peripherals
ST7232Axx-Auto
Figure 40. Output compare timing diagram, fTIMER = fCPU/2
Internal CPU clock
Timer clock
Counter register
2ECF
2ED0
2ED1 2ED2
2ED3
2ED4
2ED3
Output compare register i (OCRi)
Output compare flag i (OCFi)
OCMPi pin (OLVLi = 1)
Figure 41. Output compare timing diagram, fTIMER = fCPU/4
Internal CPU clock
Timer clock
Counter register
2ECF 2ED0
2ED3
Output compare register i (OCRi)
Output compare flag i (OCFi)
e
t
le
OCMPi pin (OLVLi = 1)
)
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88/201
c
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2ED1 2ED2 2ED3 2ED4
o
s
b
O
-
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)
s
t(
ST7232Axx-Auto
On-chip peripherals
One pulse mode
One pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one pulse mode uses the input capture1 function and the output compare1 function.
Procedure
To use one pulse mode:
1.
Load the OC1R register with the value corresponding to the length of the pulse using
the appropriate formula below according to the timer clock source used
2.
Select the following in the CR1 register:
3.
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse
–
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse
–
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input)
Select the following in the CR2 register:
c
u
d
)
s
t(
–
Set the OC1E bit (the OCMP1 pin is then dedicated to the output compare 1
function)
–
Set the OPM bit
–
Select the timer clock CC[1:0] (see Table 36: CR2 register description)
e
t
le
Figure 42. One pulse mode sequence
o
s
b
O
-
o
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P
One pulse mode cycle
When event occurs
on ICAP1
)
s
(
ct
u
d
o
r
P
e
When
counter = OCIR
ICR1 = counter
OCMP1 = OLVL2
Counter is reset to FFFCh
ICF1 bit is set
OCMP1 = OLVL1
s
b
O
t
e
l
o
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the input capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
1.
Reading the SR register while the ICFi bit is set
2.
Accessing (reading or writing) the ICiLR register
89/201
On-chip peripherals
ST7232Axx-Auto
The OC1R register value required for a specific timing application can be calculated using
the following formula:
OCiR value =
t * fCPU
-5
PRESC
Where:
t
= Pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC =
Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 36: CR2
register description)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
t
= Pulse period (in seconds)
c
u
d
fEXT = External timer clock frequency (in hertz)
)
s
t(
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin, (see Figure 43).
Note:
The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate
an output compare interrupt.
2
When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
3
If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin.
4
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
e
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)
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ct
90/201
u
d
o
o
s
b
O
-
5
When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the one pulse mode.
6
In Flash devices, Timer A OCF2 bit is forced by hardware to 0.
r
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1
ST7232Axx-Auto
On-chip peripherals
Figure 43. One pulse mode timing example
01F8
IC1R
Counter
FFFC FFFD
01F8
FFFE
2ED3
2ED0
2ED1 2ED2
FFFC
FFFD
2ED3
ICAP1
OLVL2
OCMP1
OLVL2
OLVL1
Compare1
1.
IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
Figure 44. Pulse width modulation mode timing example with 2 output compare
functions
Counter 34E2 FFFC FFFD
FFFE
OLVL2
OCMP1
34E2
e
t
le
)
s
t(
FFFC
c
u
d
OLVL2
OLVL1
OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
)
s
(
ct
2ED1 2ED2
Compare1
Compare2
1.
2ED0
Compare2
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-
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91/201
On-chip peripherals
ST7232Axx-Auto
Pulse width modulation mode
Pulse width modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse width modulation mode uses the complete output compare 1 function plus the OC2R
register, and so this functionality can not be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are taken into account only at the end of the
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
Procedure
To use pulse width modulation mode:
1.
Load the OC2R register with the value corresponding to the period of the signal using
the appropriate formula below according to the timer clock source used
2.
Load the OC1R register with the value corresponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the appropriate formula below according to the timer
clock source used
3.
Select the following in the CR1 register:
4.
c
u
d
)
s
t(
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register
–
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC2R register
Select the following in the CR2 register:
e
t
le
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P
–
Set OC1E bit (the OCMP1 pin is then dedicated to the output compare 1 function)
–
Set the PWM bit
–
Select the timer clock (CC[1:0]) (see Table 36: CR2 register description)
o
s
b
O
-
Figure 45. Pulse width modulation cycle
)
s
(
ct
o
r
P
e
t
e
l
o
s
b
O
du
Pulse width modulation cycle
When
counter = OC1R
OCMP1 = OLVL1
When
counter = OC2R
Counter is reset to FFFCh
OCMP1 = OLVL2
ICF1 bit is set
If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin.
92/201
ST7232Axx-Auto
On-chip peripherals
The OCiR register value required for a specific timing application can be calculated using
the following formula::
t * fCPU
OCiR value =
-5
PRESC
Where:
t
= Signal or pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC =
Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 36)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
t
= Signal or pulse period (in seconds)
fEXT = External timer clock frequency (in hertz)
c
u
d
)
s
t(
The output compare 2 event causes the counter to be initialized to FFFCh (see Figure 44)
Note:
o
r
P
1
After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
2
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the output
compare interrupt is inhibited.
3
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
4
In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
5
When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
e
t
le
)
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On-chip peripherals
10.3.4
ST7232Axx-Auto
Low power modes
Table 32.
Effect of low power modes on 16-bit timer
Mode
10.3.5
Description
Wait
No effect on 16-bit timer.
Timer interrupts cause the device to exit from wait mode.
Halt
16-bit timer registers are frozen.
In halt mode, the counter stops counting until halt mode is exited. Counting resumes from
the previous count when the MCU is woken up by an interrupt with ‘exit from halt mode’
capability or from the counter reset value when the MCU is woken up by a reset.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the MCU is woken up by an interrupt with ‘exit from halt mode’
capability, the ICFi bit is set, and the counter value present when exiting from halt mode is
captured into the ICiR register.
Interrupts
Table 33.
16-bit timer interrupt control/wake-up capability(1)
Interrupt event
Event flag Enable control bit
Input capture 1 event/counter
reset in PWM mode
ICF1
Input capture 2 event
ICF2
Output compare 1 event
(not available in PWM mode)
OCF1
Output compare 2 event
(not available in PWM mode)
OCF2
ICIE
e
t
le
o
s
b
O
-
c
u
d
Exit from wait
)
s
t(
Exit from halt
o
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P
Yes
No
OCIE
Timer overflow event
TOF
)
s
(
ct
TOIE
1. The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 7: Interrupts).
These events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
u
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ST7232Axx-Auto
10.3.6
On-chip peripherals
Summary of timer modes
Table 34.
Summary of timer modes
Timer resources
Modes
Input
capture 1
Input
capture 2
Input capture(1)and/or(2)
Output
compare 1
Output compare
2
Yes
Yes
Yes(2)
Yes
Output compare(1)and/or(2)
Yes
Not
recommended(1)
One pulse mode
Partially(2)
No
No
Not
recommended(3)
PWM mode
No
1. See note 4 in One pulse mode on page 89
2. See note 5 and 6 in One pulse mode on page 89
3. See note 4 in Pulse width modulation mode on page 92
10.3.7
c
u
d
16-bit timer registers
)
s
t(
Each timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) relating to the two input captures, the two output compares, the
counter and the alternate counter.
e
t
le
Control register 1 (CR1)
CR1
7
6
5
ICIE
OCIE
TOIE
R/W
R/W
Table 35.
Bit
t
e
l
o
O
bs
6
5
Reset value: 0000 0000 (00h)
4
3
2
1
0
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
R/W
R/W
R/W
R/W
R/W
CR1 register description
Bit name
Function
ICIE
Input capture interrupt enable
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the
SR register is set
OCIE
Output compare interrupt enable
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of
the SR register is set
TOIE
Timer overflow interrupt enable
0: Interrupt is inhibited
1: A timer interrupt is enabled whenever the TOF bit of the SR
register is set
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7
c
u
d
(t s)
R/W
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s
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95/201
On-chip peripherals
Table 35.
ST7232Axx-Auto
CR1 register description (continued)
Bit
4
3
2
1
0
Bit name
Function
FOLV2
Forced output compare 2
This bit is set and cleared by software.
0: No effect on the OCMP2 pin
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E
bit is set and even if there is no successful comparison
FOLV1
Forced output compare 1
This bit is set and cleared by software.
0: No effect on the OCMP1 pin
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is
set and even if there is no successful comparison
OLVL2
Output level 2
This bit is copied to the OCMP2 pin whenever a successful
comparison occurs with the OC2R register and OCxE is set in the
CR2 register. This value is copied to the OCMP1 pin in one pulse
mode and pulse width modulation mode.
IEDG1
Input edge 1
This bit determines which type of level transition on the ICAP1 pin
triggers the capture.
0: A falling edge triggers the capture
1: A rising edge triggers the capture
OLVL1
Output level 1
The OLVL1 bit is copied to the OCMP1 pin whenever a successful
comparison occurs with the OC1R register and the OC1E bit is set in
the CR2 register.
c
u
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e
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le
)
s
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e
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o
s
b
O
96/201
o
s
b
O
-
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)
s
t(
ST7232Axx-Auto
On-chip peripherals
Control register 2 (CR2)
CR2
Reset value: 0000 0000 (00h)
7
6
5
4
OC1E
OC2E
OPM
PWM
R/W
R/W
R/W
R/W
Table 36.
3
2
1
0
CC[1:0]
IEDG2
EXEDG
R/W
R/W
R/W
CR2 register description
Bit
7
Bit name
Function
OCIE
Output compare 1 pin enable
This bit is used only to output the signal from the timer on the
OCMP1 pin (OLV1 in output compare mode, both OLV1 and OLV2 in
PWM and one-pulse mode). Whatever the value of the OC1E bit, the
output compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for
general-purpose I/O)
1: OCMP1 pin alternate function enabled
c
u
d
6
Output compare 2 pin enable
This bit is used only to output the signal from the timer on the
OCMP2 pin (OLV2 in output compare mode). Whatever the value of
the OC2E bit, the output compare 2 function of the timer remains
active.
0: OCMP2 pin alternate function disabled (I/O pin free for generalpurpose I/O)
1: OCMP2 pin alternate function enabled
OC2E
e
t
le
5
OPM
r
P
e
u
d
o
s
b
O
t
e
l
o
3:2
PWM
CC[1:0]
o
r
P
o
s
b
O
-
One pulse mode
0: One pulse mode is not active
1: One pulse mode is active, the ICAP1 pin can be used to trigger
one pulse on the OCMP1 pin; the active transition is given by the
IEDG1 bit. The length of the generated pulse depends on the
contents of the OC1R register.
)
s
(
ct
4
)
s
t(
Pulse width modulation
0: PWM mode is not active
1: PWM mode is active, the OCMP1 pin outputs a programmable
cyclic signal; the length of the pulse depends on the value of OC1R
register; the period depends on the value of OC2R register.
Clock control
The timer clock mode depends on the following bits:
00: timer clock = fCPU/4
01: timer clock = fCPU/2
10: timer clock = fCPU/8
11: timer clock = external clock (where available)
Note: If the external clock pin is not available, programming the
external clock configuration stops the counter.
97/201
On-chip peripherals
Table 36.
ST7232Axx-Auto
CR2 register description (continued)
Bit
Bit name
1
0
Function
IEDG2
Input edge 2
This bit determines which type of level transition on the ICAP2 pin
triggers the capture.
0: A falling edge triggers the capture
1: A rising edge triggers the capture
EXEDG
External clock edge
This bit determines which type of level transition on the external
clock pin EXTCLK triggers the counter register.
0: A falling edge triggers the counter register
1: A rising edge triggers the counter register
Control/status register (CSR)
CSR
Reset value: xxxx x0xx (xxh)
7
6
5
4
3
2
ICF1
OCF1
TOF
ICF2
OCF2
TIMD
R
R
R
R
R
R/W
Table 37.
CSR register description
Bit
7
ICF1
6
s
b
O
98/201
5
4
OCF1
)
s
t(
0
Reserved
c
u
d
-
o
r
P
Function
Input capture flag 1
0: No input capture (reset value)
1: An input capture has occurred on the ICAP1 pin or the counter
has reached the OC2R value in PWM mode. To clear this bit, first
read the SR register, then read or write the low byte of the IC1R
(IC1LR) register.
)
s
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ct
u
d
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e
t
e
l
o
e
t
le
Bit name
1
o
s
b
O
-
Output compare flag 1
0: No match (reset value)
1: The content of the free running counter has matched the content
of the OC1R register. To clear this bit, first read the SR register, then
read or write the low byte of the OC1R (OC1LR) register.
TOF
Timer overflow flag
0: No timer overflow (reset value)
1: The free running counter rolled over from FFFFh to 0000h. To
clear this bit, first read the SR register, then read or write the low
byte of the CR (CLR) register.
Note: Reading or writing the ACLR register does not clear TOF
ICF2
Input capture flag 2
0: No input capture (reset value)
1: An input capture has occurred on the ICAP2 pin. To clear this bit,
first read the SR register, then read or write the low byte of the IC2R
(IC2LR) register.
ST7232Axx-Auto
On-chip peripherals
Table 37.
Bit
CSR register description (continued)
Bit name
Function
OCF2
Output compare flag 2
0: No match (reset value)
1: The content of the free running counter has matched the content
of the OC2R register. To clear this bit, first read the SR register, then
read or write the low byte of the OC2R (OC2LR) register.
2
TIMD
Timer disable
This bit is set and cleared by software. When set, it freezes the timer
prescaler and counter and disables the output functions (OCMP1
and OCMP2 pins) to reduce power consumption. Access to the timer
registers is still available, allowing the timer configuration to be
changed, or the counter reset, while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
1:0
-
3
Reserved, must be kept cleared
Input capture 1 high register (IC1HR)
c
u
d
)
s
t(
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the input capture 1 event).
IC1HR
7
Reset value: undefined
6
5
4
e
t
le
3
MSB
R
o
r
P
R
R
so
R
R
2
1
0
LSB
R
R
R
b
O
-
Input capture 1 low register (IC1LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input capture 1 event).
)
s
(
ct
du
5
R
R
IC1LR
7
6
o
r
P
e
MSB
t
e
l
o
R
Reset value: undefined
4
3
2
1
0
LSB
R
R
R
R
R
Output compare 1 high register (OC1HR)
O
bs
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
OC1HR
7
Reset value: 1000 0000 (80h)
6
5
4
3
2
1
MSB
R/W
0
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
99/201
On-chip peripherals
ST7232Axx-Auto
Output compare 1 low register (OC1LR)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
OC1LR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
MSB
R/W
0
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output compare 2 high register (OC2HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
OC2HR
7
Reset value: 1000 0000 (80h)
6
5
4
3
2
1
MSB
R/W
R/W
R/W
R/W
R/W
c
u
d
R/W
Output compare 2 low register (OC2LR)
R/W
)
s
t(
0
LSB
R/W
o
r
P
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
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t
le
so
OC2LR
7
6
5
MSB
R/W
R/W
(s)
R/W
b
O
4
R/W
3
Reset value: 0000 0000 (00h)
2
1
0
LSB
R/W
R/W
R/W
R/W
t
c
u
Counter high register (CHR)
d
o
r
P
e
This is an 8-bit register that contains the high part of the counter value.
CHR
t
e
l
o
7
6
Reset value: 1111 1111 (FFh)
5
4
3
2
1
MSB
bs
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100/201
R
R
0
LSB
R
R
R
R
R
R
ST7232Axx-Auto
On-chip peripherals
Counter low register (CLR)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after accessing the CSR register clears the
TOF bit.
CLR
Reset value: 1111 1100 (FCh)
7
6
5
4
3
2
1
MSB
0
R
LSB
R
R
R
R
R
R
R
Alternate counter high register (ACHR)
This is an 8-bit register that contains the high part of the counter value.
ACHR
7
Reset value: 1111 1111 (FFh)
6
5
4
3
2
1
MSB
R
R
R
R
R
Alternate counter low register (ACLR)
c
u
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R
R
)
s
t(
0
LSB
R
o
r
P
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after an access to CSR register does not clear
the TOF bit in the CSR register.
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ACLR
7
6
5
R
)
s
(
ct
MSB
R
R
o
s
b
O
4
R
3
R
Reset value: 1111 1100 (FCh)
2
1
0
LSB
R
R
R
u
d
o
Input capture 2 high register (IC2HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the input capture 2 event).
r
P
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t
e
l
o
IC2HR
s
b
O
7
Reset value: undefined
6
5
4
3
2
1
MSB
R
0
LSB
R
R
R
R
R
R
R
101/201
On-chip peripherals
ST7232Axx-Auto
Input capture 2 low register (IC2LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input capture 2 event).
IC2LR
7
Reset value: undefined
6
5
4
3
2
1
0
MSB
R
LSB
R
R
R
R
R
R
R
16-bit timer register map and reset values
Table 38.
16-bit timer register map and reset values
Address (Hex.) Register label
102/201
5
4
3
2
1
0
CR1
Reset value
Timer A: 31
Timer B: 41
CR2
Reset value
OC1E OC2E OPM
0
0
0
PWM
0
CC1
0
CC0
0
Timer A: 33
Timer B: 43
CSR
Reset value
ICF1
x
ICF2
x
OCF2
x
TIMD
0
x
Timer A: 34
Timer B: 44
IC1HR
Reset value
MSB
x
x
x
x
x
x
x
LSB
x
Timer A: 35
Timer B: 45
IC1LR
Reset value
MSB
x
x
x
x
x
x
x
LSB
x
Timer A: 36
Timer B: 46
OC1HR
Reset value
MSB
1
0
0
0
0
0
0
LSB
0
Timer A: 37
Timer B: 47
OC1LR
Reset value
MSB
0
0
0
0
0
0
0
LSB
0
Timer A: 3E
Timer B: 4E
OC2HR
Reset value
MSB
1
0
0
0
0
0
0
LSB
0
Timer A: 3F
Timer B: 4F
OC2LR
Reset value
MSB
0
0
0
0
0
0
0
LSB
0
Timer A: 38
Timer B: 48
du
CHR
Reset value
MSB
1
1
1
1
1
1
1
LSB
1
Timer A: 39
Timer B: 49
CLR
Reset value
MSB
1
1
1
1
1
1
0
LSB
0
Timer A: 3A
Timer B: 4A
ACHR
Reset value
MSB
1
1
1
1
1
1
1
LSB
1
Timer A: 3B
Timer B: 4B
ACLR
Reset value
MSB
1
1
1
1
1
1
0
LSB
0
Timer A: 3C
Timer B: 4C
IC2HR
Reset value
MSB
x
x
x
x
x
x
x
LSB
x
Timer A: 3D
Timer B: 4D
IC2LR
Reset value
MSB
x
x
x
x
x
x
x
LSB
x
t
e
l
o
O
6
Timer A: 32
Timer B: 42
ICIE
0
)
s
(
ct
o
r
P
e
bs
7
OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1
0
0
0
0
0
0
OCF1 TOF
x
x
o
s
b
O
-
e
t
le
)
s
t(
IEDG2 EXEDG
0
0
c
u
d
o
r
P
OLVL1
0
x
ST7232Axx-Auto
On-chip peripherals
10.4
Serial peripheral interface (SPI)
10.4.1
Introduction
The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves
however the SPI interface can not be a master in a multi-master system.
10.4.2
Main features
●
Full duplex synchronous transfers (on 3 lines)
●
Simplex synchronous transfers (on 2 lines)
●
Master or slave operation
●
Six master mode frequencies (fCPU/4 max.)
●
fCPU/2 max. slave mode frequency (see note below)
●
SS management by software or hardware
●
Programmable clock polarity and phase
●
End of transfer interrupt flag.
●
Write collision, master mode fault and overrun flags
c
u
d
)
s
t(
Note:
In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
10.4.3
General description
e
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o
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P
Figure 46 shows the serial peripheral interface (SPI) block diagram. There are 3 registers:
o
s
b
O
-
●
SPI control register (SPICR)
●
SPI control/status register (SPICSR)
●
SPI data register (SPIDR)
)
s
(
ct
The SPI is connected to external devices through 4 pins:
●
MISO: master in/slave out data
●
MOSI: master out / slave in data
●
SCK: serial clock out by SPI masters and input by SPI slaves
u
d
o
r
P
e
●
t
e
l
o
SS: Slave select:
This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves
individually and to avoid contention on the data lines. Slave SS inputs can be driven by
standard I/O ports on the master MCU.
s
b
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103/201
On-chip peripherals
ST7232Axx-Auto
Figure 46. Serial peripheral interface block diagram
Data/address bus
Read
SPIDR
Read buffer
Interrupt request
MOSI
MISO
8-bit shift register
7
0
SPICSR
SPIF WCOL OVR MODF
SOD
0
SSM
SSI
Write
SOD bit
SS
SCK
0
SPI state control
7
SPIE
SS
)
s
(
ct
Functional description
)
s
t(
0
o
r
P
SPR2 MSTR CPOL CPHA SPR1 SPR0
Master control
Serial clock generator
c
u
d
SPICR
SPE
1
e
t
le
o
s
b
O
-
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 47.
u
d
o
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
r
P
e
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
t
e
l
o
s
b
O
To use a single data line, the MISO and MOSI pins must be connected at each node ( in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see Figure 50) but master and
slave must be programmed with the same timing mode.
104/201
ST7232Axx-Auto
On-chip peripherals
Figure 47. Single master/single slave application
Master
MSbit
Slave
LSbit
8-bit shift register
SPI clock
generator
MSbit
MISO
MISO
MOSI
MOSI
SCK
SCK
SS
+5V
LSbit
8-bit shift register
SS
Not used if SS is managed by software
Slave select management
)
s
t(
As an alternative to using the SS pin to control the slave select signal, the application can
choose to manage the slave select signal by software. This is configured by the SSM bit in
the SPICSR register (see Figure 49)
c
u
d
o
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P
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
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In master mode:
●
SS internal must be held high continuously
In slave mode:
o
s
b
O
-
There are two cases depending on the data/clock timing relationship (see Figure 48):
If CPHA = 1 (data latched on 2nd clock edge):
)
s
(
ct
●
SS internal must be held low during the entire transmission. This implies that in single
slave applications the SS pin either can be tied to VSS, or made free for standard I/O by
managing the SS function by software (SSM = 1 and SSI = 0 in the in the SPICSR
register)
u
d
o
If CPHA = 0 (data latched on 1st clock edge):
r
P
e
●
t
e
l
o
SS internal must be held low during byte transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a write
collision error occurs when the slave writes to the shift register (see Write collision error
(WCOL) on page 110).
s
b
O
105/201
On-chip peripherals
ST7232Axx-Auto
Figure 48. Generic SS timing diagram
MOSI/MISO
Byte 2
Byte 1
Byte 3
Master SS
Slave SS
if CPHA = 0
Slave SS
if CPHA = 1
Figure 49. Hardware/software slave select management
SSM bit
SSI bit
1
SS external pin
0
SS internal
e
t
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Master mode operation
c
u
d
)
s
t(
o
r
P
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
Note:
o
s
b
O
-
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
)
s
(
ct
To operate the SPI in master mode, perform the following steps in order:
1.
Write to the SPICR register:
–
Select the clock frequency by configuring the SPR[2:0] bits
–
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 50 shows the four possible configurations.
u
d
o
r
P
e
Note: The slave must have the same CPOL and CPHA settings as the master.
2.
t
e
l
o
bs
O
Note:
3.
Write to the SPICSR register:
–
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin
high for the complete byte transmit sequence.
Write to the SPICR register:
–
Set the MSTR and SPE bits
1
If the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not
taken into account.
2
MSTR and SPE bits remain set only if SS is high).
The transmit sequence begins when software writes a byte in the SPIDR register.
106/201
ST7232Axx-Auto
On-chip peripherals
Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the most significant bit of the MOSI pin first.
When data transfer is complete:
●
The SPIF bit is set by hardware
●
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
Note:
1.
An access to the SPICSR register while the SPIF bit is set
2.
A read to the SPIDR register
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
)
s
t(
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1.
c
u
d
Write to the SPICSR register to perform the following actions:
–
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see Figure 50)
o
r
P
Note: The slave must have the same CPOL and CPHA settings as the master.
–
2.
e
t
le
Manage the SS pin as described in Slave select management on page 105 and
Figure 48. If CPHA = 1 SS must be held low continuously. If CPHA = 0 SS must be
held low during byte transmission and pulled up between each byte to let the slave
write in the shift register.
o
s
b
O
-
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
)
s
(
ct
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the most significant bit of the MISO pin first.
u
d
o
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
r
P
e
When data transfer is complete:
t
e
l
o
●
s
b
O
Note:
●
The SPIF bit is set by hardware
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1.
An access to the SPICSR register while the SPIF bit is set
2.
A write or a read to the SPIDR register
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
107/201
On-chip peripherals
ST7232Axx-Auto
The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an overrun condition (see Overrun condition
(OVR) on page 110).
10.4.4
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (see Figure 50).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge
Figure 50, shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the
MISO pin, the MOSI pin are directly connected between the master and the slave device.
Note:
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
c
u
d
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)
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108/201
o
s
b
O
-
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ST7232Axx-Auto
On-chip peripherals
Figure 50. Data clock timing diagram
CPHA = 1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MSbit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
MOS1
(from slave)
MSbit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSbit
LSbit
SS
(to slave)
Capture strobe
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CPHA = 0
SCK
(CPOL = 1)
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SCK
(CPOL = 0)
MISO
(from master)
MSbit
MOS1
(from slave)
MSbit
SS
(to slave)
Bit 5
Bit 4
Bit3
Bit 6
Bit 5
Bit 4
Bit3
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Bit 2
Bit 1
LSbit
Bit 2
Bit 1
LSbit
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Capture strobe
1.
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-
Bit 6
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This figure should not be used as a replacement for parametric information. Refer to Section 12: Electrical characteristics.
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109/201
On-chip peripherals
10.4.5
ST7232Axx-Auto
Error flags
Master mode fault (MODF)
Master mode fault occurs when the master device has its SS pin pulled low.
When a master mode fault occurs:
●
The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set
●
The SPE bit is reset. This blocks all output from the device and disables the SPI
peripheral.
●
The MSTR bit is reset, thus forcing the device into slave mode
Clearing the MODF bit is done through a software sequence:
Note:
1.
A read access to the SPICSR register while the MODF bit is set
2.
A write to the SPICR register
To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high
during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their
original state during or after this clearing sequence.
)
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Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set
except in the MODF bit clearing sequence.
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Overrun condition (OVR)
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An overrun condition occurs, when the master device has sent a data byte and the slave
device has not cleared the SPIF bit issued from the previously transmitted byte.
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When an overrun occurs, the OVR bit is set and an interrupt request is generated if the SPIE
bit is set.
o
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-
In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A
read to the SPIDR register returns this byte. All other bytes are lost.
The OVR bit is cleared by reading the SPICSR register.
)
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Write collision error (WCOL)
u
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A write collision occurs when the software tries to write to the SPIDR register while a data
transfer is taking place with an external device. When this happens, the transfer continues
uninterrupted and the software write is unsuccessful.
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Write collisions can occur both in master and slave mode. See also Slave select
management on page 105.
t
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Note:
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A‘read collision’ never occurs since the received data byte is placed in a buffer in which
access is always synchronous with the MCU operation.
The WCOL bit in the SPICSR register is set if a write collision occurs.
No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software sequence (see Figure 51).
110/201
ST7232Axx-Auto
On-chip peripherals
Figure 51. Clearing the WCOL bit (write collision flag) software sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st step
Read SPICSR
Result
2nd step
Read SPIDR
SPIF = 0
WCOL = 0
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st step
Read SPICSR
Result
2nd step
1.
WCOL = 0
Read SPIDR
Writing to the SPIDR register instead of reading it does not reset the WCOL bits.
Single master systems
)
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A typical single master system may be configured, using an MCU as the master and four
MCUs as slaves (see Figure 52).
c
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The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
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The SS pins are pulled high during reset since the master device ports are forced to be
inputs at that time, thus disabling the slave devices.
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Note:
To prevent a bus conflict on the MISO line the master allows only one active slave device
during a transmission.
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-
For more security, the slave device may respond to the master with the received data byte.
Then the master receives the previous byte back from the slave device if all MISO and MOSI
pins are connected and the slave has not written to its SPIDR register.
)
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Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
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111/201
On-chip peripherals
ST7232Axx-Auto
Figure 52. Single master/multiple slave configuration
SS
SS
SS
SCK
SCK
Slave MCU
Slave MCU
MOSI
MISO
MOSI
MISO
MOSI
SS
SCK
SCK
Slave MCU
MISO
MOSI
MISO
Slave MCU
MOSI
MISO
Master
MCU
5V
10.4.6
Ports
SCK
SS
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Low power modes
Table 39.
Effect of low power modes on SPI
Mode
Description
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Wait
No effect on SPI.
SPI interrupt events cause the device to exit from wait mode.
Halt
SPI registers are frozen.
In halt mode, the SPI is inactive. SPI operation resumes when the MCU is
woken up by an interrupt with ‘exit from halt mode’ capability. The data received
is subsequently read from the SPIDR register when the software is running
(interrupt vector fetching). If several data are received before the wake up event,
then an overrun error is generated. This error can be detected after the fetch of
the interrupt routine that woke up the device.
)
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u
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Using the SPI to wakeup the MCU from halt mode
r
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In slave configuration, the SPI is able to wakeup the ST7 device from halt mode through a
SPIF interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
Note:
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Caution:
112/201
When waking up from halt mode, if the SPI remains in slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from halt mode state to normal
state. If the SPI exits from slave mode, it returns to normal state immediately.
The SPI can wake up the ST7 from halt mode only if the slave select signal (external SS pin
or the SSI bit in the SPICSR register) is low when the ST7 enters halt mode. So if slave
selection is configured as external (see Slave select management on page 105), make sure
the master drives a low level on the SS pin when the slave enters halt mode.
ST7232Axx-Auto
10.4.7
On-chip peripherals
Interrupts
Table 40.
SPI interrupt control/wake-up capability(1)
Interrupt event
Event flag
SPI end of transfer event
SPIF
Master mode fault event
MODF
Enable control bit
Exit from wait
Exit from halt
Yes
SPIE
Yes
No
Overrun error
OVR
1. The SPI interrupt events are connected to the same interrupt vector (see Section 7: Interrupts). They
generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the CC register
is reset (RIM instruction).
10.4.8
SPI registers
Control register (SPICR)
SPICR
7
6
5
4
3
2
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
R/W
R/W
R/W
R/W
R/W
R/W
Table 41.
SPICR register description
Bit
SPIE
SPE
r
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O
5
SPR2
1
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0
SPR[1:0]
R/W
Function
o
s
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-
Serial peripheral interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or
OVR = 1 in the SPICSR register
)
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6
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Bit name
7
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Reset value: 0000 xxxx (0xh)
Serial peripheral output enable
This bit is set and cleared by software. It is also cleared by hardware
when, in master mode, SS = 0 (see Master mode fault (MODF) on
page 110). The SPE bit is cleared by reset, so the SPI peripheral is
not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Divider enable
This bit is set and cleared by software and is cleared by reset. It is
used with the SPR[1:0] bits to set the baud rate (see bits [1:0]
below).
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: The SPR2 bit has no effect in slave mode
113/201
On-chip peripherals
Table 41.
ST7232Axx-Auto
SPICR register description (continued)
Bit
4
3
2
Bit name
Function
MSTR
Master mode
This bit is set and cleared by software. It is also cleared by hardware
when, in master mode, SS = 0 (see Master mode fault (MODF) on
page 110).
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input
to an output and the functions of the MISO and MOSI pins are
reversed.
CPOL
Clock polarity
This bit is set and cleared by software. This bit determines the idle
state of the serial clock. The CPOL bit affects both the master and
slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication byte boundaries, the
SPI must be disabled by resetting the SPE bit.
CPHA
Clock phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge
1: The second clock transition is the first capture edge
Note: The slave must have the same CPOL and CPHA settings as
the master.
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1:0
SPR[1:0]
Serial clock frequency
These bits are set and cleared by software. Used with the SPR2 bit,
they select the baud rate of the SPI serial clock SCK output by the SPI
in master mode:
100: serial clock = fCPU/4
000: serial clock = fCPU/8
001: serial clock = fCPU/16
110: serial clock = fCPU/32
010: serial clock = fCPU/64
011: serial clock = fCPU/128
Note: These 2 bits have no effect in slave mode.
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114/201
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ST7232Axx-Auto
On-chip peripherals
Control/status register (SPICSR)
SPICSR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
SPIF
WCOL
OVR
MODF
-
SOD
SSM
SSI
R
R
R
R
R/W
R/W
R/W
R/W
Table 42.
SPICSR register description
Bit
7
Bit name
Function
SPIF
Serial peripheral data transfer flag
This bit is set by hardware when a transfer has been completed. An
interrupt is generated if SPIE = 1 in the SPICR register. It is cleared
by a software sequence (an access to the SPICSR register followed
by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared
1: Data transfer between the device and an external device has been
completed
Note: While the SPIF bit is set, all writes to the SPIDR register are
inhibited until the SPICSR register is read.
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6
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4
MODF
3
-
2
SOD
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-
SPI overrun error
This bit is set by hardware when the byte currently being received in
the shift register is ready to be transferred into the SPIDR register
while SPIF = 1 (see Overrun condition (OVR) on page 110). An
interrupt is generated if SPIE = 1 in SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
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OVR
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Write collision status
This bit is set by hardware when a write to the SPIDR register is
done during a transmit sequence. It is cleared by a software
sequence (see Figure 51).
0: No write collision occurred
1: A write collision has been detected
WCOL
5
)
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Mode fault flag
This bit is set by hardware when the SS pin is pulled low in master
mode (see Master mode fault (MODF) on page 110). An SPI
interrupt can be generated if SPIE = 1 in the SPICSR register. This
bit is cleared by a software sequence (an access to the SPICR
register while MODF = 1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Reserved, must be kept cleared.
SPI output disable
This bit is set and cleared by software. When set, it disables the
alternate function of the SPI output (MOSI in master mode/MISO in
slave mode).
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
115/201
On-chip peripherals
Table 42.
ST7232Axx-Auto
SPICSR register description (continued)
Bit
Bit name
1
Function
SSM
SS management
This bit is set and cleared by software. When set, it disables the
alternate function of the SPI SS pin and uses the SSI bit value
instead. See Slave select management on page 105.
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit.
External SS pin free for general-purpose I/O)
SSI
SS internal mode
This bit is set and cleared by software. It acts as a ‘chip select’ by
controlling the level of the SS slave select signal when the SSM bit is
set.
0 : Slave selected
1 : Slave deselected
0
Data I/O register (SPIDR)
SPIDR
)
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Reset value: undefined
7
6
5
4
3
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2
D[7:0]
R/W
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1
0
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The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register initiates transmission/reception of another byte.
Note:
o
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1
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
2
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
)
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Warning:
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A write to the SPIDR register places data directly into the
shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see Figure 46).
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116/201
ST7232Axx-Auto
On-chip peripherals
SPI register map and reset values
Table 43.
SPI register map and reset values
Addres (Hex.)
Register label
7
6
5
4
3
2
1
0
0021h
SPIDR
Reset value
MSB
x
x
x
x
x
x
x
LSB
x
0022h
SPICR
Reset value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
0023h
SPICSR
Reset value
SPIF WCOL
0
0
OVR
0
MODF
0
0
SOD
0
SSM
0
SSI
0
10.5
Serial communications interface (SCI)
10.5.1
Introduction
)
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The serial communications interface (SCI) offers a flexible means of full-duplex data
exchange with external equipment requiring an industry standard NRZ asynchronous serial
data format. The SCI offers a very wide range of baud rates using two baud rate generator
systems.
10.5.2
Main features
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●
Full duplex, asynchronous communications
●
NRZ standard format (mark/space)
●
Dual baud rate generator systems
●
Independently programmable transmit and receive baud rates up to 500K baud
●
Programmable data word length (8 or 9 bits)
●
Receive buffer full, transmit buffer empty and end of transmission flags
●
Two receiver wake up modes:
●
●
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●
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–
Address bit (MSB)
–
Idle line
o
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Muting function for multiprocessor configurations
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●
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Separate enable bits for transmitter and receiver
Four error detection flags:
–
Overrun error
–
Noise error
–
Frame error
–
Parity error
Five interrupt sources with flags:
–
Transmit data register empty
–
Transmission complete
–
Receive data register full
–
Idle line received
–
Overrun error detected
117/201
On-chip peripherals
●
Parity control:
●
10.5.3
ST7232Axx-Auto
–
Transmits parity bit
–
Checks parity of received data byte
Reduced power consumption mode
General description
The interface is externally connected to another device by two pins (see Figure 54):
●
TDO: Transmit data output. When the transmitter and the receiver are disabled, the
output pin returns to its I/O port configuration. When the transmitter and/or the receiver
are enabled and nothing is to be transmitted, the TDO pin is at high level.
●
RDI: Receive data input is the serial data input. Oversampling techniques are used for
data recovery by discriminating between valid incoming data and noise.
Through these pins, serial data is transmitted and received as frames comprising:
●
An idle line prior to transmission or reception
●
A start bit
●
A data word (8 or 9 bits) least significant bit first
●
A stop bit indicating that the frame is complete
This interface uses two types of baud rate generator:
●
A conventional type for commonly-used baud rates
●
An extended type with a prescaler offering a very wide range of baud rates even with
non-standard oscillator frequencies.
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ST7232Axx-Auto
On-chip peripherals
Figure 53. SCI block diagram
Write
Read
DR (data register)
Transmit data register (TDR)
Received data register (RDR)
Transmit shift register
Received shift register
TDO
RDI
CR1
R8
T8
SCID
M
Wake up
unit
WAKE PCE
Transmit control
TCIE RIE
ILIE
TE
RE
RWU SBK
SCI interrupt control
)
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Transmitter clock
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fCPU
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/16
PIE
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TDRE TC
)
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Receiver clock
Receiver control
CR2
TIE
PS
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RDRF IDLE
OR
SR
NF
FE
PE
o
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-
Transmitter rate control
/PR
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
Receiver rate control
Conventional baud rate generator
119/201
On-chip peripherals
10.5.4
ST7232Axx-Auto
Functional description
The block diagram of the serial control interface, is shown in Figure 53. It contains 6
dedicated registers:
●
Two control registers (SCICR1 and SCICR2)
●
A status register (SCISR)
●
A baud rate register (SCIBRR)
●
An extended prescaler receiver register (SCIERPR)
●
An extended prescaler transmitter register (SCIETPR)
Refer to the register descriptions in Section 10.5.7 for the definitions of each bit.
Serial data format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see Figure 53).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
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An idle character is interpreted as an entire frame of ‘1’s followed by the start bit of the next
frame which contains data.
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A break character is interpreted on receiving ‘0’s for some multiple of the frame period. At
the end of the last break frame the transmitter inserts an extra ‘1’ bit to acknowledge the
start bit.
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Transmission and reception are driven by their own baud rate generator.
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ST7232Axx-Auto
On-chip peripherals
Figure 54. Word length programming
9-bit word length (M bit is set)
Possible
parity bit
Data frame
Start
bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Next
start
bit
Stop
bit
Idle frame
Start
Bit
Break frame
Extra
’1’
Next data frame
Start
bit
8-bit word length (M bit is reset)
Possible
parity bit
Data frame
Start
bit
Bit1
Bit0
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Next data frame
Start
bit
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Idle frame
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Extra
’1’
Break frame
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Transmitter
Stop
bit
Next
start
bit
)
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Start
bit
o
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O
-
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.
)
s
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Character transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this
mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 53).
●
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●
●
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●
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Procedure
Select the M bit to define the word length
Select the desired baud rate using the SCIBRR and the SCIETPR registers
Set the TE bit to assign the TDO pin to the alternate function and to send an idle frame
as first transmission
Access the SCISR register and write the data to send in the SCIDR register (this
sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
1.
An access to the SCISR register
2.
A write to the SCIDR register
121/201
On-chip peripherals
ST7232Axx-Auto
The TDRE bit is set by hardware and it indicates:
●
The TDR register is empty
●
The data transfer is beginning
●
The next data can be written in the SCIDR register without overwriting the previous
data
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR
register.
When a transmission is taking place, a write instruction to the SCIDR register stores the
data in the TDR register and which is copied in the shift register at the end of the current
transmission.
When no transmission is taking place, a write instruction to the SCIDR register places the
data directly in the shift register, the data transmission starts, and the TDRE bit is
immediately set.
When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt
is generated if the TCIE is set and the I bit is cleared in the CCR register.
Clearing the TC bit is performed by the following software sequence:
Note:
1.
An access to the SCISR register
2.
A write to the SCIDR register
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The TDRE and TC bits are cleared by the same software sequence.
Break characters
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Setting the SBK bit loads the shift register with a break character. The break frame length
depends on the M bit (see Figure 54).
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As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this
bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the
recognition of the start bit of the next frame.
Idle characters
)
s
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Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the
current word.
Note:
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Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in
the SCIDR.
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122/201
ST7232Axx-Auto
On-chip peripherals
Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9
bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this
mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the
received shift register (see Figure 53).
Procedure
●
Select the M bit to define the word length
●
Select the desired baud rate using the SCIBRR and the SCIERPR registers
●
Set the RE bit, this enables the receiver which begins searching for a start bit
When a character is received:
●
The RDRF bit is set. It indicates that the content of the shift register is transferred to the
RDR.
●
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register
●
The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
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Clearing the RDRF bit is performed by the following software sequence done by:
1.
An access to the SCISR register
2.
A read to the SCIDR register
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The RDRF bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
Break character
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When a break character is received, the SCI handles it as a framing error.
Idle character
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When an idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.
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Overrun error
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An overrun error occurs when a character is received when RDRF has not been reset. Data
can not be transferred from the shift register to the RDR register as long as the RDRF bit is
not cleared.
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When an overrun error occurs:
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●
The OR bit is set
●
The RDR content is not lost
●
The shift register is overwritten
●
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read
operation.
123/201
On-chip peripherals
ST7232Axx-Auto
Noise error
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise. Normal data bits are considered valid if three consecutive samples
(8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit
detection, the NF flag is set on the basis of an algorithm combining both valid edge
detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set
during start bit reception, there should be a valid edge detection as well as three valid
samples.
When noise is detected in a frame:
●
The NF flag is set at the rising edge of the RDRF bit
●
Data is transferred from the shift register to the SCIDR register
●
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The NF flag is reset by a SCISR register read operation followed by a SCIDR register read
operation.
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During reception, if a false start bit is detected (example, 8th, 9th, 10th samples are
011,101,110), the frame is discarded and the receiving sequence is not started for this
frame. There is no RDRF bit set for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid
frame is received.
Note:
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See also Noise error causes on page 129.
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If the application start bit is not long enough to match the above requirements, then the NF
flag may get set due to the short start bit. In this case, the NF flag may be ignored by the
application software when the first valid byte is received.
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ST7232Axx-Auto
On-chip peripherals
Figure 55. SCI baud rate and extended prescaler block diagram
Transmitter clock
Extended prescaler transmitter rate control
SCIETPR
Extended transmitter prescaler register
SCIERPR
Extended receiver prescaler register
Receiver clock
Extended prescaler receiver rate control
Extended prescaler
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fCPU
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Transmitter rate control
/16
/PR
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SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
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Receiver rate control
Conventional baud rate generator
125/201
On-chip peripherals
ST7232Axx-Auto
Framing error
A framing error is detected when:
●
The stop bit is not recognized on reception at the expected time, following either a desynchronization or excessive noise.
●
A break is received
When the framing error is detected:
●
the FE bit is set by hardware
●
Data is transferred from the Shift register to the SCIDR register
●
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read
operation.
Conventional baud rate generation
)
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The baud rate for the receiver and transmitter (Rx and Tx) are set independently and
calculated as follows:
Tx =
fCPU
(16*PR)*TR
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fCPU
Rx =
(16*PR)*RR
where:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
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TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits)
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RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits).
All these bits are in the SCIBRR register (see Baud rate register (SCIBRR) on page 136).
Example: If fCPU is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and
receive baud rates are 38400 baud.
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Note:
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
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Extended baud rate generation
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The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value
prescaler, whereas the conventional baud rate generator retains industry standard software
compatibility.
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Note:
126/201
The extended baud rate generator block diagram is described in Figure 55.
The output clock rate sent to the transmitter or to the receiver is the output from the 16
divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR
register.
The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value
other than zero.
ST7232Axx-Auto
On-chip peripherals
The baud rates are calculated as follows:
fCPU
fCPU
Rx =
Tx =
16*ERPR*(PR*RR)
16*ETPR*(PR*TR)
where:
ETPR = 1,..,255 (see Extended transmit prescaler division register (SCIETPR) on
page 137)
ERPR = 1,.. 255 (see Extended receive prescaler division register (SCIERPR) on page 137)
Receiver muting and wake up feature
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant SCI
service overhead for all non addressed receivers.
The non addressed devices may be placed in sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in sleep mode:
None of the reception status bits can be set.
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All the receive interrupts are inhibited.
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A muted receiver may be awakened by one of the following two ways:
●
by idle line detection if the WAKE bit is reset
●
by address mark detection if the WAKE bit is set
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Receiver wakes-up by idle line detection when the receive line has recognised an idle frame.
Then the RWU bit is reset by hardware but the IDLE bit is not set.
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Receiver wakes-up by address mark detection when it received a ‘1’ as the most significant
bit of a word, thus indicating that the message is an address. The reception of this particular
word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the
receiver to receive this word normally and to use it as an address word.
Caution:
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In mute mode, do not write to the SCICR2 register. If the SCI is in mute mode during the
read operation (RWU = 1) and an address mark wake up event occurs (RWU is reset)
before the write operation, the RWU bit is set again by this write operation. Consequently
the address byte is lost and the SCI is not woken up from mute mode.
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Parity control
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Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in Table 44.
127/201
On-chip peripherals
ST7232Axx-Auto
Table 44.
Frame formats(1)
M bit
PCE bit
SCI frame
0
0
| SB | 8 bit data | STB |
0
1
| SB | 7-bit data | PB | STB |
1
0
| SB | 9-bit data | STB |
1
1
| SB | 8-bit data PB | STB |
1. Legend: SB = start bit, STB = stop bit, PB = parity bit.
Note:
In case of wake up by an address mark, the MSB bit of the data is taken into account and
not the parity bit
Even parity
The parity bit is calculated to obtain an even number of ‘1s’ inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example, data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0).
Odd parity
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The parity bit is calculated to obtain an odd number of ‘1s’ inside the frame made of the 7 or
8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
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Example, data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1).
Transmission mode
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If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted
but is changed by the parity bit.
Reception mode
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If the PCE bit is set then the interface checks if the received data byte has an even number
of ‘1s’ if even parity is selected (PS = 0) or an odd number of ‘1s’ if odd parity is selected
(PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is
generated if PIE is set in the SCICR1 register.
SCI clock tolerance
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During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th
samples is considered as the bit value. For a valid bit detection, all the three samples should
have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and
10th samples are 0, 1 and 1 respectively, then the bit value is ‘1’, but the noise flag bit is set
because the three samples values are not the same.
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128/201
Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples
have the desired bit value. This means the clock frequency should not vary more than 6/16
(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when
receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed
3.75%.
ST7232Axx-Auto
Note:
On-chip peripherals
The internal sampling clock of the microcontroller samples the pin value on every falling
edge. Therefore, the internal sampling clock and the time the application expects the
sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit
length is 64µs), then the 8th, 9th and 10th samples are at 28µs, 32µs and 36µs respectively
(the first sample starting ideally at 0µs). But if the falling edge of the internal clock occurs
just before the pin value changes, the samples would then be out of sync by ~4µs. This
means the entire bit length must be at least 40µs (36µs for the 10th sample + 4µs for
synchronization with the internal sampling clock).
Clock deviation causes
The causes which contribute to the total deviation are:
●
DTRA: Deviation due to transmitter error (local oscillator error of the transmitter or the
transmitter is transmitting at a different baud rate).
●
DQUANT: Error due to the baud rate quantisation of the receiver
●
DREC: Deviation of the local oscillator of the receiver. This deviation can occur during
the reception of one complete SCI message assuming that the deviation has been
compensated at the beginning of the message.
●
DTCL: Deviation due to the transmission line (generally due to the transceivers)
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All the deviations of the system should be added and compared to the SCI clock tolerance:
DTRA + DQUANT + DREC + DTCL < 3.75%
Noise error causes
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See also description of noise error in Receiver on page 123.
Start bit
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The noise flag (NF) is set during start bit reception if one of the following conditions occurs:
1.
A valid falling edge is not detected. A falling edge is considered to be valid if the 3
consecutive samples before the falling edge occurs are detected as '1' and, after the
falling edge occurs, during the sampling of the 16 samples, if one of the samples
numbered 3, 5 or 7 is detected as a ‘1’.
2.
During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is
detected as a ‘1’.
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Therefore, a valid start bit must satisfy both the above conditions to prevent the noise flag
getting set.
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Data bits
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The noise flag (NF) is set during normal data bit reception if the following condition occurs:
During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the
same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
Therefore, a valid data bit must have samples 8, 9 and 10 at the same value to prevent the
noise flag being set.
129/201
On-chip peripherals
ST7232Axx-Auto
Figure 56. Bit sampling in reception mode
RDI line
Sampled values
Sample clock
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6/16
7/16
7/16
One bit time
10.5.5
Low power modes
Table 45.
Effect of low power modes on SCI
Mode
Description
Wait
No effect on SCI.
SCI interrupts cause the device to exit from wait mode.
SCI registers are frozen.
Halt
10.5.6
Table 46.
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(s)
Event flag Enable control bit
ct
Transmit data register empty
du
Transmission complete
Received data ready to be read
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Overrun error detected
Idle line detected
Parity error
O
130/201
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SCI interrupt control/wake-up capability
Interrupt event
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In halt mode, the SCI stops transmitting/receiving until halt mode is
exited.
Interrupts
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TDRE
TIE
TC
TCIE
Exit from wait
Exit from halt
Yes
No
RDRF
RIE
OR
IDLE
ILIE
PE
PIE
The SCI interrupt events are connected to the same interrupt vector.
These events generate an interrupt if the corresponding enable control bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
ST7232Axx-Auto
10.5.7
On-chip peripherals
SCI registers
Status register (SCISR)
SCISR
Reset value: 1100 0000 (C0h)
7
6
5
4
3
2
1
0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PE
R
R
R
R
R
R
R
R
Table 47.
SCISR register description
Bit
7
Bit name
Function
TDRE
Transmit data register empty
This bit is set by hardware when the content of the TDR register has
been transferred into the shift register. An interrupt is generated if the
TIE bit = 1 in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register followed by a write to the
SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data are not transferred to the shift register unless the TDRE
bit is cleared.
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RDRF
IDLE
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Transmission complete
This bit is set by hardware when transmission of a frame containing
data is complete. An interrupt is generated if TCIE = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the
SCISR register followed by a write to the SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note: TC is not set after the transmission of a preamble or a break.
TC
5
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Received data ready flag
This bit is set by hardware when the content of the RDR register has
been transferred to the SCIDR register. An interrupt is generated if
RIE = 1 in the SCICR2 register. It is cleared by a software sequence
(an access to the SCISR register followed by a read to the SCIDR
register).
0: Data are not received
1: Received data are ready to be read
Idle line detect
This bit is set by hardware when an idle line is detected. An interrupt
is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a
software sequence (an access to the SCISR register followed by a
read to the SCIDR register).
0: No idle line is detected
1: Idle line is detected
Note: The IDLE bit is not set again until the RDRF bit is set (i.e. a
new idle line occurs).
131/201
On-chip peripherals
Table 47.
ST7232Axx-Auto
SCISR register description (continued)
Bit
3
2
Bit name
Function
OR
Overrun error
This bit is set by hardware when the word currently being received in
the shift register is ready to be transferred into the RDR register
while RDRF = 1. An interrupt is generated if RIE = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the
SCISR register followed by a read to the SCIDR register).
0: No overrun error
1: Overrun error is detected
Note: When the IDLE bit is set the RDR register content is not lost
but the shift register is overwritten.
NF
Noise flag
This bit is set by hardware when noise is detected on a received
frame. It is cleared by a software sequence (an access to the SCISR
register followed by a read to the SCIDR register).
0: No noise is detected
1: Noise is detected
Note: The NF bit does not generate an interrupt as it appears at the
same time as the RDRF bit which itself generates an interrupt.
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Framing error
This bit is set by hardware when a de-synchronization, excessive
noise or a break character is detected. It is cleared by a software
sequence (an access to the SCISR register followed by a read to the
SCIDR register).
0: No framing error is detected
1: Framing error or break character is detected
Note: The FE bit does not generate an interrupt as it appears at the
same time as the RDRF bit which itself generates an interrupt. If the
word currently being transferred causes both frame error and
overrun error, it is transferred and only the OR bit is set.
FE
0
PE
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Parity error
This bit is set by hardware when a parity error occurs in receiver
mode. It is cleared by a software sequence (a read to the status
register followed by an access to the SCIDR data register). An
interrupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
1: Parity error
ST7232Axx-Auto
On-chip peripherals
Control register 1 (SCICR1)
SCICR1
Reset value: x000 0000 (x0b)
7
6
5
4
3
2
1
0
R8
T8
SCID
M
WAKE
PCE
PS
PIE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 48.
SCICR1 register description
Bit
Bit name
Function
7
R8
Receive data bit 8
This bit is used to store the 9th bit of the received word when M = 1.
6
T8
Transmit data bit 8
This bit is used to store the 9th bit of the transmitted word when
M = 1.
5
4
3
SCID
M
Word length
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: The M bit must not be modified during a data transfer (both
transmission and reception).
WAKE
Wake up method
This bit determines the SCI wake up method, it is set or cleared by
software.
0: Idle line
1: Address mark
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Disabled for low power consumption
When this bit is set the SCI prescalers and outputs are stopped at
the end of the current byte transfer in order to reduce power
consumption.This bit is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
PCE
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Parity control enable
This bit selects the hardware parity control (generation and
detection). When the parity control is enabled, the computed parity is
inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and
parity is checked on the received data. This bit is set and cleared by
software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
0: Parity control disabled
1: Parity control enabled
133/201
On-chip peripherals
Table 48.
ST7232Axx-Auto
SCICR1 register description (continued)
Bit
Bit name
Function
PS
Parity selection
This bit selects the odd or even parity when the parity
generation/detection is enabled (PCE bit set). It is set and cleared by
software. The parity is selected after the current byte.
0: Even parity
1: Odd parity
PIE
Parity interrupt enable
This bit enables the interrupt capability of the hardware parity control
when a parity error is detected (PE bit set). It is set and cleared by
software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
1
0
Control register 2 (SCICR2)
SCICR2
7
6
5
4
3
2
TIE
TCIE
RIE
ILIE
TE
RE
R/W
R/W
R/W
R/W
R/W
R/W
Table 49.
Bit name
7
TIE
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134/201
4
TCIE
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Pr
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1
od
0
RWU
SBK
R/W
R/W
Function
Transmitter interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR
register
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SCICR2 register description
Bit
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Reset value: 0000 0000 (00h)
Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR
register
RIE
Receiver interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in
the SCISR register
ILIE
Idle line interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR
register
ST7232Axx-Auto
On-chip peripherals
Table 49.
SCICR2 register description (continued)
Bit
Bit name
Function
TE
Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note 1: During transmission, an ‘0’ pulse on the TE bit (‘0’ followed
by ‘1’) sends a preamble (idle line) after the current word.
Note 2: When TE is set there is a 1 bit-time delay before the
transmission starts.
Caution The TDO pin is free for general purpose I/O only when the
TE and RE bits are both cleared (or if TE is never set).
RE
Receiver enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
3
2
1
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Receiver wake up
This bit determines if the SCI is in mute mode or not. It is set and
cleared by software and can be cleared by hardware when a wake
up sequence is recognized.
0: Receiver in active mode
1: Receiver in mute mode
Note: Before selecting mute mode (setting the RWU bit), the SCI
must receive some data first, otherwise it cannot function in mute
mode with wakeup by idle line detection.
SBK
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Send break
This bit set is used to send break characters. It is set and cleared by
software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter sends
a BREAK word at the end of the current word.
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Data register (SCIDR)
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Contains the received or transmitted data character, depending on whether it is read from or
written to.
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SCIDR
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7
Reset value: undefined
6
5
4
3
2
1
0
DR[7:0]
R/W
The data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 53).
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 53).
135/201
On-chip peripherals
ST7232Axx-Auto
Baud rate register (SCIBRR)
SCIBRR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
SCP[1:0]
SCT[2:0]
SCR[2:0]
R/W
R/W
R/W
Table 50.
SCIBRR register description
Bit
7:6
Bit name
Function
SCP[1:0]
First SCI prescaler
These 2 prescaling bits allow several standard clock division ranges:
00: PR prescaling factor = 1
01: PR prescaling factor = 3
10: PR prescaling factor = 4
11: PR prescaling factor = 13
SCT[2:0]
SCI transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and SCP0 bits define the
total division applied to the bus clock to yield the transmit rate clock
in conventional baud rate generator mode:
000: TR dividing factor = 1
001: TR dividing factor = 2
010: TR dividing factor = 4
011: TR dividing factor = 8
100: TR dividing factor = 16
101: TR dividing factor = 32
110: TR dividing factor = 64
111: TR dividing factor = 128
c
u
d
5:3
e
t
le
r
P
e
s
b
O
136/201
SCR[2:0]
o
s
b
O
-
)
s
t(
o
r
P
SCI receiver rate divisor
These 3 bits, in conjunction with the SCP[1:0] bits define the total
division applied to the bus clock to yield the receive rate clock in
conventional baud rate generator mode:
000: RR dividing factor = 1
001: RR dividing factor = 2
010: RR dividing factor = 4
011: RR dividing factor = 8
100: RR dividing factor = 16
101: RR dividing factor = 32
110: RR dividing factor = 64
111: RR dividing factor = 128
)
s
(
ct
u
d
o
2:0
t
e
l
o
0
ST7232Axx-Auto
On-chip peripherals
Extended receive prescaler division register (SCIERPR)
Allows setting of the extended prescaler rate division factor for the receive circuit.
SCIERPR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
ERPR[7:0]
R/W
Table 51.
Bit
7:0
SCIERPR register description
Bit name
Function
ERPR[7:0]
8-bit extended receive prescaler register
The extended baud rate generator is activated when a value different
from 00h is stored in this register. Therefore the clock frequency
issued from the 16 divider (see Figure 55) is divided by the binary
factor set in the SCIERPR register (in the range 1 to 255).
The extended baud rate generator is not used after a reset.
c
u
d
Extended transmit prescaler division register (SCIETPR)
)
s
t(
Allows setting of the external prescaler rate division factor for the transmit circuit.
SCIETPR
7
6
5
4
e
t
le
3
o
s
b
O
ETPR[7:0]
o
r
P
Reset value: 0000 0000 (00h)
2
1
0
R/W
Table 52.
Bit
SCIETPR register description
Bit name
d
o
r
P
e
uc
7:0
t
e
l
o
ETPR[7:0]
(t s)
Function
8-bit extended transmit prescaler register
The extended baud rate generator is activated when a value different
from 00h is stored in this register. Therefore the clock frequency
issued from the 16 divider (see Figure 55) is divided by the binary
factor set in the SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not used after a reset.
s
b
O
137/201
On-chip peripherals
ST7232Axx-Auto
Baud rate selection
Table 53.
Baud rate selection
Conditions
Symbol
Parameter
fCPU
Accuracy
vs.
standard
Conventional mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 13
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
~0.16%
fTx
fRx
Standard Baud rate Unit
Prescaler
Communication
8MHz
frequency
300
~300.48
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
38400 ~38461.54
Extended mode
ETPR (or ERPR) = 35,
TR (or RR) = 1, PR = 1
~0.79%
SCI register map and reset values
Address (Hex.) Register label
c
u
d
5
e
t
le
4
3
2
1
0
SCISR
Reset value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
0051h
SCIDR
Reset value
MSB
x
x
x
x
x
x
x
LSB
x
0052h
SCIBRR
Reset value
SCP1 SCP0
0
0
SCT2
0
SCT1
0
SCT0
0
0053h
SCICR1
Reset value
R8
x
T8
0
SCID
0
M
0
WAKE
0
PCE
0
PS
0
PIE
0
SCICR2
Reset value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
SCIERPR
Reset value
MSB
0
0
0
0
0
0
0
LSB
0
SCIPETPR
Reset value
MSB
0
0
0
0
0
0
0
LSB
0
t
e
l
o
0057h
)
s
(
ct
u
d
o
r
P
e
0055h
138/201
6
o
r
P
0050h
0054h
s
b
O
7
)
s
t(
14400 ~14285.71
SCI register map and reset values
Table 54.
Hz
o
s
b
O
-
SCR2 SCR1 SCR0
0
0
0
ST7232Axx-Auto
On-chip peripherals
10.6
10-bit A/D converter (ADC)
10.6.1
Introduction
The on-chip analog to digital converter (ADC) peripheral is a 10-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 16
multiplexed analog input channels (refer to device pin out description) that allow the
peripheral to convert the analog voltage levels from up to 16 different sources.
The result of the conversion is stored in a 10-bit data register. The A/D converter is
controlled through a control/status register.
10.6.2
Main features
●
10-bit conversion
●
Up to 16 channels with multiplexed input
●
Linear successive approximation
●
Data register (DR) which contains the results
●
Conversion complete status flag
●
On/off bit (to reduce consumption)
c
u
d
The block diagram is shown in Figure 57.
Figure 57. ADC block diagram
fCPU
DIV 4
0
DIV 2
fADC
1
EOC
SPE
ED
AD
ON
)
s
(
ct
u
d
o
r
P
e
AIN0
AIN1
s
b
O
t
e
l
o
e
t
le
o
s
b
O
0
CH3
CH2
CH1 CH0
)
s
t(
o
r
P
ADCCSR
4
Analog
MUX
Analog to digital converter
AINx
ADCDRH
D9
D8
ADCDRL
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
139/201
On-chip peripherals
10.6.3
ST7232Axx-Auto
Functional description
The conversion is monotonic, meaning that the result never decreases if the analog input
does not decrease and never increases if the analog input does not increase.
If the input voltage (VAIN) is greater than VAREF (high-level voltage reference) then the
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in Section 12:
Electrical characteristics.
RAIN is the maximum recommended impedance for an analog input signal. If the impedance
is too high, this results in a loss of accuracy due to leakage and sampling not being
completed in the alloted time.
A/D converter configuration
)
s
t(
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to
Section 9: I/O ports. Using these pins as analog inputs does not affect the ability of the port
to be read as a logic input.
c
u
d
o
r
P
In the ADCCSR register select the CS[3:0] bits to assign the analog channel to convert.
e
t
le
Starting the conversion
In the ADCCSR register set the ADON bit to enable the A/D converter and to start the
conversion. From this time on, the ADC performs a continuous conversion of the selected
channel.
When a conversion is complete:
o
s
b
O
-
●
The EOC bit is set by hardware
●
The result is in the ADCDR register
)
s
(
ct
A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit.
u
d
o
To read the 10 bits, perform the following steps:
r
P
e
1.
2.
3.
t
e
l
o
Note:
s
b
O
140/201
Poll the EOC bit
Read the ADCDRL register
Read the ADCDRH register. This clears EOC automatically
The data is not latched, so both the low and the high data register must be read before the
next conversion is complete, so it is recommended to disable interrupts while reading the
conversion result.
To read only 8 bits, perform the following steps:
1.
Poll the EOC bit
2.
Read the ADCDRH register. This clears EOC automatically
ST7232Axx-Auto
On-chip peripherals
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
10.6.4
Low power modes
Note:
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed.
Table 55.
10.6.5
Effect of low power modes on 10-bit ADC
Mode
Description
Wait
No effect on A/D converter
Halt
A/D converter disabled.
After wakeup from halt mode, the A/D converter requires a stabilization time
tSTAB (see Section 12: Electrical characteristics) before accurate conversions
can be performed.
c
u
d
Interrupts
None.
10.6.6
10-bit ADC registers
e
t
le
Control/status register (ADCCSR)
ADCCSR
7
6
5
EOC
SPEED
ADON
R
R/W
Table 56.
u
d
o
s
b
O
t
e
l
o
7
6
5
ct
R/W
4
3
o
r
P
Reset value: 0000 0000 (00h)
2
1
0
CH[3:0]
-
R/W
0
ADCCSR register description
r
P
e
Bit
(s)
o
s
b
O
-
)
s
t(
Bit name
Function
EOC
End of conversion
This bit is set by hardware. It is cleared by hardware when software
reads the ADCDRH register or writes to any bit of the ADCCSR
register.
0: Conversion is not complete
1: Conversion complete
SPEED
ADC clock selection
This bit is set and cleared by software.
0: fADC = fCPU/4
1: fADC = fCPU/2
ADON
A/D converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
141/201
On-chip peripherals
Table 56.
ST7232Axx-Auto
ADCCSR register description (continued)
Bit
Bit name
4
0
3:0
Function
Reserved, must be kept cleared.
Channel selection
These bits are set and cleared by software. They select the analog
input to convert:
0000: channel pin = AIN0
0001: channel pin = AIN1
0010: channel pin = AIN2
0011: channel pin = AIN3
0100: channel pin = AIN4
0101: channel pin = AIN5
0110: channel pin = AIN6
0111: channel pin = AIN7
1000: channel pin = AIN8
1001: channel pin = AIN9
1010: channel pin = AIN10
1011: channel pin = AIN11
1100: channel pin = AIN12
1101: channel pin = AIN13
1110: channel pin = AIN14
1111: channel pin = AIN15
Note: The number of channels is device dependent. Refer to the
Section 2: Pin description.
CH[3:0]
c
u
d
Data register (ADCDRH)
ADCDRH
7
6
5
4
e
t
le
so
b
O
-
3
)
s
t(
o
r
P
Reset value: 0000 0000 (00h)
2
1
0
D[9:2]
Table 57.
Bit
)
s
(
ct
ADCDRH register description
du
Bit name
o
r
P
e
7:0
R
D[9:2]
Function
MSB of converted analog value
Data register (ADCDRL)
t
e
l
o
ADCDRL
bs
O
142/201
7
6
Reset value: 0000 0000 (00h)
5
4
3
2
1
0
0
D[1:0]
-
R
ST7232Axx-Auto
On-chip peripherals
Table 58.
ADCDRL register description
Bit
Bit name
Function
7:2
0
Reserved, must be kept cleared
1:0
D[1:0]
LSB of converted analog value
ADC register map and reset value
Table 59.
ADC register map and reset values
Address (Hex.)
Register label
7
6
5
4
3
2
1
0
0
CH3
0
CH2
0
CH1
0
CH0
0
0070h
ADCCSR
Reset value
EOC
0
0071h
ADCDRH
Reset value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
0072h
ADCDRL
Reset value
0
0
0
0
0
0
D1
0
D0
0
SPEED ADON
0
0
c
u
d
e
t
le
)
s
(
ct
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
143/201
Instruction set
ST7232Axx-Auto
11
Instruction set
11.1
CPU addressing modes
The CPU features 17 different addressing modes which can be classified in 7 main groups
(see Table 60).
Table 60.
CPU addressing mode groups
Addressing mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset byte,#5
c
u
d
)
s
t(
The CPU instruction set is designed to minimize the number of bytes required per
instruction. To do so, most of the addressing modes may be subdivided in two sub-modes
called long and short:
e
t
le
o
r
P
●
Long addressing mode is more powerful because it can use the full 64 Kbyte address
space, however it uses more bytes and more CPU cycles.
●
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
)
s
(
ct
o
s
b
O
-
The ST7 assembler optimizes the use of long and short addressing modes.
u
d
o
r
P
e
t
e
l
o
s
b
O
144/201
ST7232Axx-Auto
Table 61.
Instruction set
CPU addressing mode overview
Mode
Syntax
Destination
Pointer
address
Pointer
size
Length
(bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No offset
Direct
Indexed ld A,(X)
00..FF
+0
Short
Direct
Indexed ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed ld A,($1000,X) 0000..FFFF
Short
Indirect
ld A,[$10]
00..FF
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect Indexed ld A,([$10],X)
00..1FE
00..FF
byte
+2
Long
Indirect Indexed
ld
A,([$10.w],X)
0000..FFFF
00..FF
word
Relative
Direct
jrne loop
PC+/-127
Relative
Indirect
jrne [$10]
PC+/-127
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
btjt
$10,#7,skip
00..FF
Bit
Indirect Relative
btjt
[$10],#7,skip
00..FF
Relative
)
s
(
ct
+2
00..FF
o
s
b
O
-
e
t
le
Pr
00..FF
00..FF
uc
od
byte
byte
)
s
t(
+2
+1
+2
+1
+2
+2
byte
+3
u
d
o
r
P
e
t
e
l
o
s
b
O
145/201
Instruction set
11.1.1
ST7232Axx-Auto
Inherent instructions
All inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Table 62.
Inherent instructions
Inherent instruction
NOP
No operation
TRAP
S/W interrupt
WFI
Wait for interrupt (low power mode)
HALT
Halt oscillator (lowest power mode)
RET
Sub-routine return
IRET
Interrupt sub-routine return
SIM
Set interrupt mask (level 3)
RIM
Reset interrupt mask (level 0)
SCF
Set carry flag
RCF
Reset carry flag
RSP
Reset stack pointer
LD
Load
CLR
Clear
PUSH/POP
Push/pop to/from the stack
INC/DEC
e
t
le
c
u
d
)
s
t(
o
r
P
o
s
b
O
-
Increment/decrement
TNZ
Test negative or zero
CPL, NEG
1 or 2 complement
(s)
MUL
ct
SLL, SRL, SRA, RLC, RRC
SWAP
11.1.2
Function
o
r
P
e
du
Byte multiplication
Shift and rotate operations
Swap nibbles
Immediate instructions
Immediate instructions have two bytes, the first byte contains the opcode, the second byte
contains the operand value.
t
e
l
o
bs
O
146/201
Table 63.
Immediate instructions
Immediate Instruction
Function
LD
Load
CP
Compare
BCP
Bit compare
AND, OR, XOR
Logical operations
ADC, ADD, SUB, SBC
Arithmetic operations
ST7232Axx-Auto
11.1.3
Instruction set
Direct instructions
In direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two sub-modes:
●
Direct instructions (short)
The address is a byte, thus requires only one byte after the opcode, but only allows
00 - FF addressing space.
●
Direct instructions (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes
after the opcode.
11.1.4
Indexed instructions (no offset, short, long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three sub-modes:
●
Indexed (no offset)
)
s
t(
There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing
space.
●
c
u
d
Indexed (short)
o
r
P
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE
addressing space.
●
e
t
le
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes
after the opcode.
11.1.5
o
s
b
O
-
Indirect instructions (short, long)
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
)
s
(
ct
The pointer address follows the opcode. The indirect addressing mode consists of two submodes:
●
u
d
o
Indirect (short)
r
P
e
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF
addressing space, and requires 1 byte after the opcode.
t
e
l
o
●
s
b
O
Indirect (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte
addressing space, and requires 1 byte after the opcode.
147/201
Instruction set
11.1.6
ST7232Axx-Auto
Indirect indexed instructions (short, long)
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
The indirect indexed addressing mode consists of two sub-modes:
●
Indirect indexed (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE
addressing space, and requires 1 byte after the opcode.
●
Indirect indexed (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte
addressing space, and requires 1 byte after the opcode.
Table 64.
Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes
Long and short instructions
Load
CP
Compare
AND, OR, XOR
Logical operations
ADC, ADD, SUB, SBC
Arithmetic addition/substraction operations
BCP
Bit compare
Short instructions and functions
Short instructions only
CLR
)
s
(
ct
TNZ
CPL, NEG
u
d
o
BSET, BRES
r
P
e
BTJT, BTJF
e
t
le
c
u
d
o
r
P
o
s
b
O
-
Function
Clear
INC, DEC
Increment/decrement
Test negative or zero
1 or 2 complement
Bit operations
Bit test and jump operations
SLL, SRL, SRA, RLC, RRC
Shift and rotate operations
SWAP
Swap nibbles
CALL, JP
Call or jump subroutine
t
e
l
o
148/201
)
s
t(
LD
Table 65.
s
b
O
Function
ST7232Axx-Auto
11.1.7
Instruction set
Relative mode instructions (direct, indirect)
This addressing mode is used to modify the PC register value, by adding an 8-bit signed
offset to it.
Table 66.
Relative mode instructions (direct and indirect)
Available relative direct/indirect instructions
Function
JRxx
Conditional jump
CALLR
Call relative
The relative addressing mode consists of two sub-modes:
●
Relative (direct)
The offset is following the opcode.
●
Relative (indirect)
The offset is defined in memory, which address follows the opcode.
11.2
Instruction groups
c
u
d
)
s
t(
The ST7 family devices use an instruction set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Table 67.
Instruction groups
Load and transfer
LD
CLR
Stack operation
PUSH
POP
Increment/decrement
INC
DEC
Compare and tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
BSET
BRES
Conditional bit test and branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Bit operation
o
r
P
e
Shift and rotates
c
u
d
(t s)
Unconditional jump or call
t
e
l
o
bs
e
t
le
o
r
P
RSP
o
s
b
O
-
Conditional branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Condition code flag modification
SIM
RIM
SCF
RCF
RET
O
149/201
Instruction set
11.3
ST7232Axx-Auto
Using a pre-byte
The instructions are described with one to four opcodes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:
PC-2
End of previous instruction
PC-1
Prebyte
PC
Opcode
PC+1
Additional word (0 to 2) according to the number of bytes required to compute
the effective address
These prebytes enable instructions in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instructions in X or the instructions using
direct addressing mode. The prebytes are:
c
u
d
)
s
t(
PDY 90
Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one
PIX 92
Replace an instruction using direct, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode
e
t
le
o
r
P
It also changes an instruction using X indexed addressing mode to an instruction
using indirect X indexed addressing mode
PIY 91
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
s
b
O
150/201
o
s
b
O
-
Replace an instruction using X indirect indexed addressing mode by a Y one
ST7232Axx-Auto
Table 68.
Instruction set
Instruction set overview
Mnemo
Description
Function/example
Dst
Src
I1
H
I0
N
Z
C
ADC
Add with carry
A=A+M+C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A, memory
tst (A . M)
A
M
N
Z
BRES
Bit reset
bres Byte, #3
M
BSET
Bit set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1 M
C
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1 M
C
CALL
Call subroutine
CALLR
Call subroutine relative
CLR
Clear
CP
Arithmetic compare
tst(Reg - M)
reg
CPL
One complement
A = FFH-A
reg, M
DEC
Decrement
dec Y
reg, M
HALT
Halt
IRET
Interrupt routine return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute jump
jp [TBL.w]
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
JRIH
Jump if ext. INT pin = 1
JRIL
Jump if ext. INT pin = 0
JRH
Jump if H = 1
JRNH
Jump if H = 0
JRM
Jump if I1:0 = 11
I1:0 = 11 ?
Jump if I1:0 <> 11
I1:0 <> 11 ?
Jump if N = 1 (minus)
N=1?
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned >=
s
b
O
JRPL
M
Pr
1
)
s
(
ct
jrf *
u
d
o
r
P
e
t
e
l
o
JRNM
JRMI
reg, M
reg, M
e
t
le
I1
1
N
Z
C
N
Z
1
N
Z
N
Z
N
Z
uc
od
)
s
t(
0
0
H
I0
C
o
s
b
O
-
(ext. INT pin high)
(ext. INT pin low)
H=1?
H=0?
151/201
Instruction set
Table 68.
ST7232Axx-Auto
Instruction set overview (continued)
Mnemo
Description
Function/example
Dst
Src
JRUGT
Jump if (C + Z = 0)
Unsigned >
JRULE
Jump if (C + Z = 1)
Unsigned <=
LD
Load
dst <= src
reg, M
M, reg
MUL
Multiply
X, A = X * A
A, X, Y
X, Y, A
NEG
Negate (2's compl)
neg $10
reg, M
NOP
No operation
OR
OR operation
A=A+M
A
M
pop reg
reg
M
POP
Pop from the stack
pop CC
CC
M
M
PUSH
Push onto the stack
push Y
RCF
Reset carry flag
C=0
RET
Subroutine return
RIM
Enable interrupts
I1:0 = 10 (level 0)
RLC
Rotate left true C
C <= A <= C
reg, M
RRC
Rotate right true C
C => A => C
reg, M
RSP
Reset stack pointer
S = Max allowed
SBC
Substract with carry
A=A-M-C
SCF
Set carry flag
C=1
SIM
Disable interrupts
I1:0 = 11 (level 3)
SLA
Shift left arithmetic
C <= A <= 0
SLL
Shift left logic
SRL
Shift right logic
SRA
Shift right arithmetic
SUB
Substraction
SWAP
SWAP nibbles
TNZ
Test for neg and zero
tnz lbl1
S/W trap
S/W interrupt
t
e
l
o
TRAP
WFI
s
b
O
XOR
152/201
r
P
e
I0
N
Z
N
Z
0
I1
C
H
0
I0
N
Z
C
N
Z
N
Z
C
)
s
t(
0
reg, CC
c
u
d
1
e
t
le
A
0
o
r
P
M
so
b
O
-
N
Z
C
N
Z
C
N
Z
C
1
1
1
N
Z
C
reg, M
N
Z
C
0 => A => C
reg, M
0
Z
C
A7 => A => C
reg, M
N
Z
C
A=A-M
A
N
Z
C
A7-A4 <=> A3-A0
reg, M
N
Z
N
Z
N
Z
)
s
(
ct
M
Wait for interrupt
Exclusive OR
H
reg, M
C <= A <= 0
u
d
o
I1
A = A XOR M
A
M
1
1
1
0
ST7232Axx-Auto
Electrical characteristics
12
Electrical characteristics
12.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
12.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25°C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3σ).
12.1.2
Typical values
c
u
d
)
s
t(
Unless otherwise specified, typical data are based on TA = 25°C, VDD = 5V. They are given
only as design guidelines and are not tested.
12.1.3
Typical curves
e
t
le
o
r
P
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
12.1.4
Loading capacitor
o
s
b
O
-
The loading conditions used for pin parameter measurement are shown in Figure 58.
)
s
(
ct
Figure 58. Pin loading conditions
u
d
o
r
P
e
t
e
l
o
ST7 pin
CL
s
b
O
153/201
Electrical characteristics
12.1.5
ST7232Axx-Auto
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 59.
Figure 59. Pin input voltage
ST7 pin
VIN
12.2
Absolute maximum ratings
)
s
t(
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
c
u
d
12.2.1
Voltage characteristics
Table 69.
Voltage characteristics
Symbol
o
s
b
O
Ratings
VDD - VSS
Supply voltage
VPP - VSS
Programming voltage
(t s)
e
t
le
o
r
P
Input voltage on true open drain pin
VIN(1)(2)
uc
Input voltage on any other pin
d
o
r
P
e
O
6.5
13
VSS - 0.3 to 6.5
50
|VSSA - VSSx|
50
Variations between digital and analog ground pins
VESD(HBM)
Electro-static discharge voltage (human body model)
VESD(MM)
Electro-static discharge voltage (machine model)
V
VSS - 0.3 to
VDD + 0.3
|∆VDDx| and |∆VSSx| Variations between different digital power pins
t
e
l
o
bs
Maximum value Unit
mV
See Section 12.7.3 on
page 167
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up
or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must
not be directly tied to VDD or VSS.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
154/201
ST7232Axx-Auto
12.2.2
Electrical characteristics
Current characteristics
Table 70.
Current characteristics
Symbol
Ratings
Maximum value Unit
Total current into VDD power lines
(source(1))
32-pin device
75
IVDD
44-pin device
150
Total current out of VSS ground lines
(sink)(1)
32-pin device
75
IVSS
44-pin device
150
IIO
IINJ(PIN)
(2)(3)
mA
mA
Output current sunk by any standard I/O and control pin
20
Output current sunk by any high sink I/O pin
40
Output current source by any I/Os and control pin
- 25
Injected current on VPP pin
±5
Injected current on RESET pin
±5
Injected current on OSC1 and OSC2 pins
±5
Injected current on Flash device pin PB0
+5
c
u
d
Injected current on any other pin(4)(5)
ΣIINJ(PIN)
(2)
±5
Total injected current (sum of all I/O and control
ro
pins)(4)
P
e
let
mA
)
s
t(
± 25
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
o
s
b
O
-
3. Negative injection disturbs the analog performance of the device. See note 3 in Section 12.12.3: ADC
accuracy on page 181.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
)
s
(
ct
5. True open drain I/O port pins do not accept positive injection.
12.2.3
Thermal characteristics
Table 71.
u
d
o
Thermal characteristics
r
P
e
Symbol
s
b
O
t
e
l
o
TSTG
TJ
Ratings
Storage temperature range
Value
Unit
-65 to +150
°C
Maximum junction temperature (see Section 13.2: Thermal characteristics)
155/201
Electrical characteristics
12.3
ST7232Axx-Auto
Operating conditions
Table 72.
General operating conditions
Symbol
fCPU
Parameter
Conditions
TA
Max
Unit
0
8
MHz
3.8
5.5
Internal clock frequency
Operating voltage
(except Flash write/erase)
VDD
Min
V
Operating voltage for Flash
write/erase
Ambient temperature range
VPP = 11.4 to 12.6V
4.5
5.5
A suffix version
-40
85
B suffix version
-40
105
C suffix version
-40
125
°C
Figure 60. fCPU max versus VDD
fCPU [MHz]
c
u
d
8
Functionality not
guaranteed in this area
6
4
e
t
le
2
1
0
3.5
3.8 4.0
)
s
t(
o
r
P
Functionality guaranteed
in this area (unless otherwise
specified in the tables
of parametric data)
o
s
b
O
4.5
5.5
Supply voltage [V]
)
s
(
ct
1. Some temperature ranges are only available with a specific package and memory size. Refer to
Section 14: Device configuration and ordering information.
u
d
o
Warning:
r
P
e
t
e
l
o
s
b
O
156/201
Do not connect 12V to VPP before VDD is powered on, as this
may damage the device.
ST7232Axx-Auto
12.4
Electrical characteristics
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for halt mode
for which the clock is stopped).
12.4.1
Current consumption
Table 73.
Current consumption
Symbol
Parameter
Flash
devices
Conditions
Supply current in run
mode(2)
IDD
Typ
Typ
Max(1)
1
1.4
2.4
4.4
2.3
3.5
5.3
7.0
1.3
2.0
3.6
7.1
2.0
3.0
5
10
mA
0.48
0.53
0.63
0.80
1
1.1
1.2
1.4
0.6
0.7
0.8
1.1
1.8
2.1
2.4
3.0
mA
0.6
0.9
1.3
2.3
1.8
2.2
2.6
3.6
1
1.5
2.5
4.5
1.3
2.0
3.3
6
mA
430
470
530
660
950
1000
1050
1200
70
100
200
350
200
300
600
1200
µA
-40°C ≤ TA ≤ +85°C
<1
10
<1
10
-40°C ≤ TA ≤ +125°C
5
50
<1
50
60
100
180
340
160
200
300
500
22
44
86
170
30
60
120
300
fOSC = 2MHz, fCPU = 1MHz
fOSC = 4MHz, fCPU = 2MHz
fOSC = 8MHz, fCPU = 4MHz
fOSC = 16MHz, fCPU = 8MHz
fOSC = 2MHz, fCPU = 1MHz
fOSC = 4MHz, fCPU = 2MHz
fOSC = 8MHz, fCPU = 4MHz
fOSC = 16MHz, fCPU = 8MHz
e
t
le
so
fOSC = 2MHz, fCPU = 62.5kHz
Supply current in slow fOSC = 4MHz, fCPU = 125kHz
fOSC = 8MHz, fCPU = 250kHz
wait mode(2)
fOSC = 16MHz, fCPU = 500kHz
(s)
Supply current in halt
mode(3)
od
t
c
u
Supply current in
active halt mode(4)
1.
s
b
O
t
e
l
o
r
P
e
Unit
Max(1)
fOSC = 2MHz, fCPU = 62.5kHz
Supply current in slow fOSC = 4MHz, fCPU = 125kHz
fOSC = 8MHz, fCPU = 250kHz
mode(2)
fOSC = 16MHz, fCPU = 500kHz
Supply current in wait
mode(2)
ROM
devices
b
O
-
fOSC = 2MHz
fOSC = 4MHz
fOSC = 8MHz
fOSC = 16MHz
c
u
d
o
r
P
)
s
t(
µA
µA
Data based on characterization results, tested in production at VDD max. and fCPU max.
2. Measurements are done in the following conditions:
- Progam executed from RAM, CPU running with RAM access. The increase in consumption when
executing from Flash is 50%.
- All I/O pins in input mode with a static value at VDD or VSS (no load)
- All peripherals in reset state.
- Clock input (OSC1) driven by external square wave.
- In slow and slow wait mode, fCPU is based on fOSC divided by 32.
To obtain the total current consumption of the device, add the clock source (Section 12.5.3) and the
peripheral power consumption (Section 12.4.3).
3. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load). Data based
on characterization results, tested in production at VDD max. and fCPU max.
4. Data based on characterisation results, not tested in production. All I/O pins in push-pull 0 mode (when
applicable) with a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave.
To obtain the total current consumption of the device, add the clock source consumption (Section 12.5.3).
157/201
Electrical characteristics
ST7232Axx-Auto
Power consumption vs fCPU: Flash devices
Figure 61. Typical IDD in run mode
6
5
Idd (mA)
4
2MHZ
4MHz
3
8MHz
16MHz
2
1
6
5.
7
5.
4
5.
1
4.
8
4.
5
4.
2
3.
9
3.
6
3.
3
3
0
Vdd (V)
c
u
d
Figure 62. Typical IDD in slow mode
1.2
1
e
t
le
so
0.6
r
P
e
t
e
l
o
s
b
O
158/201
Vdd (V)
2MHZ
4MHz
8MHz
6
16MHz
5.
7
5.
4
4.
8
3.
6
3.
3
3
u
d
o
4.
5
)
s
(
ct
0
b
O
4.
2
0.2
3.
9
0.4
5.
1
Idd (mA)
0.8
o
r
P
)
s
t(
ST7232Axx-Auto
Electrical characteristics
Figure 63. Typical IDD in wait mode
3.5
3
Idd (mA)
2.5
2MHZ
2
4MHz
1.5
8MHz
16MHz
1
0.5
6
5.
7
5.
4
5.
1
4.
8
4.
5
4.
2
3.
9
3.
6
3
3.
3
0
Vdd (V)
Figure 64. Typ. IDD in slow wait mode
c
u
d
0.9
0.8
0.7
o
r
P
2MHZ
0.5
(s)
4MHz
8MHz
16MHz
6
5.
4
5.
1
3.
6
3.
3
3
0
o
s
b
O
4.
5
0.1
4.
8
0.2
4.
2
0.3
5.
7
e
t
le
0.4
3.
9
Idd (mA)
0.6
)
s
t(
Vdd (V)
12.4.2
t
c
u
Supply and clock managers
d
o
r
P
e
The previous current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for halt mode).
t
e
l
o
Table 74.
O
bs
Supply current of clock sources
Symbol
Parameter
IDD(RES)
Supply current of resonator
oscillator(1)(2)
IDD(PLL)
PLL supply current
Conditions
Typ
Max
see Section 12.5.3
on page 162
VDD = 5V
360
Unit
µA
µA
1. Data based on characterization results done with the external components specified in Section 12.5.3 , not
tested in production.
2. As the oscillator is based on a current source, the consumption does not depend on the voltage.
159/201
Electrical characteristics
12.4.3
ST7232Axx-Auto
On-chip peripherals
Table 75.
On-chip peripherals
Symbol
Parameter
Conditions
Typ
IDD(TIM) 16-bit timer supply current(1)
Unit
50
(2)
IDD(SPI) SPI supply current
TA = 25°C, fCPU = 4MHz, VDD = 5.0V
IDD(SCI) SCI supply current(3)
µA
400
IDD(ADC) ADC supply current when converting(4)
1. Data based on a differential IDD measurement between reset configuration (timer counter running at
fCPU/4) and timer counter stopped (only TIMD bit set). Data valid for one timer.
2. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent
SPI master communication at maximum speed (data sent equal to 55h). This measurement includes the
pad toggling consumption.
3. Data based on a differential IDD measurement between SCI low power state (SCID=1) and a permanent
SCI data transmit sequence.
4. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions.
12.5
c
u
d
Clock and timing characteristics
Subject to general operating conditions for VDD, fCPU, and TA.
12.5.1
e
t
le
General timings
Table 76.
General timings
Symbol
Parameter
tc(INST)
Instruction cycle time
tv(IT)
)
s
(
ct
o
s
b
O
-
Interrupt reaction time(2)
tv(IT) = ∆tc(INST) + 10
u
d
o
Conditions
fCPU = 8MHz
fCPU = 8MHz
)
s
t(
o
r
P
Min
Typ(1)
Max
Unit
2
3
12
tCPU
250
375
1500
ns
10
22
tCPU
1.25
2.75
µs
1. Data based on typical application software.
r
P
e
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles
needed to finish the current instruction execution.
t
e
l
o
s
b
O
160/201
ST7232Axx-Auto
12.5.2
Electrical characteristics
External clock source
Table 77.
External clock source
Symbol
Parameter
VOSC1H
OSC1 input pin high level voltage
VDD - 1
VDD
VOSC1L
OSC1 input pin low level voltage
VSS
VSS + 1
tw(OSC1H)
tw(OSC1L)
tr(OSC1)
tf(OSC1)
Ilkg
Conditions
see Figure 65
OSC1 high or low time(1)
Min
Typ
Max
Unit
V
5
ns
(1)
OSC1 rise or fall time
15
OSC1 Input leakage current
VSS ≤ VIN ≤ VDD
±1
µA
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 65. Typical application with an external clock source
90%
VOSC1H
10%
c
u
d
VOSC1L
tf(OSC1)
tr(OSC1)
tw(OSC1H)
OSC2
o
s
b
O
-
o
r
P
tw(OSC1L)
e
t
le
)
s
t(
Not connected internally
External clock source
(s)
fOSC
Ilkg
OSC1
ST72XXX
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
161/201
Electrical characteristics
12.5.3
ST7232Axx-Auto
Crystal and ceramic resonator oscillators
The ST7 internal clock can be supplied with four different crystal/ceramic resonator
oscillators. All the information given in this paragraph are based on characterization results
with specified typical external components. In the application, the resonator and the load
capacitors have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, package, accuracy...).
Table 78.
Oscillator parameters
Symbol
Parameter
frequency(1)
Conditions
Min
Max
Unit
LP: Low power oscillator
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
1
>2
>4
>8
2
4
8
16
MHz
20
40
kΩ
fOSC
Oscillator
RF
Feedback resistor(2)
CL1
CL2
Recommended load capacitance
versus equivalent serial resistance of
the crystal or ceramic resonator (RS)
RS = 200Ω LP oscillator
RS = 200Ω MP oscillator
RS = 200Ω MS oscillator
RS = 100ΩHS oscillator
OSC2 driving current
VIN = VSS
LP oscillator
MP oscillator
MS oscillator
HS oscillator
i2
e
t
le
22
22
18
15
)
s
t(
o
r
P
80
160
310
610
150
250
460
910
c
u
d
56
46
33
33
1. The oscillator selection can be optimized in terms of supply current using a high quality resonator with
small RS value. Refer to crystal/ceramic resonator manufacturer for more details.
o
s
b
O
-
2. Data based on characterisation results, not tested in production.
Figure 66. Typical application with a crystal or ceramic resonator
)
s
(
ct
i2
When resonator with integrated capacitors
o
r
P
e
t
e
l
o
s
b
O
162/201
du
CL1
fOSC
OSC1
Resonator
CL2
RF
OSC2
ST72XXX
pF
µA
ST7232Axx-Auto
Table 79.
Examples of typical resonators
Reference(1)
Oscil.
Freq.
Characteristic(2)
CL1 CL2 tSU(osc)
[pF] [pF] [ms](3)
LP
CSA2.00MG
2MHz
∆fOSC =
[±0.5%tolerance,±0.3%∆Ta, ±0.3%aging, ±x.x%correl]
22
22
4
MP
CSA4.00MG
4MHz
∆fOSC =
[±0.5%tolerance,±0.3%∆Ta, ±0.3%aging, ±x.x%correl]
22
22
2
CSA8.00MTZ
8MHz
∆fOSC =
[±0.5%tolerance,±0.5%∆Ta, ±0.3%aging, ±x.x%correl]
33
33
1
16MHz
∆fOSC =
[±0.5%tolerance,±0.3%∆Ta, ±0.3%aging, ±x.x%correl]
33
33
0.7
MURATA
Ceramic
Electrical characteristics
MS
CSA16.00MXZ040
HS
(4)
1. Resonators all have different characteristics. Contact the manufacturer to obtain the appropriate values of external
components and to verify oscillator performance.
2. Resonator characteristics given by the ceramic resonator manufacturer.
3. tSU(OSC) is the typical oscillator start-up time measured between VDD = 2.8V and the fetch of the first instruction (with a
quick VDD ramp-up from 0 to 5V (< 50µs).
4. 3rd overtone resonators require specific validation by the resonator manufacturer.
12.5.4
c
u
d
PLL characteristics
Table 80.
PLL characteristics
Symbol
fOSC
∆ fCPU/fCPU
Parameter
Conditions
e
t
le
PLL input frequency range
Instantaneous PLL
jitter(1)
1. Data characterized but not tested.
Min
2
fOSC = 4 MHz.
o
s
b
O
-
o
r
P
Typ
0.7
)
s
t(
Max
Unit
4
MHz
2
%
The user must take the PLL jitter into account in the application (for example in serial
communication or sampling of high frequency signals). The PLL jitter is a periodic effect,
which is integrated over several CPU cycles. Therefore the longer the period of the
application signal, the less it is impacted by the PLL jitter.
)
s
(
ct
Figure 67 shows the PLL jitter integrated on application signals in the range 125kHz to
2MHz. At frequencies of less than 125KHz, the jitter is negligible.
u
d
o
r
P
e
Figure 67. Integrated PLL jitter vs signal frequency
t
e
l
o
O
bs
+/-Jitter
(%) 1.2
1
0.8
0.6
0.4
0.2
0
max
typ
4
2
1 500 250 125
MHz MHz MHz kHz kHz kHz
Application Frequency
1. Measurement conditions: fCPU = 8MHz.
163/201
Electrical characteristics
ST7232Axx-Auto
12.6
Memory characteristics
12.6.1
RAM and hardware registers
Table 81.
RAM and hardware registers
Symbol
VRM
Parameter
Conditions
(1)
Data retention mode
Halt mode (or reset)
Min
Typ
Max
1.6
Unit
V
1. Minimum VDD supply voltage without losing data stored in RAM (in halt mode or under reset) or in
hardware registers (only in halt mode). Not tested in production.
12.6.2
Flash memory
Table 82.
Characteristics of dual voltage HDFlash memory
Dual voltage HDFlash memory
Symbol
Parameter
Conditions
Read mode
0
Write/erase mode
1
fCPU
Operating frequency
VPP
Programming voltage(2)
4.5V ≤VDD ≤5.5V
IDD
Supply current(3)
Write/erase
IPP
VPP current(3)
tVPP
Internal VPP stabilization time
tRET
Data retention time
NRW
Write erase cycles
e
t
le
Read (VPP = 12V)
Write/erase
(s)
TPROG Programming or erasing
TERASE temperature range
Min(1)
so
b
O
-
11.4
Pr
Max(1)
Typ
8
uc
8
od
)
s
t(
12.6
<10
Unit
MHz
V
µA
200
µA
30
mA
10
µs
TA = 55°C
20
Years
TA = 85°C
100
Cycles
t
c
u
-40
25
85
°C
1. Data based on characterization results, not tested in production.
2. VPP must be applied only during the programming or erasing operation and not permanently for reliability
reasons.
d
o
r
P
e
3. Data based on simulation results, not tested in production.
t
e
l
o
s
b
O
164/201
ST7232Axx-Auto
12.7
Electrical characteristics
Electromagnetic compatability (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
12.7.1
Functional electromagnetic susceptibility (EMS)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electro magnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the
IEC 1000 - 4 - 2 standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000 - 4 - 4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
c
u
d
)
s
t(
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
o
r
P
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
e
t
le
o
s
b
O
-
The software flowchart must include the management of runaway conditions such as:
●
Corrupted program counter
●
Unexpected reset
●
Critical data corruption (control registers...)
)
s
(
ct
Prequalification trials
u
d
o
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the oscillator pins for 1
second.
r
P
e
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behaviour is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
t
e
l
o
s
b
O
165/201
Electrical characteristics
Table 83.
ST7232Axx-Auto
Electromagnetic test results
Symbol
VFESD
VFFTB
12.7.2
Parameter
Voltage limits to be applied on
any I/O pin to induce a
functional disturbance
Fast transient voltage burst
limits to be applied through
100pF on VDD and VDD pins to
induce a functional disturbance
Conditions
Level/class
ROM device, VDD = 5V, TA = +25°C,
fOSC = 8MHz conforms to IEC 1000 - 4 - 2
4A
Flash device, VDD = 5V, TA = +25°C,
fOSC = 8MHz conforms to IEC 1000 - 4 - 2
4B
VDD = 5V, TA = +25°C, fOSC = 8MHz
conforms to IEC 1000 - 4 - 4
4A
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling two LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 84.
EMI emissions(1)
Sym. Parameter
Cond.
Device/package
Monitored
frequency band
o
r
P
16/8MHz
25
27
30MHz to 130MHz
30
36
130MHz to 1GHz
18
23
SAE EMI level
3.0
3.5
0.1MHz to 30MHz
25
27
30MHz to 130MHz
30
36
130MHz to 1GHz
18
23
Peak
level(2)
o
r
P
e
VDD = 5V, TA = +25°C conforming to SAE J 1752/3
SEMI
SAE EMI level
3.0
3.5
0.1MHz to 30MHz
12
18
30MHz to 130MHz
19
25
130MHz to 1GHz
15
22
t
e
l
o
SAE EMI level
3
3.5
0.1MHz to 30MHz
12
15
bs
30MHz to 130MHz
23
26
130MHz to 1GHz
15
20
O
SAE EMI level
3.0
3.5
o
s
b
O
-
ct
du
e
t
le
Flash/LQFP32
(s)
dBµV
-
dBµV
-
dBµV
-
dBµV
8K ROM/LQFP44
1. Refer to Application Note AN1709 for data on other package types
166/201
Unit
8K Flash/LQFP44
2. Data based on characterization results, not tested in production
3. Under completion
Max vs. [fOSC/fCPU]
8/4MHz
0.1MHz to 30MHz
ROM/LQFP32(3)
c
u
d
)
s
t(
-
ST7232Axx-Auto
12.7.3
Electrical characteristics
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the device
is stressed in order to determine its performance in terms of electrical sensitivity.
Electro-static discharge (ESD)
Electro-static discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the AEC-Q100-002/003/011 standard. For more details, refer to the application
note AN1181.
Table 85.
ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class
VESD(HBM)
Electro-static discharge voltage
(human body model)
TA = +25°C
conforming to AEC-Q100002
H1C
VESD(MM)
Electro-static discharge voltage
(machine model)
TA = +25°C
conforming to AEC-Q100003
M2
Electro-static discharge voltage
VESD(CDM)
(charged device model)
TA = +25°C
conforming to AEC-Q100011
2000
uc
d
o
r
P
e
let
C3B
Maximum
Unit
value(1)
)
s
t(
200
V
> 500 to ≤
750 with
corner
pins > 750
o
s
b
O
-
1. Data based on characterization results, not tested in production
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
)
s
(
ct
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/0 pin
u
d
o
These tests are compliant with EIA/JESD 78A and AEC-Q100/004 IC latch-up standards.
r
P
e
Table 86.
Symbol
s
b
O
t
e
l
o
LU
Latch up results
Parameter
Static latch-up class
Conditions
Class
TA = +125°C
conforming to JESD 78A and AEC-Q100/004
II level A
167/201
Electrical characteristics
ST7232Axx-Auto
12.8
I/O port pin characteristics
12.8.1
General characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Table 87.
I/O general port pin characteristics
Symbol
Parameter
Conditions
VIL
Input low level voltage
(standard voltage devices)(1)
VIH
Input high level voltage(1)
Vhys
IINJ(PIN)(3)
Schmitt trigger voltage hysteresis
Max
Unit
0.3 x VDD
V
V
0.7
Injected current on Flash device pin
PB0
0
+4
VDD = 5V
±4
Total injected current
(sum of all I/O and control pins)
c
u
d
VSS ≤VIN ≤VDD
Input leakage current
IS
Static current consumption induced by
Floating input mode(4)(5)
each floating input pin
RPU
Weak pull-up equivalent resistor(6)
CIO
I/O pin capacitance
Output high to low level fall time(1)
time(1)
tr(IO)out
Output low to high level rise
tw(IT)in
External interrupt pulse time(7)
)
s
(
ct
mA
)
s
t(
±25
Ilkg
tf(IO)out
Typ
0.7 x VDD
(2)
Injected current on other I/O pins
ΣIINJ(PIN)(3)
Min
±1
VIN = VSS, VDD = 5V
e
t
le
o
r
P
200
50
250
5
so
kΩ
pF
25
CL = 50pF between
10% and 90%
b
O
-
120
µA
ns
25
1
tCPU
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specification. A
positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. Refer to Section 12.2.2 on
page 155 for more details.
u
d
o
4. Static peak current value taken at a fixed VIN value, based on design simulation and technology characteristics, not tested
in production. This value depends on VDD and temperature values.
r
P
e
5. The Schmitt trigger that is connected to every I/O port is disabled for analog inputs only when ADON bit is ON and the
particular ADC channel is selected (with port configured in input floating mode). When the ADON bit is OFF, static current
consumption may result. This can be avoided by keeping the input voltage of this pin close to VDD or VSS.
t
e
l
o
6. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described
in Figure 69).
s
b
O
7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
168/201
ST7232Axx-Auto
Electrical characteristics
Figure 68. Unused I/O pins configured as input
VDD
ST7XXX
10kΩ
Unused I/O port
Unused I/O port
10kΩ
ST7XXX
1.
I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC
robustness and lower cost.
Figure 69. Typical IPU vs. VDD with VIN = VSS
90
Ta=1 40°C
80
Ta=9 5°C
70
Ta=2 5°C
Ipu(uA )
c
u
d
Ta=-45 °C
60
50
o
r
P
40
30
e
t
le
20
10
so
0
2
)
s
(
ct
2.5
3
3.5
4
4.5
Vdd(V)
5
5.5
)
s
t(
6
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
169/201
Electrical characteristics
12.8.2
ST7232Axx-Auto
Output driving current
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 88.
Output driving current
Symbol
Parameter
Conditions
VOL(1)
VOH(2)
Output low level voltage for a high sink
I/O pin when 4 pins are sunk at same
time (see Figure 71 and Figure 73)
VDD = 5V
Output low level voltage for a standard
I/O pin when 8 pins are sunk at same
time (see Figure 70)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 72 and Figure 75)
Min
Max
IIO = +5mA
1.2
IIO = +2mA
0.5
IIO = +20mA,
TA ≤ 85°C
TA > 85°C
1.3
1.5
IIO = +8mA
0.6
Unit
V
IIO = -5mA,
TA ≤ 85°C
TA > 85°C
VDD - 1.4
VDD - 1.6
IIO = -2mA
VDD - 0.7
)
s
t(
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the
sum of IIO (I/O ports and control pins) must not exceed IVSS.
c
u
d
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and
the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins do not have VOH.
Figure 70. Typical VOL at VDD = 5V (std. ports)
e
t
le
1.4
V ol (V ) at Vdd=5V
1.2
1
0.8
)
s
(
ct
o
r
P
e
t
e
l
o
s
b
O
170/201
du
0.6
o
r
P
o
s
b
O
-
Ta =14 0°C "
0.4
Ta =95 °C
Ta =25 °C
0.2
Ta =-45 °C
0
0
5
0.005
10
0.01
IIOIio(A)
(mA)
15
0.015
ST7232Axx-Auto
Electrical characteristics
Figure 71. Typ. VOL at VDD = 5V (high-sink ports)
1
0.9
Vol(V) at V dd=5V
0.8
0.7
0.6
0.5
0.4
Ta= 140 °C
0.3
Ta= 95 °C
0.2
Ta= 25 °C
0.1
Ta= -45°C
0
10
0
20 0.02
IIO (mA)
Iio(A)
0.01
30
0.03
Figure 72. Typical VOH at VDD = 5V
c
u
d
5.5
Vdd-Voh (V) at Vdd=5V
5
4.5
4
e
t
le
3.5
)
s
t(
o
r
P
V dd= 5V 1 40°C m in
so
3
V dd= 5v 95°C m in
b
O
-
2.5
2
-10
-0.01
)
s
(
ct
u
d
o
-8
V dd= 5v 25°C m in
V dd= 5v -4 5°C m in
-6
-4
-2
-0.008 -0.006 -0.004
-0.002
0
0
IIOIio(mA)
(A)
Figure 73. Typical VOL vs. VDD (std. ports)
r
P
e
1
0.9
Ta=2 5°C
Ta= 95°C
Ta= 140 °C
0.7
Ta=9 5°C
0.35
Ta=1 40°C
Vol(V) at Iio=2mA
O
bs
Ta=-4 5°C
0.4
Ta= 25°C
0.8
Vol(V) at Iio=5m A
t
e
l
o
0.45
Ta= -4 5°C
0.6
0.5
0.4
0.3
0.2
0.3
0.25
0.2
0.15
0.1
0.1
0.05
0
2
2.5
3
3.5
4
Vdd(V)
4.5
5
5.5
6
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
171/201
Electrical characteristics
ST7232Axx-Auto
Figure 74. Typical VOL vs. VDD (high-sink ports)
1 .6
0 .6
Ta = 140 °C
1 .4
0 .5
Ta =95 °C
1 .2
Ta =25 °C
Ta =-45°C
Vol(V ) at Iio=20m A
Vol(V ) at Iio=8m A
0 .4
0 .3
0 .2
1
0 .8
0 .6
Ta= 14 0°C
0 .4
Ta=9 5°C
0 .1
Ta=2 5°C
0 .2
Ta=-45 °C
0
0
2
2.5
3
3.5
4
4.5
5
5.5
2
6
2.5
3
3.5
4
4.5
5
5.5
6
V dd(V )
V dd (V )
Figure 75. Typical VOH vs. VDD
5.5
c
u
d
6
Ta= -4 5°C
5
Vdd-Voh(V) at Iio=-5mA
V dd-V oh(V) at Iio=-2m A
5
4.5
4
3.5
Ta= -4 5°C
3
Ta= 25°C
Ta= 95°C
2.5
Ta= 25°C
)
s
t(
o
r
P
Ta= 95°C
Ta= 140°C
4
e
t
le
3
o
s
b
O
2
1
Ta= 140°C
2
0
2
2.5
3
3.5
4
u
d
o
t
e
l
o
s
b
O
172/201
5
)
s
(
ct
Vdd(V)
r
P
e
4.5
5.5
6
2
2.5
3
3.5
4
Vdd(V)
4.5
5
5.5
6
ST7232Axx-Auto
Electrical characteristics
12.9
Control pin characteristics
12.9.1
Asynchronous RESET pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 89.
Asynchronous RESET pin
Symbol
Parameter
Conditions
Vhys
Schmitt trigger voltage hysteresis(1)
Input low level voltage
VIH
Input high level voltage(2)
IIO
Driving current on RESET pin
2.5
VDD = 5V
tw(RSTL)out Generated reset pulse duration
External reset pulse hold time
IIO = +2mA
V
0.2
0.5
2
Weak pull-up equivalent resistor
Filtered glitch
Unit
0.85 x VDD
voltage(3)
Output low level
tg(RSTL)in
Max
0.16 x VDD
VOL
th(RSTL)in
Typ
(2)
VIL
RON
Min
mA
VDD = 5V
20
30
120
Internal reset sources
20
30
42(4)
(5)
2.5
duration(6)
c
u
d
200
1. Hysteresis voltage between Schmitt trigger switching levels.
2. Data based on characterization results, not tested in production.
kΩ
)
s
t(
µs
µs
ns
o
r
P
3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVSS.
e
t
le
4. Data guaranteed by design, not tested in production.
o
s
b
O
-
5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the
RESET pin with a duration below th(RSTL)in can be ignored.
6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy
environments.
)
s
(
ct
Figure 76. RESET pin protection
u
d
o
User external
reset circuit
t
e
l
o
r
P
e
s
b
O
VDD
ST72XXX
RON
Internal reset
Filter
0.01µF
Pulse generator
Watchdog
Required
1. The reset network protects the device against parasitic resets.
2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (watchdog).
3. 3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the VIL max. level specified in Section 12.9.1 . Otherwise the reset is not taken into account internally.
4. 4. Because the reset circuit is designed to allow the internal reset to be output in the RESET pin, the user must ensure that
the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified
for IINJ(RESET) in Section 12.2.2 on page 155.
173/201
Electrical characteristics
12.9.2
ST7232Axx-Auto
ICCSEL/VPP pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 90.
ICCSEL/VPP pin characteristics
Symbol
VIL
Parameter
Conditions
Input low level voltage(1)
VIH
Input high level voltage
Ilkg
Input leakage current
(1)
Min
Max
Flash versions
VSS
0.2
ROM versions
VSS
0.3 x VDD
Flash versions
VDD - 0.1
12.6
ROM versions
0.7 x VDD
VDD
VIN = VSS
Unit
V
±1
uA
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 77. Two typical applications with ICCSEL/VPP pin
ICCSEL/VPP
VPP
Programming
tool
c
u
d
10kΩ
ST72XXX
)
s
t(
ST72XXX
o
r
P
e
t
le
1. When ICC mode is not required by the application ICCSEL/VPP pin must be tied to VSS.
12.10
o
s
b
O
-
Timer peripheral characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
)
s
(
ct
Refer to Section 9: I/O ports for more details on the input/output alternate function
characteristics (output compare, input capture, external clock, PWM output...).
Data based on design simulation and/or characterisation results, not tested in production.
12.10.1
r
P
e
Table 91.
t
e
l
o
Symbol
bs
O
tw(ICAP)in
tres(PWM)
16-bit timer
Parameter
Conditions
Input capture pulse time
Min
Typ
Max
Unit
1
tCPU
2
PWM resolution time
fCPU = 8MHz
250
ns
fEXT
Timer external clock frequency
0
fCPU/4
fPWM
PWM repetition rate
0
fCPU/4
ResPWM
174/201
u
d
o
16-bit timer
PWM resolution
16
MHz
bit
ST7232Axx-Auto
Electrical characteristics
12.11
Communication interface characteristics
12.11.1
SPI (serial peripheral interface)
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Data based on design simulation and/or characterisation results, not tested in production.
When no communication is on-going the data output line of the SPI (MOSI in master mode,
MISO in slave mode) has its alternate function capability released. In this case, the pin
status depends on the I/O port configuration. Refer to Section 9: I/O ports for more details
on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).
Table 92.
SPI characteristics
Symbol
fSCK
1/tc(SCK)
tr(SCK)
tf(SCK)
tsu(SS)(1)
th(SS)
(1)
Parameter
SPI clock frequency
Conditions
Min
Master fCPU = 8MHz
0
SPI clock rise and fall
time
SS hold time
120
Data input setup time
Master
Slave
th(MI)(1)
th(SI)(1)
Data input hold time
Master
Slave
ta(SO)(1)
Data output access
time
)
s
(
ct
tv(SO)(1)
Data output valid time
(1)
Data output hold time
(1)
Data output valid time
(1)
Data output hold time
th(SO)
o
r
P
e
tv(MO)
th(MO)
t
e
l
o
c
u
d
120
Slave
tsu(MI)(1)
tsu(SI)(1)
tdis(SO)
du
MHz
fCPU/2 = 4
)
s
t(
see Table 2: Device pin description
SS setup time(2)
Data output disable
time
Unit
fCPU/128 = 0.0625 fCPU/4 = 2
Slave fCPU = 8MHz
tw(SCKH)(1)
Master
SCK high and low time
Slave
tw(SCKL)(1)
(1)
Max
o
r
P
100
90
e
t
le
so
b
O
-
100
100
100
100
ns
0
120
Slave
Slave (after enable
edge)
Master (after enable
edge)
240
90
0
120
0
1. Data based on design simulation and/or characterization results, not tested in production
s
b
O
2. Depends on fCPU. For example, if fCPU = 8 MHz, then tCPU = 1/fCPU = 125ns and tsu(SS) = 175ns.
175/201
Electrical characteristics
ST7232Axx-Auto
Figure 78. SPI slave timing diagram with CPHA = 0
SS INPUT
SCK INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
tw(SCKH)
tw(SCKL)
ta(SO)
MISO OUTPUT
see note 2
tv(SO)
MSB OUT
th(SO)
tdis(SO)
tr(SCK)
tf(SCK)
BIT6 OUT
LSB OUT
see note 2
th(SI)
tsu(SI)
MOSI INPUT
MSB IN
LSB IN
BIT1 IN
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD.
c
u
d
)
s
t(
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends of the I/O port configuration.
Figure 79. SPI slave timing diagram with CPHA = 1
SS INPUT
SCK INPUT
tsu(SS)
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
tw(SCKH)
tw(SCKL)
ta(SO)
MISO OUTPUT
MSB OUT
od
see note 2
tsu(SI)
r
P
e
t
e
l
o
(s)
t
c
u
HZ
MOSI INPUT
e
t
le
tc(SCK)
o
s
b
O
tv(SO)
th(SO)
BIT6 OUT
o
r
P
th(SS)
tr(SCK)
tf(SCK)
LSB OUT
see note 2
th(SI)
MSB IN
tdis(SO)
BIT1 IN
LSB IN
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD.
s
b
O
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends of the I/O port configuration.
176/201
ST7232Axx-Auto
Electrical characteristics
Figure 80. SPI master timing diagram
SS INPUT
tc(SCK)
SCK INPUT
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA=1
CPOL=0
CPHA = 1
CPOL = 1
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
tsu(MI)
MISO INPUT
MSB IN
BIT6 IN
tv(MO)
MOSI OUTPUT
see note 2
MSB OUT
LSB IN
th(MO)
BIT6 OUT
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD.
LSB OUT
c
u
d
)
s
t(
see note 2
o
r
P
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends of the I/O port
configuration.
e
t
le
)
s
(
ct
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
177/201
Electrical characteristics
12.12
ST7232Axx-Auto
10-bit ADC characteristics
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 93.
10-bit ADC characteristics
Symbol
fADC
Parameter
Conditions
Min
ADC clock frequency
0.7 * VDD ≤ VAREF ≤ VDD
Analog reference voltage
VAREF
Conversion voltage range(1)
VAIN
Input leakage current for analog input (2)
Ilkg
Typ
Max
Unit
0.4
2
MHz
3.8
VDD
VSSA
VAREF
V
-40°C ≤ TA ≤ +85°C
±250
nA
+85°C < TA ≤ +125°C
±1
µA
External input impedance
RAIN
kΩ
see Figure 81
and Figure 82
CAIN
External capacitor on analog input
fAIN
Variation freq. of analog input signal
CADC
Internal sample and hold capacitor
tADC
Conversion time (sample + hold)
fCPU = 8MHz, SPEED = 0 fADC = 2MHz
tADC
– No of sample capacitor loading cycles
– No. of hold conversion cycles
pF
Hz
12
pF
uc
7.5
d
o
r
P
e
let
)
s
t(
4
11
µs
1/fADC
1. Any added external serial resistor downgrades the ADC accuracy (especially for resistance greater than 10kΩ). Data based
on characterization results, not tested in production.
2. Injecting negative current on adjacent pins may result in increased leakage currents. Software filtering of the converted
analog value is recommended.
o
s
b
O
-
Max. RAIN (Kohm)
Figure 81. RAIN max. vs fADC with CAIN = 0pF
45
40
uc
od
r
P
e
t
e
l
o
s
b
O
35
30
25
(t s)
2 M Hz
1M Hz
20
15
10
5
0
0
10
30
70
CPARASITIC (pF)
1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad
capacitance (3pF). A high CPARASITIC value downgrades conversion accuracy. To remedy this, fADC should be reduced.
178/201
ST7232Axx-Auto
Electrical characteristics
Max. RAIN (Kohm)
Figure 82. Recommended CAIN and RAIN values
C ain 10 nF
1000
C ain 22 nF
C ain 47 nF
100
10
1
0.1
0.01
0.1
1
10
f AIN(KHz)
1. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization
time and decreased to allow the use of a larger serial resistor (RAIN).
Figure 83. Typical A/D converter application
RAIN
AINx
VAIN
CAIN
12.12.1
)
s
t(
ST72XXX
VDD
VT
0.6V
VT
0.6V
2kΩ(max)
Ilkg
e
t
le
o
r
P
c
u
d
10-bit A/D
conversion
CADC
12pF
o
s
b
O
-
Analog power supply and reference pins
)
s
(
ct
Depending on the MCU pin count, the package may feature separate VAREF and VSSA
analog power supply pins. These pins supply power to the A/D converter cell and function
as the high and low reference voltages for the conversion. In some packages, VAREF and
VSSA pins are not available (refer to Section 2: Pin description on page 19). In this case the
analog supply and reference pads are internally bonded to the VDD and VSS pins.
u
d
o
r
P
e
Separation of the digital and analog power pins allow board designers to improve A/D
performance. Conversion accuracy can be impacted by voltage drops and noise in the event
of heavily loaded or badly decoupled power supply lines (see Section 12.12.2: General PCB
design guidelines on page 180).
t
e
l
o
s
b
O
179/201
Electrical characteristics
12.12.2
ST7232Axx-Auto
General PCB design guidelines
To obtain best results, some general design and layout rules should be followed when
designing the application PCB to shield the noise-sensitive, analog physical interface from
noise-generating CMOS logic signals.
●
Use separate digital and analog planes. The analog ground plane should be connected
to the digital ground plane via a single point on the PCB.
●
Filter power to the analog power planes. It is recommended to connect capacitors, with
good high frequency characteristics, between the power and ground lines, placing
0.1µF and optionally, if needed 10pF capacitors as close as possible to the ST7 power
supply pins and a 1 to 10µF capacitor close to the power source (see Figure 84).
●
The analog and digital power supplies should be connected in a star nework. Do not
use a resistor, as VAREF is used as a reference voltage by the A/D converter and any
resistance would cause a voltage drop and a loss of accuracy.
●
Properly place components and route the signal traces on the PCB to shield the analog
inputs. Analog signals paths should run over the analog ground plane and be as short
as possible. Isolate analog signals from digital signals that may switch while the analog
inputs are being sampled by the A/D converter. Do not toggle digital outputs on the
same I/O port as the A/D input being converted.
c
u
d
Figure 84. Power supply filtering
o
r
P
ST72XXX
1 to 10µF
0.1µF
e
t
le
ST7 digital noise
filtering
VDD
Power
source supply
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
s
b
O
180/201
o
s
b
O
-
External noise
filtering
0.1µF
VSS
VDD
VAREF
VSSA
)
s
t(
ST7232Axx-Auto
12.12.3
Electrical characteristics
ADC accuracy
Table 94.
ADC accuracy with VDD = 5.0V
Symbol
Parameter
Conditions
Typ
Max(1)
|ET|
Total unadjusted error (2)
4
6
|EO|
(2)
Offset error
3
5
|EG|
Gain error(2)
0.5
4.5
|ED|
Differential linearity error(2)
1.5
4.5
1.5
4.5
|EL|
CPU in run mode @ fADC = 2 MHz.
Integral linearity error
(2)
Unit
LSB
1. Data based on characterization results, monitored in production to guarantee 99.73% within ± max value
from -40°C to 125°C (± 3σ distribution limits).
2. ADC accuracy vs. negative injection current: Injecting negative current may reduce the accuracy of the
conversion being performed on another analog input. Any positive injection current within the limits
specified for IINJ(PIN) and ΣIINJ(PIN) in Section 12.8 does not affect the ADC accuracy.
Figure 85. ADC accuracy characteristics
Digital result ADCDR
c
u
d
EG
1023
1022
1LSB
IDEAL
1021
V
–V
AREF
SSA
= -------------------------------------------1024
(2)
e
t
le
(3)
7
(1)
6
EO
4
EL
3
o
r
P
(1) = Example of an actual transfer curve
ET
5
)
s
t(
o
s
b
O
-
(2) = Ideal transfer curve
(3) = End point correlation line
ED
2
1 LSBIDEAL
1
0
1
2
3
4
(s)
5
t
c
u
VSSA
6
7
Vin (LSBIDEAL)
10211022 1023 1024
VAREF
d
o
r
P
e
1. Legend:
ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves
EO = Offset error: deviation between the first actual transition and the first ideal one
EG = Gain error: deviation between the last ideal transition and the last actual one
ED = Differential linearity error: maximum deviation between actual steps and the ideal one
EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line
t
e
l
o
s
b
O
181/201
Package characteristics
ST7232Axx-Auto
13
Package characteristics
13.1
Package mechanical data
Figure 86. 32-pin LQFP outline
D
A
D1
A2
A1
e
E1 E
b
c
c
u
d
L1
L
Table 95.
32-pin LQFP mechanical data
e
t
le
mm
Dim.
Min
Typ
A
0.050
A2
1.350
b
0.300
o
r
P
e
D
t
e
l
o
s
b
O
o
r
P
inches
Typ
ct
du
0.090
(s)
1.400
0.370
Max
0.0630
0.150
0.0020
0.0059
1.450
0.0531
0.0551
0.0571
0.450
0.0118
0.0146
0.0177
0.200
0.0035
0.0079
9.000
0.3543
D1
7.000
0.2756
E
9.000
0.3543
E1
7.000
0.2756
e
0.800
0.0315
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
182/201
b
O
-
Min
h
1.600
A1
C
so
Max
)
s
t(
1.000
0.0394
ST7232Axx-Auto
Package characteristics
Figure 87. 44-pin LQFP outline
A
A2
D
D1
A1
b
e
E1 E
L
c
L1
h
Table 96.
44-pin LQFP mechanical data
mm
Min
Typ
Max
A
0.050
A2
1.350
1.400
b
0.300
0.370
C
0.090
)
s
(
ct
0.0571
0.450
0.0118
0.0146
0.0177
0.200
0.0035
0.000
0.0079
b
O
-
10.000
0.3937
12.000
0.4724
E1
10.000
0.3937
e
0.800
0.0315
o
r
P
e
E
s
b
O
0.0551
0.0630
0.0059
0.4724
du
Max
0.0531
so
1.450
0.0020
12.000
D1
t
e
l
o
Typ
P
e
let
0.150
D
ro
Min
1.600
A1
c
u
d
inches
Dim.
)
s
t(
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
1.000
0.0236
183/201
Package characteristics
13.2
ST7232Axx-Auto
Thermal characteristics
Table 97.
Thermal characteristics
Symbol
RthJA
PD
TJmax
Ratings
Value
Unit
Package thermal resistance (junction to ambient)
LQFP32
LQFP44
70
52
°C/W
Power dissipation(1)
500
mW
150
°C
Maximum junction temperature
(2)
1. The maximum power dissipation is obtained from the formula PD = (TJ-TA)/RthJA. The power dissipation of
an application can be defined by the user with the formula: PD = PINT + PPORT where PINT is the chip
internal power (IDD x VDD) and PPORT is the port power dissipation depending on the ports used in the
application.
2. The maximum chip-junction temperature is based on technology characteristics.
13.3
Soldering information
c
u
d
)
s
t(
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second
level interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
e
t
le
o
r
P
ECOPACK is an ST trademark. ECOPACK® specifications are available at www.st.com.
Compatibility
o
s
b
O
-
ECOPACK® LQFP packages are fully compatible with Lead (Pb) containing soldering
process (see application note AN2034).
Table 98.
Package
Plating material devices
u
d
o
LQFP32
r
P
e
LQFP44
t
e
l
o
s
b
O
184/201
)
s
(
ct
Soldering compatibility (wave and reflow soldering process)
Pb solder paste
Pb-free solder paste
Yes
Yes
NiPdAu (Nickel-Palladium-Gold)
Sn (pure Tin)
ST7232Axx-Auto
Device configuration and ordering information
14
Device configuration and ordering information
14.1
Introduction
Each device is available for production in user programmable versions (Flash) as well as in factory coded
versions (ROM/FASTROM).
ST7232A-Auto are ROM versions. ST72P32A-Auto devices are factory advanced service technique
ROM (FASTROM) versions: they are factory-programmed HDFlash devices.
Flash devices are shipped to customers with a default content (FFh), while ROM factory coded parts
contain the code supplied by the customer. This implies that Flash devices have to be configured by the
customer using the option bytes while the ROM devices are factory-configured.
14.2
Flash devices
14.2.1
Flash configuration
Table 99.
Flash option bytes
Static option byte 0
7
6
5
4
3
2
Static option byte 1
1
0
7
6
o
r
P
4
OSCTYPE
Reserved
1
1
1
1
3
2
1
OSCRANGE
FMP_R PKG1 RSTC
HALT SW
1
5
e
t
le
WDG
Default
c
u
d
)
s
t(
1
1
)
s
(
ct
o
s
b
O
1
See
note
1
1
1
0
2
1
0
1
0
0
1
1
0
PLL
OFF
1
1. Depends on device type as defined in Table 102: Package selection (OPT7) on page 187
The option bytes allows the hardware configuration of the microcontroller to be selected. They have no
address in the memory map and can be accessed only in programming mode (for example using a
standard ST7 programming tool). The default content of the Flash is fixed to FFh. To program directly the
Flash devices using ICP, Flash devices are shipped to customers with an internal clock source selected.
In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list).
u
d
o
r
P
e
t
e
l
o
s
b
O
185/201
Device configuration and ordering information
ST7232Axx-Auto
Table 100. Option byte 0 description
Bit
7
Bit name
Function
WDG HALT
Watchdog reset on halt
This option bit determines if a reset is generated when entering halt mode while the
watchdog is active.
0: No reset generation when entering halt mode
1: Reset generation when entering halt mode
6
WDG SW
5:1
-
0
Hardware or software watchdog
This option bit selects the watchdog type
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Reserved, must be kept at default value
FMP_R
Flash memory read-out protection
Read-out protection, when selected, provides a protection against program
memory content extraction and against write access to Flash memory.
Erasing the option bytes when the FMP_R option is selected causes the whole
user memory to be erased first, and the device can be reprogrammed. Refer to
Section 4.3.1: Read-out protection on page 28 and the ST7 Flash programming
reference manual for more details.
0: Read-out protection enabled
1: Read-out protection disabled
c
u
d
Table 101. Option byte 1 description
Bit
7
6
Function
PKG1
Pin package selection bit
This option bit selects the package (see Table 102)
Note: On the chip, each I/O port has 8 pads. Pads that are not bonded to external
pins are in input pull-up configuration after reset. The configuration of these pads
must be kept at reset state to avoid added current consumption.
RSTC
Reset clock cycle selection
This option bit selects the number of CPU cycles applied during the reset phase
and when exiting halt mode. For resonator oscillators, it is advised to select 4096
due to the long crystal stabilization time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
e
t
le
186/201
r
P
e
t
e
l
o
s
b
O
o
r
P
Bit name
)
s
(
ct
u
d
o
5:4
)
s
t(
OSCTYPE[1:0]
o
s
b
O
-
Oscillator type
These option bits select the ST7 main clock source type:
00: Clock source = Resonator oscillator
01: Reserved
10: Reserved
11: Clock source = External source
ST7232Axx-Auto
Device configuration and ordering information
Table 101. Option byte 1 description (continued)
Bit
Bit name
Function
Oscillator range
When the resonator oscillator is selected, these option bits select the resonator
oscillator current source corresponding to the frequency range of the used
resonator. Otherwise, these bits are used to select the normal frequency range.
OSCRANGE[2:0]
000: Typ. frequency range (LP) = >1~2MHz
001: Typ. frequency range (MP) = >2~4MHz)
010: Typ. frequency range (MS) = >4~8MHz)
011: Typ. frequency range (HS) = >8~16MHz)
3:1
0
PLL OFF
PLL activation
This option bit activates the PLL which allows multiplication by two of the main
input clock frequency. The PLL must not be used with the internal RC oscillator.
The PLL is guaranteed only with an input frequency between 2 and 4MHz.
0: PLL x2 enabled
1: PLL x2 disabled
Caution: The PLL can be enabled only if the ‘OSC RANGE’ (OPT3:1) bits are
configured to ‘MP - 2~4MHz’. Otherwise, the device functionality is not
guaranteed.
Caution 2: When the PLL is used with an external clock signal, the clock signal
must be available on the OSCIN pin before the reset signal is released.
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Table 102. Package selection (OPT7)
14.2.2
Version
Selected package
J
LQFP44
K
LQFP32
Flash ordering information
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PKG1
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The following Table 103 serves as a guide for ordering.
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Table 103. Flash user programmable device types
Order code(1)
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ST72F32AK1TARE
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ST72F32AK1TCRE
Package
Flash memory (Kbytes)
40°C +85°C
4K
40°C +125°C
LQFP32
ST72F32AK2TARE
40°C +85°C
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8K
ST72F32AK2TCRE
40°C +125°C
40°C +85°C
ST72F32AJ1TARE
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4K8
ST72F32AJ1TCRE
40°C +125°C
LQFP44
ST72F32AJ2TARE
ST72F32AJ2TCRE
Temperature range
40°C +85°C
8K
40°C +125°C
1. R = Tape and reel (left blank if tray)
187/201
Device configuration and ordering information
ST7232Axx-Auto
Figure 88. Flash commercial product code structure
DEVICE PINOUT PROG MEM PACKAGE TEMP RANGE R E
E = Lead-free (ECOPACK®)
Conditioning options
R = Tape and reel (left blank if tray)
A = -40 to +85°C
C = -40 to +125°C
T = Low profile quad flat pack
1 = 4 Kbytes
2 = 8 Kbytes
K = 32 pins
J = 44 pins
ST72F32A
14.3
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ROM device ordering information and transfer of customer
code
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Customer code is made up of the ROM/FASTROM contents and the list of the selected
options (if any). The ROM/FASTROM contents are to be sent with the S19 hexadecimal file
generated by the development tool. All unused bytes must be set to FFh. Complete the
appended ST72P32A/ST7232A (3.8 to 5.5V) microcontroller option list on page 191 to
communicate the selected options to STMicroelectronics.
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Refer to application note AN1635 for information on the counter listing returned by ST after
code has been transferred.
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Table 104: FASTROM factory coded device types on page 189 and Table 105: ROM factory
coded device types on page 190 serve as guides for ordering. The STMicroelectronics
Sales Organization will be pleased to provide detailed information on contractual points.
Caution:
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The readout protection binary value is inverted between ROM and Flash products. The
option byte checksum differs between ROM and Flash.
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ST7232Axx-Auto
Device configuration and ordering information
Table 104. FASTROM factory coded device types
Order code(1)
Package
Flash memory (Kbytes)
Temperature range
ST72P32A(K1)TAxxxRE
40°C +85°C
4K
ST72P32A(K1)TCxxxRE
40°C +125°C
LQFP32
ST72P32A(K2)TAxxxRE
40°C +85°C
8K
ST72P32A(K2)TCxxxRE
40°C +125°C
40°C +85°C
ST72P32A(J1)TAxxxRE
4K
ST72P32A(J1)TCxxxRE
40°C +125°C
LQFP44
ST72P32A(J2)TAxxxRE
40°C +85°C
8K
ST72P32A(J2)TCxxxRE
40°C +125°C
1. The two characters in parentheses which represent the pinout and program memory size are for reference
only and are not visible in the final commercial product order code.
‘xxx’ represents the code name defined by STMicroelectronics: It denotes the ROM code, pinout and
program memory size.
R = Tape and Reel (left blank if Tray)
Figure 89. FASTROM commercial product code structure
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DEVICE PACKAGE TEMP RANGE xxx R E
E = Lead-free (ECOPACK®)
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Conditioning options:
R = Tape and reel (left blank if tray)
Code name (defined by STMicroelectronics)
(denotes ROM code, pinout and program memory size)
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A = -40 to +85°C
B = -40 to +105°C
C = -40 to +125°C
T = Low profile quad flat pack
(s)
ST72P32A
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Device configuration and ordering information
ST7232Axx-Auto
Table 105. ROM factory coded device types
Order code(1)
Package
Flash memory (Kbytes)
Temperature range
ST7232A(K1)TA/xxxRE
40°C +85°C
4K
ST7232A(K1)TC/xxxRE
40°C +125°C
LQFP32
ST7232A(K2)TA/xxxRE
40°C +85°C
8K
ST7232A(K2)TC/xxxRE
40°C +125°C
40°C +85°C
ST7232A(J1)TA/xxxRE
4K
ST7232A(J1)TC/xxxRE
40°C +125°C
LQFP44
ST7232A(J2)TA/xxxRE
40°C +85°C
8K
ST7232A(J2)TC/xxxRE
40°C +125°C
1. The two characters in parentheses which represent the pinout and program memory size are for reference
only and are not visible in the final commercial product order code.
‘xxx’ represents the code name defined by STMicroelectronics: It denotes the ROM code, pinout and
program memory size.
R = Tape and Reel (left blank if Tray)
Figure 90. ROM commercial product code structure
DEVICE PACKAGE TEMP RANGE
/
xxx
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E = Lead-free (ECOPACK®)
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Conditioning options:
R = Tape and reel (left blank if tray)
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Code name (defined by STMicroelectronics)
(denotes ROM code, pinout and program memory size)
A = -40 to +85°C
B = -40 to +105°C
C = -40 to +125°C
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T = Low profile quad flat pack
ST7232A
ST7232Axx-Auto
Device configuration and ordering information
ST72P32A/ST7232A (3.8 to 5.5V) microcontroller option list
(Last update: September 2007)
Customer:
Address:
.....................................................................
.....................................................................
.....................................................................
Contact:
.....................................................................
Phone No: .....................................................................
Reference/ROM or FASTROM code: ...............................
The FASTROM/ROM code name is assigned by STMicroelectronics.
FASTROM/ROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
---------------------------------------------------------------------------------------------------------------------------------------------ROM
4K
8K
---------------------------------------------------------------------------------------------------------------------------------------------LQFP32:
[ ] ST7232A(K1)T
[ ] ST7232A(K2)T
LQFP44:
[ ] ST7232A(J1)T
[ ] ST7232A(J2)T
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------FASTROM
4K
8K
---------------------------------------------------------------------------------------------------------------------------------------------LQFP32:
[ ] ST72P32A(K1)T
[ ] ST72P32A(K2)T
LQFP44:
[ ] ST72P32A(J1)T
[ ] ST72P32A(J2)T
---------------------------------------------------------------------------------------------------------------------------------------------Conditioning (check only one option):
LQFP packaged product
[ ] Tape and reel
[ ] Tray
Temperature range:
[ ] B (-40°C to +105°C)
[ ] A (-40°C to +85°C)
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[ ] C (-40°C to +125°C)
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Special marking:
[ ] No
[ ] Yes ".........................." (LQFP32 7 char., other pkg. 10 char. max)
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Clock source selection:
[ ] Resonator
[ ] External clock(1)
[ ] Disabled
Reset delay:
[ ] 256 cycles
Watchdog selection:
[ ] Software activation
Watchdog reset on halt:
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Date
Signature
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[ ] Reset
[ ] Disabled
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PLL(1)(2):
Readout protection(3):
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] Enabled
[ ] 4096 cycles
[ ] Hardware activation
[ ] No reset
[ ] Enabled
............................
.............................
1. PLL not supported with external clock source
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2. The PLL can be enabled only if the resonator is configured to ‘Medium power: 2~4MHz’
3. The readout protection binary value is inverted between ROM and Flash products. The option byte
checksum differs between ROM and Flash.
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Device configuration and ordering information
14.4
Development tools
14.4.1
Introduction
ST7232Axx-Auto
Development tools for the ST7 microcontrollers include a complete range of hardware
systems and software tools from STMicroelectronics and third-party tool suppliers. The
range of tools includes solutions to help you evaluate microcontroller peripherals, develop
and debug your application, and program your microcontrollers.
14.4.2
Evaluation tools and starter kits
ST offers complete, affordable starter kits and full-featured evaluation boards that allow you
to evaluate microcontroller features and quickly start developing ST7 applications. Starter
kits are complete, affordable hardware/software tool packages that include features and
samples to help you quickly start developing your application. ST evaluation boards are
open-design, embedded systems, which are developed and documented to serve as
references for your application design. They include sample application software to help you
demonstrate, learn about and implement your ST7’s features.
14.4.3
Development and debugging tools
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Application development for ST7 is supported by fully optimizing C compilers and the ST7
assembler-linker toolchain, which are all seamlessly integrated in the ST7 integrated
development environments in order to facilitate the debugging and fine-tuning of your
application. The cosmic C compiler is available in a free version that outputs up to 16 Kbytes
of code.
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The range of hardware tools includes cost effective ST7-DVP3 series emulators. These
tools are supported by the ST7 Toolset from STMicroelectronics, which includes the STVD7
integrated development environment (IDE) with high-level language debugger, editor,
project manager and integrated programming interface.
14.4.4
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Programming tools
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During the development cycle, the ST7-DVP3 and ST7-EMU3 series emulators and the
RLink provide in-circuit programming capability for programming the Flash microcontroller
on your application board.
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ST also provides dedicated a low-cost dedicated in-circuit programmer, the ST7-STICK, as
well as ST7 socket boards which provide all the sockets required for programming any of the
devices in a specific ST7 subfamily on a platform that can be used with any tool with incircuit programming capability for ST7.
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For production programming of ST7 devices, ST’s third-party tool partners also provide a
complete range of gang and automated programming solutions, which are ready to integrate
into your production environment.
For additional ordering codes for spare parts, accessories and tools available for the ST7
(including from third party manufacturers), refer to the online product selector at
www.st.com/mcu.
ST7232Axx-Auto
Device configuration and ordering information
Table 106. STMicroelectronics development tools
Emulation
Supported
products
Programming
ST7 DVP3 series
Emulator
Connection kit
ST7232AJ,
ST72F32AJ
ST7MDT20DVP3
ST7MDT20T44/DVP
ST7232AK,
ST72F32AK
ST7MDT20DVP3
ST7MDT20T32/DVP
ST7 EMU3 series
Emulator
Active probe
and TEB
ST7MDT20
J-EMU3
ST7MDT20
J-TEB
ICC socket
board
ST7SB20
J/xx(1)
1. Add suffix /EU, /UK, /US for the power supply of your region.
14.4.5
Socket and emulator adapter information
For information on the type of socket that is supplied with the emulator, refer to the
suggested list of sockets in Table 107.
Note:
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Before designing the board layout, it is recommended to check the overall dimensions of the
socket as they may be greater than the dimensions of the device.
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For footprint and other mechanical information about these sockets and adapters, refer to
the manufacturer’s datasheet (www.ironwoodelectronics.com for LQFP32 7 x 7).
Table 107. Suggested list of socket types
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LQFP32 7 X 7
IRONWOOD SF-QFE32SA-L-01
LQFP44 10 X10
YAMAICHI IC149-044-*52-*5
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14.5
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Socket
(supplied with ST7MDT20J-EMU3)
Device
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Emulator adapter
(supplied with ST7MDT20J-EMU3)
IRONWOOD SK-UGA06/32A-01
YAMAICHI ICP-044-5
ST7 application notes
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For all revelant application notes, refer to www.st.com.
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Known limitations
ST7232Axx-Auto
15
Known limitations
15.1
All Flash and ROM devices
15.1.1
Safe connection of OSC1/OSC2 pins
The OSC1 and/or OSC2 pins must not be left unconnected otherwise the ST7 main
oscillator may start and, in this configuration, could generate an fOSC clock frequency in
excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state.
Refer to Section 6.4: Multi-oscillator (MO) on page 37.
15.1.2
External interrupt missed
To avoid any risk of generating a parasitic interrupt, the edge detector is automatically
disabled for one clock cycle during an access to either DDR and OR. Any input signal edge
during this period is not detected and does not generate an interrupt.
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This case can typically occur if the application refreshes the port configuration registers at
intervals during runtime.
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Workaround
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The workaround is based on software checking the level on the interrupt pin before and after
writing to the PxOR or PxDDR registers. If there is a level change (depending on the
sensitivity programmed for this pin) the interrupt routine is invoked using the call instruction
with three extra PUSH instructions before executing the interrupt routine (this is to make the
call compatible with the IRET instruction at the end of the interrupt service routine).
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But detection of the level change does not make sure that edge occurs during the critical
one cycle duration and the interrupt has been missed. This may lead to occurrence of same
interrupt twice (one hardware and another with software call).
To avoid this, a semaphore is set to ‘1’ before checking the level change. The semaphore is
changed to level '0' inside the interrupt routine. When a level change is detected, the
semaphore status is checked and if it is ‘1’ this means that the last interrupt has been
missed. In this case, the interrupt routine is invoked with the call instruction.
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There is another possible case that is, if writing to PxOR or PxDDR is done with global
interrupts disabled (interrupt mask bit set). In this case, the semaphore is changed to ‘1’
when the level change is detected. Detecting a missed interrupt is done after the global
interrupts are enabled (interrupt mask bit reset) and by checking the status of the
semaphore. If it is ‘1’ this means that the last interrupt was missed and the interrupt routine
is invoked with the call instruction.
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To implement the workaround, the following software sequence is to be followed for writing
into the PxOR/PxDDR registers. The example is for Port PF1 with falling edge interrupt
sensitivity. The software sequence is given for both cases (global interrupt
disabled/enabled).
ST7232Axx-Auto
Known limitations
Case 1: Writing to PxOR or PxDDR with global interrupts enabled:
LD A,#01
LD sema,A; set the semaphore to '1'
LD A,PFDR
AND A,#02
LD X,A; store the level before writing to PxOR/PxDDR
LD A,#$90
LD PFDDR,A ; Write to PFDDR
LD A,#$ff
LD PFOR,A ; Write to PFOR
LD A,PFDR
AND A,#02
LD Y,A; store the level after writing to PxOR/PxDDR
LD A,X; check for falling edge
cp A,#02
jrne OUT
TNZ Y
jrne OUT
LD A,sema ; check the semaphore status if edge is detected
CP A,#01
jrne OUT
call call_routine ; call the interrupt routine
OUT:LD A,#00
LD sema,A
.call_routine ; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt ; entry to interrupt routine
LD A,#00
LD sema,A
IRET
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Case 2: Writing to PxOR or PxDDR with global interrupts disabled:
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SIM ; set the interrupt mask
LD A,PFDR
AND A,#$02
LD X,A ; store the level before writing to PxOR/PxDDR
LD A,#$90
LD PFDDR,A ; Write into PFDDR
LD A,#$ff
LD PFOR,A ; Write to PFOR
LD A,PFDR
AND A,#$02
LD Y,A ; store the level after writing to PxOR/PxDDR
LD A,X ; check for falling edge
cp A,#$02
jrne OUT
TNZ Y
jrne OUT
LD A,#$01
LD sema,A ; set the semaphore to '1' if edge is detected
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Known limitations
ST7232Axx-Auto
RIM ; reset the interrupt mask
LD A,sema ; check the semaphore status
CP A,#$01
jrne OUT
call call_routine ; call the interrupt routine
RIM
OUT:RIM
JP while_loop
.call_routine ; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt ; entry to interrupt routine
LD A,#$00
LD sema,A
IRET
15.1.3
Unexpected reset fetch
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If an interrupt request occurs while a ‘POP CC’ instruction is executed, the interrupt
controller does not recognise the source of the interrupt and, by default, passes the reset
vector address to the CPU.
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Workaround
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To solve this issue, a ‘POP CC’ instruction must always be preceded by a ‘SIM’ instruction.
15.1.4
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Clearing active interrupts outside interrupt routine
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When an active interrupt request occurs at the same time as the related flag is being
cleared, an unwanted reset may occur.
Note:
Clearing the related interrupt mask does not generate an unwanted reset.
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Concurrent interrupt context
The symptom does not occur when the interrupts are handled normally, i.e. when:
●
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The interrupt flag is cleared within its own interrupt routine
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●
●
The interrupt flag is cleared within any interrupt routine
The interrupt flag is cleared in any part of the code while this interrupt is disabled
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If these conditions are not met, the symptom can be avoided by implementing the following
sequence:
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Perform SIM and RIM operation before and after resetting an active interrupt request.
Example:
SIM
Reset interrupt flag
RIM
196/201
ST7232Axx-Auto
Known limitations
Nested interrupt context
The symptom does not occur when the interrupts are handled normally, i.e. when:
●
The interrupt flag is cleared within its own interrupt routine
●
The interrupt flag is cleared within any interrupt routine with higher or identical priority
leve
●
The interrupt flag is cleared in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can be avoided by implementing the following
sequence:
PUSH CC
SIM
Reset interrupt flag
POP CC
15.1.5
16-bit timer PWM mode
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In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R
register (OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on
the OLVL1 and OLVL2 settings.
15.1.6
TIMD set simultaneously with OC interrupt
Description
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If the 16-bit timer is disabled at the same time as the output compare event occurs, then the
output compare flag gets locked and cannot be cleared before the timer is enabled again.
Impact on the application
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If output compare interrupt is enabled, then the output compare flag cannot be cleared in the
timer interrupt routine. Consequently the interrupt service routine is called repeatedly and
the application gets stuck which causes the watchdog reset if enabled by the application.
Workaround
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Disable the timer interrupt before disabling the timer. While enabling, first enable the timer,
then the timer interrupts.
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Perform the following to disable the timer:
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●
●
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TACR1 or TBCR1 = 0x00h; // Disable the compare interrupt
TACSR | or TBCSR | = 0x40; // Disable the timer
Perform the following to enable the timer again:
●
TACSR & or TBCSR & = ~0x40; // Enable the timer
●
TACR1 or TBCR1 = 0x40; // Enable the compare interrup
197/201
Known limitations
15.1.7
ST7232Axx-Auto
SCI wrong break duration
Description
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.
In some cases, the break character may have a longer duration than expected:
- 20 bits instead of 10 bits if M = 0
- 22 bits instead of 11 bits if M = 1.
In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.
This may lead to generate one break more than expected.
Occurrence
The occurrence of the problem is random and proportional to the baudrate. With a transmit
frequency of 19200 baud (fCPU = 8MHz and SCIBRR = 0xC9), the wrong break duration
occurrence is around 1%.
Workaround
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If this wrong duration is not compliant with the communication protocol in the application,
software can request that an idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.
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The exact sequence is:
15.1.8
●
Disable interrupts
●
Reset and set TE (IDLE request)
●
Set and reset SBK (break request)
●
Re-enable interrupts
39-pulse ICC entry mode
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For Flash devices, ICC mode entry using ST7 application clock (39 pulses) is not supported.
External clock mode must be used (36 pulses). Refer to the ST7 Flash Programming
Reference Manual.
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ST7232Axx-Auto
Known limitations
15.2
ROM devices only
15.2.1
I/O port A and F configuration
When using an external quartz crystal or ceramic resonator, a few fOSC2 clock periods may
be lost when the signal pattern in Table 108 occurs . This is because this pattern causes the
device to enter test mode and return to user mode after a few clock periods. User program
execution and I/O status are not changed, only a few clock cycles are lost.
This happens with either one of the following configurations (see also Table 108):
PA3 = 0, PF4 = 1, PF1 = 0 while PLL option is disabled and PF0 is toggling.
PA3 = 0, PF4 = 1, PF1 = 0, PF0 = 1 while PLL option is enabled.
Table 108. Port A and F configuration
PLL
PA3
PF4
PF1
PF0
OFF
0
1
0
Toggling
ON
0
1
0
1
Clock disturbance
Max. 2 clock cycles lost at each rising or
falling edge of PF0
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Max. 1 clock cycle lost out of every 16
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As a consequence, for cycle-accurate operations, these configurations are prohibited in
either input or output mode.
Workaround
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To avoid this occurring, it is recommended to connect one of these pins to GND (PF4 or
PF0) or VDD (PA3 or PF1).
15.2.2
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External clock source with PLL
PLL is not supported with external clock source.
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Revision history
16
ST7232Axx-Auto
Revision history
Table 109. Document revision history
Date
Revision
28-Jan-2008
1
Changes
Initial release
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ST7232Axx-Auto
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
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