STMICROELECTRONICS ST7LITE49M

ST7LITE49M
8-bit MCU with single voltage Flash memory
data EEPROM, ADC, 8/12-bit timers, and I²C interface
Features
■
■
■
Memories
– 4 Kbytes single voltage extended Flash
(XFlash) Program memory with
Read-Out Protection
In-Circuit Programming and In-Application
programming (ICP and IAP)
Endurance: 10K write/erase cycles
guaranteed
Data retention: 20 years at 55 °C
– 384 bytes RAM
– 128 bytes data EEPROM with Read-Out
Protection.
300K write/erase cycles guaranteed,
data retention: 20 years at 55 °C.
Clock, Reset and Supply Management
– 3-level low voltage supervisor (LVD) for
main supply and an auxiliary voltage
detector (AVD) for safe power-on/off
– Clock sources: Internal trimmable 8 MHz
RC oscillator, auto wake-up internal low
power - low frequency oscillator,
crystal/ceramic resonator or external clock
– Five power saving modes: Halt, Active-Halt,
Auto Wake-up from Halt, Wait and Slow
I/O Ports
– Up to 24 multifunctional bidirectional I/Os
– 8 high sink outputs
Table 1.
LQFP32
(7x7mm)
■
5 timers
– Configurable watchdog timer
– Dual 8-bit Lite timers with prescaler,
1 real time base and 1 input capture
– Dual 12-bit Auto-reload timers with 4 PWM
outputs, input capture, output compare,
dead-time generation and enhanced one
pulse mode functions
■
Communication interface:
– I²C multimaster interface
■
A/D converter: 10 input channels
■
Interrupt management
– 13 interrupt vectors plus TRAP and RESET
■
Instruction set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode
detection
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
■
Development tools
– Full HW/SW development package
– DM (Debug Module)
Device summary
Features
July 2007
SDIP32
ST7LITE49M
Program memory - bytes
4K
RAM (stack) - bytes
384 (128)
Data EEPROM - bytes
128
Operating supply
2.4 to 5.5 V
CPU frequency
Up to 8 MHz
Operating temperature
-40 to +125 °C
Packages
LQFP32, SDIP32
Rev 2
1/188
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1
Contents
ST7LITE49M
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Register and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
Flash programmable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3
Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
In-Circuit Programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.2
In Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5
Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5.1
Read-Out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5.2
Flash Write/Erase Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.6
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.7
Description of the Flash Control/Status register (FCSR) . . . . . . . . . . . . . 24
Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3
Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4
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4.3.1
5.3.1
Read operation (E2LAT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.2
Write operation (E2LAT=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.1
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.2
Active-Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.3
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5
Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.6
Data EEPROM Read-Out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.7
EEPROM Control/Status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . . 28
ST7LITE49M
6
7
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.1
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.2
Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.3
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.4
Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.5
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1
7.2
7.3
7.4
7.5
8
Contents
RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1.1
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1.2
Auto Wake Up RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.1
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.2
Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.3
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3.2
Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.3.3
External Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.3.4
Internal Low Voltage Detector (LVD) Reset . . . . . . . . . . . . . . . . . . . . . . 40
7.3.5
Internal Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.4.1
Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.4.2
Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.4.3
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.5.1
Main Clock Control/Status register (MCCSR) . . . . . . . . . . . . . . . . . . . . 45
7.5.2
RC Control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.5.3
AVD Threshold Selection register (AVDTHCR) . . . . . . . . . . . . . . . . . . . 46
7.5.4
CLOCK Controller Control/Status register (CKCNTCSR) . . . . . . . . . . . 47
7.5.5
System Integrity (SI) Control/Status register (SICSR) . . . . . . . . . . . . . . 47
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Contents
9
ST7LITE49M
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.2
Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4/188
Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.2.2
Interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.3
Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.4
Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.5
Description of interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.5.1
CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.5.2
Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 55
8.5.3
External Interrupt Control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . 58
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.3
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.4
Active-Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.5
10
8.2.1
9.4.1
Active-Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.4.2
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Auto Wake Up from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.5.1
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.5.2
AWUFH Control/Status register (AWUCSR) . . . . . . . . . . . . . . . . . . . . . 68
9.5.3
AWUFH Prescaler register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2.1
Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2.2
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.2.3
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.2.4
Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.3
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.4
Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.5
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.7
Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ST7LITE49M
11
Contents
10.7.1
Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.7.2
Other ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
11.1
11.2
11.3
11.4
Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
11.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
11.1.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
11.1.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
11.1.4
Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.1.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.1.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Dual 12-bit autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.2.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.2.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.2.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.2.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.2.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Lite timer 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.3.2
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.3.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.3.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.3.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.3.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.4.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.4.4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.5
11.4.5
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
11.4.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
11.4.7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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ST7LITE49M
11.5.2
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.5.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.5.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
11.5.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
11.5.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.1
12.2
ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.1.1
Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.1.2
Immediate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.1.3
Direct modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.1.4
Indexed modes (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . 135
12.1.5
Indirect modes (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.1.6
Indirect Indexed modes (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.1.7
Relative modes (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.2.1
13
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
13.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
13.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
13.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
13.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
13.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
13.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
13.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
13.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
13.4
13.5
6/188
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
13.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
13.3.2
Operating conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . 145
13.3.3
Auxiliary Voltage Detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . 146
13.3.4
Voltage drop between AVD flag setting and LVD reset generation . . . 146
13.3.5
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
13.4.1
Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
13.4.2
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 153
ST7LITE49M
Contents
13.5.1
13.6
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
13.6.1
Auto Wake Up from Halt oscillator (AWU) . . . . . . . . . . . . . . . . . . . . . . 155
13.6.2
Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 155
13.7
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
13.8
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
13.9
13.8.1
Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 157
13.8.2
Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
13.8.3
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 158
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
13.9.1
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
13.9.2
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
13.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
13.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
13.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
14
Device configuration and ordering information . . . . . . . . . . . . . . . . . 175
14.1
16
14.1.1
Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14.1.2
Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
14.2
Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
14.3
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
14.4
15
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14.3.1
Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
14.3.2
Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
14.3.3
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
14.3.4
Order codes for development and programming tools . . . . . . . . . . . . . 179
14.3.5
Order codes for ST7LITE49M development tools . . . . . . . . . . . . . . . . 179
ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
15.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
15.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7/188
List of tables
ST7LITE49M
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
8/188
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Interrupt software priority truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CPU clock delay during Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Internal RC Prescaler Selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Reset source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Clock register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Setting the interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interrupt vector vs ISPRx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Enabling/disabling Active-Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
AWU register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DR Value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PA5:0, PB7:0, PC7:4 and PC2:0 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PA7:6 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PC3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
I/O port register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Watchdog timer register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Effect of low power modes on autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Effect of low power modes on Lite timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Lite Timer register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7-bit slave receiver:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7-bit slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7-bit master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7-bit master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10-bit slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10-bit slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10-bit master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10-bit master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
ST7LITE49M
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
List of tables
Effect of low power modes on the I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Configuration of I2C delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
I2C register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Effect of low power modes on the A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Channel selection using CH[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Configuring the ADC clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
ADC register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Instructions supporting Inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Instructions supporting Inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . 135
Instructions supporting Direct, Indexed, Indirect and Indirect Indexed addressing modes136
Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Operating characteristics with AVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Voltage drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Internal RC oscillator characteristics (3.3 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SCL frequency (multimaster I2C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
AWU from Halt characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RAM and hardware registers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Flash program memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Data EEPROM memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
ADC accuracy with VDD = 3.3 to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
ADC accuracy with VDD = 2.7 to 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
ADC accuracy with VDD = 2.4 to 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Configuration of sector size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Supported part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
9/188
List of tables
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
10/188
ST7LITE49M
Development tool order codes for the ST7LITE49M family . . . . . . . . . . . . . . . . . . . . . . . 179
ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
32-pin plastic dual in-line package, shrink 400mil width, mechanical data . . . . . . . . . . . . 184
32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . . . . . . . . 185
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
ST7LITE49M
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
32-pin SDIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
32-pin LQFP 7x7 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Typical ICC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
EEPROM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data EEPROM write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
RESET sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
RESET sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Low Voltage Detector vs Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Active-Halt timing overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Active-Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Single Timer mode (ENCNTR2=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Dual Timer mode (ENCNTR2=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PWM polarity inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
PWM signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Dead time generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Block diagram of output compare mode (single timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Block diagram of Input Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Input Capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Long range Input Capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Long range Input Capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11/188
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
Figure 98.
Figure 99.
Figure 100.
12/188
ST7LITE49M
Block diagram of One Pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
One Pulse mode and PWM timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Dynamic DCR2/3 update in One Pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Force Overflow timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Lite timer 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Input Capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
fCPU maximum operating frequency versus VDD supply voltage . . . . . . . . . . . . . . . . . . 145
Frequency vs voltage at four different ambient temperatures (RC at 5 V) . . . . . . . . . . . . 148
Frequency vs voltage at four different ambient temperatures (RC at 3.3 V). . . . . . . . . . . 148
Accuracy in % vs voltage at 4 different ambient temperatures (RC at 5 V) . . . . . . . . . . . 149
Accuracy in % vs voltage at 4 different ambient temperatures (RC at 3.3V) . . . . . . . . . . 149
Typical IDD in Run vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Typical IDD in WFI vs. fCPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Typical IDD in Slow mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Typical IDD in Slow-Wait mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Typical IDD vs. temperature at VDD = 5V and fCPU = 8 MHz . . . . . . . . . . . . . . . . . . . . . 152
Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Rpu resistance versus voltage at four different temperatures . . . . . . . . . . . . . . . . . . . . . . 161
Ipu current versus voltage at four different temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 161
Typical VOL at VDD = 2.4 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Typical VOL at VDD = 3 V (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Typical VOL at VDD = 5 V (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Typical VOL at VDD = 2.4 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Typical VOL at VDD = 3 V (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Typical VOL at VDD = 5 V (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Typical VOL vs. VDD at IIO = 2 mA (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Typical VOL vs. VDD at IIO = 4 mA (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Typical VOL vs VDD at IIO = 2 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Typical VOL vs VDD at IO = 8 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Typical VOL vs VDD at IIO = 12 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Typical VDD-VOH vs. IIO at VDD = 2.4 V (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Typical VDD-VOH vs. IIO at VDD = 3 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Typical VDD-VOH vs. IIO at VDD = 5 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Typical VDD-VOH vs. IIO at VDD = 2.4 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Typical VDD-VOH vs. IIO at VDD = 3 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Typical VDD-VOH vs. IIO at VDD = 5 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Typical VDD-VOH vs. VDD at IIO = 2 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Typical VDD-VOH vs. VDD at IIO = 4 mA (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
RESET pin protection when LVD is enabled3)4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
32-pin plastic dual in-line package, shrink 400mil width, package outline . . . . . . . . . . . . 184
ST7LITE49M
List of figures
Figure 101. 32-pin low profile quad flat package (7x7), package outline . . . . . . . . . . . . . . . . . . . . . . . 185
13/188
Description
1
ST7LITE49M
Description
The ST7LITE49M is a member of the ST7 microcontroller family. All ST7 devices are based
on a common industry-standard 8-bit core, featuring an enhanced instruction set.
The ST7LITE49M features Flash memory with byte-by-byte In-Circuit Programming (ICP)
and In-Application Programming (IAP) capability.
Under software control, the ST7LITE49M device can be placed in Wait, Slow, or Halt mode,
reducing power consumption when the application is in idle or standby state.
The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
The ST7LITE49M features an on-chip Debug Module (DM) to support In-Circuit Debugging
(ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference
Manual.
Figure 1.
General block diagram
CLKIN
OSC1
OSC2
/2
Ext.
OSC
1MHz
to
16MHz
Int.
8 MHz
RC OSC
Int.
32 kHz
RC OSC
/2
8-bit
dual Lite timer
VDD
VSS
Power
Supply
RESET
Control
8-bit core
ALU
Flash
Program
Memory
(4K bytes)
RAM
(384 bytes)
Data EEPROM
(128 bytes)
ADDRESS AND DATA BUS
LVD, AVD
14/188
12-bit
Auto-reload
dual timer
Internal
clock
Port A
PA7:0
(8 bits)
Port B
PB7:0
(8 bits)
Port C
PC7:0
(8 bits)
10-bit ADC
I2 C
Watchdog
Debug module
ST7LITE49M
Pin description
Figure 2.
32-pin SDIP package pinout
BREAK/PC7
PA0(HS)
ATIC/PA1(HS)
ATPWM0/PA2(HS)
ATPWM1/PA3(HS)
ATPWM2/MCO/PA4(HS)
ATPWM3/PA5(HS)
I2CDATA/PA6(HS)
I2CCLK/PA7(HS)
RESET
NC
VDD
VSS
OSC1/CLKIN
OSC2
VSSA
1 ei2
2
32
ei2
3
30
4
5
6
31
29
28
ei0
ei2
27
7
26
8
25
9
24
10
11
23
ei1
22
12
21
13
20
14
19
15
18
16
17
PC6
PC5
PC4/LTIC
PC3/ICCCLK
PC2/ICCDATA
PC1/AIN9
PC0/AIN8
PB7/AIN7
PB6/AIN6
PB5/AIN5
PB4/AIN4
PB3/AIN3
PB2/AIN2
PB1/AIN1/CKIN
PB0/AIN0
VDDA
(HS) 20mA high sink capability
eix associated external interrupt vector
32-pin LQFP 7x7 package pinout
PA2(HS)/ATPWM
PA1(HS)/ATIC
PA0(HS)
PC7/BREAK
PC6
PC5
PC4/LTIC
PC3/ICCCLK
Figure 3.
ATPWM1/PA3(HS)
ATPWM2/MCO/PA4(HS)
ATPWM3/PA5(HS)
I2CDATA/PA6(HS)
I2CCLK/PA7(HS)
RESET
NC
VDD
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
ei2
ei0
22
21
20
ei1 19
18
17
9 10 11 12 13 14 15 16
VSS
OSC1/CLKIN
OSC2
VSSA
VDDA
AIN0/PB0
CKIN/AIN1/PB1
AIN2/PB2
2
Pin description
PC2/ICCDATA
PC1/AIN9
PC0/AIN8
PB7/AIN7
PB6/AIN6
PB5/AIN5
PB4/AIN4
PB3/AIN3
(HS) 20mA high sink capability
eix associated external interrupt vector
15/188
Pin description
ST7LITE49M
Legend / Abbreviations for Table 2:
Type: I = input, O = output, S = supply
In/Output level:CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
●
Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
●
Output: OD = open drain, PP = push-pull
The RESET configuration of each pin is shown in bold which is valid as long as the device is
in reset state.
Device pin description
Input
Output
1
5
PA3(HS)/ATPWM1
I/O
CT
HS
x
2
6
PA4(HS)/
ATPWM2/MCO
I/O
CT
HS
x
3
7
PA5 (HS)ATPWM3
I/O
CT
HS
x
4
8
PA6(HS)/
I2CDATA
I/O
CT
HS
x
I/O
CT
HS
ei0
Output
ana
float
Input
Main
function
(after reset)
Alternate
function
ATPWM1
PP
Pin name
OD(1)
SDIP32
Port/control
LQFP32
Type
Level
int
Pin
number
wpu
Table 2.
x
x
Port A3 (HS)
x
x
Port A4 (HS) ATPWM2/MCO
x
x
Port A5 (HS)
ATPWM3
T
Port A6 (HS)
I2CDATA
T
Port A7 (HS)
I2CCLK
ei0
5
9
PA7(HS)/I2CCLK
6
10
RESET
12
VDD(2)
S
Digital Supply Voltage
9
13
VSS(2)
S
Digital Ground Voltage
10
14
OSC1
I
Resonator oscillator inverter
input or External clock input
11
15
OSC2
O
Resonator oscillator output
16
VSSA(2)
S
Analog Ground Voltage
17
VDDA(2)
S
Analog Supply Voltage
8
12
13
16/188
x
x
x
Reset
ST7LITE49M
Table 2.
Pin description
Device pin description
Pin
number
Port/control
OD(1)
PP
18
PB0/AIN0
I/O
CT
x
x
x
x
Port B0
AIN0
15
19
PB1/AIN1/CLKIN
I/O
CT
x
x
x
x
Port B1
AIN1/External
clock source
16
20
PB2/AIN2
I/O
CT
x
x
x
x
Port B2
AIN2
17
21
PB3/AIN3
I/O
CT
x
x
x
x
Port B3
AIN3
18
22
PB4/AIN4
I/O
CT
x
x
x
x
Port B4
AIN4
19
23
PB5/AIN5
I/O
CT
x
x
x
x
Port B5
AIN5
20
24
PB6/AIN6
I/O
CT
x
x
x
x
Port B6
AIN6
21
25
PB7/AIN7
I/O
CT
x
x
x
x
Port B7
AIN7
22
26
PC0/AIN8
I/O
CT
x
x
x
x
Port C0
AIN8
23
27
PC1/AIN9
I/O
CT
x
x
x
x
Port C1
AIN9
24
28
PC2/ICCDATA
I/O
CT
x
x
x
Port C2
ICCDATA
25
29
PC3/ICCCLK
I/O
CT
x
x
x
Port C3
ICCCLK
26
30
PC4/LTIC
I/O
CT
x
x
x
Port C4
LTIC
x
x
Port C5
x
x
Port C6
int
wpu
Input
float
Output
14
Input
Pin name
ana
Alternate
function
SDIP32
Main
function
(after reset)
LQFP32
Type
Level
ei1
ei2
x
Output
ei2
27
31
PC5
I/O
CT
x
28
32
PC6
I/O
CT
x
x
x
x
x
x
x
x
Port A1 (HS)
ATIC
x
x
Port A2 (HS)
ATPWM0
ei2
29
1
PC7/BREAK
I/O
CT
30
2
PA0 (HS)
I/O
CT
HS
x
31
3
PA1 (HS)/ATIC
I/O
CT
HS
x
32
4
PA2 (HS)/ATPWM0
I/O
CT
HS
x
ei0
Port C7
BREAK
Port A0 (HS)
1. In the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to VDD are not
implemented).
2. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground.
17/188
Register and memory mapping
3
ST7LITE49M
Register and memory mapping
As shown in Figure 4, the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, 384 bytes of
RAM, 128 bytes of data EEPROM and 4 Kbytes of Flash program memory. The RAM space
includes up to 128 bytes for the stack from 180h to 1FFh.
The highest address bytes contain the user reset and interrupt vectors.
The Flash memory contains two sectors (see Figure 4) mapped in the upper part of the ST7
addressing space so the reset and interrupt vectors are located in Sector 0 (FFE0h-FFFFh).
The size of Flash Sector 0 and other device options are configurable by option bytes (refer
to Section 14.1 on page 175).
Caution:
Memory locations marked as “Reserved” must never be accessed. Accessing a reserved
area can have unpredictable effects on the device.
Figure 4.
0000h
007Fh
0080h
Memory map
HW registers
(seeTable 3)
RAM
(384 bytes)
0080h
00FFh
0100h
017Fh
0180h
01FFh
0200h
01FFh
Short Addressing
RAM (zero page)
RAM
128 bytes Stack
DEE0h
DEE1h
Reserved
0FFFh
1000h
DEE2h
DEE3h
Data EEPROM
(128 bytes)
107Fh
1080h
FFFFh
18/188
RCCRL0
RCCRH1
RCCRL1
see Section 7.1.1
Reserved
4K Flash
program memory
Flash Memory
(4K)
3 Kbytes
(SECTOR 1)
1 Kbyte
(SECTOR 0)
EFFFh
F000h
FFDFh
FFE0h
RCCRH0
Interrupt & Reset Vectors
(see Table 17)
F000h
FFFFh
ST7LITE49M
Table 3.
Register and memory mapping
Hardware register map(1)
Address
Block
Register label
Register name
Reset status
Remarks
0000h
0001h
0002h
Port A
PADR
PADDR
PAOR
Port A Data register
Port A Data Direction register
Port A Option register
00h
00h
00h
R/W
R/W
R/W
0003h
0004h
0005h
Port B
PBDR
PBDDR
PBOR
Port B Data register
Port B Data Direction register
Port B Option register
00h
00h
00h
R/W
R/W
R/W
0006h
0007h
0008h
Port C
PCDR
PCDDR
PCOR
Port C Data register
Port C Data Direction register
Port C Option register
00h
00h
08h
R/W
R/W
R/W
0009h to
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
Reserved area (3 bytes)
LITE
TIMER
LTCSR2
LTARR
LTCNTR
LTCSR1
LTICR
Lite Timer Control/Status register 2
Lite Timer Auto-reload register
Lite Timer Counter register
Lite Timer Control/Status register 1
Lite Timer Input Capture register
0Fh
00h
00h
0x00 0000b
xxh
R/W
R/W
Read Only
R/W
Read Only
AUTORELOAD
TIMER
ATCSR
CNTR1H
CNTR1L
ATR1H
ATR1L
PWMCR
PWM0CSR
PWM1CSR
PWM2CSR
PWM3CSR
DCR0H
DCR0L
DCR1H
DCR1L
DCR2H
DCR2L
DCR3H
DCR3L
ATICRH
ATICRL
ATCSR2
BREAKCR
ATR2H
ATR2L
DTGR
BREAKEN
Timer Control/Status register
Counter register 1 High
Counter register 1 Low
Auto-Reload register 1 High
Auto-Reload register 1 Low
PWM Output Control register
PWM 0 Control/Status register
PWM 1 Control/Status register
PWM 2 Control/Status register
PWM 3 Control/Status register
PWM 0 Duty Cycle register High
PWM 0 Duty Cycle register Low
PWM 1 Duty Cycle register High
PWM 1 Duty Cycle register Low
PWM 2 Duty Cycle register High
PWM 2 Duty Cycle register Low
PWM 3 Duty Cycle register High
PWM 3 Duty Cycle register Low
Input Capture register High
Input Capture register Low
Timer Control/Status register 2
Break Control register
Auto-Reload register 2 High
Auto-Reload register 2 Low
Dead Time Generation register
Break Enable register
0x00 0000b
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
03h
00h
00h
00h
00h
03h
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
FFh
FFh
FFh
FFh
00h
R/W
R/W
R/W
R/W
R/W
002Bh to
002Ch
002Dh
002Eh
002Fh
0030h
0031h
Reserved area (2 bytes)
ITC
ISPR0
ISPR1
ISPR2
ISPR3
EICR
Interrupt Software Priority register 0
Interrupt Software Priority register 1
Interrupt Software Priority register 2
Interrupt Software Priority register 3
External Interrupt Control register
19/188
Register and memory mapping
Table 3.
Address
ST7LITE49M
Hardware register map(1) (continued)
Block
Register label
0032h
Register name
Reset status
Remarks
Reserved area (1 byte)
0033h
WDG
WDGCR
Watchdog Control register
7Fh
R/W
0034h
FLASH
FCSR
Flash Control/Status register
00h
R/W
0035h
EEPROM
EECSR
Data EEPROM Control/Status register
00h
R/W
0036h
0037h
0038h
ADC
ADCCSR
ADCDRH
ADCDRL
A/D Control Status register
A/D Data register High
A/D Data Low / test register
00h
xxh
0xh
R/W
Read Only
R/W
0039h
Reserved area (1 byte)
003Ah
MCC
MCCSR
Main Clock Control/Status register
00h
R/W
003Bh
003Ch
Clock and
Reset
RCCR
SICSR
RC oscillator Control register
System Integrity Control/Status register
FFh
011x 0x00b
R/W
R/W
003Dh
AVD
AVDTHCR
AVD Threshold Selection register / RC
prescaler
00h
R/W
003Eh to
0047h
0048h
0049h
Reserved area (10 bytes)
AWU
AWUCSR
AWUPR
AWU Control/Status register
AWU Preload register
FFh
00h
R/W
R/W
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
DM(2)
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DMCR2
DM Control register
DM Status register
DM Breakpoint register 1 High
DM Breakpoint register 1 Low
DM Breakpoint register 2 High
DM Breakpoint register 2 Low
DM Control register 2
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0051h
Clock
Controller
CKCNTCSR
Clock Controller Status register
09h
R/W
00h
00h
00h
00h
00h
40h
00h
R/W
Read only
Read only
R/W
R/W
R/W
R/W
0052h to
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
Reserved area (18 bytes)
I2C
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
I2C Control register
I2C Status register 1
I2C Status register 2
2
I C Clock Control register
I2C Own Address register 1
I2C Own Address register 2
I2C Data register
1. Legend: x=undefined, R/W=read/write.
2. For a description of the Debug Module registers, see ICC protocol reference manual.
20/188
ST7LITE49M
Flash programmable memory
4
Flash programmable memory
4.1
Introduction
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be
electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in
parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using In-Circuit Programming or In-Application Programming.
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
4.3
Main features
●
ICP (In-Circuit Programming)
●
IAP (In-Application Programming)
●
ICT (In-Circuit Testing) for downloading and executing user application test patterns in
RAM
●
Sector 0 size configurable by option byte
●
Read-out and write protection
Programming modes
The ST7 can be programmed in three different ways:
4.3.1
●
Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte row
and data EEPROM (if present) can be programmed or erased.
●
In-Circuit Programming. In this mode, Flash sectors 0 and 1, option byte row and data
EEPROM (if present) can be programmed or erased without removing the device from
the application board.
●
In-Application Programming. In this mode, sector 1 and data EEPROM (if present) can
be programmed or erased without removing the device from the application board and
while the application is running.
In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on
a printed circuit board (PCB) to communicate with an external programming device
connected via cable. ICP is performed in three steps:
Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific
signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the
ST7 enters ICC mode, it fetches a specific Reset vector which points to the ST7 System
Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes
from the ICC interface.
●
Download ICP Driver code in RAM from the ICCDATA pin
●
Execute ICP Driver code in RAM to program the Flash memory
21/188
Flash programmable memory
ST7LITE49M
Depending on the ICP Driver code downloaded in RAM, Flash memory programming can
be fully customized (number of bytes to program, program locations, or selection of the
serial communication interface for downloading).
4.3.2
In Application Programming (IAP)
This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in
ICP mode).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored etc.)
IAP mode can be used to program any memory areas except Sector 0, which is Write/Erase
protected to allow recovery in case errors occur during the programming operation.
4.4
ICC interface
ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These
pins are:
●
RESET: device reset
●
VSS: device power supply ground
●
ICCCLK: ICC output serial clock pin
●
ICCDATA: ICC input serial data pin
●
OSC1: main clock input for external source
●
VDD: application board power supply (optional, see Note 3)
If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal
isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an
ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the
application. If they are used as inputs by the application, isolation such as a serial resistor
has to be implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
During the ICP session, the programming tool must control the RESET pin. This can lead to
conflicts between the programming tool and the application reset circuit if it drives more than
5mA at high level (push pull output or pull-up resistor<1 kΩ). A schottky diode can be used
to isolate the application RESET circuit in this case. When using a classical RC network with
R>1 kΩ or a reset management IC with open drain output and pull-up resistor>1 kΩ, no
additional components are needed. In all cases the user must ensure that no external reset
is generated by the application during the ICC session.
The use of pin 7 of the ICC connector depends on the Programming Tool architecture. This
pin must be connected when using most ST Programming Tools (it is used to monitor the
application power supply). Please refer to the Programming Tool manual.
Pin 9 has to be connected to the PB1/CLKIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is not programmed in the option byte. ST7
devices with multi-oscillator capability need to have OSC2 grounded in this case.
In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of
the selection in the option byte.
22/188
ST7LITE49M
During normal operation the ICCCLK pin must be internally or externally pulled- up (external
pull-up of 10 kΩ mandatory in noisy environment) to avoid entering ICC mode unexpectedly
during a reset. In the application, even if the pin is configured as output, any reset will put it
back in input pull-up.
Figure 5.
Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
OPTIONAL
(See Note 4)
9
7
5
3
1
10
8
6
4
2
APPLICATION BOARD
APPLICATION
RESET SOURCE
See Note 2
CL2
CL1
See Note 1 and Caution
APPLICATION
I/O
ICCDATA
RESET
ST7
ICCCLK
See Note 1
PB1/CLKIN
APPLICATION
POWER SUPPLY
VDD
Caution:
Flash programmable memory
23/188
Flash programmable memory
4.5
ST7LITE49M
Memory protection
There are two different types of memory protection: Read-Out Protection and Write/Erase
Protection which can be applied individually.
4.5.1
Read-Out Protection
Read-Out Protection, when selected provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller. Both program and data EEPROM memory are protected.
In Flash devices, this protection is removed by reprogramming the option. In this case, both
program and data EEPROM memory are automatically erased and the device can be
reprogrammed.
Read-Out Protection selection depends on the device type:
4.5.2
●
In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
●
In ROM devices it is enabled by mask option specified in the option list.
Flash Write/Erase Protection
Write/Erase Protection, when set, makes it impossible to both overwrite and erase program
memory. It does not apply to EEPROM data. Its purpose is to provide advanced security to
applications and prevent any change being made to the memory content. Write/Erase
Protection is enabled through the FMP_W bit in the option byte.
Caution:
Once set, Write/Erase Protection can never be removed. A write-protected Flash
device is no longer reprogrammable.
4.6
Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual.
4.7
Description of the Flash Control/Status register (FCSR)
This register controls the XFlash erasing and programming using ICP, IAP or other
programming methods.
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys
are sent automatically.
Reset value: 000 0000 (00h)
7
0
0
0
0
0
0
Read/write
24/188
OPT
LAT
PGM
ST7LITE49M
Data EEPROM
5
Data EEPROM
5.1
Introduction
The Electrically Erasable Programmable Read Only Memory can be used as a non volatile
back-up for storing data. Using the EEPROM requires a basic access protocol described in
this chapter.
5.2
Main features
●
Up to 32 bytes programmed in the same cycle
●
EEPROM mono-voltage (charge pump)
●
Chained erase and programming cycles
●
Internal control of the global programming cycle duration
●
Wait mode management
●
Read-Out Protection
Figure 6.
EEPROM block diagram
HIGH VOLTAGE
PUMP
EECSR
0
0
0
0
0
ADDRESS
DECODER
4
0
E2LAT E2PGM
EEPROM
MEMORY MATRIX
(1 ROW = 32 x 8 BITS)
ROW
DECODER
128
4
128
DATA
MULTIPLEXER
32 x 8 BITS
DATA LATCHES
4
ADDRESS BUS
DATA BUS
25/188
Data EEPROM
5.3
ST7LITE49M
Memory access
The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the
EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these
different memory access modes.
5.3.1
Read operation (E2LAT=0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR
register is cleared.
On this device, Data EEPROM can also be used to execute machine code. Take care not to
write to the Data EEPROM while executing from it. This would result in an unexpected code
being executed.
5.3.2
Write operation (E2LAT=1)
To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains
cleared). When a write access to the EEPROM area occurs, the value is latched inside the
32 data latches according to its address.
When PGM bit is set by the software, all the previous bytes written in the data latches (up to
32) are programmed in the EEPROM cells. The effective high address (row) is determined
by the last EEPROM write sequence. To avoid wrong programming, the user must take care
that all the bytes written between two programming sequences have the same high address:
only the five Least Significant Bits of the address can change.
At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.
Note:
Care should be taken during the programming cycle. Writing to the same memory location
will over-program the memory (logical AND between the two write access data result)
because the data latches are only cleared at the end of the programming cycle and by the
falling edge of the E2LAT bit. It is not possible to read the latched data (see Figure 9).
Figure 7.
Data EEPROM programming flowchart
READ MODE
E2LAT=0
E2PGM=0
READ BYTES
IN EEPROM AREA
WRITE MODE
E2LAT=1
E2PGM=0
WRITE UP TO 32 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
START PROGRAMMING CYCLE
E2LAT=1
E2PGM=1 (set by software)
0
CLEARED BY HARDWARE
26/188
E2LAT
1
ST7LITE49M
Data EEPROM
Figure 8.
Data EEPROM write operation
⇓ Row / byte ⇒
ROW
DEFINITION
0 1 2 3
...
30
31
Physical Address
0
00h...1Fh
1
20h...3Fh
...
N
Nx20h...Nx20h+1Fh
Read operation impossible
Byte 1
E2LAT bit
Byte 2
Byte 32
Read operation possible
Programming cycle
PHASE 1
PHASE 2
Writing data latches
Waiting E2PGM and E2LAT to fall
Set by USER application
Cleared by hardware
E2PGM bit
1. If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not
guaranteed.
5.4
Power saving modes
5.4.1
Wait mode
The DATA EEPROM can enter Wait mode on execution of the WFI instruction of the
microcontroller or when the microcontroller enters Active-Halt mode.The DATA EEPROM
will immediately enter this mode if there is no programming in progress, otherwise the DATA
EEPROM will finish the cycle and then enter Wait mode.
5.4.2
Active-Halt mode
Refer to Wait mode.
5.4.3
Halt mode
The DATA EEPROM immediately enters Halt mode if the microcontroller executes the HALT
instruction. Therefore the EEPROM will stop the function in progress, and data may be
corrupted.
5.5
Access error handling
If a read access occurs while E2LAT=1, then the data bus will not be driven.
If a write access occurs while E2LAT=0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by a RESET action), the integrity of the data in
memory will not be guaranteed.
27/188
Data EEPROM
5.6
ST7LITE49M
Data EEPROM Read-Out Protection
The Read-Out Protection is enabled through an option bit (see Section 14.1: Option bytes).
When this option is selected, the programs and data stored in the EEPROM memory are
protected against Read-out (including a re-write protection). In Flash devices, when this
protection is removed by reprogramming the option byte, the entire Program memory and
EEPROM is first automatically erased.
Note:
Both Program Memory and data EEPROM are protected using the same option bit.
Figure 9.
Data EEPROM programming cycle
READ OPERATION POSSIBLE
READ OPERATION NOT POSSIBLE
Internal
Programming
voltage
ERASE CYCLE
WRITE OF
DATA LATCHES
WRITE CYCLE
tPROG
LAT
PGM
5.7
EEPROM Control/Status register (EECSR)
Address: 0035h
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
E2LAT
E2PGM
Read/write
Bits 7:2 = Reserved, forced by hardware to 0
0: Read mode
1: Write mode
Bit 1 = E2LAT Latch Access Transfer bit: this bit is set by software.
It is cleared by hardware at the end of the programming cycle. It can only be cleared by
software if the E2PGM bit is cleared
Bit 0 = E2PGM Programming Control and Status bit
This bit is set by software to begin the programming cycle. At the end of the
programming cycle, this bit is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note:
28/188
If the E2PGM bit is cleared during the programming cycle, the memory data is not
guaranteed.
ST7LITE49M
Central processing unit
6
Central processing unit
6.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.
6.2
6.3
Main features
●
63 basic instructions
●
Fast 8-bit by 8-bit multiply
●
17 main addressing modes
●
Two 8-bit index registers
●
16-bit stack pointer
●
Low power modes
●
Maskable hardware interrupts
●
Non-maskable software interrupt
CPU registers
The six CPU registers shown in Figure 10. They are not present in the memory mapping
and are accessed by specific instructions.
Figure 10. CPU registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
15
PCH
8 7
PCL
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1 1 1 H I
0
N Z C
CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8 7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
29/188
Central processing unit
6.3.1
ST7LITE49M
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
6.3.2
Index registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective
addresses or temporary storage areas for data manipulation. (The Cross-Assembler
generates a precede instruction (PRE) to indicate that the following instruction refers to the
Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and
popped from the stack).
6.3.3
Program Counter (PC)
The Program Counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter low which is
the LSB) and PCH (Program Counter high which is the MSB).
6.3.4
Condition Code register (CC)
The 8-bit Condition Code register contains the interrupt mask and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
Reset value: 111x 1xxx
7
1
0
1
I1
H
I0
N
Z
C
Read/write
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic management bits
Bit 4 = H Half carry bit
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during
an ADD or ADC instruction. It is reset by hardware during the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
30/188
ST7LITE49M
Central processing unit
Bit 3 = I Interrupt mask bit
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM
and JRNM instructions.
Note:
Interrupts requested while I is set are latched and can be processed when I is cleared. By
default an interrupt routine is not interruptible because the I bit is set by hardware at the start
of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared
by software in the interrupt routine, pending interrupts are serviced regardless of the priority
level of the current interrupt routine.
Bit 2 = N Negative bit
This bit is set and cleared by hardware. It is representative of the result sign of the last
arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero bit
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow bit
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
Interrupt management bits
Bit 5,3 = I1, I0 Interrupt bits
The combination of the I1 and I0 bits gives the current interrupt software priority.
These two bits are set/cleared by hardware when entering in interrupt. The loaded
value is given by the corresponding bits in the interrupt software priority registers
(IxSPR). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI
and PUSH/POP instructions. See Section 10.6: Interrupts for more details.
31/188
Central processing unit
*
Table 4.
6.3.5
ST7LITE49M
Interrupt software priority truth table
Interrupt software priority
I1
I0
Level 0 (main)
1
0
Level 1
0
1
Level 2
0
0
Level 3 (= interrupt disable)
1
1
Stack Pointer (SP)
Reset value: 01FFh
15
0
0
0
0
0
0
0
8
7
1
1
0
SP6 SP5 SP4 SP3 SP2 SP1 SP0
Read/write
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 11).
Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD
instruction.
Note:
When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 11.
●
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
●
On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
32/188
ST7LITE49M
Central processing unit
Figure 11. Stack manipulation example
CALL
Subroutine
PUSH Y
Interrupt
Event
POP Y
RET
or RSP
IRET
@ 0180h
SP
SP
CC
A
SP
CC
A
X
X
X
PCH
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
SP
@ 01FFh
Y
CC
A
SP
SP
Stack Higher Address = 01FFh
Stack Lower Address = 0180h
33/188
Supply, reset and clock management
7
ST7LITE49M
Supply, reset and clock management
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. The main features are the following:
●
Clock Management
–
8 MHz internal RC oscillator (enabled by option byte)
–
Auto Wake Up RC oscillator (enabled by option byte)
–
1 to 16 MHz or 32kHz External crystal/ceramic resonator (selected by option byte)
–
External Clock Input (enabled by option byte)
●
Reset Sequence Manager (RSM)
●
System Integrity Management (SI)
–
Main supply Low voltage detection (LVD) with reset generation (enabled by option
byte)
–
Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main
supply (enabled by option byte)
7.1
RC oscillator adjustment
7.1.1
Internal RC oscillator
The device contains an internal RC oscillator with a specific accuracy for a given device,
temperature and voltage range (4.5V-5.5V). It must be calibrated to obtain the frequency
required in the application. This is done by software writing a 10-bit calibration value in the
RCCR (RC Control register) and in the bits 6:5 in the SICSR (SI Control Status register).
Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each
time the device is reset, the calibration value must be loaded in the RCCR. Predefined
calibration values are stored in EEPROM for 3 and 5 V VDD supply voltages at 25 °C (see
Table 5).
Table 5.
Predefined RC oscillator calibration values
ST7LITE49M
RCCR
Conditions
RCCRH0
VDD= 5V
TA= 25°C
fRC = 8 MHz
DEE0h(1) (CR[9:2])
VDD = 3.3 V
TA= 25°C
fRC = 8 MHz
DEE2h(1) (CR[9:2])
RCCRL0
RCCRH1
RCCRL1
Address
DEE1h(1) (CR[1:0])
DEE3h(1) (CR[1:0])
1. The DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area in non-volatile memory.
They are read-only bytes for the application code. This area cannot be erased or programmed by any ICC
operations.
For compatibility reasons with the SICSR register, CR[1:0] bits are stored in the 5th and 6th position of
DEE1 and DEE3 addresses.
34/188
ST7LITE49M
Supply, reset and clock management
In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of
the selection in the option byte.
Section 13: Electrical characteristics on page 142 for more information on the frequency
and accuracy of the RC oscillator.
To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100nF, between the VDD and VSS pins and also between the VDDA and
VSSA pins as close as possible to the ST7 device.
These bytes are systematically programmed by ST, including on FASTROM devices.
Caution:
If the voltage or temperature conditions change in the application, the frequency may need
to be recalibrated. Refer to application note AN1324 for information on how to calibrate the
RC frequency using an external reference signal.
7.1.2
Auto Wake Up RC oscillator
The ST7LITE49M also contains an Auto Wake Up RC oscillator. This RC oscillator should
be enabled to enter Auto Wake-up from Halt mode.
The Auto Wake Up (AWU) RC oscillator can also be configured as the startup clock through
the CKSEL[1:0] option bits (see Section 14.1: Option bytes on page 175).
This is recommended for applications where very low power consumption is required.
Switching from one startup clock to another can be done in run mode as follows (see
Figure 12):
Case 1 Switching from internal RC to AWU
1.
Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator
2.
The RC_FLAG is cleared and the clock output is at 1.
3.
Wait 3 AWU RC cycles till the AWU_FLAG is set
4.
The switch to the AWU clock is made at the positive edge of the AWU clock signal
5.
Once the switch is made, the internal RC is stopped
Case 2 Switching from AWU RC to internal RC
Note:
1.
Reset the RC/AWU bit to enable the internal RC oscillator
2.
Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is
running on internal RC clock.
3.
Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC
cycles)
4.
The switch to the internal RC clock is made at the positive edge of the internal RC clock
signal
5.
Once the switch is made, the AWU RC is stopped
1
When the internal RC is not selected, it is stopped so as to save power consumption.
2
When the internal RC is selected, the AWU RC is turned on by hardware when entering
Auto Wake-Up from Halt mode.
3
When the external clock is selected, the AWU RC oscillator is always on.
35/188
Supply, reset and clock management
ST7LITE49M
Figure 12. Clock switching
Internal RC Set RC/AWU
AWU RC
Poll AWU_FLAG until set
Reset RC/AWU
AWU RC
Internal RC
Poll RC_FLAG until set
Figure 13. Clock management block diagram
CK2
CK1
CR9
AVDTHCR
CK0
CR8
CR7
CR6
CR5
CR1
CR4
CR3
CR2
RCCR
SICSR
CR0
Tunable
RC Oscillator
RC/AWU CKCNTCSR
8 MHz (fRC)
Prescaler
8MHz
4MHz
2MHz
1MHz
500kHz
CLKSEL[1:0]
Option bits
CLKIN
OSC2
AWU RC OSC
Clock controller
RC OSC
CLKIN
CLKIN
CLKIN
/OSC1
12-BIT
AT TIMER 2
fCPU
OSC
1-16 MHz
or 32kHz
fOSC
/2
DIVIDER
CLKIN/2
OSC
/2
DIVIDER
CLKIN/2
OSC/2
CLKSEL[1:0]
Option bits
8-BIT
LITE TIMER 2 COUNTER
fOSC
/32 DIVIDER
fOSC/32
fOSC
1
0
fLTIMER
(1ms timebase @ 8 MHz fOSC)
fCPU
TO CPU AND
PERIPHERALS
MCO SMS MCCSR
fCPU
36/188
MCO
ST7LITE49M
7.2
Supply, reset and clock management
Multi-oscillator (MO)
The main clock of the ST7 can be generated by four different source types coming from the
multi-oscillator block (1 to 16MHz):
●
An external source
●
5 different configurations for crystal or ceramic resonator oscillators
●
An internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Table 6. Refer to the electrical characteristics section for more details.
7.2.1
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
Note:
When the Multi-Oscillator is not used OSCI1 and OSCI2 must be tied to ground, and PB1 is
selected by default as the external clock.
7.2.2
Crystal/ceramic oscillators
In this mode, with a self-controlled gain feature, oscillator of any frequency from 1 to 16MHz
can be placed on OSC1 and OSC2 pins. This family of oscillators has the advantage of
producing a very accurate rate on the main clock of the ST7. In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and start-up stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the RESET phase to avoid losing time in the
oscillator start-up phase.
7.2.3
Internal RC oscillator
In this mode, the tunable 1% RC oscillator is used as main clock source. The two oscillator
pins have to be tied to ground.
The calibration is done through the RCCR[7:0] and SICSR[6:5] registers.
37/188
Supply, reset and clock management
Table 6.
ST7LITE49M
ST7 clock sources
External Clock
Hardware Configuration
ST7
OSC1
OSC2
EXTERNAL
Internal RC Oscillator
Crystal/Ceramic Resonators
SOURCE
38/188
ST7
OSC1
CL1
OSC2
CL2
LOAD
CAPACITORS
ST7
OSC1
OSC2
ST7LITE49M
Supply, reset and clock management
7.3
Reset sequence manager (RSM)
7.3.1
Introduction
The reset sequence manager includes three RESET sources as shown in Figure 15:
Note:
●
External RESET source pulse
●
Internal LVD RESET (Low Voltage Detection)
●
Internal WATCHDOG RESET
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 12.2.1 on page 139 for further details.
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
mapping.
The basic RESET sequence consists of 3 phases as shown in Figure 14:
Caution:
●
Active Phase depending on the RESET source
●
256 or 4096 CPU clock cycle delay (see Table 7)
When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay is
automatically selected depending on the clock source chosen by option byte.
The Reset vector fetch phase duration is 2 clock cycles.
Table 7.
CPU clock delay during Reset sequence
Clock source
CPU clock
cycle delay
Internal RC 8MHz Oscillator
4096
Internal RC 32kHz Oscillator
256
External clock (connected to CLKIN/PB1 pin)
4096
External Crystal/Ceramic Oscillator
(connected to OSC1/OSC2 pins)
4096
External Crystal/Ceramic 1-16MHz
Oscillator
4096
External Crystal/Ceramic 32kHz
Oscillator
256
Figure 14. RESET sequence phases
RESET
Active Phase
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
39/188
Supply, reset and clock management
7.3.2
ST7LITE49M
Asynchronous External RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Electrical Characteristic
section for more details.
A RESET signal originating from an external source must have a duration of at least
th(RSTL)in in order to be recognized (see Figure 16). This detection is asynchronous and
therefore the MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
Figure 15. Reset block diagram
VDD
RON
RESET
INTERNAL
RESET
Filter
PULSE
GENERATOR
WATCHDOG RESET
ILLEGAL OPCODE RESET 1)
LVD RESET
1. See Section 12.2.1: Illegal Opcode Reset on page 139 for more details on illegal opcode reset conditions.
7.3.3
External Power-On Reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until VDD is over
the minimum level specified for the selected fOSC frequency.
A proper reset signal for a slow rising VDD supply can generally be provided by an external
RC network connected to the RESET pin.
7.3.4
Internal Low Voltage Detector (LVD) Reset
Two different Reset sequences caused by the internal LVD circuitry can be distinguished:
●
Power-On Reset
●
Voltage Drop Reset
The device RESET pin acts as an output that is pulled low when VDD is lower than VIT+
(rising edge) or VDD lower than VIT- (falling edge) as shown in Figure 16.
The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.
40/188
ST7LITE49M
7.3.5
Supply, reset and clock management
Internal Watchdog Reset
The Reset sequence generated by a internal Watchdog counter overflow is shown in
Figure 16.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
Figure 16. RESET sequences
VDD
VIT+(LVD)
VIT-(LVD)
RUN
LVD
RESET
RUN
ACTIVE PHASE
EXTERNAL
RESET
ACTIVE
PHASE
WATCHDOG
RESET
RUN
ACTIVE
PHASE
RUN
tw(RSTL)out
th(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU)
VECTOR FETCH
41/188
Supply, reset and clock management
7.4
ST7LITE49M
System integrity management (SI)
The System Integrity Management block contains the Low voltage Detector (LVD) and
Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.
Note:
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 12.2.1 on page 139 for further details.
7.4.1
Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the VDD supply
voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well
as the power-down keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when VDD is below:
●
VIT+(LVD)when VDD is rising
●
VIT-(LVD) when VDD is falling
The LVD function is illustrated in Figure 17.
The voltage threshold can be configured by option byte to be low, medium or high. See
Section 14.1 on page 175.
Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD),
the MCU can only be in two modes:
●
Under full software control
●
In static safe reset
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU
to reset other devices.
Note:
Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur
in the application, it is recommended to pull VDD down to 0V to ensure optimum restart
conditions. Refer to circuit example in Figure 96 on page 171 and note 4.
The LVD is an optional function which can be selected by option byte. See Section 14.1 on
page 175.
It allows the device to be used without any external RESET circuitry.
If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset.
It is recommended to make sure that the VDD supply voltage rises monotonously when the
device is exiting from Reset, to ensure the application functions properly.
Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD
levels are not correlated. Refer to section Section 13.3.2 on page 145 and Section 13.3.3 on
page 146 for more details.
Caution:
42/188
If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will
clear the watchdog flag.
ST7LITE49M
Supply, reset and clock management
Figure 17. Low Voltage Detector vs Reset
VDD
Vhys
VIT+(LVD)
VIT-(LVD)
RESET
Figure 18. Reset and supply management block diagram
WATCHDOG
TIMER (WDG)
RESET
RESET SEQUENCE
MANAGER
(RSM)
STATUS FLAG
SYSTEM INTEGRITY MANAGEMENT
AVD Interrupt Request
SICSR
0
VSS
VDD
CR1 CR0
WDGF
0
LVDRF AVDF AVDIE
LOW VOLTAGE
DETECTOR
(LVD)
AUXILIARY VOLTAGE
DETECTOR
(AVD)
7.4.2
Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD)
and VIT+(AVD) reference value and the VDD main supply voltage (VAVD). The VIT-(AVD)
reference value for falling voltage is lower than the VIT+(AVD) reference value for rising
voltage in order to avoid parasitic detection (hysteresis).
The output of the AVD comparator is directly readable by the application software through a
real time status bit (AVDF) in the SICSR register. This bit is read only.
Monitoring the VDD main supply
The AVD threshold is selected by the AVD[1:0] bits in the AVDTHCR register.
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the
VIT+(AVD) or VIT-(AVD) threshold (AVDF bit is set).
In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing
software to shut down safely before the LVD resets the microcontroller. See Figure 19.
The interrupt on the rising edge is used to inform the application that the VDD warning state
is over.
43/188
Supply, reset and clock management
Note:
ST7LITE49M
Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD
levels are not correlated. Refer to Section 13.3.2 on page 145 and Section 13.3.3 on page
146 for more details.
Figure 19. Using the AVD to monitor VDD
VDD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
Vhyst
VIT+(AVD)
VIT-(AVD)
VIT+(LVD)
VIT-(LVD)
AVDF bit
0
1
RESET
0
1
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT Cleared by
reset
LVD RESET
7.4.3
INTERRUPT Cleared by
hardware
Low power modes
Table 8.
Low power modes
Mode
Description
Wait
No effect on SI. AVD interrupts cause the device to exit from Wait mode.
Halt
The SICSR register is frozen.
The AVD remains active but the AVD interrupt cannot be used to exit from Halt
mode.
Interrupts
The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit
(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Table 9.
44/188
Description of interrupt events
Interrupt event
Event flag
Enable
Control
bit
Exit from
Wait
Exit from
Halt
AVD event
AVDF
AVDIE
Yes
No
ST7LITE49M
Supply, reset and clock management
7.5
Register description
7.5.1
Main Clock Control/Status register (MCCSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
MCO
SMS
Read/write
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = MCO Main Clock Out enable bit
This bit is read/write by software and cleared by hardware after a reset. This bit allows
to enable the MCO output clock.
0: MCO clock disabled, I/O port free for general purpose I/O.
1: MCO clock enabled.
Bit 0 = SMS Slow mode selection bit
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the input clock fOSC or fOSC/32.
0: Normal mode (fCPU = fOSC
1: Slow mode (fCPU = fOSC/32)
7.5.2
RC Control register (RCCR)
Reset value: 1111 1111 (FFh)
7
CR9
0
CR8
CR7
CR6
CR5
CR4
CR3
CR2
Read/write
Bits 7:0 = CR[9:2] RC Oscillator Frequency Adjustment bits
These bits must be written immediately after reset to adjust the RC oscillator frequency
and to obtain an accuracy of 1%. The application can store the correct value for each
voltage range in EEPROM and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
These bits are used with the CR[1:0] bits in the SICSR register. Refer to Section 7.5 on
page 45.
Note:
To tune the oscillator, write a series of different values in the register until the correct
frequency is reached. The fastest method is to use a dichotomy starting with 80h.
45/188
Supply, reset and clock management
7.5.3
ST7LITE49M
AVD Threshold Selection register (AVDTHCR)
Reset value: 0000 0000 (00h)
7
CK2
0
CK1
CK0
0
0
0
AVD1
AVD0
Read/write
Bits 7:5 = CK[2:0] internal RC Prescaler Selection
These bits are set by software and cleared by hardware after a reset. These bits select
the prescaler of the internal RC oscillator. See Figure 13 on page 36 and Table 10.
If the internal RC is used with a supply operating range below 3.3V, a division ratio of at
least 2 must be enabled in the RC prescaler.
Table 10.
Internal RC Prescaler Selection bits
CK2
CK1
CK0
fOSC
0
0
1
fRC/2
0
1
0
fRC/4
0
1
1
fRC/8
1
0
0
fRC/16
others
fRC
Bits 4:2 = Reserved, must be kept cleared.
Bits 1:0 = AVD[1:0] AVD Threshold selection. These bits are used to select the AVD
threshold. They are set and cleared by software. They are set by hardware after a reset.
Bit 1 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt
request is generated when the AVDF bit is set. Refer to Figure 19 for additional details
0: VDD over AVD threshold
1: VDD under AVD threshold
Bit 0 = AVDIE Voltage Detector interrupt enable bit
This bit is set and cleared by software. It enables an interrupt to be generated when the
AVDF flag is set. The pending interrupt information is automatically cleared when
software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
46/188
ST7LITE49M
7.5.4
Supply, reset and clock management
CLOCK Controller Control/Status register (CKCNTCSR)
Reset value: 0000 1001 (09h)
7
0
0
0
0
0
AWU_FLAG
RC_FLAG
0
RC/AWU
Read/write
Bits 7:4 = Reserved, must be kept cleared.
Bit 3 = AWU_FLAG AWU Selection bit
This bit is set and cleared by hardware.
0: No switch from AWU to RC requested
1: AWU clock activated and temporization completed
Bit 2 = RC_FLAG RC Selection bit
This bit is set and cleared by hardware.
0: No switch from RC to AWU requested
1: RC clock activated and temporization completed
Bit 1 = Reserved, must be kept cleared.
Bit 0 = RC/AWU RC/AWU Selection bit
0: RC enabled
1: AWU enabled (default value)
7.5.5
System Integrity (SI) Control/Status register (SICSR)
Reset value: 011x 0x00 (xxh)
7
0
0
CR1
CR0
WDGRF
0
LVDRF
AVDF
AVDIE
Read/write
Bit 7 = Reserved, must be kept cleared
Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits
These bits, as well as CR[9:2] bits in the RCCR register must be written immediately
after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. Refer
to Section 7.1.1: Internal RC oscillator on page 34.
Bit 4 = WDGRF Watchdog Reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It is
set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD
Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
The WDGRF and the LVDRF flags are used to select the reset source (see Table 11).
47/188
Supply, reset and clock management
Table 11.
ST7LITE49M
Reset source selection
RESET source
LVDRF
WDGRF
External RESET pin
0
0
Watchdog
0
1
LVD
1
X
Bit 3 = Reserved, must be kept cleared
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled
by option byte, the LVDRF bit value is undefined.
The LVDRF flag is not cleared when another RESET type occurs (external or
watchdog), the LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can
not.
Bit 1 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt
request is generated when the AVDF bit is set. Refer to Figure 19 and to Section for
additional details.
0: VDD over AVD threshold
1: VDD under AVD threshold
Bit 0 = AVDIE Voltage Detector Interrupt Enable bit
This bit is set and cleared by software. It enables an interrupt to be generated when the
AVDF flag is set. The pending interrupt information is automatically cleared when
software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Table 12.
Address
Clock register mapping and reset values
Register
label
7
6
5
4
3
2
1
0
003Ah
MCCSR
Reset
Value
0
0
0
0
0
0
MCO
0
SMS
0
003Bh
RCCR
Reset
Value
CR9
1
CR8
1
CR7
1
CR6
1
CR5
1
CR4
1
CR3
1
CR2
1
003Ch
SICSR
Reset
Value
0
CR1
1
CR0
1
WDGRF
0
0
LVDRF
x
AVDF
x
AVDIE
0
(Hex.)
48/188
ST7LITE49M
Table 12.
Address
Supply, reset and clock management
Clock register mapping and reset values (continued)
Register
label
7
6
5
4
3
2
1
0
003Dh
AVDTHCR
Reset
Value
CK2
0
CK1
0
CK0
0
0
0
0
AVD1
0
AVD0
0
0051h
CKCNTCS
R
Reset
Value
0
0
0
0
AWU_FLAG
1
RC_FLAG
0
0
RC/AWU
1
(Hex.)
49/188
Interrupts
ST7LITE49M
8
Interrupts
8.1
Introduction
The ST7 enhanced interrupt management provides the following features:
●
Hardware interrupts
●
Software interrupt (TRAP)
●
Nested or concurrent interrupt management with flexible interrupt priority and level
management:
–
Up to 4 software programmable nesting levels
–
13 interrupt vectors fixed by hardware
–
2 non maskable events: RESET, TRAP
This interrupt management is based on:
●
Bit 5 and bit 3 of the CPU CC register (I1:0),
●
Interrupt software priority registers (ISPRx),
●
Fixed interrupt vector addresses located at the high addresses of the memory mapping
(FFE0h to FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.
8.2
Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx
registers which give the interrupt software priority level of each interrupt vector (see
Table 13). The processing flow is shown in Figure 20.
When an interrupt request has to be serviced:
●
Normal processing is suspended at the end of the current instruction execution.
●
The PC, X, A and CC registers are saved onto the stack.
●
I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx
registers of the serviced interrupt vector.
●
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to interrupt mappin table for
vector addresses).
The interrupt service routine should end with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note:
50/188
As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
ST7LITE49M
Table 13.
Interrupts
Interrupt software priority levels
Interrupt software priority
Level
Level 0 (main)
I1
I0
1
0
Low
Level 1
1
0
Level 2
0
High
Level 3 (= interrupt disable)
1
1
Figure 20. Interrupt processing flowchart
FETCH NEXT
INSTRUCTION
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
TLI
Interrupt has the same or a
lower software priority
than current one
N
Y
Y
EXECUTE
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
N
I1:0
Interrupt has a higher
software priority
than current one
PENDING
INTERRUPT
RESET
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
51/188
Interrupts
8.2.1
ST7LITE49M
Servicing pending interrupts
As several interrupts can be pending at the same time, the interrupt to be taken into account
is determined by the following two-step process:
●
The highest software priority interrupt is serviced,
●
If several interrupts have the same software priority then the interrupt with the highest
hardware priority is serviced first.
Figure 21 describes this decision process.
Figure 21. Priority decision process
PENDING
INTERRUPTS
Same
SOFTWARE
PRIORITY
Different
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.
Note:
8.2.2
1
The hardware priority is exclusive while the software one is not. This allows the previous
process to succeed with only one interrupt.
2
RESET and TRAP can be considered as having the highest software priority in the decision
process.
Interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (RESET, TRAP) and the maskable type (external or from internal peripherals).
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see Figure 20). After stacking the PC, X, A and CC registers (except for RESET), the
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit Halt mode.
●
TRAP (non maskable software interrupt)
This software interrupt is serviced when the TRAP instruction is executed. It will be
serviced according to the flowchart in Figure 20.
●
RESET
The RESET source has the highest priority in the ST7. This means that the first current
routine has the highest software priority (level 3) and the highest hardware priority.
See the RESET chapter for more details.
52/188
ST7LITE49M
Interrupts
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
●
External interrupts
External interrupts allow the processor to exit from Halt low power mode.
External interrupt sensitivity is software selectable through the External Interrupt
Control register (EICR).
External interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these will be logically ORed.
●
Peripheral interrupts
Usually the peripheral interrupts cause the MCU to exit from Halt mode except those
mentioned in Table 17: Interrupt mapping.
A peripheral interrupt occurs when a specific flag is set in the peripheral status
registers and if the corresponding enable bit is set in the peripheral control register.
The general sequence for clearing an interrupt is based on an access to the status
register followed by a read or write to an associated register.
Note:
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
being serviced) will therefore be lost if the clear sequence is executed.
8.3
Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column “Exit from Halt” in Table 17: Interrupt mapping). When several pending interrupts are
present while exiting Halt mode, the first one serviced can only be an interrupt with exit from
Halt mode capability and it is selected through the same decision process shown in
Figure 21.
Note:
If an interrupt, that is not able to Exit from Halt mode, is pending with the highest priority
when exiting Halt mode, this interrupt is serviced after the first one serviced.
53/188
Interrupts
8.4
ST7LITE49M
Concurrent and nested management
The following Figure 22 and Figure 23 show two different interrupt management modes. The
first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the
nested mode in Figure 23. The interrupt hardware priority is given in this order from the
lowest to the highest: MAIN, IT5, IT4, IT3, IT2, IT1, IT0. The software priority is given for
each interrupt.
Caution:
A stack overflow may occur without notifying the software of the failure.
IT1
IT0
IT4
IT5
IT2
SOFTWARE
PRIORITY
LEVEL
IT0
IT1
IT2
IT2
IT3
IT4
RIM
IT5
MAIN
MAIN
11 / 10
I1
I0
3
1 1
3
1 1
3
1 1
3
1 1
3
1 1
3
1 1
USED STACK = 10 BYTES
HARDWARE PRIORITY
IT3
Figure 22. Concurrent interrupt management
3/0
10
IT1
IT0
IT4
IT5
IT2
TLI
IT0
IT1
IT1
IT2
IT2
IT3
RIM
IT4
MAIN
11 / 10
54/188
SOFTWARE
PRIORITY
LEVEL
IT4
MAIN
10
I1
I0
3
1 1
3
1 1
2
0 0
1
0 1
3
1 1
3
1 1
3/0
USED STACK = 20 BYTES
HARDWARE PRIORITY
IT3
Figure 23. Nested interrupt management
ST7LITE49M
Interrupts
8.5
Description of interrupt registers
8.5.1
CPU CC register interrupt bits
Reset value: 111x 1010(xAh)
7
1
0
1
I1
H
I0
N
Z
C
Read/write
Bit 5, 3 = I1, I0 Software Interrupt Priority bits
These two bits indicate the current interrupt software priority (see Table 14).
These two bits are set/cleared by hardware when entering in interrupt. The loaded
value is given by the corresponding bits in the interrupt software priority registers
(ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see Table 16: Dedicated interrupt instruction set).
TRAP and RESET events can interrupt a level 3 program.
Table 14.
Setting the interrupt software priority
Interrupt software priority
Level
Level 0 (main)
I1
I0
1
0
Low
Level 1
1
0
Level 2
0
High
Level 3 (= interrupt disable*)
8.5.2
1
1
Interrupt software priority registers (ISPRx)
All ISPRx register bits are read/write except bit 7:4 of ISPR3 which are read only.
Reset value: 1111 1111 (FFh)
7
0
ISPR0
I1_3
I0_3
I1_2
I0_2
I1_1
I0_1
I1_0
I0_0
ISPR1
I1_7
I0_7
I1_6
I0_6
I1_5
I0_5
I1_4
I0_4
ISPR2
I1_11
I0_11
I1_10
I0_10
I1_9
I0_9
I1_8
I0_8
ISPR3
1
1
1
1
1
1
I1_12
I0_12
ISPRx registers contain the interrupt software priority of each interrupt vector. Each interrupt
vector (except RESET and TRAP) has corresponding bits in these registers to define its
software priority. This correspondence is shown in Table 15.
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0
bits in the CC register.
55/188
Interrupts
ST7LITE49M
The RESET and TRAP vectors have no software priorities. When one is serviced, the I1 and
I0 bits of the CC register are both set.
Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is
kept (Example: previous = CFh, write = 64h, result = 44h).
Table 15.
Interrupt vector vs ISPRx bits
Vector address
ISPRx bits
FFFBh-FFFAh
I1_0 and I0_0 bits(1)
FFF9h-FFF8h
I1_1 and I0_1 bits
...
...
FFE1h-FFE0h
I1_13 and I0_13 bits
1. Bits in the ISPRx registers can be read and written but they are not significant in the interrupt process
management.
Caution:
If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior
has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
Table 16.
Dedicated interrupt instruction set(1)
Instruction
New description
Function/Example
HALT
Entering Halt mode
IRET
Interrupt routine return
Pop CC, A, X, PC
JRM
Jump if I1:0 = 11 (level 3)
I1:0 = 11
JRNM
Jump if I1:0 <> 11
I1:0 <> 11
POP CC
Pop CC from the Stack
RIM
I1
H
1
I0
N
Z
C
0
I1
H
I0
N
Z
C
Mem => CC
I1
H
I0
N
Z
C
Enable interrupt (level 0 set)
Load 10 in I1:0 of CC
1
0
SIM
Disable interrupt (level 3 set)
Load 11 in I1:0 of CC
1
1
TRAP
Software trap
Software NMI
1
1
WFI
Wait for interrupt
1
0
1. During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the
current software priority up to the next IRET instruction or one of the previously mentioned instructions.
56/188
ST7LITE49M
Table 17.
Number
Interrupts
Interrupt mapping
Source
block
Description
RESET
Reset
Register
label
Exit
Priority
from
order HALT or
AWUFH
Address
vector
yes
FFFEh-FFFFh
no
FFFCh-FFFDh
N/A
TRAP
Software interrupt
0
AWU
Auto Wake Up interrupt
AWUCSR
1
AVD
Auxiliary Voltage Detector interrupt
N/A
2
ei0
External interrupt 0 (Port A)
3
ei1
External interrupt 1 (Port B)
4
ei2
External interrupt 2 (Port C)
5
9
I
2C
10(2)
11
12
FFF8h-FFF9h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
no
FFEEh-FFEFh
AT timer overflow 1 interrupt
no
FFECh-FFEDh
AT timer Overflow 2 interrupt
no
FFEAh-FFEBh
no
FFE8h-FFE9h
yes
FFE6h-FFE7h
no
FFE4h-FFE5h
no
FFE2h-FFE3h
ATCSR
I2C
interrupt
N/A
Lite timer RTC interrupt
LITE TIMER
no
yes
AT timer input Capture interrupt
8
FFFAh-FFFBh
no
AT TIMER
7
yes
FFF6h-FFF7h
N/A
AT timer Output Compare interrupt
6
(2)
Highest
Priority
(1)
Lite timer Input Capture interrupt
Lite timer RTC2 interrupt
LTCSR2
Lowest
Priority
1. This interrupt exits the MCU from Auto Wake-up from Halt mode only.
2. These interrupts exit the MCU from Active-Halt mode only.
57/188
Interrupts
8.5.3
ST7LITE49M
External Interrupt Control register (EICR)
Reset value: 0000 0000 (00h)
7
0
0
0
IS21
IS20
IS11
IS10
IS01
IS00
Read/write
Bits 7:6 = Reserved, must be kept cleared.
Bits 5:4 = IS2[1:0] ei2 sensitivity bits
These bits define the interrupt sensitivity for ei2 (Port C) according to Table 18.
Bits 3:2 = IS1[1:0] ei1 sensitivity bits
These bits define the interrupt sensitivity for ei1 (Port B) according to Table 18.
Bits 1:0 = IS0[1:0] ei0 sensitivity bits
These bits define the interrupt sensitivity for ei0 (Port A) according to Table 18.
Note:
1
These 8 bits can be written only when the I bit in the CC register is set.
2
Changing the sensitivity of a particular external interrupt clears this pending interrupt. This
can be used to clear unwanted pending interrupts. Refer to Section : External interrupt
function.
Table 18.
58/188
Interrupt sensitivity bits
ISx1
ISx0
External interrupt sensitivity
0
0
Falling edge & low level
0
1
Rising edge only
1
0
Falling edge only
1
1
Rising and falling edge
ST7LITE49M
Power saving modes
9
Power saving modes
9.1
Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 24):
●
Slow
●
Wait (and Slow-Wait)
●
Active Halt
●
Auto Wake up From Halt (AWUFH)
●
Halt
After a reset the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency (fOSC).
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 24. Power saving mode transitions
High
Run
Slow
Wait
Slow Wait
Active Halt
Halt
Low
POWER CONSUMPTION
59/188
Power saving modes
9.2
ST7LITE49M
Slow mode
This mode has two targets:
●
To reduce power consumption by decreasing the internal clock in the device,
●
To adapt the internal clock frequency (fCPU) to the available supply voltage.
Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables
Slow mode.
In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked
at this lower frequency.
Note:
Slow-Wait mode is activated when entering Wait mode while the device is already in Slow
mode.
Figure 25. Slow mode clock transition
fOSC/32
fOSC
fCPU
fOSC
SMS
NORMAL RUN MODE
REQUEST
9.3
Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During Wait mode, the I bit of the CC register is cleared, to
enable all interrupts. All other registers and memory remain unchanged. The MCU remains
in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches
to the starting address of the interrupt or Reset service routine.
The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake
up.
Refer to Figure 26 for a desription of the Wait mode flowchart..
60/188
ST7LITE49M
Power saving modes
Figure 26. Wait mode flowchart
WFI INSTRUCTION
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
OFF
0
N
RESET
Y
N
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
OFF
ON
0
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
ON
X 1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
9.4
Active-Halt and Halt modes
Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in ActiveHalt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following
table:
Table 19.
Enabling/disabling Active-Halt and Halt modes
LTCSR TBIE
bit
ATCSR OVFIE
ATCSRCK1 bit ATCSRCK0 bit
bit
0
x
x
0
0
0
x
x
0
1
1
1
1
x
x
x
x
1
0
1
Meaning
Active-Halt mode disabled
Active-Halt mode enabled
61/188
Power saving modes
9.4.1
ST7LITE49M
Active-Halt mode
Active-Halt mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ instruction when active halt mode is enabled.
The MCU can exit Active-Halt mode on reception of a Lite timer/ AT timer interrupt or a
Reset.
●
When exiting Active-Halt mode by means of a Reset, a 256 CPU cycle delay occurs.
After the start up delay, the CPU resumes operation by fetching the Reset vector which
woke it up (see Figure 28).
●
When exiting Active-Halt mode by means of an interrupt, the CPU immediately
resumes operation by servicing the interrupt vector which woke it up (see Figure 28).
When entering Active-Halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-Halt mode, only the main oscillator and the selected timer counter (LT/AT) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
Caution:
As soon as Active-Halt is enabled, executing a HALT instruction while the Watchdog is
active does not generate a Reset if the WDGHALT bit is reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Figure 27. Active-Halt timing overview
RUN
[Active Halt Enabled]
ACTIVE
HALT
HALT
INSTRUCTION
256 CPU
CYCLE DELAY 1)
RESET
OR
INTERRUPT
RUN
FETCH
VECTOR
1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET.
62/188
ST7LITE49M
Power saving modes
Figure 28. Active-Halt mode flowchart
HALT INSTRUCTION
(Active Halt enabled)
OSCILLATOR
ON
PERIPHERALS 2) OFF
CPU
OFF
I BIT
0
N
RESET
N
Y
INTERRUPT 3)
Y
OSCILLATOR
ON
PERIPHERALS 2) OFF
CPU
ON
I BIT
X 4)
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I BITS
ON
ON
ON
X 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET.
2. Peripherals clocked with an external clock source can still be active.
3. Only the Lite timer RTC and AT timer interrupts can exit the MCU from Active-Halt mode.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
9.4.2
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the HALT instruction when active halt mode is disabled.
The MCU can exit Halt mode on reception of either a specific interrupt (see Table 17:
Interrupt mapping) or a Reset. When exiting Halt mode by means of a Reset or an interrupt,
the main oscillator is immediately turned on and the 256 CPU cycle delay is used to stabilize
it. After the start up delay, the CPU resumes operation by servicing the interrupt or by
fetching the Reset vector which woke it up (see Figure 30).
When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog Reset (see Section 14.1: Option bytes for
more details).
63/188
Power saving modes
ST7LITE49M
Figure 29. Halt timing overview
RUN
HALT
HALT
INSTRUCTION
256 CPU CYCLE
DELAY
RUN
RESET
OR
INTERRUPT
FETCH
VECTOR
[Active Halt disabled]
1. A reset pulse of at least 42µs must be applied when exiting from Halt mode.
Figure 30. Halt mode flowchart
HALT INSTRUCTION
(Active Halt disabled)
ENABLE
WDGHALT 1)
WATCHDOG
0
DISABLE
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2) OFF
CPU
OFF
I BIT
0
N
RESET
N
Y
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
OFF
ON
X 4)
256 CPU CLOCK CYCLE
DELAY 5)
OSCILLATOR
PERIPHERALS
CPU
I BITS
ON
ON
ON
X 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
Table 17: Interrupt mapping for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
5. The CPU clock must be switched to 1MHz (RC/8) or AWU RC before entering Halt mode.
64/188
ST7LITE49M
Power saving modes
Halt mode recommendations
9.5
●
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
●
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
●
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
●
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a Program Counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
●
As the HALT instruction clears the I bit in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits before executing the HALT instruction.
This avoids entering other peripheral interrupt routines after executing the external
interrupt routine corresponding to the wake-up event (reset or external interrupt).
Auto Wake Up from Halt mode
Auto Wake Up From Halt (AWUFH) mode is similar to Halt mode with the addition of a
specific internal RC oscillator for wake-up (Auto Wake-Up from Halt oscillator) which
replaces the main clock which was active before entering Halt mode. Compared to ActiveHalt mode, AWUFH has lower power consumption (the main clock is not kept running), but
there is no accurate realtime clock available.
It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR
register has been set.
Figure 31. AWUFH mode block diagram
AWU RC
oscillator
fAWU_RC
/64
divider
to 8-bit timer Input Capture
AWUFH
prescaler/1 .. 255
AWUFH
interrupt
(ei0 source)
65/188
Power saving modes
ST7LITE49M
As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR
register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by
a fixed divider and a programmable prescaler controlled by the AWUPR register. The output
of this prescaler provides the delay time. When the delay has elapsed, the following actions
are performed:
●
the AWUF flag is set by hardware,
●
an interrupt wakes-up the MCU from Halt mode,
●
the main oscillator is immediately turned on and the 256 CPU cycle delay is used to
stabilize it.
After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The
AWU flag and its associated interrupt are cleared by software reading the AWUCSR
register.
To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated
by measuring the clock frequency fAWU_RC and then calculating the right prescaler value.
Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run
mode. This connects fAWU_RC to the Input Capture of the 8-bit Lite timer, allowing the
fAWU_RC to be measured using the main oscillator clock as a reference timebase.
Similarities with Halt mode
The following AWUFH mode behaviour is the same as normal Halt mode:
●
The MCU can exit AWUFH mode by means of any interrupt with exit from Halt
capability or a reset (see Section 9.4: Active-Halt and Halt modes).
●
When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
●
In AWUFH mode, the main oscillator is turned off causing all internal processing to be
stopped, including the operation of the on-chip peripherals. None of the peripherals are
clocked except those which get their clock supply from another clock generator (such
as an external or auxiliary oscillator like the AWU oscillator).
●
The compatibility of watchdog operation with AWUFH mode is configured by the
WDGHALT option bit in the option byte. Depending on this setting, the HALT
instruction when executed while the watchdog system is enabled, can generate a
watchdog Reset.
Figure 32. AWUF Halt timing diagram
tAWU
RUN MODE
HALT MODE
256 tCPU
RUN MODE
fCPU
fAWU_RC
Clear
by software
AWUFH interrupt
66/188
ST7LITE49M
Power saving modes
Figure 33. AWUFH mode flowchart
HALT INSTRUCTION
(Active-Halt disabled)
(AWUCSR.AWUEN=1)
ENABLE
WDGHALT 1)
WATCHDOG
DISABLE
0
1
WATCHDOG
RESET
AWU RC OSC
ON
MAIN OSC
OFF
2)
PERIPHERALS OFF
CPU
OFF
I[1:0] BITS
10
N
RESET
N
Y
INTERRUPT 3)
Y
AWU RC OSC
OFF
MAIN OSC
ON
PERIPHERALS OFF
CPU
ON
I[1:0] BITS
XX 4)
256 CPU CLOCK
CYCLE DELAY
AWU RC OSC
OFF
MAIN OSC
ON
PERIPHERALS ON
CPU
ON
I[1:0] BITS
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external
interrupt). Refer to Table 17: Interrupt mapping for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
67/188
Power saving modes
ST7LITE49M
9.5.1
Register description
9.5.2
AWUFH Control/Status register (AWUCSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
AWU
F
AWUM
AWUEN
Read/Write
Bits 7:3 = Reserved
Bit 2= AWUF Auto Wake Up flag
This bit is set by hardware when the AWU module generates an interrupt and cleared
by software on reading AWUCSR. Writing to this bit does not change its value.
0: No AWU interrupt occurred
1: AWU interrupt occurred
Bit 1= AWUM Auto Wake Up Measurement bit
This bit enables the AWU RC oscillator and connects its output to the Input Capture of
the 8-bit Lite timer. This allows the timer to be used to measure the AWU RC oscillator
dispersion and then compensate this dispersion by providing the right value in the
AWUPRE register.
0: Measurement disabled
1: Measurement enabled
Bit 0 = AWUEN Auto Wake Up From Halt Enabled bit
This bit enables the Auto Wake Up From Halt feature: once Halt mode is entered, the
AWUFH wakes up the microcontroller after a time delay dependent on the AWU
prescaler value. It is set and cleared by software.
0: AWUFH (Auto Wake Up From Halt) mode disabled
1: AWUFH (Auto Wake Up From Halt) mode enabled
Note:
68/188
Whatever the clock source, this bit should be set to enable the AWUFH mode once the
HALT instruction has been executed.
ST7LITE49M
9.5.3
Power saving modes
AWUFH Prescaler register (AWUPR)
Reset value: 1111 1111 (FFh)
7
0
AWUPR7
AWUPR6
AWUPR5
AWUPR4
AWUPR3
AWUPR2
AWUPR1
AWUPR0
Read/Write
Bits 7:0= AWUPR[7:0] Auto Wake Up Prescaler
These 8 bits define the AWUPR Dividing factor (see Table 20).
Table 20.
Configuring the dividing factor
AWUPR[7:0]
Dividing factor
00h
Forbidden
01h
1
...
...
FEh
254
FFh
255
In AWU mode, the time during which the MCU stays in Halt mode, tAWU, is given by the
equation below. See also Figure 32 on page 66.
1
t AWU = 64 × AWUPR × -------------------- + t RCSTRT
f AWURC
The AWUPR prescaler register can be programmed to modify the time during which the
MCU stays in Halt mode before waking up automatically.
Note:
If 00h is written to AWUPR, the AWUPR remains unchanged.
Table 21.
AWU register mapping and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
0048h
AWUCSR
Reset
Value
0
0
0
0
0
AWUF
AWUM
AWUEN
0049h
AWUPR
Reset
Value
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
1
1
1
1
1
1
1
1
69/188
I/O ports
ST7LITE49M
10
I/O ports
10.1
Introduction
The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be
programmed independently either as a digital input or digital output. In addition, specific pins
may have several other functions. These functions can include external interrupt, alternate
signal input/output for on-chip peripherals or analog input.
10.2
Functional description
A Data register (DR) and a Data Direction register (DDR) are always associated with each
port. The Option register (OR), which allows input/output options, may or may not be
implemented. The following description takes into account the OR register. Refer to the Port
Configuration table for device specific information.
An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit
x corresponding to pin x of the port.
Figure 34 shows the generic I/O block diagram.
10.2.1
Input modes
Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital
value from that I/O pin.
If an OR bit is available, different input modes can be configured by software: floating or pullup. Refer to I/O Port Implementation section for configuration.
Note:
1
Writing to the DR modifies the latch value but does not change the state of the input pin.
2
Do not use read/modify/write instructions (BSET/BRES) to modify the DR register.
External interrupt function
Depending on the device, setting the ORx bit while in input mode can configure an I/O as an
input with interrupt. In this configuration, a signal edge or level input on the I/O generates an
interrupt request via the corresponding interrupt vector (eix).
Falling or rising edge sensitivity is programmed independently for each interrupt vector. The
External Interrupt Control register (EICR) or the Miscellaneous register controls this
sensitivity, depending on the device.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout
description and interrupt section). If several I/O interrupt pins on the same interrupt vector
are selected simultaneously, they are logically combined. For this reason if one of the
interrupt pins is tied low, it may mask the others.
External interrupts are hardware interrupts. Fetching the corresponding interrupt vector
automatically clears the request latch. Changing the sensitivity of a particular external
interrupt clears this pending interrupt. This can be used to clear unwanted pending
interrupts.
70/188
ST7LITE49M
I/O ports
Spurious interrupts
When enabling/disabling an external interrupt by setting/resetting the related OR register bit,
a spurious interrupt is generated if the pin level is low and its edge sensitivity includes
falling/rising edge. This is due to the edge detector input which is switched to '1' when the
external interrupt is disabled by the OR register.
To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and
falling edge for disabling) has to be selected before changing the OR register bit and
configuring the appropriate sensitivity again.
Caution:
In case a pin level change occurs during these operations (asynchronous signal input), as
interrupts are generated according to the current sensitivity, it is advised to disable all
interrupts before and to reenable them after the complete previous sequence in order to
avoid an external interrupt occurring on the unwanted edge.
This corresponds to the following steps:
a)
Set the interrupt mask with the SIM instruction (in cases where a pin level change
could occur)
b)
Select rising edge
a)
Enable the external interrupt through the OR register
a)
Select the desired sensitivity if different from rising edge
a)
Reset the interrupt mask with the RIM instruction (in cases where a pin level
change could occur)
2. To disable an external interrupt:
a)
10.2.2
Set the interrupt mask with the SIM instruction SIM (in cases where a pin level
change could occur)
b)
Select falling edge
c)
Disable the external interrupt through the OR register
a)
Select rising edge
a)
Reset the interrupt mask with the RIM instruction (in cases where a pin level
change could occur)
Output modes
Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the
I/O through the latch. Reading the DR bits returns the previously stored value.
If an OR bit is available, different output modes can be selected by software: push-pull or
open-drain. Refer to I/O Port Implementation section for configuration.
Table 22.
DR Value and output pin status
DR
Push-Pull
Open-Drain
0
VOL
VOL
1
VOH
Floating
71/188
I/O ports
10.2.3
ST7LITE49M
Alternate functions
Many ST7s I/Os have one or more alternate functions. These may include output signals
from, or input signals to, on-chip peripherals.Table 2 describes which peripheral signals can
be input/output to which ports.
A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the
on-chip peripheral as an output (enable bit in the peripheral’s control register). The
peripheral configures the I/O as an output and takes priority over standard I/O programming.
The I/O’s state is readable by addressing the corresponding I/O data register.
Configuring an I/O as floating enables alternate function input. It is not recommended to
configure an I/O as pull-up as this will increase current consumption. Before using an I/O as
an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur.
Configure an I/O as input floating for an on-chip peripheral signal which can be input and
output.
Caution:
I/Os which can be configured as both an analog and digital alternate function need special
attention. The user must control the peripherals so that the signals do not arrive at the same
time on the same pin. If an external clock is used, only the clock alternate function should be
employed on that I/O pin and not the other alternate function.
Figure 34. I/O port general block diagram
ALTERNATE
OUTPUT
REGISTER
ACCESS
From on-chip peripheral
1
VDD
0
ALTERNATE
ENABLE
BIT
P-BUFFER
(see table below)
PULL-UP
(see table below)
DR
VDD
DDR
PULL-UP
CONDITION
DATA BUS
OR
PAD
If implemented
OR SEL
N-BUFFER
DIODES
(see table below)
DDR SEL
DR SEL
CMOS
SCHMITT
TRIGGER
1
0
EXTERNAL
INTERRUPT
REQUEST (eix)
72/188
ANALOG
INPUT
ALTERNATE
INPUT
Combinational
Logic
SENSITIVITY
SELECTION
To on-chip peripheral
FROM
OTHER
BITS Note: Refer to the Port Configuration
table for device specific information.
ST7LITE49M
I/O ports
Table 23.
I/O port mode options(1)
Diodes
Configuration mode
Pull-Up
Floating with/without Interrupt
Off
Pull-up with Interrupt
On
Input
P-Buffer
to VDD
to VSS
On
On
Off
Push-pull
Output
On
Off
Open Drain (logic level)
Off
1. Off means implemented not activated, On means implemented and activated.
Table 24.
I/O port configuration
Hardware configuration
DR REGISTER ACCESS
DR
REGISTER
INPUT (1)
PAD
W
DATA BUS
R
ALTERNATE INPUT
To on-chip peripheral
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (eix)
INTERRUPT COMBINATIONAL POLARITY
LOGIC SELECTION
CONDITION
PUSH-PULL OUTPUT(2)
OPEN-DRAIN OUTPUT(2)
ANALOG INPUT
DR REGISTER ACCESS
PAD
DR
REGISTER
R/W
DATA BUS
DR REGISTER ACCESS
PAD
DR
REGISTER
ALTERNATE
ENABLE
BIT
R/W
DATA BUS
ALTERNATE
OUTPUT
From on-chip peripheral
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
73/188
I/O ports
10.2.4
ST7LITE49M
Analog alternate function
Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled
by the ADC registers) switches the analog voltage present on the selected pin to the
common analog rail, connected to the ADC input.
Analog Recommendations
Do not change the voltage level or loading on any I/O while conversion is in progress. Do not
have clocking pins located close to a selected analog pin.
Caution:
The analog input voltage level must be within the limits stated in the absolute maximum
ratings.
10.3
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific I/O port features such as ADC input or open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 35.
Other transitions are potentially risky and should be avoided, since they may present
unwanted side-effects such as spurious interrupt generation.
Figure 35. Interrupt I/O port state transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
XX
10.4
= DDR, OR
Unused I/O pins
Unused I/O pins must be connected to fixed voltage levels. Refer to Section 13.9: I/O port
pin characteristics.
10.5
Low power modes
s
Table 25.
74/188
Effect of low power modes on I/O ports
Mode
Description
Wait
No effect on I/O ports. External interrupts cause the device to exit from Wait
mode.
Halt
No effect on I/O ports. External interrupts cause the device to exit from Halt
mode.
ST7LITE49M
10.6
I/O ports
Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM
instruction).
Table 26.
Description of interrupt events
Interrupt Event
Event flag
Enable
Control bit
Exit from
Wait
Exit from
Halt
External interrupt on selected
external event
-
DDRx
ORx
Yes
Yes
See application notes AN1045 software implementation of I2C bus master, and AN1048 software LCD driver
10.7
Device-specific I/O port configuration
The I/O port register configurations are summarised in Section 10.7.1: Standard ports and
Section 10.7.2: Other ports.
10.7.1
Standard ports
Table 27.
10.7.2
PA5:0, PB7:0, PC7:4 and PC2:0 pins
Mode
DDR
OR
floating input
0
0
pull-up interrupt input
0
1
open drain output
1
0
push-pull output
1
1
Mode
DDR
OR
floating input
0
0
interrupt input
0
1
open drain output
1
0
push-pull output
1
1
Other ports
Table 28.
PA7:6 pins
75/188
I/O ports
ST7LITE49M
M
Table 29.
Table 30.
PC3 pins
Mode
DDR
OR
floating input
0
0
pull-up input
0
1
open drain output
1
0
push-pull output
1
1
Port configuration
Input
Port
Output
Pin name
OR = 0
OR = 1
OR = 0
OR = 1
PA5:0
floating
pull-up interrupt
open drain
push-pull
PA7:6
floating
interrupt
Port B
PB7:0
floating
pull-up interrupt
open drain
push-pull
floating
pull-up interrupt
open drain
push-pull
Port C
PC7:4,
PC2:0
PC3
floating
pull-up
open drain
push-pull
Port A
Table 31.
Address
true open drain
I/O port register mapping and reset values
Register
label
7
6
5
4
3
2
1
0
0000h
PADR
Reset Value
MSB
0
0
0
0
0
0
0
LSB
0
0001h
PADDR
Reset Value
MSB
0
0
0
0
0
0
0
LSB
0
0002h
PAOR
Reset Value
MSB
0
0
0
0
0
0
0
LSB
0
0003h
PBDR
Reset Value
MSB
0
0
0
0
0
0
0
LSB
0
0004h
PBDDR
Reset Value
MSB
0
0
0
0
0
0
0
LSB
0
0005h
PBOR
Reset Value
MSB
0
0
0
0
0
0
0
LSB
0
0006h
PCDR
Reser Value
MSB
0
0
0
0
0
0
0
LSB
0
0007h
PCDDR
Reset Value
MSB
0
0
0
0
0
0
0
LSB
0
0008h
PCOR
Reset Value
MSB
0
0
0
0
1
0
0
LSB
0
(Hex.)
76/188
ST7LITE49M
On-chip peripherals
11
On-chip peripherals
11.1
Watchdog timer (WDG)
11.1.1
Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before the T6 bit becomes cleared.
11.1.2
11.1.3
Main features
●
Programmable free-running downcounter (64 increments of 16000 CPU cycles)
●
Programmable reset
●
Reset (if watchdog activated) when the T6 bit reaches zero
●
Optional reset on HALT instruction (configurable by option byte)
●
Hardware Watchdog selectable by option byte
Functional description
The counter value stored in the CR register (bits T[6:0]), is decremented every 16000
machine cycles, and the length of the timeout period can be programmed by the user in 64
increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the RESET
pin for typically 30µs.
Figure 36. Watchdog block diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
WDGA
T6
T5
T4
T3
T2
T1
T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER
÷16000
77/188
On-chip peripherals
ST7LITE49M
The application program must write in the CR register at regular intervals during normal
operation to prevent an MCU reset. This downcounter is free-running: it counts down even if
the watchdog is disabled. The value to be stored in the CR register must be between FFh
and C0h (see Table 32: Watchdog timing):
●
The WDGA bit is set (watchdog enabled)
●
The T6 bit is set to prevent generating an immediate reset
●
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset.
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the watchdog is activated, the HALT instruction will generate a Reset.
Watchdog timing(1)(2)
Table 32.
fCPU = 8MHz
WDG
counter code
min
[ms]
max
[ms]
C0h
1
2
FFh
127
128
1. The timing variation shown in Table 32 is due to the unknown status of the prescaler when writing to the
CR register.
2. The number of CPU clock cycles applied during the Reset phase (256 or 4096) must be taken into account
in addition to these timings.
11.1.4
Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the CR is not used.
Refer to the option byte description in Section 14 on page 175.
Using Halt mode with the WDG (WDGHALT option)
If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
Same behaviour in active-halt mode.
11.1.5
Interrupts
None.
78/188
ST7LITE49M
11.1.6
On-chip peripherals
Register description
Control register (WDGCR)
Reset value: 0111 1111 (7Fh)
7
WDGA
0
T6
T5
T4
T3
T2
T1
T0
Read/Write
Bit 7 = WDGA Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1,
the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note:
This bit is not used if the hardware watchdog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB)
These bits contain the decremented value. A reset is produced when it rolls over from
40h to 3Fh (T6 becomes cleared).
Table 33.
Address
(Hex.)
0033h
Watchdog timer register mapping and reset values
Register
label
7
6
5
4
3
2
1
0
WDGCR
Reset
Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
79/188
On-chip peripherals
ST7LITE49M
11.2
Dual 12-bit autoreload timer
11.2.1
Introduction
The 12-bit Autoreload timer can be used for general-purpose timing functions. It is based on
one or two free-running 12-bit upcounters with an Input Capture register and four PWM
output channels. There are 7 external pins:
11.2.2
80/188
●
Four PWM outputs
●
ATIC/LTIC pins for the Input Capture function
●
BREAK pin for forcing a break condition on the PWM outputs
Main features
●
Single Timer or Dual Timer mode with two 12-bit upcounters (CNTR1/CNTR2) and two
12-bit autoreload registers (ATR1/ATR2)
●
Maskable overflow interrupts
●
PWM mode
–
Generation of four independent PWMx signals
–
Dead time generation for Half bridge driving mode with programmable dead time
–
Frequency 2kHz-4MHz (@ 8 MHz fCPU)
–
Programmable duty-cycles
–
Polarity control
–
Programmable output modes
●
Output Compare mode
●
Input Capture mode
–
12-bit Input Capture register (ATICR)
–
Triggered by rising and falling edges
–
Maskable IC interrupt
–
Long range Input Capture
●
Internal/External Break control
●
Flexible Clock control
●
One Pulse mode on PWM2/3
●
Force update
ST7LITE49M
On-chip peripherals
Figure 37. Single Timer mode (ENCNTR2=0)
ATIC
12-bit Input Capture
Edge Detection Circuit
Output Compare
PWM0 Duty Cycle Generator
OE0
Dead Time
Generator
OE1
DTE bit
OE2
12-Bit Autoreload register 1
PWM2 Duty Cycle Generator
12-Bit Upcounter 1
PWM0
Break Function
PWM1 Duty Cycle Generator
CMP
Interrupt
OE3
PWM3 Duty Cycle Generator
PWM1
PWM2
PWM3
OVF1 interrupt
BPEN bit
Clock
Control
OFF
fCPU
1 ms from
Lite timer
Figure 38. Dual Timer mode (ENCNTR2=1)
ATIC
12-bit Input Capture
Edge Detection Circuit
Output Compare
12-Bit Autoreload register 1
PWM1 Duty Cycle Generator
OVF1 interrupt
OVF2 interrupt
12-Bit Upcounter 2
OE0
Dead Time
Generator
OE1
DTE bit
OE2
PWM2 Duty Cycle Generator
PWM3 Duty Cycle Generator
One Pulse
mode
PWM0
Break Function
12-Bit Upcounter 1
PWM0 Duty Cycle Generator
CMP
Interrupt
OE3
PWM1
PWM2
PWM3
12-Bit Autoreload register 2
Output Compare
Clock
Control
OP_EN bit
BPEN bit
OFF
fCPU
CMP Interrupt
1 ms from
Lite timer
LTIC
81/188
On-chip peripherals
11.2.3
ST7LITE49M
Functional description
PWM mode
This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx
output pins.
●
PWM frequency
The four PWM signals can have the same frequency (fPWM) or can have two different
frequencies. This is selected by the ENCNTR2 bit which enables Single Timer or Dual
Timer mode (see Figure 37 and Figure 38). The frequency is controlled by the counter
period and the ATR register value. In Dual Timer mode, PWM2 and PWM3 can be
generated with a different frequency controlled by CNTR2 and ATR2.
f PWM = f COUNTER ⁄ ( 4096 – ATR )
Following the above formula, if fCOUNTER equals 4 Mhz, the maximum value of fPWM is
2 MHz (ATR register value = 4094), and the minimum value is 1 KHz (ATR registe r
value = 0).
The maximum value of ATR is 4094 because it must be lower than the DC4R value
which must be 4095 in this case.
To update the DCRx registers at 32MHz, the following precautions must be taken:
●
–
If the PWM frequency is < 1MHz and the TRANx bit is set asynchronously, it
should be set twice after a write to the DCRx registers.
–
If the PWM frequency is > 1MHz, the TRANx bit should be set along with
FORCEx bit with the same instruction (use a load instruction and not 2 bset
instructions).
Duty cycle
The duty cycle is selected by programming the DCRx registers. These are preload
registers. The DCRx values are transferred in Active duty cycle registers after an
overflow event if the corresponding transfer bit (TRANx bit) is set.
The TRAN1 bit controls the PWMx outputs driven by counter 1 and the TRAN2 bit
controls the PWMx outputs driven by counter 2.
PWM generation and output compare are done by comparing these active DCRx
values with the counter.
The maximum available resolution for the PWMx duty cycle is:
Resolution = 1 ⁄ ( 4096 – ATR )
where ATR is equal to 0. With this maximum resolution, 0% and 100% duty cycle can
be obtained by changing the polarity.
At reset, the counter starts counting from 0.
When a upcounter overflow occurs (OVF event), the preloaded Duty cycle values are
transferred to the active Duty Cycle registers and the PWMx signals are set to a high
level. When the upcounter matches the active DCRx value the PWMx signals are set to
a low level. To obtain a signal on a PWMx pin, the contents of the corresponding active
DCRx register must be greater than the contents of the ATR register.
82/188
ST7LITE49M
On-chip peripherals
The maximum value of ATR is 4094 because it must be lower than the DCR value
which must be 4095 in this case.
Polarity inversion
●
The polarity bits can be used to invert any of the four output signals. The inversion is
synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2
register is set (reset value). See Figure 39.
Figure 39. PWM polarity inversion
inverter
PWMx
PIN
PWMx
PWMxCSR register
OPx
TRANx
DFF
ATCSR2 register
counter
overflow
The Data Flip Flop (DFF) applies the polarity inversion when triggered by the counter
overflow input.
Output control
●
The PWMx output signals can be enabled or disabled using the OEx bits in the
PWMCR register.
Figure 40. PWM function
COUNTER
4095
DUTY CYCLE
REGISTER
(DCRx)
AUTO-RELOAD
REGISTER
(ATR)
PWMx OUTPUT
000
t
WITH OE=1
AND OPx=0
WITH OE=1
AND OPx=1
83/188
On-chip peripherals
ST7LITE49M
Figure 41. PWM signal from 0% to 100% duty cycle
fCOUNTER
ATR= FFDh
PWMx OUTPUT
WITH MOD00=1
AND OPx=1
PWMx OUTPUT
WITH MOD00=1
AND OPx=0
COUNTER
FFDh
FFEh
FFFh
FFDh
FFEh
FFFh
FFDh
FFEh
DCRx=000h
DCRx=FFDh
DCRx=FFEh
DCRx=000h
t
Dead time generation
A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is
required for half-bridge driving where PWM signals must not be overlapped. The nonoverlapping PWM0/PWM1 signals are generated through a programmable dead time by
setting the DTE bit.
Dead time = DT [ 6:0 ] × Tcounter1
DTGR[7:0] is buffered inside so as to avoid deforming the current PWM cycle. The DTGR
effect will take place only after an overflow.
Note:
84/188
1
Dead time is generated only when DTE=1 and DT[6:0] ≠ 0. If DTE is set and DT[6:0]=0,
PWM output signals will be at their reset state.
2
Half Bridge driving is possible only if polarities of PWM0 and PWM1 are not inverted, i.e. if
OP0 and OP1 are not set. If polarity is inverted, overlapping PWM0/PWM1 signals will be
generated.
3
Dead Time generation does not work at 1msec timebase.
ST7LITE49M
On-chip peripherals
Figure 42. Dead time generation
Tcounter1
CK_CNTR1
CNTR1
DCR0
DCR0+1
OVF
ATR1
if DTE = 0
counter = DCR0
PWM 0
counter = DCR1
PWM 1
if DTE = 1
Tdt
PWM 0
Tdt
PWM 1
Tdt = DT[6:0] x Tcounter1
In the above example, when the DTE bit is set:
●
PWM goes low at DCR0 match and goes high at ATR1+Tdt
●
PWM1 goes high at DCR0+Tdt and goes low at ATR match.
With this programmable delay (Tdt), the PWM0 and PWM1 signals which are generated are
not overlapped.
Break function
The break function can be used to perform an emergency shutdown of the application being
driven by the PWM signals.
The break function is activated by the external BREAK pin. This can be selected by using
the BRSEL bit in BREAKCR register. In order to use the break function it must be previously
enabled by software setting the BPEN bit in the BREAKCR register.
The Break active level can be programmed by the BREDGE bit in the BREAKCR register.
When an active level is detected on the BREAK pin, the BA bit is set and the break function
is activated. In this case, the PWM signals are forced to BREAK value if respective OEx bit
is set in PWMCR register.
Software can set the BA bit to activate the break function without using the BREAK pin. The
BREN1 and BREN2 bits in the BREAKEN register are used to enable the break activation
on the 2 counters respectively. In Dual Timer mode, the break for PWM2 and PWM3 is
enabled by the BREN2 bit. In Single Timer mode, the BREN1 bit enables the break for all
PWM channels.
85/188
On-chip peripherals
ST7LITE49M
When a break function is activated (BA bit =1 and BREN1/BREN2 =1):
●
The break pattern (PWM[3:0] bits in the BREAKCR) is forced directly on the PWMx
output pins if respective OEx is set. (after the inverter).
●
The 12-bit PWM counter CNTR1 is put to its reset value, i.e. 00h (if BREN1 = 1).
●
The 12-bit PWM counter CNTR2 is put to its reset value,i.e. 00h (if BREN2 = 1).
●
ATR1, ATR2, Preload and Active DCRx are put to their reset values.
●
Counters stop counting.
When the break function is deactivated after applying the break (BA bit goes from 1 to 0 by
software), Timer takes the control of PWM ports.
Figure 43. Block diagram of break function
BRSEL
BREDGE BREAKCR register
BREAK pin
Level
Selection
BREAKCR register
BA
BPEN
OEx
PWM3 PWM2 PWM1 PWM0
PWM0
PWM1
(Inverters)
PWM0
PWM1
PWM2
PWM2
PWM3
PWM3
BREAKEN register
PWM0/1 Break Enable
BREN2 BREN1
PWM2/3 Break Enable
ENCNTR2 bit
Output compare mode
To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers.
When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and
DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is
generated if the CMPIE bit is set.
In Single Timer mode the output compare function is performed only on CNTR1. The
difference between both the modes is that, in Single Timer mode, CNTR1 can be compared
with any of the four DCR registers, and in Dual Timer mode, CNTR1 is compared with DCR0
or DCR1 and CNTR2 is compared with DCR2 or DCR3.
Note:
86/188
1
The output compare function is only available for DCRx values other than 0 (reset value).
2
Duty cycle registers are buffered internally. The CPU writes in Preload Duty Cycle registers
and these values are transferred in Active Duty Cycle registers after an overflow event if the
corresponding transfer bit (TRANx bit) is set. Output compare is done by comparing these
active DCRx values with the counters.
ST7LITE49M
On-chip peripherals
Figure 44. Block diagram of output compare mode (single timer)
DCRx
PRELOAD DUTY CYCLE REG0/1/2/3
(ATCSR2) TRAN1
(ATCSR) OVF
ACTIVE DUTY CYCLE REGx
OUTPUT COMPARE CIRCUIT
CNTR1
COUNTER 1
CMPFx (PWMxCSR)
CMP
INTERRUPT REQUEST
CMPIE (ATCSR)
Input Capture mode
The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter
CNTR1 after a rising or falling edge is detected on the ATIC pin. When an Input Capture
occurs, the ICF bit is set and the ATICR register contains the value of the free running
upcounter. An IC interrupt is generated if the ICIE bit is set. The ICF bit is reset by reading
the ATICRH/ATICRL register when the ICF bit is set. The ATICR is a read only register and
always contains the free running upcounter value which corresponds to the most recent
Input Capture. Any further Input Capture is inhibited while the icf bit is set.
Figure 45. Block diagram of Input Capture mode
ATIC
12-BIT INPUT CAPTURE REGISTER
ATICR
IC INTERRUPT
REQUEST
ATCSR
ICF
ICIE
CK1
CK0
fLTIMER
(1 ms
timebase
@ 8MHz)
fCPU
32MHz
OFF
12-BIT UPCOUNTER1
CNTR1
ATR1
12-BIT AUTORELOAD REGISTER
87/188
On-chip peripherals
ST7LITE49M
Figure 46. Input Capture timing diagram
fCOUNTER
COUNTER1
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
ATIC PIN
INTERRUPT
ATICR READ
INTERRUPT
ICF FLAG
xxh
09h
04h
t
Long range input Capture
Pulses that last more than 8 µs can be measured with an accuracy of 4 µs if fOSC equals 8
MHz in the following conditions:
●
The 12-bit AT4 timer is clocked by the Lite timer (RTC pulse: CK[1:0] = 01 in the ATCSR
register)
●
The ICS bit in the ATCSR2 register is set so that the LTIC pin is used to trigger the AT4
timer capture.
●
The signal to be captured is connected to LTIC pin
●
Input Capture registers LTICR, ATICRH and ATICRL are read
This configuration allows to cascade the Lite timer and the 12-bit AT4 timer to get a 20-bit
Input Capture value. Refer to Figure 47.
Figure 47. Long range Input Capture block diagram
LTICR
8-bit Input Capture register
fOSC/32
8 LSB bits
8-bit Timebase Counter1
LITE TIMER
20
cascaded
bits
12-Bit ARTIMER
ATR1
12-bit AutoReload register
ICS
LTIC
1
ATIC
88/188
0
fLTIMER
fcpu
32MHz
OFF
CNTR1
12-bit Upcounter1
ATICR
12-bit Input Capture register
12 MSB bits
ST7LITE49M
On-chip peripherals
Since the Input Capture flags (ICF) for both timers (AT4 timer and LT timer) are set when
signal transition occurs, software must mask one interrupt by clearing the corresponding
ICIE bit before setting the ICS bit.
If the ICS bit changes (from 0 to 1 or from 1 to 0), a spurious transition might occur on the
Input Capture signal because of different values on LTIC and ATIC. To avoid this situation, it
is recommended to do as follows:
1.
First, reset both ICIE bits.
2.
Then set the ICS bit.
3.
Reset both ICF bits.
4.
And then set the ICIE bit of desired interrupt.
Computing a pulse length in long Input Capture mode is not straightforward since both
timers are used. The following steps are required:
1.
2.
At the first Input Capture on the rising edge of the pulse, we assume that values in the
registers are the following:
–
LTICR = LT1
–
ATICRH = ATH1
–
ATICRL = ATL1
–
Hence ATICR1 [11:0] = ATH1 & ATL1. Refer to Figure 48 on page 90.
At the second Input Capture on the falling edge of the pulse, we assume that the values
in the registers are as follows:
–
LTICR = LT2
–
ATICRH = ATH2
–
ATICRL = ATL2
–
Hence ATICR2 [11:0] = ATH2 & ATL2.
Now pulse width P between first capture and second capture is given by:
P = decimal × ( F9 – LT1 + LT2 + 1 ) × 0.004ms
+ decimal ( ( FFF × N ) + N + ATICR2 – ATICR1 – 1 ) × 1ms
where N is the number of overflows of 12-bit CNTR1.
89/188
On-chip peripherals
ST7LITE49M
Figure 48. Long range Input Capture timing diagram
fOSC/32
TB Counter1
CNTR1
F9h
00h
___
LT1
F9h
00h
___
___
ATH1 & ATL1
___
___
LT2
___
___
ATH2 & ATL2
LTIC
LTICR
00h
LT1
LT2
ATICRH
0h
ATH1
ATH2
ATICRL
00h
ATL1
ATL2
ATICR = ATICRH[3:0] & ATICRL[7:0]
90/188
ST7LITE49M
On-chip peripherals
One Pulse mode
One Pulse mode can be used to control PWM2/3 signal with an external LTIC pin. This
mode is available only in Dual Timer mode i.e. only for CNTR2, when the OP_EN bit in
PWM3CSR register is set.
One Pulse mode is activated by the external LTIC input. The active edge of the LTIC pin is
selected by the OPEDGE bit in the PWM3CSR register.
After getting the active edge of the LTIC pin, CNTR2 is reset (000h) and PWM3 is set to
high. CNTR2 starts counting from 000h, when it reaches the active DCR3 value then PWM3
goes low. Till this time, any further transitions on the LTIC signal will have no effect. If there
are LTIC transistions after CNTR2 reaches DCR3 value, CNTR2 is reset again and PWM3
goes high.
If there is no LTIC active edge, CNTR2 counts until it reaches the ATR2 value, then it is reset
again and PWM3 is set to high. The counter again starts couting from 000h, when it reaches
the active DCR3 value PWM3 goes low, the counter counts until it reaches ATR2, it resets
and PWM3 is set to high and so on.
The same operation applies for PWM2, but in this case the comparison is done on DCR2.
OP_EN and OPEDGE bits take effect on the fly and are not synchronized with Counter 2
overflow. The output bit OP2/3 can be used to inverse the polarity of PWM2/3 in one-pulse
mode. The update of these bits (OP2/3) is synchronized with the counter 2 overflow, they
will be updated if the TRAN2 bit is set.
The time taken from activation of LTIC input and CNTR2 reset is between 1 and 2 tcpu
cycles, i.e. 125n to 250ns (with 8MHz fcpu).
Litetimer Input Capture interrupt should be disabled while 12-bit ARtimer is in One Pulse
mode. This is to avoid spurious interrupts.
The priority of the various conditions for PWM3 is the following: Break > one-pulse mode
with active LTIC edge > Forced overflow by s/w > one-pulse mode without active LTIC edge
> normal PWM operation.
It is possible to update DCR2/3 and OP2/3 at the counter 2 reset, the update is
synchronized with the counter reset. This is managed by the overflow interrupt which is
generated if counter is reset either due to ATR match or active pulse at LTIC pin. DCR2/3
and OP2/3 update in one-pulse mode is performed dynamically using a software force
update. DCR3 update in this mode is not synchronized with any event. That may lead to a
longer next PWM3 cycle duration than expected just after the change.
In One Pulse mode ATR2 value must be greater than DCR2/3 value for PWM2/3. (opposite
to normal PWM mode).
If there is an active edge on the LTIC pin after the counter has reset due to an ATR2 match,
then the timer again gets reset and appears as modified Duty cycle depending on whether
the new DCR value is less than or more than the previous value.
The TRAN2 bit should be set along with the FORCE2 bit with the same instruction after a
write to the DCR register.
ATR2 value should be changed after an overflow in one pulse mode to avoid any irregular
PWM cycle.
When exiting from one pulse mode, the OP_EN bit in the PWM3CSR register should be
reset first and then the ENCNTR2 bit (if counter 2 must be stopped).
91/188
On-chip peripherals
ST7LITE49M
How to enter One Pulse mode
The steps required to enter One Pulse mode are the following:
1.
Load ATR2H/ATR2L with required value.
2.
Load DCR3H/DCR3L for PWM3. ATR2 value must be greater than DCR3.
3.
Set OP3 in PWM3CSR if polarity change is required.
4.
Select CNTR2 by setting ENCNTR2 bit in ATCSR2.
5.
Set TRAN2 bit in ATCSR2 to enable transfer.
6.
"Wait for Overflow" by checking the OVF2 flag in ATCSR2.
7.
Select counter clock using CK<1:0> bits in ATCSR.
8.
Set OP_EN bit in PWM3CSR to enable one-pulse mode.
9.
Enable PWM3 by OE3 bit of PWMCR.
The "Wait for Overflow" in step 6 can be replaced by a forced update.
Follow the same procedure for PWM2 with the bits corresponding to PWM2.
Note:
When break is applied in one-pulse mode, CNTR2, DCR2/3 & ATR2 registers are reset. So,
these registers have to be intialised again when break is removed.
Figure 49. Block diagram of One Pulse mode
LTIC pin
Edge
Selection
12-bit Upcounter 2
OPEDGE OP_EN
PWM3CSR register
PWM
Generation
12-bit AutoReload register 2
PWM2/3
12-bit Active DCR2/3
OP2/3
Figure 50. One Pulse mode and PWM timing diagram
OP_EN=1
fcounter2
CNTR2
000
DCR2/3
ATR2
DCR2/3
000
DCR2/3
ATR2
DCR2/3
ATR2
LTIC
OP_EN=0 1)
PWM2/3
fcounter2
CNTR2
OVF
OVF
OVF
LTIC
PWM2/3
Note 1:
92/188
When OP_EN=0, LTIC edges are not taken into account as the timer runs in PWM mode.
ATR2
000
ST7LITE49M
On-chip peripherals
Figure 51. Dynamic DCR2/3 update in One Pulse mode
fcounter2
CNTR2
000
FFF
000
(DCR3)old
(DCR3)new
ATR2
000
OP_EN=1
LTIC
FORCE2
TRAN2
DCR2/3
(DCR2/3)old
(DCR2/3)new
PWM2/3
extra PWM3 period due to DCR3
update dynamically in one-pulse
mode.
93/188
On-chip peripherals
ST7LITE49M
Force update
In order not to wait for the counterx overflow to load the value into active DCRx registers, a
programmable counterx overflow is provided. For both counters, a separate bit is provided
which when set, make the counters start with the overflow value, i.e. FFFh. After overflow,
the counters start counting from their respective auto reload register values.
These bits are FORCE1 and FORCE2 in the ATCSR2 register. FORCE1 is used to force an
overflow on Counter 1 and, FORCE2 is used for Counter 2. These bits are set by software
and reset by hardware after the respective counter overflow event has occurred.
This feature can be used at any time. All related features such as PWM generation, Output
Compare, Input Capture, One-pulse (refer to Figure 51: Dynamic DCR2/3 update in One
Pulse mode) etc can be used this way.
Figure 52. Force Overflow timing diagram
fCNTRx
FORCEx
CNTRx
E03
FFF
E04
ARRx
FORCE2 FORCE1
ATCSR2 register
11.2.4
Low power modes
Table 34.
11.2.5
Mode
Description
Wait
No effect on AT timer
Halt
AT timer halted.
Interrupts
Table 35.
Note:
94/188
Effect of low power modes on autoreload timer
Description of interrupt events
Interrupt Event
Event
Flag
Enable
Control bit
Exit from
Wait
Exit from
Halt
Exit from
Active-Halt
Overflow Event
OVF1
OVIE1
Yes
No
Yes
AT4 IC Event
ICF
ICIE
Yes
No
No
Overflow Event2
OVF2
OVIE2
Yes
No
No
The AT4 IC is connected to an interrupt vector. The OVF event is mapped on a separate
vector (see Interrupts chapter).
They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt
mask in the CC register is reset (RIM instruction).
ST7LITE49M
11.2.6
On-chip peripherals
Register description
Timer Control Status register (ATCSR)
Reset value: 0x00 0000 (x0h)
7
0
0
ICF
ICIE
CK1
CK0
OVF1
OVFIE1
CMPIE
Read / Write
Bit 7 = Reserved
Bit 6 = ICF Input Capture flag
This Bit is set by hardware and cleared by software by reading the ATICR register (a
read access to ATICRH or ATICRL clears this flag). Writing to this bit does not change
the bit value.
0: No Input Capture
1: An Input Capture Has Occurred
Bit 5 = ICIE IC Interrupt Enable bit
This bit is set and cleared by software.
0: Input Capture Interrupt Disabled
1: Input Capture Interrupt Enabled
Bits 4:3 = CK[1:0] Counter Clock Selection bits
These bits are set and cleared by software and cleared by hardware after a reset. they
select the clock frequency of the counter.
Table 36.
Counter clock selection
Counter clock selection
CK1
CK0
OFF
0
0
selection forbidden
1
1
fLTIMER (1 ms timebase @ 8 MHz)
0
1
fCPU
1
0
Bit 2 = OVF1 Overflow flag
This bit is set by hardware and cleared by software by reading the ATCSR register. It
indicates the transition of the Counter1 CNTR1 from FFFh to ATR1 value.
0: No Counter Overflow Occurred
1: Counter Overflow Occurred
Bit 1 = OVFIE1 Overflow Interrupt Enable bit
This bit is read/write by software and cleared by hardware after a reset.
0: Overflow Interrupt Disabled.
1: Overflow Interrupt Enabled.
95/188
On-chip peripherals
ST7LITE49M
Bit 0 = CMPIE Compare Interrupt Enable bit
This bit is read/write by software and cleared by hardware after a reset. it can be used
to mask the interrupt generated when any of the cmpfx bit is set.
0: Output Compare Interrupt Disabled.
1: Output Compare Interrupt Enabled.
Counter register 1 High (CNTR1H)
Reset value: 0000 0000 (00h)
15
0
8
0
0
CNTR1_
11
0
CNTR1_
10
CNTR1_9
CNTR1_8
Read only
Counter register 1 Low (CNTR1L)
Reset value: 0000 0000 (00h)
7
CNTR1_7
0
CNTR1_6
CNTR1_5
CNTR1_4
CNTR1_3
CNTR1_2
CNTR1_1
CNTR1_0
Read only
Bits 15:12 = Reserved
Bits 11:0 = CNTR1[11:0] Counter value
This 12-bit register is read by software and cleared by hardware after a reset. The
counter CNTR1 increments continuously as soon as a counter clock is selected. To
obtain the 12-bit value, software should read the counter value in two consecutive read
operations. As there is no latch, it is recommended to read LSB first. In this case,
CNTR1H can be incremented between the two read operations and to have an
accurate result when ftimer=fCPU, special care must be taken when CNTR1L values
close to FFh are read.
When a counter overflow occurs, the counter restarts from the value specified in the
ATR1 register.
Autoreload register (ATR1H)
Reset value: 0000 0000 (00h)
15
0
8
0
0
0
ATR11
Read/write
96/188
ATR10
ATR9
ATR8
ST7LITE49M
On-chip peripherals
Autoreload register (ATR1L)
Reset value: 0000 0000 (00h)
7
ATR7
0
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
Read/write
Bits 11:0 = ATR1[11:0] Autoreload register 1:
This is a 12-bit register which is written by software. The ATR1 register value is
automatically loaded into the upcounter CNTR1 when an overflow occurs. The register
value is used to set the PWM frequency.
PWM Output Control register (PWMCR)
Reset value: 0000 0000 (00h)
7
0
0
OE3
0
OE2
0
OE1
0
OE0
Read/write
Bits 7:0 = OE[3:0] PWMx output enable bits
These bits are set and cleared by software and cleared by hardware after a reset.
0: PWM mode disabled. PWMx Output Alternate function disabled (I/O pin free for
general purpose I/O)
1: PWM mode enabled
PWMX Control Status register (PWMxCSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
OP_EN
OPEDGE
OPx
CMPFx
Read/write
Bits 7:4= Reserved, must be kept cleared.
Bit 3 = OP_EN One Pulse Mode Enable bit
This bit is read/write by software and cleared by hardware after a reset. This bit enables
the One Pulse feature for PWM2 and PWM3 (only available for PWM3CSR)
0: One Pulse mode disable for PWM2/3.
1: One Pulse mode enable for PWM2/3.
Bit 2 = OPEDGE One Pulse Edge Selection bit
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the polarity of the LTIC signal for One Pulse feature. This bit will be effective only if
OP_EN bit is set (only available for PWM3CSR)
0: Falling edge of LTIC is selected.
1: Rising edge of LTIC is selected.
97/188
On-chip peripherals
ST7LITE49M
Bit 1 = OPx PWMx Output Polarity bit
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the polarity of the PWM signal.
0: The PWM signal is not inverted.
1: The PWM signal is inverted.
Bit 0 = CMPFx PWMx Compare flag
This bit is set by hardware and cleared by software by reading the PWMxCSR register.
It indicates that the upcounter value matches the Active DCRx register value.
0: Upcounter value does not match DCRx value.
1: Upcounter value matches DCRx value.
Break Control register (BREAKCR)
Reset value: 0000 0000 (00h)
7
0
0
BREDGE
BA
BPEN
PWM3
PWM2
PWM1
PWM0
Read/write
Bit 7 = Reserved.
Bit 6 = BREDGE Break Input Edge Selection bit
This bit is read/write by software and cleared by hardware after reset. It selects the
active level of Break signal.
0: Low level of Break selected as active level
1: High level of Break selected as active level
Bit 5 = BA Break Active bit
This bit is read/write by software, cleared by hardware after reset and set by hardware
when the active level defined by the BREDGE bit is applied on the BREAK pin. It
activates/deactivates the Break function.
0: Break not active
1: Break active
Bit 4 = BPEN Break Pin Enable bit
This bit is read/write by software and cleared by hardware after Reset.
0: Break pin disabled
1: Break pin enabled
Bits 3:0 = PWM[3:0] Break Pattern bits
These bits are read/write by software and cleared by hardware after a reset. They are
used to force the four PWMx output signals into a stable state when the Break function
is active and corresponding OEx bit is set.
98/188
ST7LITE49M
On-chip peripherals
PWMx Duty Cycle register High (DCRxH)
Reset value: 0000 0000 (00h)
15
0
8
0
0
0
DCR11
DCR10
DCR9
DCR8
Read/write
Bits 15:12 = Reserved.
PWMx Duty Cycle register Low (DCRxL)
Reset value: 0000 0000 (00h)
7
DCR7
0
DCR6
DCR5
DCR4
DCR3
DCR2
DCR1
DCR0
Read/write
Bits 11:0 = DCRx[11:0] PWMx Duty Cycle Value: this 12-bit value is written by software. It
defines the duty cycle of the corresponding PWM output signal (see Figure 40).
In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of
the PWMx output signal (see Figure 40). In Output Compare mode, they define the value to
be compared with the 12-bit upcounter value.
Input Capture register High (ATICRH)
Reset value: 0000 0000 (00h)
15
0
8
0
0
0
ICR11
ICR10
ICR9
ICR8
Read only
Bits 15:12 = Reserved.
99/188
On-chip peripherals
ST7LITE49M
Input Capture register Low (ATICRL)
Reset value: 0000 0000 (00h)
7
ICR7
0
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
ICR0
Read only
Bits 11:0 = ICR[11:0] Input Capture Data.
This is a 12-bit register which is readable by software and cleared by hardware after a
reset. The ATICR register contains captured the value of the 12-bit CNTR1 register
when a rising or falling edge occurs on the ATIC or LTIC pin (depending on ICS).
Capture will only be performed when the ICF flag is cleared.
Break Enable register (BREAKEN)
Reset value: 0000 0011 (03h)
7
0
0
0
0
0
0
0
BREN2
BREN1
Read/write
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = BREN2 Break Enable for Counter 2 bit
This bit is read/write by software. It enables the break functionality for Counter2 if BA bit
is set in BREAKCR. It controls PWM2/3 if ENCNTR2 bit is set.
0: No Break applied for CNTR2
1: Break applied for CNTR2
Bit 0 = BREN1 Break Enable for Counter 1 bit
This bit is read/write by software. It enables the break functionality for Counter1. If BA
bit is set, it controls PWM0/1 by default, and controls PWM2/3 also if ENCNTR2 bit is
reset.
0: No Break applied for CNTR1
1: Break applied for CNTR1
100/188
ST7LITE49M
On-chip peripherals
Timer Control register 2 (ATCSR2)
Reset value: 0000 0011 (03h)
7
FORCE2
0
FORCE1
ICS
OVFIE2
OVF2
ENCNTR2
TRAN2
TRAN1
Read/write
Bit 7 = FORCE2 Force Counter 2 Overflow bit
This bit is read/set by software. When set, it loads FFFh in the CNTR2 register. It is
reset by hardware one CPU clock cycle after counter 2 overflow has occurred.
0 : No effect on CNTR2
1 : Loads FFFh in CNTR2
Note:
This bit must not be reset by software
Bit 6 = FORCE1 Force Counter 1 Overflow bit
This bit is read/set by software. When set, it loads FFFh in CNTR1 register. It is reset
by hardware one CPU clock cycle after counter 1 overflow has occurred.
0 : No effect on CNTR1
1 : Loads FFFh in CNTR1
Note:
This bit must not be reset by software
Bit 5 = ICS Input Capture Shorted bit
This bit is read/write by software. It allows the ATtimer CNTR1 to use the LTIC pin for
long Input Capture.
0 : ATIC for CNTR1 Input Capture
1 : LTIC for CNTR1 Input Capture
Bit 4 = OVFIE2 Overflow interrupt 2 enable bit
This bit is read/write by software and controls the overflow interrupt of counter2.
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
Bit 3 = OVF2 Overflow flag
This bit is set by hardware and cleared by software by reading the ATCSR2 register. It
indicates the transition of the counter2 from FFFh to ATR2 value.
0: No counter overflow occurred
1: Counter overflow occurred
Bit 2 = ENCNTR2 Enable counter2 for PWM2/3
This bit is read/write by software and switches the PWM2/3 operation to the CNTR2
counter. If this bit is set, PWM2/3 will be generated using CNTR2.
0: PWM2/3 is generated using CNTR1.
1: PWM2/3 is generated using CNTR2.
Note:
Counter 2 gets frozen when the ENCNTR2 bit is reset. When ENCNTR2 is set again, the
counter will restart from the last value.
101/188
On-chip peripherals
ST7LITE49M
Bit 1= TRAN2 Transfer enable2 bit
This bit is read/write by software, cleared by hardware after each completed transfer
and set by hardware after reset. It controls the transfers on CNTR2.
It allows the value of the Preload DCRx registers to be transferred to the Active DCRx
registers after the next overflow event.
The OPx bits are transferred to the shadow OPx bits in the same way.
Note:
1
DCR2/3 transfer will be controlled using this bit if ENCNTR2 bit is set.
2
This bit must not be reset by software
Bit 0 = TRAN1 Transfer enable 1 bit
This bit is read/write by software, cleared by hardware after each completed transfer
and set by hardware after reset. It controls the transfers on CNTR1. It allows the value
of the Preload DCRx registers to be transferred to the Active DCRx registers after the
next overflow event.
The OPx bits are transferred to the shadow OPx bits in the same way.
Note:
1
DCR0,1 transfers are always controlled using this bit.
2
DCR2/3 transfer will be controlled using this bit if ENCNTR2 is reset.
3
This bit must not be reset by software
Autoreload register 2 (ATR2H)
Reset value: 0000 0000 (00h)
15
0
8
0
0
0
ATR11
ATR10
ATR9
ATR8
Read/write
Autoreload register (ATR2L)
Reset value: 0000 0000 (00h)
7
ATR7
0
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
Read/write
Bits 11:0 = ATR2[11:0] Autoreload register 2
This is a 12-bit register which is written by software. The ATR2 register value is
automatically loaded into the upcounter CNTR2 when an overflow of CNTR2 occurs. The
register value is used to set the PWM2/PWM3 frequency when ENCNTR2 is set.
102/188
ST7LITE49M
On-chip peripherals
Dead Time Generator register (Dtgr)
Reset value: 0000 0000 (00h)
7
0
DTE
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Read/write
Bit 7 = DTE Dead Time Enable bit
This bit is read/write by software. It enables a dead time generation on PWM0/PWM1.
0: No Dead time insertion.
1: Dead time insertion enabled.
Bits 6:0 = DT[6:0] Dead Time value
These bits are read/write by software. They define the dead time inserted between
PWM0/PWM1. Dead time is calculated as follows:
Dead Time = DT[6:0] x Tcounter1
Note:
If DTE is set and DT[6:0]=0, PWM output signals will be at their reset state.
Table 37.
Register mapping and reset values
Add.
(Hex)
Register
label
7
6
5
4
3
2
1
0
0011
ATCSR
Reset Value
0
ICF
0
ICIE
0
CK1
0
CK0
0
OVF1
0
OVFIE1
0
CMPIE
0
0012
CNTR1H
Reset Value
0
0
0
0
0013
CNTR1L CNTR1_7 CNTR1_8 CNTR1_7 CNTR1_6 CNTR1_3
Reset Value
0
0
0
0
0
0014
ATR1H
Reset Value
0
0
0
0
ATR11
0
ATR10
0
ATR9
0
ATR8
0
0015
ATR1L
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
0016
PWMCR
Reset Value
0
OE3
0
0
OE2
0
0
OE1
0
0
OE0
0
0017
PWM0CSR
Reset Value
0
0
0
0
0
0
OP0
0
CMPF0
0
0018
PWM1CSR
Reset Value
0
0
0
0
0
0
OP1
0
CMPF1
0
0019
PWM2CSR
Reset Value
0
0
0
0
0
0
OP2
0
CMPF2
0
001A
PWM3CSR
Reset Value
0
0
0
0
OP_EN
0
OPEDGE
0
OP3
0
CMPF3
0
001B
DCR0H
Reset Value
0
0
0
0
DCR11
0
DCR10
0
DCR9
0
DCR8
0
CNTR1_11 CNTR1_10 CNTR1_9 CNTR1_8
0
0
0
0
CNTR1_2 CNTR1_1 CNTR1_0
0
0
0
103/188
On-chip peripherals
Table 37.
ST7LITE49M
Register mapping and reset values (continued)
Add.
(Hex)
Register
label
7
6
5
4
3
2
1
0
001C
DCR0L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
001D
DCR1H
Reset Value
0
0
0
0
DCR11
0
DCR10
0
DCR9
0
DCR8
0
001E
DCR1L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
001F
DCR2H
Reset Value
0
0
0
0
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0020
DCR2L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
0021
DCR3H
Reset Value
0
0
0
0
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0022
DCR3L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
0023
ATICRH
Reset Value
0
0
0
0
ICR11
0
ICR10
0
ICR9
0
ICR8
0
0024
ATICRL
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
0025
FORCE2
ATCSR2
Reset Value
0
FORCE1
0
ICS
0
OVFIE2
0
OVF2
0
ENCNTR2
0
TRAN2
1
TRAN1
1
0026
BREAKCR
Reset Value
0
BREDGE
0
BA
0
BPEN
0
PWM3
0
PWM2
0
PWM1
0
PWM0
0
0027
ATR2H
Reset Value
0
0
0
0
ATR11
0
ATR10
0
ATR9
0
ATR8
0
0028
ATR2L
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
0029
DTGR
Reset Value
DTE
0
DT6
0
DT5
0
DT4
0
DT3
0
DT2
0
DT1
0
DT0
0
002A
BREAKEN
Reset Value
0
0
0
0
0
0
BREN2
1
BREN1
1
104/188
ST7LITE49M
On-chip peripherals
11.3
Lite timer 2 (LT2)
11.3.1
Introduction
The Lite timer can be used for general-purpose timing functions. It is based on two freerunning 8-bit upcounters and an 8-bit Input Capture register
11.3.2
Main Features
●
●
Realtime Clock
–
One 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 MHz fOSC)
–
One 8-bit upcounter with autoreload and programmable timebase period from 4µs
to 1.024ms in 4µs increments (@ 8 MHz fOSC)
–
2 Maskable timebase interrupts
Input Capture
–
●
8-bit Input Capture register (LTICR)
Maskable interrupt with wake-up from Halt mode capability
Figure 53. Lite timer 2 Block Diagram
fOSC/32
LTTB2
LTCNTR
Interrupt request
LTCSR2
8-bit TIMEBASE
COUNTER 2
0
0
0
0
0
0
TB2IE TB2F
8
LTARR
fLTIMER
8-bit AUTORELOAD
REGISTER
/2
8-bit TIMEBASE
COUNTER 1
fLTIMER
8
To 12-bit AT TImer
1
0 Timebase
1 or 2 ms
(@ 8 MHz
fOSC)
LTICR
LTIC
8-bit
INPUT CAPTURE
REGISTER
LTCSR1
ICIE
ICF
TB
TB1IE TB1F
LTTB1 INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
105/188
On-chip peripherals
11.3.3
ST7LITE49M
Functional description
Timebase Counter 1
The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it
starts incrementing from 0 at a frequency of fOSC/32. An overflow event occurs when the
counter rolls over from F9h to 00h. If fOSC = 8 MHz, then the time period between two
counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the
LTCSR1 register.
When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is
generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1
register.
Input Capture
The 8-bit Input Capture register is used to latch the free-running upcounter (Counter 1) 1
after a rising or falling edge is detected on the LTIC pin. When an Input Capture occurs, the
ICF bit is set and the LTICR register contains the counter 1 value. An interrupt is generated
if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.
The LTICR is a read-only register and always contains the data from the last Input Capture.
Input Capture is inhibited if the ICF bit is set.
Timebase Counter 2
Counter 2 is an 8-bit autoreload upcounter. It can be read by accessing the LTCNTR
register. After an MCU reset, it increments at a frequency of fOSC/32 starting from the value
stored in the LTARR register. A counter overflow event occurs when the counter rolls over
from FFh to the LTARR reload value. Software can write a new value at any time in the
LTARR register, this value will be automatically loaded in the counter when the next overflow
occurs.
When Counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an
interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software
reading the LTCSR2 register.
Figure 54. Input Capture timing diagram
4µs
(@ 8 MHz fOSC)
fCPU
fOSC/32
8-bit COUNTER 1
01h
02h
03h
04h
05h
06h
07h
CLEARED
BY S/W
READING
LTIC REGISTER
LTIC PIN
ICF FLAG
LTICR REGISTER
xxh
04h
07h
t
106/188
ST7LITE49M
11.3.4
On-chip peripherals
Low power modes
Table 38.
11.3.5
Effect of low power modes on Lite timer 2
Mode
Description
Slow
No effect on Lite timer
(this peripheral is driven directly by fOSC/32)
Wait
No effect on Lite timer
Active Halt
No effect on Lite timer
Halt
Lite timer stops counting
Interrupts
Table 39.
Description of interrupt events
Interrupt Event
Event
Flag
Enable
Control
Bit
Timebase 1 Event
TB1F
TB1IE
Timebase 2 Event
TB2F
TB2IE
IC Event
ICF
ICIE
Exit
from
Active
Halt
Exit
from
Wait
Exit
from
Halt
Yes
Yes
No
No
No
The TBxF and ICF interrupt events are connected to separate interrupt vectors (see
Section 8: Interrupts).
They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the
interrupt mask in the CC register is reset (RIM instruction).
11.3.6
Register description
Lite Timer Control/Status register 2 (LTCSR2)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
TB2IE
TB2F
Read / Write
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = TB2IE Timebase 2 Interrupt enable bit
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
107/188
On-chip peripherals
ST7LITE49M
Bit 0 = TB2F Timebase 2 Interrupt flag
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred
Lite Timer Autoreload register (LTARR)
Reset value: 0000 0000 (00h)
7
AR7
0
AR6
AR5
AR4
AR3
AR2
AR1
AR0
Read / Write
Bits 7:0 = AR[7:0] Counter 2 Reload value
These bits register is read/write by software. The LTARR value is automatically loaded into
Counter 2 (LTCNTR) when an overflow occurs.
Lite Timer Counter 2 (LTCNTR)
Reset value: 0000 0000 (00h)
7
CNT7
0
CNT6
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0
Read only
Bits 7:0 = CNT[7:0] Counter 2 Reload value
This register is read by software. The LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
Lite Timer Control/status register (LTCSR1)
Reset value: 0x00 0000 (x0h)
7
ICIE
0
ICF
TB
TB1IE
TB1F
Read / Write
Bit 7 = ICIE Interrupt Enable bit
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
108/188
ST7LITE49M
On-chip peripherals
Bit 6 = ICF Input Capture flag
This bit is set by hardware and cleared by software by reading the LTICR register.
Writing to this bit does not change the bit value.
0: No Input Capture
1: An Input Capture has occurred
Note:
After an MCU reset, software must initialize the ICF bit by reading the LTICR register
Bit 5 = TB Timebase period selection bit
This bit is set and cleared by software.
0: Timebase period = tOSC * 8000 (1ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2ms @ 8 MHz)
Bit 4 = TB1IE Timebase Interrupt enable bit
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
Bit 3 = TB1F Timebase Interrupt flag
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
Bits 2:0 = Reserved
Lite Timer Input Capture register (LTICR)
Reset value: 0000 0000 (00h)
7
ICR7
0
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
ICR0
Read only
Bits 7:0 = ICR[7:0] Input Capture value
These bits are read by software and cleared by hardware after a reset. If the ICF bit in the
LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling
edge occurs on the LTIC pin.
Table 40.
Address
Lite Timer register mapping and reset values
Register
label
7
6
5
4
3
2
1
0
0C
LTCSR2
Reset Value
0
0
0
0
0
0
TB2IE
0
TB2F
0
0D
LTARR
Reset Value
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
(Hex.)
109/188
On-chip peripherals
Table 40.
Address
ST7LITE49M
Lite Timer register mapping and reset values
Register
label
7
6
5
4
3
2
1
0
0E
LTCNTR
Reset Value
CNT7
0
CNT6
0
CNT5
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
0F
LTCSR1
Reset Value
ICIE
0
ICF
x
TB
0
TB1IE
0
TB1F
0
0
0
0
10
LTICR
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
(Hex.)
110/188
ST7LITE49M
On-chip peripherals
11.4
I2C bus interface (I2C)
11.4.1
Introduction
The I2C Bus Interface serves as an interface between the microcontroller and the serial I2C
bus. It provides both multimaster and slave functions, and controls all I2C bus-specific
sequencing, protocol, arbitration and timing. It supports fast I2C mode (400kHz).
11.4.2
Main features
●
Parallel-bus/I2C protocol converter
●
Multi-master capability
●
7-bit/10-bit Addressing
●
Transmitter/Receiver flag
●
End-of-byte transmission flag
●
Transfer problem detection
I2C
master features:
●
Clock generation
●
I2C bus busy flag
●
Arbitration Lost Flag
●
End of byte transmission flag
●
Transmitter/Receiver Flag
●
Start bit detection flag
●
Start and Stop generation
I2C slave features:
11.4.3
●
Stop bit detection
●
I2C bus busy flag
●
Detection of misplaced start or stop condition
●
Programmable I2C Address detection
●
Transfer problem detection
●
End-of-byte transmission flag
●
Transmitter/Receiver flag
General description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa, using either an interrupt or polled handshake. The interrupts are
enabled or disabled by software. The interface is connected to the I2C bus by a data pin
(SDAI) and by a clock pin (SCLI). It can be connected both with a standard I2C bus and a
Fast I2C bus. This selection is made by software.
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On-chip peripherals
ST7LITE49M
Mode selection
The interface can operate in the four following modes:
●
Slave transmitter/receiver
●
Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to master after it generates a START
condition and from master to slave in case of arbitration loss or a STOP generation, allowing
then Multi-Master capability.
Communication flow
In Master mode, it initiates a data transfer and generates the clock signal. A serial data
transfer always begins with a start condition and ends with a stop condition. Both start and
stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognising its own address (7 or 10-bit), and the
General Call address. The General Call address detection may be enabled or disabled by
software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is
always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to Figure 55.
Figure 55. I2C bus protocol
SDA
ACK
MSB
SCL
1
2
8
START
CONDITION
9
STOP
CONDITION
VR02119B
Acknowledge may be enabled and disabled by software.
The I2C interface address and/or general call address can be selected by software.
The speed of the I2C interface may be selected between Standard (up to 100KHz) and Fast
I2C (up to 400KHz).
SDA/SCL line control
Transmitter mode: the interface holds the clock line low before transmission to wait for the
microcontroller to write the byte in the Data register.
Receiver mode: the interface holds the clock line low after reception to wait for the
microcontroller to read the byte in the Data register.
The SCL frequency (Fscl) is controlled by a programmable clock divider which depends on
the I2C bus mode.
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ST7LITE49M
On-chip peripherals
When the I2C cell is enabled, the SDA and SCL ports must be configured as floating inputs.
In this case, the value of the external pull-up resistor used depends on the application.
When the I2C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
Figure 56. I2C interface block diagram
DATA REGISTER (DR)
SDA or SDAI
DATA CONTROL
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
SCL or SCLI
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
CONTROL LOGIC
STATUS REGISTER 2 (SR2)
INTERRUPT
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On-chip peripherals
11.4.4
ST7LITE49M
Functional description
Refer to the CR, SR1 and SR2 registers in Section 11.4.7. for the bit definitions.
By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it
initiates a transmit or receive sequence.
First the interface frequency must be configured using the FRi bits in the OAR2 register.
Slave mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register; then it is compared with the address of the interface or the General Call
address (if selected by software).
Note:
In 10-bit addressing mode, the comparision includes the header sequence (11110xx0) and
the two most significant bits of the address.
●
Header matched (10-bit mode only): the interface generates an acknowledge pulse if
the ACK bit is set.
●
Address not matched: the interface ignores it and waits for another Start condition.
●
Address matched: the interface generates in sequence:
–
Acknowledge pulse if the ACK bit is set.
–
EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see
Figure 57 Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or Transmitter mode.
In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It
will enter transmit mode on receiving a repeated Start condition followed by the header
sequence with matching address bits and the least significant bit set (11110xx1) .
Slave receiver
Following the address reception and after SR1 register has been read, the slave receives
bytes from the SDA line into the DR register via the internal shift register. After each byte
the interface generates in sequence:
●
Acknowledge pulse if the ACK bit is set
●
EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 57 Transfer sequencing EV2).
Slave transmitter
Following the address reception and after SR1 register has been read, the slave sends
bytes from the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding
the SCL line low (see Figure 57 Transfer sequencing EV3).
When the acknowledge pulse is received the EVF and BTF bits are set by hardware with an
interrupt if the ITE bit is set.
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On-chip peripherals
Closing slave communication
After the last data byte is transferred a Stop Condition is generated by the master. The
interface detects this condition and sets:
EVF and STOPF bits with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR2 register (see Figure 57 Transfer sequencing
EV4).
Error cases
Note:
●
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop then the interface discards the data, released the lines and waits for
another Start condition.
If it is a Start then the interface discards the data and waits for the next slave address
on the bus.
●
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with
an interrupt if the ITE bit is set.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
In both cases, SCL line is not held low; however, the SDA line can remain low if the last bits
transmitted are all 0. It is then necessary to release both lines by software. The SCL line is
not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released
after the transfer of the current byte.
SMBus compatibility
ST7 I2C is compatible with SMBus V1.1 protocol. It supports all SMBus adressing modes,
SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave
Driver For ST7 I2C Peripheral.
115/188
On-chip peripherals
ST7LITE49M
Master mode
To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent, the EVF and SB bits are set by hardware with an interrupt if
the ITE bit is set.
The master then waits for a read of the SR1 register followed by a write in the DR register
with the Slave address, holding the SCL line low (see Figure 57 Transfer sequencing
EV5).
Slave address transmission
1.
Note:
The slave address is then sent to the SDA line via the internal shift register.
–
In 7-bit addressing mode, one address byte is sent.
–
In 10-bit addressing mode, sending the first byte including the header sequence
causes the following event. The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
2.
The master then waits for a read of the SR1 register followed by a write in the DR
register, holding the SCL line low (see Figure 57 Transfer sequencing EV9).
3.
Then the second address byte is sent by the interface.
4.
After completion of this transfer (and acknowledge from the slave if the ACK bit is set),
the EVF bit is set by hardware with interrupt generation if the ITE bit is set.
5.
The master waits for a read of the SR1 register followed by a write in the CR register
(for example set PE bit), holding the SCL line low (see Figure 57 Transfer sequencing
EV6).
6.
Next the master must enter Receiver or Transmitter mode.
In 10-bit addressing mode, to switch the master to Receiver mode, software must generate
a repeated Start condition and resend the header sequence with the least significant bit set
(11110xx1).
Master receiver
Following the address transmission and after SR1 and CR registers have been accessed,
the master receives bytes from the SDA line into the DR register via the internal shift
register. After each byte the interface generates in sequence:
●
Acknowledge pulse if the ACK bit is set
●
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 57 Transfer sequencing EV7).
To close the communication: before reading the last byte from the DR register, set the STOP
bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).
Note:
116/188
In order to generate the non-acknowledge pulse after the last received data byte, the ACK
bit must be cleared just before reading the second last data byte.
ST7LITE49M
On-chip peripherals
Master transmitter
Following the address transmission and after SR1 register has been read, the master
sends bytes from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see Figure 57 Transfer sequencing EV8).
When the acknowledge bit is received, the interface sets EVF and BTF bits with an interrupt
if the ITE bit is set.
To close the communication: after writing the last byte to the DR register, set the STOP bit to
generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit
cleared).
Error cases
Note:
●
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and BERR bits are set by hardware with an interrupt if ITE is set.
Note that BERR will not be set if an error is detected during the first pulse of each 9-bit
transaction:
Single Master mode
If a Start or Stop is issued during the first pulse of a 9-bit transaction, the BERR flag will
not be set and transfer will continue however the BUSY flag will be reset. To work
around this, slave devices should issue a NACK when they receive a misplaced Start or
Stop. The reception of a NACK or BUSY by the master in the middle of communication
gives the possibility to reinitiate transmission.
Multimaster mode
Normally the BERR bit would be set whenever unauthorized transmission takes place
while transfer is already in progress. However, an issue will arise if an external master
generates an unauthorized Start or Stop while the I2C master is on the first pulse pulse
of a 9-bit transaction. It is possible to work around this by polling the BUSY bit during
I2C master mode transmission. The resetting of the BUSY bit can then be handled in a
similar manner as the BERR flag being set.
●
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by
hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
●
ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and
the interface goes automatically back to slave mode (the M/SL bit is cleared).
In all these cases, the SCL line is not held low; however,the SDA line can remain low if the
last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL
line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
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On-chip peripherals
ST7LITE49M
Figure 57. Transfer sequencing
Table 41.
7-bit slave receiver:
S Address A
Data1
A
Data2
A
DataN
A
P
.....
EV1
Table 42.
EV2
EV2
EV2
7-bit slave transmitter
S Address A
Data1 A
Data
N
Data2 A
....
.
EV1 EV3
Table 43.
S
EV5
S
Data1
EV3
A
Data2
EV6
Data1
A
Data2
EV6 EV8
Header
A
EV7
Address A
Table 45.
P
EV31
EV4
....
EV7 .
DataN
NA
P
A
....
.
EV7
7-bit master transmitter
EV5
S
EV3
NA
7-bit master receiver
Address A
Table 44.
EV4
EV8
Data
N
A
EV8
P
EV8
10-bit slave receiver
A
Address
A
Data1
A
DataN
A
P
.....
EV1
Table 46.
EV2
EV2
EV4
10-bit slave transmitter
Sr Header A
Data
N
Data1 A
A
P
...
EV1 EV3
Table 47.
S
EV31
EV4
DataN A
P
EV3
10-bit master transmitter
Header A
Address A
Data1
A
....
EV5
Table 48.
EV9
EV6 EV8
EV8
EV8
10-bit master receiver
Sr
Header A
Data1
A
DataN A
P
.....
EV5
EV6
EV7
EV7
1. S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge, EVx=Event (with interrupt
if ITE=1).
2. EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
3. EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
4. EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
5. EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines
(STOP=1, STOP=0) or by writing DR register (DR=FFh). If lines are released by STOP=1, STOP=0, the
118/188
ST7LITE49M
On-chip peripherals
subsequent EV4 is not seen.
6. EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
7. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
8. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
9. EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
10. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
11. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
11.4.5
Low power modes
Effect of low power modes on the I2C interface
Table 49.
Mode
Description
Wait
I
No effect on I2C interface.
interrupts cause the device to exit from Wait mode.
I2C registers are frozen.
In Halt mode, the I interface is inactive and does not acknowledge data on the bus. The
I2C interface resumes operation when the MCU is woken up by an interrupt with “exit from
Halt mode” capability.
2C
Halt
11.4.6
2C
Interrupts
Figure 58. Event flags and interrupt generation
ADD10
BTF
ADSL
SB
AF
STOPF
ARLO
BERR
ITE
INTERRUPT
EVF
*
* EVF can also be set by EV6 or an error from the SR2 register.
Table 50.
Description of interrupt events
Exit
from
Wait
Exit
from
Halt
ADD10
Yes
No
End of byte Transfer Event
BTF
Yes
No
Address Matched Event (Slave mode)
ADSL
Yes
No
Start Bit Generation Event (Master mode)
SB
Yes
No
Interrupt Event(1)
Event
Flag
10-bit Address Sent Event (Master mode)
Enable
Control
Bit
ITE
Acknowledge Failure Event
AF
Yes
No
Stop Detection Event (Slave mode)
STOPF
Yes
No
Arbitration Lost Event (Multimaster configuration)
ARLO
Yes
No
Bus Error Event
BERR
Yes
No
2
1. The I C interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is
reset (RIM instruction).
119/188
On-chip peripherals
11.4.7
ST7LITE49M
Register description
I2C Control register (CR)
Reset value: 0000 0000 (00h)
7
0
0
0
PE
ENGC
START
ACK
STOP
ITE
Read / Write
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral Enable bit
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Note:
When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset.
All outputs are released while PE=0
When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.
To enable the I2C interface, write the CR register TWICE with PE=1 as the first write only
activates the interface (only PE is set).
Bit 4 = ENGC Enable General Call bit
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored).
0: General Call disabled
1: General Call enabled
Note:
In accordance with the I2C standard, when GCAL addressing is enabled, an I2C slave can
only receive data. It will not transmit data to the master.
Bit 3 = START Generation of a Start condition bit. This bit is set and cleared by software. It
is also cleared by hardware when the interface is disabled (PE=0) or when the Start
condition is sent (with interrupt generation if ITE=1).
●
In master mode:
0: No start generation
1: Repeated start generation
●
In slave mode:
0: No start generation
1: Start generation when the bus is free
Bit 2 = ACK Acknowledge enable bit
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or a data byte is received
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ST7LITE49M
On-chip peripherals
Bit 1 = STOP Generation of a Stop condition bit
This bit is set and cleared by software. It is also cleared by hardware in master mode.
Note: This bit is not cleared when the interface is disabled (PE=0).
●
In master mode:
0: No stop generation
1: Stop generation after the current byte transfer or after the current Start condition is
sent. The STOP bit is cleared by hardware when the Stop condition is sent.
●
In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode
the STOP bit has to be cleared by software.
Bit 0 = ITE Interrupt Enable bit
This bit is set and cleared by software and cleared by hardware when the interface is
disabled (PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 58 for the relationship between the events and the interrupt.
SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See
Figure 57) is detected.
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On-chip peripherals
ST7LITE49M
I2C Status register 1 (SR1)
Reset value: 0000 0000 (00h)
7
EVF
0
ADD10
TRA
BUSY
BTF
ADSL
M/SL
SB
Read Only
Bit 7 = EVF Event flag
This bit is set by hardware as soon as an event occurs. It is cleared by software reading
SR2 register in case of error event or as described in Figure 57. It is also cleared by
hardware when the interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
–
BTF=1 (byte received or transmitted)
–
ADSL=1 (Address matched in Slave mode while ACK=1)
–
SB=1 (Start condition generated in Master mode)
–
AF=1 (No acknowledge received after byte transmission)
–
STOPF=1 (Stop condition detected in Slave mode)
–
ARLO=1 (Arbitration lost in Master mode)
–
BERR=1 (Bus error, misplaced Start or Stop condition detected)
–
ADD10=1 (Master has sent header byte)
–
Address byte successfully transmitted in Master mode.
Bit 6 = ADD10 10-bit addressing in Master mode
This bit is set by hardware when the master has sent the first byte in 10-bit address
mode. It is cleared by software reading SR2 register followed by a write in the DR
register of the second address byte. It is also cleared by hardware when the peripheral
is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
Bit 5 = TRA Transmitter/Receiver bit
When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically
when BTF is cleared. It is also cleared by hardware after detection of Stop condition
(STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4 = BUSY Bus busy bit
This bit is set by hardware on detection of a Start condition and cleared by hardware on
detection of a Stop condition. It indicates a communication in progress on the bus. The
BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
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On-chip peripherals
Bit 3 = BTF Byte Transfer Finished bit
This bit is set by hardware as soon as a byte is correctly received or transmitted with
interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by
a read or write of DR register. It is also cleared by hardware when the interface is
disabled (PE=0).
–
Following a byte transmission, this bit is set after reception of the acknowledge
clock pulse. In case an address byte is sent, this bit is set only after the EV6 event
(See Figure 57). BTF is cleared by reading SR1 register followed by writing the
next byte in DR register.
–
Following a byte reception, this bit is set after transmission of the acknowledge
clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading
the byte from DR register.
The SCL line is held low while BTF=1.
0: byte transfer not done
1: byte transfer succeeded
Bit 2 = ADSL Address matched bit (slave mode). This bit is set by hardware as soon as the
received slave address matched with the OAR register content or a general call is
recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1 register
or by hardware when the interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 1 = M/SL Master/Slave bit
This bit is set by hardware as soon as the interface is in Master mode (writing
START=1). It is cleared by hardware after detecting a Stop condition on the bus or a
loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
Bit 0 = SB Start bit (master mode).
This bit is set by hardware as soon as the Start condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1
register followed by writing the address byte in DR register. It is also cleared by
hardware when the interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
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On-chip peripherals
ST7LITE49M
I2C Status register 2 (SR2)
Reset value: 0000 0000 (00h)
7
0
0
0
0
AF
STOPF
ARLO
BERR
GCAL
Read Only
Bit 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 = AF Acknowledge failure bit
This bit is set by hardware when no acknowledge is returned. An interrupt is generated
if ITE=1. It is cleared by software reading SR2 register or by hardware when the
interface is disabled (PE=0).
The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at
the same time.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection bit (slave mode)
This bit is set by hardware when a Stop condition is detected on the bus after an
acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
Bit 2 = ARLO Arbitration lost bit
This bit is set by hardware when the interface loses the arbitration of the bus to another
master. An interrupt is generated if ITE=1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE=0).
After an ARLO event the interface switches back automatically to Slave mode
(M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Note:
In a Multimaster environment, when the interface is configured in Master Receive mode it
does not perform arbitration during the reception of the Acknowledge Bit. Mishandling of the
ARLO bit from the I2CSR2 register may occur when a second master simultaneously
requests the same data from the same slave and the I2C master does not acknowledge the
data. The ARLO bit is then left at 0 instead of being set.
Bit 1 = BERR Bus error bit
This bit is set by hardware when the interface detects a misplaced Start or Stop
condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
124/188
ST7LITE49M
Note:
On-chip peripherals
If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the
Master to re-synchronize communication, get the transmission acknowledged and the bus
released for further communication
Bit 0 = GCAL General Call bit (slave mode).
This bit is set by hardware when a general call address is detected on the bus while
ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the
interface is disabled (PE=0).
0: No general call address detected on bus
1: general call address detected on bus
I2C Clock Control register (CCR)
Reset value: 0000 0000 (00h)
7
FM/SM
0
CC6
CC5
CC4
CC3
CC2
CC1
CC0
Read / Write
Bit 7 = FM/SM Fast/Standard I2C mode bit
This bit is set and cleared by software. It is not cleared when the interface is disabled
(PE=0).
0: Standard I2C mode
1: Fast I2C mode
Bit 6:0 = CC[6:0] 7-bit clock divider bits
These bits select the speed of the bus (FSCL) depending on the I2C mode. They are not
cleared when the interface is disabled (PE=0).
Refer to the Electrical Characteristics section for the table of values.
Note:
The programmed FSCL assumes no load on SCL and SDA lines.
I2C Data register (DR)
Reset Value: 0000 0000 (00h)
7
D7
0
D6
D5
D4
D3
D2
D1
D0
Read / Write
Bit 7:0 = D[7:0] 8-bit Data register
These bits contain the byte to be received or transmitted on the bus.
–
Transmitter mode: byte transmission start automatically when the software writes
in the DR register.
–
Receiver mode: the first data byte is received automatically in the DR register
using the least significant bit of the address. Then, the following data bytes are
received one by one after reading the DR register.
125/188
On-chip peripherals
ST7LITE49M
I2C Own Address register (OAR1)
Reset value: 0000 0000 (00h)
7
ADD7
0
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Read / Write
●
In 7-bit addressing mode
Bit 7:1 = ADD[7:1] Interface address. These bits define the I2C bus address of the
interface. They are not cleared when the interface is disabled (PE=0).
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when
the interface is disabled (PE=0).
Note:
Address 01h is always ignored.
●
In 10-bit addressing mode
Bit 7:0 = ADD[7:0] Interface address. These are the least significant bits of the I2C bus
address of the interface. They are not cleared when the interface is disabled (PE=0).
I2C Own Address register (OAR2)
Reset value: 0100 0000 (40h)
7
FR1
0
FR0
0
0
0
ADD9
ADD8
0
Read / Write
Bit 7:6 = FR[1:0] Frequency bits
These bits are set by software only when the interface is disabled (PE=0). To configure
the interface to I2C specified delays select the value corresponding to the
microcontroller frequency fCPU.
Table 51.
Configuration of I2C delay times
fCPU
FR1
FR0
< 6 MHz
0
0
6 to 8 MHz
0
1
Bit 5:3 = Reserved
Bit 2:1 = ADD[9:8] Interface address
These are the most significant bits of the I2C bus address of the interface (10-bit mode
only). They are not cleared when the interface is disabled (PE=0).
Bit 0 = Reserved.
126/188
ST7LITE49M
On-chip peripherals
Table 52.
Address
(Hex.)
I2C register mapping and reset values
Register
label
7
6
5
4
3
2
1
0
0064h
I2CCR
Reset Value
0
0
PE
0
ENGC
0
START
0
ACK
0
STOP
0
ITE
0
0065h
I2CSR1
Reset Value
EVF
0
ADD10
0
TRA
0
BUSY
0
BTF
0
ADSL
0
M/SL
0
SB
0
0066h
I2CSR2
Reset Value
0
0
0
AF
0
STOPF
0
ARLO
0
BERR
0
GCAL
0
0067h
I2CCCR
FM/SM
Reset Value
0
CC6
0
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
0068h
I2COAR1
Reset Value
ADD7
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
0069h
I2COAR2
Reset Value
FR1
0
FR0
1
0
0
0
ADD9
0
ADD8
0
0
006Ah
I2CDR
Reset Value
MSB
0
0
0
0
0
0
0
LSB
0
127/188
On-chip peripherals
11.5
10-bit A/D converter (ADC)
11.5.1
Introduction
ST7LITE49M
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 10
multiplexed analog input channels (refer to device pin out description) that allow the
peripheral to convert the analog voltage levels from up to 7 different sources.
The result of the conversion is stored in a 10-bit Data register. The A/D converter is
controlled through a Control/Status register.
11.5.2
Main Features
●
10-bit conversion
●
Up to 7 channels with multiplexed input
●
Linear successive approximation
●
Data register (DR) which contains the results
●
Conversion complete status flag
●
On/off bit (to reduce consumption)
The block diagram is shown in Figure 59.
11.5.3
Functional description
Analog power supply
VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to
device pin out description) they are internally connected to the VDD and VSS pins.
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of
heavily loaded or badly decoupled power supply lines.
128/188
ST7LITE49M
On-chip peripherals
Figure 59. ADC block diagram
fCPU
DIV 4
DIV 2
1
0
fADC
0
1
SLOW
bit
EOC SPEED ADON
0
CH3
CH2
CH1
ADCCSR
CH0
3
AIN0
HOLD CONTROL
RADC
AIN1
ANALOG TO DIGITAL
ANALOG
MUX
CONVERTER
CADC
AIN6
ADCDRH
D9
D8
ADCDRL
D7
D6
0
D5
0
D4
0
D3
0
D2
SLOW
0
D1
D0
Digital A/D conversion result
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
If the input voltage (VAIN) is greater than VDDA (high-level voltage reference) then the
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in the Electrical
Characteristics Section.
RAIN is the maximum recommended impedance for an analog input signal. If the impedance
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the alloted time.
129/188
On-chip peripherals
ST7LITE49M
Configuring the A/D conversion
The analog input ports must be configured as input, no pull-up, no interrupt (see Section 10:
I/O ports). Using these pins as analog inputs does not affect the ability of the port to be read
as a logic input.
To assign the analog channel to convert, select the CH[2:0] bits in the ADCCSR register.
Set the ADON bit to enable the A/D converter and to start the conversion. From this time on,
the ADC performs a continuous conversion of the selected channel.
When a conversion is complete:
●
The EOC bit is set by hardware.
●
The result is in the ADCDR registers.
A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit.
To read the 10 bits, perform the following steps:
1.
Poll the EOC bit
2.
Read ADCDRL
3.
Read ADCDRH. This clears EOC automatically.
To read only 8 bits, perform the following steps:
1.
Poll EOC bit
2.
Read ADCDRH. This clears EOC automatically.
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
11.5.4
Low power modes
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Table 53.
11.5.5
130/188
Mode
Description
Wait
No effect on A/D Converter
Halt
A/D Converter disabled.
After wake up from Halt mode, the A/D Converter requires a stabilization time
tSTAB (see Electrical Characteristics) before accurate conversions can be
performed.
Interrupts
None.
Effect of low power modes on the A/D converter
ST7LITE49M
11.5.6
On-chip peripherals
Register description
Control/status register (ADCCSR)
Reset value: 0000 0000 (00h)
7
EOC
0
SPEED
ADON
0
Read only
CH3
CH2
CH1
CH0
Read/write
Bit 7 = EOC End of Conversion bit
This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH
register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection bit
This bit is set and cleared by software. It is used together with the SLOW bit to
configure the ADC clock speed. Refer to the table in the SLOW bit description
(ADCDRL register).
Bit 5 = ADON A/D Converter on bit
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bits 4:3 = Reserved. Must be kept cleared.
Bits 2:0 = CH[2:0] Channel Selection
These bits select the analog input to convert. They are set and cleared by software.
Table 54.
Channel selection using CH[2:0]
Channel Pin(1)
CH3
CH2
CH1
CH0
AIN0
0
0
0
0
AIN1
0
0
0
1
AIN2
0
0
1
0
AIN3
0
0
1
1
AIN4
0
1
0
0
AIN5
0
1
0
1
AIN6
0
1
1
0
AIN7
0
1
1
1
AIN8
1
0
0
0
AIN9
1
0
0
1
1. The number of channels is device dependent. Refer to the device pinout description.
131/188
On-chip peripherals
ST7LITE49M
Data register High (ADCDRH)
Reset value: xxxx xxxx (xxh)
7
D9
0
D8
D7
D6
D5
D4
D3
D2
Read only
Bits 7:0 = D[9:2] MSB of Analog Converted Value
Adc Control/data register Low (ADCDRL)
Reset value: 0000 00xx (0xh)
7
0
0
0
0
0
SLOW
0
D1
D0
Read/write
Bits 7:4 = Reserved. Forced by hardware to 0.
Bit 3 = SLOW Slow mode bit
This bit is set and cleared by software. It is used together with the SPEED bit in the
ADCCSR register to configure the ADC clock speed as shown on the table below.
Table 55.
Configuring the ADC clock speed
fADC(1)
SLOW
SPEED
fCPU/2
0
0
fCPU
0
1
fCPU/4
1
x
1. The maximum allowed value of fADC is 4 MHz (see Section 13.11 on page 172)
Bit 2 = Reserved. Forced by hardware to 0.
Bits 1:0 = D[1:0] LSB of Analog Converted value
Table 56.
Address
Register
label
7
6
5
4
3
2
1
0
0036h
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
0
0
CH3
0
CH2
0
CH1
0
CH0
0
0037h
ADCDRH
Reset Value
D9
x
D8
x
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
0038h
ADCDRL
Reset Value
0
0
0
0
0
0
0
SLOW
0
0
D1
x
D0
x
(Hex.)
132/188
ADC register mapping and reset values
ST7LITE49M
Instruction set
12
Instruction set
12.1
ST7 addressing modes
The ST7 core features 17 different addressing modes which can be classified in seven main
groups:
Table 57.
Description of addressing modes
Addressing mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset
byte,#5
The ST7 Instruction set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be subdivided in two submodes
called long and short:
●
Long addressing mode is more powerful because it can use the full 64 Kbyte address
space, however it uses more bytes and more CPU cycles.
●
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 58.
ST7 addressing mode overview
Mode
Syntax
Destination/
source
Pointer
address
Pointer
size
Length
(bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No Offset
Direct
Indexed
ld A,(X)
00..FF
+ 0 (with X register)
+ 1 (with Y register)
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed
ld A,($1000,X)
0000..FFFF
+2
Short
Indirect
ld A,[$10]
00..FF
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect
ld A,([$10],X)
00..1FE
00..FF
byte
+2
Indexed
133/188
Instruction set
Table 58.
ST7LITE49M
ST7 addressing mode overview (continued)
Syntax
Destination/
source
Pointer
address
Pointer
size
Length
(bytes)
ld
A,([$10.w],X)
0000..FFFF
00..FF
word
+2
Mode
1.
Long
Indirect
Indexed
Relative
Direct
jrne loop
PC128/PC+127(1)
Relative
Indirect
jrne [$10]
PC128/PC+127(1)
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
Relative
btjt
$10,#7,skip
00..FF
Bit
Indirect
Relative
btjt
[$10],#7,skip
00..FF
+1
00..FF
byte
+2
+1
00..FF
byte
+2
+2
00..FF
byte
+3
At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
12.1.1
Inherent mode
All Inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Table 59.
134/188
Instructions supporting Inherent addressing mode
Instruction
Function
NOP
No operation
TRAP
S/W interrupt
WFI
Wait for interrupt (low power mode)
HALT
Halt oscillator (lowest power mode)
RET
Subroutine return
IRET
Interrupt subroutine return
SIM
Set interrupt mask
RIM
Reset interrupt mask
SCF
Set carry flag
RCF
Reset carry flag
RSP
Reset stack pointer
LD
Load
CLR
Clear
PUSH/POP
Push/Pop to/from the stack
INC/DEC
Increment/decrement
TNZ
Test negative or zero
CPL, NEG
1 or 2 complement
ST7LITE49M
Instruction set
Table 59.
12.1.2
Instructions supporting Inherent addressing mode (continued)
Instruction
Function
MUL
Byte multiplication
SLL, SRL, SRA, RLC, RRC
Shift and rotate operations
SWAP
Swap nibbles
Immediate mode
Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte
contains the operand value.
Imm
Table 60.
12.1.3
Instructions supporting Inherent immediate addressing mode
Immediate Instruction
Function
LD
Load
CP
Compare
BCP
Bit compare
AND, OR, XOR
Logical operations
ADC, ADD, SUB, SBC
Arithmetic operations
Direct modes
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two submodes:
Direct (Short) addressing mode
The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF
addressing space.
Direct (Long) addressing mode
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after
the opcode.
12.1.4
Indexed modes (No Offset, Short, Long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three submodes:
Indexed mode (No Offset)
There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space.
Indexed mode (Short)
The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE
addressing space.
135/188
Instruction set
ST7LITE49M
Indexed mode (Long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the
opcode.
12.1.5
Indirect modes (Short, Long)
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two
submodes:
Indirect mode (Short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing
space, and requires 1 byte after the opcode.
Indirect mode (Long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
12.1.6
Indirect Indexed modes (Short, Long)
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
The indirect indexed addressing mode consists of two submodes:
Indirect Indexed mode (Short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing
space, and requires 1 byte after the opcode.
Indirect Indexed mode (Long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
Table 61.
Instructions supporting Direct, Indexed, Indirect and Indirect Indexed
addressing modes
Instructions
Function
Long and short instructions
136/188
LD
Load
CP
Compare
AND, OR, XOR
Logical operations
ADC, ADD, SUB, SBC
Arithmetic addition/subtraction operations
BCP
Bit compare
ST7LITE49M
Instruction set
Table 61.
Instructions supporting Direct, Indexed, Indirect and Indirect Indexed
addressing modes (continued)
Instructions
Function
Short instructions only
12.1.7
CLR
Clear
INC, DEC
Increment/decrement
TNZ
Test negative or zero
CPL, NEG
1 or 2 complement
BSET, BRES
Bit operations
BTJT, BTJF
Bit test and jump operations
SLL, SRL, SRA, RLC, RRC
Shift and rotate operations
SWAP
Swap nibbles
CALL, JP
Call or jump subroutine
Relative modes (Direct, Indirect)
This addressing mode is used to modify the PC register value by adding an 8-bit signed
offset to it.
Table 62.
Instructions supporting relative modes
Available Relative Direct/Indirect instructions
Function
JRxx
Conditional jump
CALLR
Call relative
The relative addressing mode consists of two submodes:
Relative mode (Direct)
The offset follows the opcode.
Relative mode (Indirect)
The offset is defined in memory, of which the address follows the opcode.
137/188
Instruction set
12.2
ST7LITE49M
Instruction groups
The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Table 63.
ST7 instruction set
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
Increment/decrement
INC
DEC
Compare and tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit operation
BSET
BRES
Conditional bit test and branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and rotate
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional jump or call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Conditional branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Condition Code Flag modification
SIM
RIM
SCF
RCF
RSP
RET
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes by:
PC-2 End of previous instruction
PC-1 Prebyte
PC Opcode
PC+1 Additional word (0 to 2) according to the number of bytes required to compute
the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using
indirect X indexed addressing mode.
PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
138/188
ST7LITE49M
12.2.1
Instruction set
Illegal Opcode Reset
In order to provide enhanced robustness to the device against unexpected behavior, a
system of illegal opcode detection is implemented: a reset is generated if the code to be
executed does not correspond to any opcode or prebyte value. This, combined with the
Watchdog, allows the detection and recovery from an unexpected fault or interference.
A valid prebyte associated with a valid opcode forming an unauthorized combination does
not generate a reset.
Table 64.
I
Illegal opcode detection
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
ADC
Add with Carry
A=A+M+C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A, Memory
tst (A . M)
A
M
N
Z
BRES
Bit Reset
bres Byte, #3
M
BSET
Bit Set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1
M
C
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1
M
C
CALL
Call subroutine
CALLR
Call subroutine relative
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
CPL
One Complement
A = FFH-A
DEC
Decrement
dec Y
HALT
Halt
IRET
Interrupt routine return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
JRIH
Jump if ext. interrupt = 1
JRIL
Jump if ext. interrupt = 0
JRH
Jump if H = 1
H=1?
JRNH
Jump if H = 0
H=0?
JRM
Jump if I = 1
I=1?
JRNM
Jump if I = 0
I=0?
JRMI
Jump if N = 1 (minus)
N=1?
reg, M
0
1
N
Z
C
reg, M
N
Z
1
reg, M
N
Z
N
Z
N
Z
M
0
H
reg, M
I
C
jrf *
139/188
Instruction set
Table 64.
ST7LITE49M
Illegal opcode detection (continued)
Mnemo
Description
Function/Example
Dst
Src
JRPL
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned >=
JRUGT
Jump if (C + Z = 0)
Unsigned >
JRULE
Jump if (C + Z = 1)
Unsigned <=
LD
Load
dst <= src
reg, M
M, reg
MUL
Multiply
X,A = X * A
A, X, Y
X, Y, A
NEG
Negate (2's compl)
neg $10
reg, M
NOP
No Operation
OR
OR operation
A=A+M
A
M
POP
Pop from the Stack
pop reg
reg
M
pop CC
CC
M
M
reg, CC
H
I
N
Z
N
Z
0
H
C
0
I
N
Z
N
Z
N
Z
C
C
PUSH
Push onto the Stack
push Y
RCF
Reset carry flag
C=0
RET
Subroutine Return
RIM
Enable Interrupts
I=0
RLC
Rotate left true C
C <= Dst <= C
reg, M
N
Z
C
RRC
Rotate right true C
C => Dst => C
reg, M
N
Z
C
RSP
Reset Stack Pointer
S = Max allowed
SBC
Subtract with Carry
A=A-M-C
N
Z
C
SCF
Set carry flag
C=1
SIM
Disable Interrupts
I=1
SLA
Shift left Arithmetic
C <= Dst <= 0
reg, M
N
Z
C
SLL
Shift left Logic
C <= Dst <= 0
reg, M
N
Z
C
SRL
Shift right Logic
0 => Dst => C
reg, M
0
Z
C
SRA
Shift right Arithmetic
Dst7 => Dst => C
reg, M
N
Z
C
SUB
Subtraction
A=A-M
A
N
Z
C
SWAP
SWAP nibbles
Dst[7..4]<=>Dst[3..0]
reg, M
N
Z
TNZ
Test for Neg & Zero
tnz lbl1
N
Z
TRAP
S/W trap
S/W interrupt
140/188
0
0
A
M
1
1
M
1
ST7LITE49M
Table 64.
Instruction set
Illegal opcode detection (continued)
Mnemo
Description
WFI
Wait for Interrupt
XOR
Exclusive OR
Function/Example
Dst
Src
H
I
N
Z
N
Z
C
0
A = A XOR M
A
M
141/188
Electrical characteristics
ST7LITE49M
13
Electrical characteristics
13.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
13.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA=25 °C and TA=TAmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
13.1.2
Typical values
Unless otherwise specified, typical data are based on TA=25 °C, VDD=5 V (for the
4.5 V≤ VDD≤ 5.5 V voltage range) and VDD=3.3 V (for the 3.0 V≤ VDD≤ 3.6 V voltage range).
They are given only as design guidelines and are not tested.
13.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
13.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 60.
Figure 60. Pin loading conditions
ST7 PIN
CL
13.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 61.
142/188
ST7LITE49M
Electrical characteristics
Figure 61. Pin input voltage
ST7 PIN
VIN
13.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 65.
Voltage characteristics
Symbol
Ratings
VDD - VSS
Supply voltage
VIN
Input voltage on any
Maximum value
pin(1)(2)
VESD(HBM)
Electrostatic discharge voltage (Human Body
model)
VESD(CDM)
Electrostatic discharge voltage (Charge Device
model)
Unit
7.0
V
VSS-0.3 to VDD+0.3
see Section 13.8.3 on page
158
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted Program Counter). To guarantee safe operation, this connection has to be done through a pullup or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the
same way to VDD or VSS according to their reset configuration.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
143/188
Electrical characteristics
Table 66.
ST7LITE49M
Current characteristics
Symbol
Ratings
IVDD
Total current into VDD power lines (source)(1)
IVSS
(1)
Total current out of VSS ground lines (sink)
IIO
IINJ(PIN)
Maximum value
(2)(3)
150
20
Output current sunk by any high sink I/O pin
40
Output current source by any I/Os and control pin
- 25
Injected current on RESET pin
±5
Injected current on OSC1/CLKIN and OSC2 pins
±5
Injected current on any other pin
ΣIINJ(PIN)(2)
75
Output current sunk by any standard I/O and control
pin
(4)
Total injected current (sum of all I/O and control
pins)(4)
Unit
mA
±5
± 20
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
3. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents
throughout the device including the analog inputs. To avoid undesirable effects on the analog functions,
care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the
analog voltage is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject
the current as far as possible from the analog input pins.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 67.
Symbol
Ratings
Value
Unit
TSTG
Storage temperature range
-65 to +150
°C
TJ
144/188
Thermal characteristics
Maximum junction temperature (see Table 105: Thermal characteristics on
page 186)
ST7LITE49M
Electrical characteristics
13.3
Operating conditions
13.3.1
General operating conditions
TA = -40 to +125 °C unless otherwise specified.
Table 68.
General operating conditions
Symbol
Parameter
VDD
Supply voltage
fCPU
CPU clock frequency
Conditions
Min
Max
fCPU = 4 MHz. max.
2.4
5.5
fCPU = 8 MHz. max.
3.3
5.5
Unit
V
3.3 V≤ VDD≤5.5 V
up to 8
2.4 V≤VDD<3.3 V
up to 4
MHz
Figure 62. fCPU maximum operating frequency versus VDD supply voltage
FUNCTIONALITY
GUARANTEED
IN THIS AREA
(UNLESS OTHERWISE
STATED IN THE
TABLES OF
PARAMETRIC DATA)
fCPU [MHz]
8
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
4
2
SUPPLY VOLTAGE [V]
0
2.0
13.3.2
2.4 2.7
3.3
3.5
4.0
4.5
5.0
5.5
Operating conditions with Low Voltage Detector (LVD)
TA = -40 to 125 °C unless otherwise specified.
,
Table 69.
Operating characteristics with LVD
Symbol
Parameter
Conditions
Min
Typ
Max
VIT+(LVD)
Reset release threshold
(VDD rise)
High Threshold
Med. Threshold
Low Threshold
3.9
3.2
2.5
4.2
3.5
2.7
4.5
3.8
3.0
VIT-(LVD)
Reset generation threshold
(VDD fall)
High Threshold
Med. Threshold
Low Threshold
3.7
3.0
2.4
4.0
3.3
2.6
4.3
3.6
2.9
Vhys
LVD voltage threshold hysteresis
VIT+(LVD)-VIT-(LVD)
Unit
V
VtPOR
IDD(LVD)
VDD rise time
rate(1)(2)
LVD/AVD current consumption
150
mV
µs/V
2
VDD = 5 V
80
140
µA
1. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on
and LVD reset release. When the VDD slope is outside these values, the LVD may not release properly the
reset of the MCU.
2. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the
application, it is recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit
example in Figure 96 on page 171.
145/188
Electrical characteristics
13.3.3
ST7LITE49M
Auxiliary Voltage Detector (AVD) thresholds
TA = -40 to 125 °C unless otherwise specified.
,
Table 70.
Operating characteristics with AVD(1)
Min (2) Typ(2) Max(2)
Symbol
Parameter
Conditions
VIT+(AVD)
1=>0 AVDF flag toggle
threshold (VDD rise)
High Threshold
Med. Threshold
Low Threshold
4.0
3.4
2.6
4.4
3.7
2.9
4.8
4.1
3.2
VIT-(AVD)
0=>1 AVDF flag toggle
threshold (VDD fall)
High Threshold
Med. Threshold
Low Threshold
3.9
3.3
2.5
4.3
3.6
2.8
4.7
4.0
3.1
Vhys
AVD voltage threshold
hysteresis
VIT+(AVD)-VIT-(AVD)
Unit
V
150
mV
1. Refer to Section : Monitoring the VDD main supply.
2. Not tested in production, guaranteed by characterization.
13.3.4
Voltage drop between AVD flag setting and LVD reset generation
Table 71. Voltage drop
Parameter
Min(1)
Typ(1)
Max(1)
AVD med. Threshold - AVD low. threshold
800
850
950
AVD high. Threshold - AVD low threshold
1400
1450
1550
AVD high. Threshold - AVD med. threshold
600
650
750
AVD low Threshold - LVD low threshold
100
200
250
AVD med. Threshold - LVD low threshold
950
1050
1150
AVD med. Threshold - LVD med. threshold
250
300
400
AVD high. Threshold - LVD low threshold
1600
1700
1800
AVD high. Threshold - LVD med. threshold
900
1000
1050
Unit
mV
1. Not tested in production, guaranteed by characterization.
146/188
ST7LITE49M
13.3.5
Electrical characteristics
Internal RC oscillator
To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100 nF, between the VDD and VSS pins as close as possible to the ST7
device
Internal RC oscillator calibrated at 5.0 V
The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option
byte).
Table 72.
Symbol
fRC
ACCRC
tsu(RC)
Internal RC oscillator characteristics (5.0 V calibration)
Parameter
Internal RC oscillator
frequency
Conditions
Min
Typ
RCCR = FF (reset value),
TA=25 °C,VDD=5 V
Max Unit
5.5
MHz
RCCR=RCCR0(1),
TA=25 °C,VDD=5 V
7.84
TA=25 °C, VDD=4.5 to 5 V(2)
-2(3)
2
%
TA=0 to +85 °C,
VDD=4.5 to 5.5 V(2)
-2.5
4
%
TA=0 to +125 °C,
VDD=4.5 to 5.5 V(2)
-3
6
%
TA=-40 to 0 °C,
VDD=4.5 to 5.5 V(2)
-4
2.5
%
Accuracy of Internal
RC oscillator with
RCCR=RCCR01)
RC oscillator setup
time
8
8.16
µs
4 (2)
TA=25 °C, VDD=5 V
1. See Section 7.1.1: Internal RC oscillator
2. Tested in production at 5.0 V only
3. TDB stands for ‘to be determined’.
Internal RC oscillator calibrated at 3.3 V
The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option
byte).
Table 73.
Internal RC oscillator characteristics (3.3 V calibration)
Symbol
Parameter
fRC
Internal RC oscillator
frequency
Conditions
Min
RCCR = FF (reset value),
TA=25 °C,VDD=3.3 V
RCCR = RCCR1(1),
TA=25 °C, VDD=3.3 V
Typ
Max
Unit
4.3
MHz
7.84
8
8.16
147/188
Electrical characteristics
Table 73.
Symbol
ACCRC
tsu(RC)
ST7LITE49M
Internal RC oscillator characteristics (3.3 V calibration)
Parameter
Accuracy of Internal
RC oscillator with
RCCR=RCCR11)
RC oscillator setup
time
Conditions
Min
TA=25 °C,
VDD=3.0 to 3.6 V(2)
Typ
Max
Unit
-2
2
%
TA=0 to +85 °C,
VDD=3.0 to 3.6 V(2)
-2.5
4
%
TA=0 to +125 °C,
VDD=3.0 to 3.6 V(2)
-3
6
%
TA=-40 to 0 °C,
VDD=3.0 to 3.6 V(2)
-4
2.5
%
4 2)
TA=25 °C, VDD=3.3 V
µs
1. See Section 7.1.1: Internal RC oscillator
2. Tested in production at 3.3 V only
Figure 63. Frequency vs voltage at four different ambient temperatures (RC at 5 V)
8.200
RC frequency (MHz)
8.160
8.120
8.080
RC5V@-40 °C
8.040
RC5V@25 °C
8.000
RC5V@85 °C
7.960
RC5V@125 °C
7.920
7.880
7.840
5.
6
5.
2
4.
8
4.
4
4.
0
3.
6
3.
2
2.
8
2.
4
7.800
VDD (V)
Figure 64. Frequency vs voltage at four different ambient temperatures (RC at 3.3 V)
RC frequency (MHz)
8.240
8.200
8.160
8.120
RC3.3V@-40 °C
8.080
RC3.3V@25 °C
8.040
RC3.3V@85 °C
8.000
RC3.3V@125 °C
7.960
7.920
7.880
7.840
2.4
2.8
3.2
3.6
4.0
4.4
VDD (V)
148/188
4.8
5.2
5.6
ST7LITE49M
Electrical characteristics
RC5V accuracy (%)
Figure 65. Accuracy in % vs voltage at 4 different ambient temperatures (RC at 5 V)
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-2.0
-2.2
RC5V%@-40 °C
RC5V%@25 °C
RC5V%@85 °C
RC5V%@125 °C
5.4
5
4.6
4.2
3.8
3.4
3
2.6
VDD (V)
RC3.3V accuracy (%)
Figure 66. Accuracy in % vs voltage at 4 different ambient temperatures (RC at 3.3V)
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
RC3.3V%@-40 °C
RC3.3C%@25 °C
RC3.3V%@85 °C
RC3.3V%@125 °C
5.4
5.0
4.6
4.2
3.8
3.4
3.0
2.6
VDD (V)
149/188
Electrical characteristics
13.4
ST7LITE49M
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for Halt mode
for which the clock is stopped).
13.4.1
Supply current
TA = -40 to +125 °C unless otherwise specified.
Table 74.
Symbol
Supply current characteristics
Parameter
Conditions
Supply current in Run mode(1)
Supply current in Slow mode(4)
Supply current in Slow-Wait mode
(5)
VDD=5V
Supply current in Wait mode(3)
Typ
Max
fCPU = 4 MHz
2.5
4.5(2)
fCPU = 8 MHz
5.0
9(2)
fCPU = 4 MHz
1.1
2(2)
fCPU = 8 MHz
2
3.5(2)
fCPU/32 = 250 kHz
550
900
fCPU/32 = 250 kHz
450
750
50
90(2)
120
200
0.5
5
(6)(7)
Supply current in AWUFH mode
Supply current in Active Halt mode
TA=85°C
Supply current in Halt mode(8)
mA
µA
TA=125°C
Supply current in Run mode(1)
fCPU = 4 MHz
1.4
2.5(2)
Supply current in Wait mode(3)
fCPU = 4 MHz
600
900(2)
Supply current in Slow mode(4)
fCPU/32 = 250 kHz
300
500(2)
fCPU/32 = 250 kHz
250
450(2)
20
40(2)
80
120(2)
0.5
5(2)
Supply current in Slow-Wait mode(5)
Supply current in AWUFH mode(6)(7)
VDD=3V
IDD
Unit
Supply current in Active Halt mode
Supply current in Halt mode(8)
TA=85°C
mA
µA
TA=125°C
1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in
reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. Data based on characterization, not tested in production.
3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)
driven by external square wave, LVD disabled.
4. Slow mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no
load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
5. Slow-Wait mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
6. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU max.
7. This consumption refers to the Halt period only and not the associated run period which is software dependent.
8. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,
tested in production at VDD max and fCPU max.
150/188
ST7LITE49M
Electrical characteristics
Idd [mA]
Figure 67. Typical IDD in Run vs. fCPU
6.0
2MHz
5.0
4MHz
4.0
8MHz
3.0
2.0
1.0
5.
6
5.
2
4.
8
4.
4
4
3.
6
3.
2
2.
8
2.
4
0.0
Vdd [V]
Figure 68. Typical IDD in WFI vs. fCPU
2MHz
Idd [mA]
2.5
4MHz
2
8MHz
1.5
1
0.5
4.
8
5.
2
5.
6
4.
8
5.
2
5.
6
4.
4
4
3.
6
3.
2
2.
8
2.
4
0
Vdd [V]
2MHz
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
4MHz
4.
4
4
3.
6
3.
2
8MHz
2.
8
2.
4
Idd [mA]
Figure 69. Typical IDD in Slow mode vs. fCPU
Vdd [V]
151/188
Electrical characteristics
ST7LITE49M
Idd [mA]
Figure 70. Typical IDD in Slow-Wait mode vs. fCPU
0.6
2MHz
0.5
4MHz
0.4
8MHz
0.3
0.2
0.1
5.
6
5.
2
4.
8
4.
4
4
3.
6
3.
2
2.
8
2.
4
0
Vdd [V]
Figure 71. Typical IDD vs. temperature at VDD = 5V and fCPU = 8 MHz
RUN
WFI
SLOW
6
SLOW-WAIT
Idd [mA]
5
4
3
2
1
0
-40°C
25°C
85°C
125°C
Temp[°C]
13.4.2
On-chip peripherals
Table 75.
On-chip peripheral characteristics
Symbol
Parameter
IDD(AT)
12-bit Auto-Reload timer supply current(1)
IDD(I2C)
I2C supply current(2)
IDD(ADC)
ADC supply current when converting(3)
Conditions
Typ
fCPU=4 MHz
VDD=3.0 V
10
fCPU=8 MHz
VDD=5.0 V
50
fCPU=4 MHz
VDD=3.0 V
600
fCPU=8 MHz
VDD=5.0 V
1000
VDD=3.0 V
400
VDD=5.0 V
600
fADC=4 MHz
Unit
µA
1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer
running in PWM mode at fcpu= 8 MHz.
2. Data based on a differential IDD measurement between reset configuration (I2C disabled) and a permanent
I2C master communication at 100 kHz (data sent equal to 55h). This measurement include the pad
toggling consumption (4.7 kOhm external pull-up on clock and data lines).
3. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions with amplifier disabled.
152/188
ST7LITE49M
Electrical characteristics
13.5
Communication interface characteristics
13.5.1
I2C interface
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDAI and SCLI). The ST7 I2C interface meets the electrical and timing
requirements of the Standard I2C communication protocol.
TA = -40°C to 125 °C, unless otherwise specified.
Table 76.
I2C interface characteristics
Symbol
Parameter
Conditions
Min
fSCL(1)
I²C SCL frequency
fCPU=4 MHz to 8 MHz,
VDD= 2.4 to 5.5 V
Max
Unit
400
kHz
1. The I2C interface will not function below the minimum clock speed of 4 MHz (see Table 77).
Table 77 gives the values to be written in the I2CCCR register to obtain the required I2C
SCL line frequency.
Table 77.
SCL frequency (multimaster I2C interface)(1)(2)(3)
I2CCCR Value
fCPU = 4 MHz
fCPU = 8 MHz
fSCL
VDD = 3.3 V
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
RP=3.3kΩ
RP=4.7kΩ
RP=3.3kΩ
RP=4.7kΩ
RP=3.3kΩ
RP=4.7kΩ
RP=3.3kΩ
RP=4.7kΩ
400
NA
NA
NA
NA
84h
83h
84h
84h
300
NA
NA
NA
NA
86h
86h
86h
86h
200
84h
84h
84h
84h
8Ah
8Ah
8Ah
8Ah
100
11h
11h
11h
11h
25h
24h
25h
24h
50
25h
25h
25h
25h
4Ch
4Ch
4Dh
4Ch
20
61h
61h
61h
62h
FFh
FFh
FFh
FFh
1. RP = External pull-up resistance, fSCL = I2C speed, NA = Not achievable, TBD = To be determined.
2. For fast mode speeds, achieved speed can have ±5% tolerance. For other speed ranges, achieved speed can have ±2%
tolerance.
3. The above variations depend on the accuracy of the external components used.
153/188
Electrical characteristics
13.6
ST7LITE49M
Clock and timing characteristics
Subject to general operating conditions for VDD, fOSC, and TA.
Table 78.
General timings
Symbol
Parameter(1)
Conditions
tc(INST)
Instruction cycle time
fCPU=8MHz
tv(IT)
Interrupt reaction time(3)
tv(IT) = ∆tc(INST) + 10
fCPU=8MHz
Min
Typ(2)
Max
Unit
2
3
12
tCPU
250
375
1500
ns
10
22
tCPU
1.25
2.75
µs
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles
needed to finish the current instruction execution.
Table 79.
External clock source characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
VOSC1H or
VCLKIN_H
OSC1/CLKIN input pin high
level voltage
0.7xVDD
VDD
VOSC1L or
VCLKIN_L
OSC1/CLKIN input pin low
level voltage
VSS
0.3xVDD
tw(OSC1H) or
tw(CLKINH)
tw(OSC1L) or
tw(CLKINL)
OSC1/CLKIN high or low
time(1)
V
see Figure 72
15
ns
tr(OSC1) or tr(CLKIN)
OSC1/CLKIN rise or fall time(1)
tf(OSC1) or tf(CLKIN)
OSCx/CLKIN Input leakage
current
IL
15
VSS≤VIN≤VDD
±1
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 72. Typical application with an external clock source
90%
VOSC1H or VCLKINH
10%
VOSC1L or VCLKINL
tr(OSC1 or CLKIN))
tf(OSC1 or CLKIN)
tw(OSC1H or CLKINH))
OSC2
tw(OSC1L or CLKINL)
Not connected internally
fOSC
EXTERNAL
CLOCK SOURCE
OSC1/CLKIN
IL
ST7xxx
154/188
Unit
µA
ST7LITE49M
13.6.1
Electrical characteristics
Auto Wake Up from Halt oscillator (AWU)
Table 80.
AWU from Halt characteristics
Symbol
Parameter(1)
fAWU
AWU Oscillator
Frequency
tRCSRT
AWU Oscillator startup
time
Conditions
Min
Typ
Max
Unit
16
32
64
kHz
50
µs
1. Guaranteed by Design. Not tested in production.
13.6.2
Crystal and ceramic resonator oscillators
The ST7 internal clock can be supplied with ten different Crystal/Ceramic resonator
oscillators. All the information given in this paragraph are based on characterization results
with specified typical external components. In the application, the resonator and the load
capacitors have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, package, accuracy...).
Table 81.
Crystal/ceramic resonator oscillator characteristics
Symbol
Parameter
Conditions
fCrOSC
Crystal Oscillator Frequency
CL1
CL2
Recommended load capacitance
versus equivalent serial
resistance of the crystal or
ceramic resonator (RS)
Min
Typ
2
Max
Unit
16
MHz
TBD(1)
pF
1. TBD stands for ‘to be determined’.
Figure 73. Typical application with a crystal or ceramic resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
i2
fOSC
CL1
OSC1
RESONATOR
CL2
OSC2
ST7LITE49M
Rd
155/188
Electrical characteristics
13.7
ST7LITE49M
Memory characteristics
TA = -40°C to 125 °C, unless otherwise specified.
Table 82.
RAM and hardware registers characteristics
Symbol
Parameter
Conditions
Min
VRM
Data retention mode(1)
Halt mode (or Reset)
1.6
Typ
Max
Unit
V
1. Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in
hardware registers (only in Halt mode). Guaranteed by construction, not tested in production.
Table 83.
Flash program memory characteristics
Symbol
Parameter
Conditions
Min
VDD
Operating voltage for Flash
Write/Erase
Refer to operating
range of VDD with TA,
Section 13.3.1 on
page 145
2.4
Programming time for 1~32
bytes(1)
TA=−40 to +125 °C
Programming time for 4 kbytes
TA=+25 °C
tprog
tRET
NRW
IDD
Data
TA=+55
retention(2)
Write erase cycles
Supply current(4)
°C(3)
Typ
Max
Unit
5.5
V
5
10
ms
0.64
1.28
s
20
years
TA=+25 °C
10K
cycles
Read / Write / Erase
modes
fCPU = 8 MHz,
VDD = 5.5 V
2.6
mA
No Read/No Write
mode
100
µA
0
0.1
µA
Typ
Max
Unit
5.5
V
10
ms
Power down mode /
Halt
1. Up to 32 bytes can be programmed at a time.
2. Data based on reliability test results and monitored in production.
3. The data retention time increases when the TA decreases.
4. Guaranteed by Design. Not tested in production.
Table 84.
Data EEPROM memory characteristics
Symbol
Parameter
Conditions
Min
VDD
Operating voltage for
EEPROM Write/Erase
Refer to operating range of
VDD with TA, Section 13.3.1 on
page 145
2.4
tprog
Programming time for
1~32 bytes
TA=−40 to +125°C
tret
Data retention(1)
TA=+55°C(2)
NRW
Write erase cycles
TA=+25°C
1. Data based on reliability test results and monitored in production.
2. The data retention time increases when the TA decreases.
156/188
5
20
years
300K cycles
ST7LITE49M
13.8
Electrical characteristics
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
13.8.1
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electro magnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electrostatic Discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test
conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
●
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
–
Corrupted Program Counter
–
Unexpected reset
–
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and Program Counter corruption) can
be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins
for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behaviour is detected, the software
can be hardened to prevent unrecoverable errors occurring (see application note
AN1015).
Table 85.
EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VDD=5 V, TA=+25 °C, fOSC=8 MHz
conforms to IEC 1000-4-2
2B
VFFTB
Fast transient voltage burst limits to be
applied through 100pF on VDD and VSS
pins to induce a functional disturbance
VDD=5 V, TA=+25 °C, fOSC=8 MHz
conforms to IEC 1000-4-4
3B
157/188
Electrical characteristics
13.8.2
ST7LITE49M
Electromagnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 86.
Symbol
EMI characteristics(1)
Parameter
Conditions
Monitored
frequency band
Max vs.
[fOSC/fCPU](2)
Unit
8/4MHz 16/8MHz
SEMI
Peak level
VDD=5V, TA=+25°C, ,
conforming to SAE
J 1752/3
0.1 MHz to 30 MHz
28
32
30 MHz to 130 MHz
31
34
130 MHz to 1 GHz
18
26
SAE EMI Level
3
3.5
dBµV
-
1. Data based on characterization results, not tested in production.
2. TBD stands for ‘to be determined’.
13.8.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: Human Body model and Machine model. This test conforms to the
JESD22-A114A/A115A standard.
Table 87.
Absolute maximum ratings
Symbol
Ratings
Conditions
Maximum
value(1)
VESD(HBM)
Electrostatic discharge voltage (Human Body
model)
TA=+25 °C
4000
VESD(CDM)
Electrostatic discharge voltage (Charge Device
model)
TA=+25 °C
500
Unit
V
1. Data based on characterization results, not tested in production.
158/188
ST7LITE49M
Electrical characteristics
Static and dynamic latch-up
●
LU: 3 complementary static tests are required on 6 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
Table 88.
Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +125 °C
A
DLU
Dynamic latch-up class
VDD = 5.5 V, fOSC = 4 MHz,
TA = +125 °C
A
159/188
Electrical characteristics
ST7LITE49M
13.9
I/O port pin characteristics
13.9.1
General characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Table 89.
General characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
VIL
Input low level voltage
VSS - 0.3
0.3VDD
VIH
Input high level voltage
0.7VDD
VDD+0.3
Vhys
Schmitt trigger voltage
hysteresis(1)
IL
Input leakage current
VSS ≤ VIN ≤ VDD
IS
Static current consumption
induced by each floating
input pin(2)
Floating input mode
RPU
Weak pull-up equivalent
resistor(3)
CIO
I/O pin capacitance
tf(IO)out
Output high to low level fall
time(1)
tr(IO)out
Output low to high level rise
time(1)
tw(IT)in
External interrupt pulse
time(4)
Unit
V
400
mV
±1
µA
VIN=VSS
400
VDD=5 V
100
120
140
kΩ
300(1)
VDD=3 V
5
pF
25
CL=50 pF
Between 10% and 90%
ns
25
1
tCPU
1. Data based on validation/design results.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 74). Static peak current value taken at a fixed VIN value,
based on design simulation and technology characteristics, not tested in production. This value depends on VDD and
temperature values.
3. The RPU pull-up equivalent resistor is based on a resistive transistor.
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 74. Two typical applications with unused I/O pin
VDD
ST7XXX
10kΩ
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
ST7XXX
1. During normal operation the ICCCLK pin must be pulled-up, internally or externally (external pull-up of 10k
mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset.
2. I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of
greater EMC robustness and lower cost.
160/188
ST7LITE49M
Electrical characteristics
Figure 75. Rpu resistance versus voltage at four different temperatures
25°C
350
-40°C
Rpu [kOhm]
300
85°C
250
125°C
200
150
100
50
5.6
5.2
4.8
4.4
4
3.6
3.2
2.8
2.4
0
Vdd [V]
Figure 76. Ipu current versus voltage at four different temperatures
Ipu current vs Vdd @ 4 temp
25°C
-40°C
85°C
125°C
80
70
50
40
30
20
10
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
2.8
2.6
0
2.4
Ipu [uA]
60
Vdd [V]
161/188
Electrical characteristics
13.9.2
ST7LITE49M
Output driving current
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 90.
Symbol
Output driving current characteristics
Parameter
Conditions
VOL(1)
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 82)
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 78 and Figure 81)
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
VOH(2)(3)
VOL(1)(3)
VOH (2)(3)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(Figure 89)
VDD = 3 V
VOL
(1)(3)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 90)
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 77)
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time (see
Figure 80)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 88)
Max
IIO=+5 mA,
TA≤ 125°C
1.0
IIO=+2mA,TA≤ 125 °C
0.4
IIO=+20mA,TA≤ 125
°C
1.3
IIO=+8mATA≤ 125 °C
0.75
IIO=-5mA,TA≤ 125
°C
VDD-1.5
IIO=-2mATA≤ 125 °C
VDD-0.8
IIO=+2mATA≤ 125 °C
0.5
IIO=+8mATA≤ 125 °C
0.5
IIO=-2mATA≤ 125 °C
VDD = 2.4 V
VOH(2)
VDD = 5 V
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 79)
Min
V
VDD-0.8
IIO=+2mATA≤ 125 °C
0.6
IIO=+8mATA≤ 125 °C
0.6
IIO=-2mATA≤ 125 °C
Unit
VDD-0.9
1. The IIO current sunk must always respect the absolute maximum rating specified in Section Table 66. and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section Table 66. and the sum of IIO
(I/O ports and control pins) must not exceed IVDD.
3. Not tested in production, based on characterization results.
162/188
ST7LITE49M
Electrical characteristics
Figure 77. Typical VOL at VDD = 2.4 V (standard)
VOL [V]
-40°C
25°C
1400
1200
1000
800
600
400
200
0
85°C
125°C
0
2
4
IIO [mA]
Figure 78. Typical VOL at VDD = 3 V (standard)
-40°C
1400
25°C
VOL [V]
1200
85°C
1000
125°C
800
600
400
200
0
0
2
4
6
IIO [mA]
Figure 79. Typical VOL at VDD = 5 V (standard)
-40°C
2000
25°C
85°C
VOL [V]
1500
125°C
1000
500
0
0
2
4
6
8
10
IIO [mA]
163/188
Electrical characteristics
ST7LITE49M
Figure 80. Typical VOL at VDD = 2.4 V (high sink)
-40°C
1200
25°C
VOL [V]
1000
85°C
800
125°C
600
400
200
0
0
2
4
6
8
10
12
14
16
IIO [mA]
Figure 81. Typical VOL at VDD = 3 V (high sink)
VOL [V]
-40°C
1600
25°C
1400
85°C
1200
125°C
1000
800
600
400
200
0
0
2
4
6
8
10
12
14
16
18
20
14
16
18
20
IIO [mA]
Figure 82. Typical VOL at VDD = 5 V (high sink)
-40°C
1000
25°C
85°C
VOL [V]
800
125°C
600
400
200
0
0
2
4
6
8
10
12
IIO [mA]
164/188
ST7LITE49M
Electrical characteristics
Figure 83. Typical VOL vs. VDD at IIO = 2 mA (standard)
-40°C
VOL[mV]
540
25°C
440
85°C
340
125°C
240
5.
6
5.
2
4.
8
4.
4
4
3.
6
3.
2
2.
8
2.
4
140
VDD [V]
Figure 84. Typical VOL vs. VDD at IIO = 4 mA (standard)
-40°C
VOL[mV]
1640
25°C
85°C
1140
125°C
640
2
6
5.
5.
8
4.
6
3.
4
2
3.
4.
8
2.
4
4
2.
140
VDD [V]
Figure 85. Typical VOL vs VDD at IIO = 2 mA (high sink)
-40°C
VOL[mV]
120
25°C
100
85°C
80
125°C
60
40
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
VDD [V]
165/188
Electrical characteristics
ST7LITE49M
Figure 86. Typical VOL vs VDD at IO = 8 mA (high sink)
VOL[mV]
-40°C
540
25°C
440
85°C
340
125°C
240
5.
6
5.
2
4.
8
4.
4
4
3.
6
3.
2
2.
8
2.
4
140
VDD [V]
Figure 87. Typical VOL vs VDD at IIO = 12 mA (high sink)
VOL[mV]
-40°C
1140
25°C
940
85°C
740
125°C
540
340
5.
6
5.
2
4.
8
4.
4
4
3.
6
3.
2
2.
8
2.
4
140
VDD [V]
VDD-VOH [mV]
Figure 88. Typical VDD-VOH vs. IIO at VDD = 2.4 V (high sink)
800
-40°C
700
25°C
600
85°C
500
125°C
400
300
200
100
0
2
4
IIO[mA]
166/188
ST7LITE49M
Electrical characteristics
Figure 89. Typical VDD-VOH vs. IIO at VDD = 3 V (high sink)
-40°C
25°C
1800
85°C
VDD-VOH [mV]
1600
125°C
1400
1200
1000
800
600
400
200
0
0
2
4
6
IIO[mA]
VDD-VOH [mV]
Figure 90. Typical VDD-VOH vs. IIO at VDD = 5 V (high sink)
4500
-40°C
4000
25°C
3500
85°C
3000
125°C
2500
2000
1500
1000
500
0
0
2
4
6
8
10
12
14
IIO[mA]
167/188
Electrical characteristics
ST7LITE49M
Figure 91. Typical VDD-VOH vs. IIO at VDD = 2.4 V (standard)
VDD-VOH [mV]
-40°C
800
25°C
700
85°C
600
125°C
500
400
300
200
100
0
0
2
IIO[mA]
Figure 92. Typical VDD-VOH vs. IIO at VDD = 3 V (standard)
1800
-40°C
VDD-VOH [mV]
1600
25°C
1400
1200
85°C
1000
125°C
800
600
400
200
0
0
2
4
6
IIO[mA]
VDD-VOH [mV]
Figure 93. Typical VDD-VOH vs. IIO at VDD = 5 V (standard)
-40°C
4500
4000
3500
3000
2500
2000
1500
1000
500
0
25°C
85°C
125°C
0
2
4
6
8
IIO[mA]
168/188
10
12
14
ST7LITE49M
Electrical characteristics
VDD-VOH [mV]
Figure 94. Typical VDD-VOH vs. VDD at IIO = 2 mA (high sink)
800
-40°C
700
25°C
600
85°C
500
125°C
400
300
200
100
6
2
5.
5.
8
4.
6
3.
4
2
3.
4
8
2.
4.
4
2.
0
VDD[V]
Figure 95. Typical VDD-VOH vs. VDD at IIO = 4 mA (high sink)
25°C
1800
1600
1400
1200
1000
800
600
400
200
0
85°C
4
5.
6
4.
5
2
8
3.
4.
4
3.
3
6
125°C
2.
VDD-VOH [mV]
-40°C
VDD [V]
169/188
Electrical characteristics
ST7LITE49M
13.10
Control pin characteristics
13.10.1
Asynchronous RESET pin
TA = -40 to 125 °C, unless otherwise specified.
Table 91.
Asynchronous RESET pin characteristics
Symbol
Parameter
VIL
Input low level voltage
VSS - 0.3
0.37VDD
VIH
Input high level voltage
0.7VDD
VDD+0.3
Vhys
Schmitt trigger voltage hysteresis(1)
VOL
Output low level
Conditions
voltage (2)
RON
Pull-up equivalent resistor(3)
tw(RSTL)out
Generated reset pulse duration
th(RSTL)in
tg(RSTL)in
External reset pulse hold
VDD=5V
VIN=VSS
Min
IIO=+2mA
VDD=5V
30
Filtered glitch duration
Max
VDD=3V
Unit
V
2
V
200
mV
50
70
90(1)
90(1)
Internal reset sources
time(4)
Typ
kΩ
µs
µs
20
200
ns
1. Data based on characterization results, not tested in production
2. The IIO current sunk must always respect the absolute maximum rating specified in Section Table 66. on page 144 and the
sum of IIO (I/O ports and control pins) must not exceed IVSS.
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax
and VDD
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
170/188
ST7LITE49M
Electrical characteristics
Figure 96. RESET pin protection when LVD is enabled3)4)
VDD
Required
Optional
(note 3)
EXTERNAL
RESET
ST7xxx
RON
INTERNAL
RESET
Filter
0.01µF
1MΩ
PULSE
GENERATOR
WATCHDOG
ILLEGAL OPCODE 5)
LVD RESET
The reset network protects the device against parasitic resets. The output of the external
reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the
RESET pin can go below the VIL max. level specified in Section 13.10.1 on page 170.
Otherwise the reset will not be taken into account internally. Because the reset circuit is
designed to allow the internal Reset to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin is less than the absolute maximum value specified
for IINJ(RESET) in Section Table 66. on page 144.
When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A
10nF pull-down capacitor is required to filter noise on the reset line.
In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down
resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect
of the power supply (this will add 5µA to the power consumption of the MCU).
Tips when using the LVD
●
Check that all recommendations related to ICCCLK and reset circuit have been applied
(see caution in Table 2 on page 16 and notes above).
●
Check that the power supply is properly decoupled (100nF + 10µF close to the MCU).
Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a
100nF + 1MΩ pull-down on the RESET pin.
●
The capacitors connected on the RESET pin and also the power supply are key to
avoid any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a
robust solution. Otherwise: replace 10nF pull-down on the RESET pin with a 5µF to
20µF capacitor.”
171/188
Electrical characteristics
ST7LITE49M
Figure 97. RESET pin protection when LVD is disabled
VDD
ST72XXX
RON
USER
EXTERNAL
RESET
CIRCUIT
INTERNAL
RESET
Filter
0.01µF
WATCHDOG
PULSE
GENERATOR
ILLEGAL OPCODE 5)
Required
1. The reset network protects the device against parasitic resets.
The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin
can go below the VIL max. level specified in Section 13.10.1 on page 170. Otherwise the reset will not be
taken into account internally.
Because the reset circuit is designed to allow the internal Reset to be output in the RESET pin, the user
must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for
IINJ(RESET) in Section Table 66. on page 144.
2. Please refer to Section 12.2.1 on page 139 for more details on illegal opcode reset conditions.
13.11
10-bit ADC characteristics
Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Table 92.
ADC characteristics
Symbol
Parameter
fADC
ADC clock frequency(2)
VAIN
Conversion voltage range
RAIN
External input resistor
Conditions
Min
Typ(1)
VSSA
4
MHz
VDDA
V
VDD = 5V, fADC=4MHz
VDD = 3.3V, fADC=4MHz
7k(3)
2.7V ≤ VDD ≤ 5.5V, fADC=2MHz
10k(3)
2.4V ≤ VDD ≤ 2.7V, fADC=1MHz
20k(3)
Internal sample and hold capacitor
3
tSTAB
Stabilization time after ADC enable
0(4)
tADC
Unit
8k(3)
CADC
Conversion time (Sample+Hold)
Max
fCPU=8MHz, fADC=4MHz
- Sample capacitor loading time
- Hold conversion time
Ω
pF
µs
3.5
4
10
1/fADC
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guidelines
and are not tested.
2. The maximum ADC clock frequency allowed within VDD = 2.4V to 2.7V operating range is 1MHz.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than the maximum
value). Data guaranteed by Design, not tested in production.
4. The stabilization time of the A/D converter is masked by the first tLOAD. The first conversion after the enable is then always
valid.
172/188
ST7LITE49M
Electrical characteristics
Figure 98. Typical application with ADC
VDD
VT
0.6V
RAIN
AINx
10-Bit A/D
Conversion
VAIN
VT
0.6V
IL
±1µA
CADC
ST7xxx
Table 93.
Symbol
(1)
ADC accuracy with VDD = 3.3 to 5.5 V
Parameter
|ET|
Total unadjusted error
|EO|
Offset error
Conditions
fCPU=8 MHz,
fADC=4 MHz(1)
Typ
Max
2.0
5.0
0.9
2.5
1.0
1.5
|EG|
Gain Error
|ED|
Differential linearity error
1.2
3.5
|EL|
Integral linearity error
1.1
4.5
Typ
Max
1.9
3.0
0.9
1.5
0.8
1.4
Unit
LSB
1. Data based on characterization results over the whole temperature range.
Table 94.
Symbol
(1)
ADC accuracy with VDD = 2.7 to 3.3 V
Parameter
|ET|
Total unadjusted error
|EO|
Offset error
Conditions
fCPU=4 MHz,
fADC=2 MHz(1)
|EG|
Gain Error
|ED|
Differential linearity error
1.4
2.5
|EL|
Integral linearity error
1.1
2.5
Typ
Max
2.5
3.5
1.1
1.5
0.5
1.5
Unit
LSB
1. Data based on characterization results over the whole temperature range.
Table 95.
Symbol
(1)
ADC accuracy with VDD = 2.4 to 2.7 V
Parameter
|ET|
Total unadjusted error
|EO|
Offset error
Conditions
fCPU=2 MHz,
fADC=1 MHz(1)
|EG|
Gain Error
|ED|
Differential linearity error
1.1
2.5
|EL|
Integral linearity error
1.2
2.5
Unit
LSB
1. Data based on characterization results at ambient temperature and above.
173/188
Electrical characteristics
ST7LITE49M
Figure 99. ADC accuracy characteristics
Digital Result
EG
1023
1022
1LSB
1021
IDEAL
V
–V
DD
SS
= --------------------------------
(2) The ideal transfer curve
1024
(3) End point correlation line
(2)
ET
7
(3)
(1)
6
5
EO
4
EL
3
ED
2
0
VSS
174/188
1
2
3
4
5
6
7
ET=Total Unadjusted Error:
maximum deviation between the
actual and the ideal transfer
curves.
EO=Offset Error: deviation
between the first actual transition
1 LSBIDEAL
1
(1) Example of an actual transfer
curve
1021 1022 1023 1024
VDD
Vin
ST7LITE49M
14
Device configuration and ordering information
Device configuration and ordering information
This device is available for production in user programmable version (Flash).
ST7LITE49M XFlash devices are shipped to customers with a default program memory
content (FFh).
14.1
Option bytes
The two option bytes allow the hardware configuration of the microcontroller to be selected.
The option bytes can be accessed only in programming mode (for example using a standard
ST7 programming tool).
14.1.1
Option byte 1
●
Bit 7:6 = CKSEL[1:0] Start-up clock selection. These bits are used to select the startup
frequency. By default, the internal RC is selected.
Table 96.
Startup clock selection
Configuration
CKSEL1
CKSEL0
Internal RC as Startup Clock
0
0
AWU RC as a Startup Clock
0
1
External crystal/ceramic resonator
1
0
External Clock
1
1
●
Bits 5:4 = Reserved, must always be 1.
●
Bits 3:2 = LVD[1:0] Low Voltage Detection selection. These option bits enable the low
voltage detection block (LVD) with a selected threshold as shown in Table 97.
Table 97.
LVD threshold configuration
Configuration
VD1
VD0
LVD Off (default value)
1
1
Highest Voltage Threshold
1
0
Medium Voltage Threshold
0
1
Lowest Voltage Threshold
0
0
●
Bit 1 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
●
Bit 0 = WDG HALT Watchdog Reset on Halt
This option bit determines if a Reset is generated when entering Halt mode while the
Watchdog is active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
175/188
Device configuration and ordering information
14.1.2
ST7LITE49M
Option byte 0
●
OPT7 = AWUCK Auto Wake Up Clock Selection
0: 32-kHz Oscillator (VLP) selected as AWU clock
1: AWU RC Oscillator selected as AWU clock.
Note:
If this bit is reset, OSCRANGE[2:0] must be set to 100.
●
OPT6:4 = OSCRANGE[2:0] Oscillator Range
When the internal RC oscillator is not selected (CKSEL1=1), these option bits (and
CKSEL0) select the range of the resonator oscillator current source or the external
clock source.
Table 98.
Selection of the resonator oscillator range
OSCRANGE(1)
2
1
0
LP
1~2MHz
0
0
0
MP
2~4MHz
0
0
1
MS
4~8MHz
0
1
0
HS
8~16MHz
0
1
1
VLP
32.768kHz
1
0
0
External Clock on OSC1/CLKIN
1
0
1
Reserved
1
1
0
External Clock on PB1
1
1
1
Typ. frequency range
with Resonator
1. When the internal RC oscillator is selected, the CLKSEL option bits must be kept at their default value in
order to select the 256 clock cycle delay (see Section 7.3).
●
OPT 3:2 = SEC[1:0] Sector 0 size definition
These option bits indicate the size of sector 0 according to Table 99.
Table 99.
●
Configuration of sector size
Sector 0 Size
SEC1
SEC0
0.5k
0
0
1k
0
1
2
1
0
4k
1
1
Bit 1 = FMP_R Read-Out Protection
Read-Out Protection, when selected provides a protection against program memory
content extraction and against write access to Flash memory. Erasing the option bytes
when the FMP_R option is selected will cause the whole memory to be erased first,
and the device can be reprogrammed. Refer to Section 4.5 on page 24 and the ST7
Flash Programming Reference Manual for more details.
0: Read-Out Protection off
1: Read-Out Protection on
176/188
ST7LITE49M
●
Device configuration and ordering information
Bit 0 = FMP_W Flash write protection
This option indicates if the Flash program memory is write protected.
Warning: When this option is selected, the program memory (and the option bit itself)
can never be erased or programmed again.
0: Write protection off
1: Write protection on
Option byte 0
Option byte 1
7
0
7
0
AWU
SEC SEC FMP FMP CKS CKS
OSCRANGE[2:0]
CK
1
0
R
W
EL1 EL0
Default
Value
1
1
1
1
1
1
0
0
0
0
Res
1
Res LVD1 LVD0
1
1
1
WDG WDG
SW HALT
1
1
177/188
Device configuration and ordering information
14.2
ST7LITE49M
Device ordering information
Table 100. Supported part numbers
Part number
ST7FLI49MK1B6
ST7FLI49MK1T6
14.3
Program
memory
(bytes)
RAM
(bytes)
Data EEPROM
(bytes)
4 K of Flash
memory
384
128
Package
SDIP32
LQFP32
Development tools
Development tools for the ST7 microcontrollers include a complete range of hardware
systems and software tools from STMicroelectronics and third-party tool suppliers. The
range of tools includes solutions to help you evaluate microcontroller peripherals, develop
and debug your application, and program your microcontrollers.
14.3.1
Starter kits
ST offers complete, affordable starter kits. Starter kits are complete hardware/software tool
packages that include features and samples to help you quickly start developing your
application.
14.3.2
Development and debugging tools
Application development for ST7 is supported by fully optimizing C Compilers and the ST7
Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated
development environments in order to facilitate the debugging and fine-tuning of your
application. The Cosmic C Compiler is available in a free version that outputs up to
16Kbytes of code.
The range of hardware tools includes a full-featured LITE4 Emulator and the low-cost RLink
in-circuit debugger/programmer. These tools are supported by the ST7 Toolset from
STMicroelectronics, which includes the STVD7 integrated development environment (IDE)
with high-level language debugger, editor, project manager and integrated programming
interface.
14.3.3
Programming tools
During the development cycle, the LITE4 emulator and the RLink provide in-circuit
programming capability for programming the Flash microcontroller on your application
board.
ST also provides a low-cost dedicated in-circuit programmer, the ST7-STICK, as well as
ST7 Socket Boards which provide all the sockets required for programming any of the
devices in a specific ST7 sub-family on a platform that can be used with any tool with incircuit programming capability for ST7.
For production programming of ST7 devices, ST’s third-party tool partners also provide a
complete range of gang and automated programming solutions, which are ready to integrate
into your production environment.
178/188
ST7LITE49M
14.3.4
Device configuration and ordering information
Order codes for development and programming tools
Table 101 below lists the ordering codes for the ST7LITE49M development and
programming tools. For additional ordering codes for spare parts and accessories, refer to
the online product selector at www.st.com/mcu.
14.3.5
Order codes for ST7LITE49M development tools
Table 101. Development tool order codes for the ST7LITE49M family
In-circuit Debugger, RLink
Series(1)
MCU
Starter kit
without demo
board
Emulator
Starter kit
with demo
board
ST7FLI49MK1T6
ST7FLI49MK1B6
Programming tool
In-circuit
programmer
LITE4 emulator(2)
(3)
STX-RLINK
STX-RLINK
ST7STICK(4)(5)
STFLITESK/RAIS(3)
ST socket
boards and
EPBs
LITE4
Socket
boardSK/RAIS
(2)
1. Available from ST or from Raisonance, www.raisonance.com.
2. Contact local ST sales office for sales types
3. USB connection to PC.
4. Add suffix /EU, /UK or /US for the power supply for your region
5. Parallel port connection to PC
14.4
ST7 application notes
Table 102. ST7 application notes
Identification
Description
Application examples
AN1658
Serial numbering implementation
AN1720
managing the Read-Out Protection in Flash microcontrollers
AN1755
A high resolution/precision thermometer using ST7 and NE555
AN1756
Choosing a DALI implementation strategy with ST7DALI
AN1812
A high precision, low cost, single supply ADC for positive and negative input voltages
Example drivers
AN 969
SCI communication between ST7 and PC
AN 970
SPI communication between ST7 and EEPROM
AN 971
I²C communication between ST7 and M24Cxx EEPROM
AN 972
ST7 software SPI master communication
AN 973
SCI software communication with a PC using ST72251 16-bit timer
AN 974
Real time clock with ST7 timer Output Compare
179/188
Device configuration and ordering information
ST7LITE49M
Table 102. ST7 application notes (continued)
Identification
Description
AN 976
Driving a buzzer through ST7 timer PWM function
AN 979
Driving an analog keyboard with the ST7 ADC
AN 980
ST7 keypad decoding techniques, implementing wake-up on keystroke
AN1017
Using the ST7 Universal Serial Bus microcontroller
AN1041
Using ST7 PWM signal to generate analog output (sinusoïd)
AN1042
ST7 routine for I²C Slave mode Management
AN1044
Multiple interrupt sources management for ST7 MCUs
AN1045
ST7 S/W implementation of I²C bus master
AN1046
UART emulation software
AN1047
Managing reception errors with the ST7 SCI peripherals
AN1048
ST7 software LCD Driver
AN1078
PWM duty cycle switch implementing true 0% & 100% duty cycle
AN1082
Description of the ST72141 motor control peripherals registers
AN1083
ST72141 BLDC motor control software and flowchart example
AN1105
ST7 pCAN peripheral driver
AN1129
PWM management for BLDC motor drives using the ST72141
AN1130
An introduction to sensorless brushless DC motor drive applications with the ST72141
AN1148
Using the ST7263 for designing a USB mouse
AN1149
Handling Suspend mode on a USB mouse
AN1180
Using the ST7263 kit to implement a USB game pad
AN1276
BLDC motor start routine for the ST72141 microcontroller
AN1321
Using the ST72141 motor control MCU in Sensor mode
AN1325
Using the ST7 USB low-speed firmware V4.x
AN1445
Emulated 16-bit slave SPI
AN1475
Developing an ST7265X mass storage application
AN1504
Starting a PWM signal directly at high level using the ST7 16-bit timer
AN1602
16-bit timing operations using ST7262 or ST7263B ST7 USB MCUs
AN1633
Device firmware upgrade (DFU) implementation in ST7 non-USB applications
AN1712
Generating a high resolution sinewave using ST7 PWMART
AN1713
SMBus slave driver for ST7 I2C peripherals
AN1753
Software UART using 12-bit ART
AN1947
ST7MC PMAC sine wave motor control software library
General purpose
AN1476
180/188
Low cost power supply for home appliances
ST7LITE49M
Device configuration and ordering information
Table 102. ST7 application notes (continued)
Identification
Description
AN1526
ST7FLITE0 quick reference note
AN1709
EMC design for ST microcontrollers
AN1752
ST72324 quick reference note
Product evaluation
AN 910
Performance benchmarking
AN 990
ST7 benefits vs industry standard
AN1077
Overview of enhanced CAN controllers for ST7 and ST9 MCUs
AN1086
U435 can-do solutions for car multiplexing
AN1103
Improved B-EMF detection for low speed, low voltage with ST72141
AN1150
Benchmark ST72 vs PC16
AN1151
Performance comparison between ST72254 & PC16F876
AN1278
LIN (Local Interconnect Network) solutions
Product migration
AN1131
Migrating applications from ST72511/311/214/124 to ST72521/321/324
AN1322
Migrating an application from ST7263 Rev.B to ST7263B
AN1365
Guidelines for migrating ST72C254 applications to ST72F264
AN1604
How to use ST7MDT1-TRAIN with ST72F264
AN2200
Guidelines for migrating ST7LITE1x applications to ST7FLITE1xB
Product optimization
AN 982
Using ST7 with ceramic resonator
AN1014
How to minimize the ST7 power consumption
AN1015
Software techniques for improving microcontroller EMC performance
AN1040
Monitoring the Vbus signal for USB self-powered devices
AN1070
ST7 checksum self-checking capability
AN1181
Electrostatic discharge sensitive measurement
AN1324
Calibrating the RC oscillator of the ST7FLITE0 MCU using the mains
AN1502
Emulated data EEPROM with ST7 HD Flash memory
AN1529
Extending the current & voltage capability on the ST7265 VDDF supply
AN1530
Accurate timebase for low-cost ST7 applications with internal RC oscillator
AN1605
Using an active RC to wake up the ST7LITE0 from power saving mode
AN1636
Understanding and minimizing ADC conversion errors
AN1828
PIR (passive infrared) detector using the ST7FLITE05/09/SUPERLITE
AN1946
Sensorless BLDC motor control and BEMF sampling methods with ST7MC
AN1953
PFC for ST7MC starter kit
181/188
Device configuration and ordering information
ST7LITE49M
Table 102. ST7 application notes (continued)
Identification
AN1971
Description
ST7LITE0 microcontrolled ballast
Programming and tools
AN 978
ST7 Visual DeVELOP software key debugging features
AN 983
Key features of the Cosmic ST7 C-compiler package
AN 985
Executing code In ST7 RAM
AN 986
Using the indirect addressing mode with ST7
AN 987
ST7 serial test controller programming
AN 988
Starting with ST7 assembly tool chain
AN1039
ST7 math utility routines
AN1071
Half duplex USB-to-serial bridge using the ST72611 USB microcontroller
AN1106
Translating assembly code from HC05 to ST7
AN1179
Programming ST7 Flash microcontrollers in remote ISP mode (In-situ programming)
AN1446
Using the ST72521 emulator to debug an ST72324 target application
AN1477
Emulated data EEPROM with XFlash memory
AN1527
Developing a USB smartcard reader with ST7SCR
AN1575
On-board programming methods for XFlash and HD Flash ST7 MCUs
AN1576
In-application programming (IAP) drivers for ST7 HD Flash or XFlash MCUs
AN1577
Device firmware upgrade (DFU) Implementation for ST7 USB applications
AN1601
Software implementation for ST7DALI-EVAL
AN1603
Using the ST7 USB device firmware upgrade development kit (DFU-DK)
AN1635
ST7 customer ROM code release information
AN1754
Data logging program for testing ST7 applications via ICC
AN1796
Field updates for Flash memory based ST7 applications using a PC comm port
AN1900
Hardware implementation for ST7DALI-EVAL
AN1904
ST7MC three-phase AC induction motor control software library
AN1905
ST7MC three-phase BLDC motor control software library
System optimization
AN1711
Software techniques for compensating ST7 ADC errors
AN1827
Implementation of SIGMA-DELTA ADC with ST7FLITE05/09
AN2009
PWM management for 3-phase BLDC motor drives using the ST7FMC
AN2030
Back EMF detection during PWM on time by ST7MC
182/188
ST7LITE49M
15
Package characteristics
Package characteristics
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
183/188
Package characteristics
15.1
ST7LITE49M
Package mechanical data
Figure 100. 32-pin plastic dual in-line package, shrink 400mil width, package outline
E
eC
A2 A
A1
L
E1
C
b
b2
e
eA
eB
D
Table 103. 32-pin plastic dual in-line package, shrink 400mil width, mechanical data
mm
inches
Dim.
Min
Typ
Max
Min
Typ
Max
A
3.56
3.76
5.08
0.140
0.148
0.200
A1
0.51
A2
3.05
3.56
4.57
0.120
0.140
0.180
b
0.36
0.46
0.58
0.014
0.018
0.023
b1
0.76
1.02
1.40
0.030
0.040
0.055
C
0.20
0.25
0.36
0.008
0.010
0.014
D
27.43
28.45
1.080
1.100
1.120
E
9.91
10.41
11.05
0.390
0.410
0.435
E1
7.62
8.89
9.40
0.300
0.350
0.370
0.020
e
1.78
0.070
eA
10.16
0.400
eB
12.70
0.500
eC
1.40
0.055
L
2.54
3.05
3.81
0.100
Number of pins
N
184/188
32
0.120
0.150
ST7LITE49M
Package characteristics
Figure 101. 32-pin low profile quad flat package (7x7), package outline
D
A
D1
A2
A1
e
E1 E
b
c
L1
L
h
Table 104. 32-pin low profile quad flat package (7x7), package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.30
C
0.09
Max
0.063
0.15
0.002
0.006
1.40
1.45
0.053
0.055
0.057
0.37
0.45
0.012
0.015
0.018
0.20
0.004
0.008
D
9.00
0.354
D1
7.00
0.276
E
9.00
0.354
E1
7.00
0.276
e
0.80
0.031
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.018
0.024
0.030
L1
1.00
0.039
Number of pins
N
32
1. Values in inches are converted from mm and rounded to 3 decimal digits.
185/188
Package characteristics
15.2
ST7LITE49M
Thermal characteristics
Table 105. Thermal characteristics(1)
Symbol
Ratings
RthJA
Package thermal resistance
(junction to ambient)
TJmax
Maximum junction
temperature(2)
PDmax
Power dissipation(3)
LQFP32
LQFP32
Value
Unit
TBD
°C/W
TBD
°C
TBD
mW
1. TBD stands for ‘to be determined’.
2. The maximum chip-junction temperature is based on technology characteristics.
3. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.
The power dissipation of an application can be defined by the user with the formula: PD=PINT+PPORT
where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation depending on the
ports used in the application.
186/188
ST7LITE49M
16
Revision history
Revision history
Table 106. Document revision history
Date
Revision
01-Jun-2007
1
Initial release.
2
Document reformatted and status updated to Full Datasheet.
Table 5. EEPROM register mapping and reset values removed.
Section 7.2.3: Internal RC oscillator updated. Section 7.5.3: AVD
Threshold Selection register (AVDTHCR): global description of
AVD[1:0] added.
Table 69: Operating characteristics with LVD: IDD(LVD) typical and
maximum values updated, and note removed; VtPOR minimum value
updated. Table 71: Voltage drop: minimum and maximum values
added. Table 72: Internal RC oscillator characteristics (5.0 V
calibration), Table 73: Internal RC oscillator characteristics (3.3 V
calibration), and Table 74: Supply current characteristics updated.
Figure 67, Figure 68, Figure 69,Figure 71, and Figure 76 updated.
Table 75: On-chip peripheral characteristics values and Note 2
updated.
tprog and NRW updated in Table 83: Flash program memory
characteristics. NRW updated in Table 84: Data EEPROM memory
characteristics.
Class updated forVFESD in Table 85: EMS characteristics. Table 86:
EMI characteristics updated. Table 86: EMI characteristics updated.
RPU and RON updated in Table 89: General characteristics and
Table 91: Asynchronous RESET pin characteristics, respectively.
13-July-2007
Changes
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ST7LITE49M
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