RV-1805-C3 - Golledge Electronics Ltd.

RV-1805-C3
Datasheet
Date: July 2014
Headquarters:
Micro Crystal AG
Mühlestrasse 14
CH-2540 Grenchen
Switzerland
Tel.
Fax
Internet
Email
Revision N°: 2.0
1/95
+41 32 655 82 82
+41 32 655 82 83
www.microcrystal.com
[email protected]
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
TABLE OF CONTENTS
1. OVERVIEW ........................................................................................................................................................ 6
1.1. GENERAL DESCRIPTION......................................................................................................................... 6
1.2. APPLICATIONS ......................................................................................................................................... 7
2. BLOCK DIAGRAM ............................................................................................................................................. 8
2.1. PINOUT ...................................................................................................................................................... 9
2.2. PIN DESCRIPTION .................................................................................................................................. 10
2.3. FUNCTIONAL DESCRIPTION ................................................................................................................. 11
2.4. DEVICE PROTECTION DIAGRAM ......................................................................................................... 11
3. REGISTER ORGANIZATION .......................................................................................................................... 12
3.1. REGISTER OVERVIEW ........................................................................................................................... 12
3.2. TIME AND DATE REGISTERS ................................................................................................................ 14
3.3. ALARM REGISTERS ............................................................................................................................... 17
3.4. CONFIGURATION REGISTERS.............................................................................................................. 20
3.5. CALIBRATION REGISTERS ................................................................................................................... 24
3.6. SLEEP CONTROL REGISTER ................................................................................................................ 25
3.7. TIMER REGISTERS ................................................................................................................................. 26
3.8. OSCILLATOR REGISTERS..................................................................................................................... 28
3.9. MISCELLANEOUS REGISTERS ............................................................................................................. 29
3.10. ANALOG CONTROL REGISTERS ......................................................................................................... 30
3.11. ID REGISTERS ........................................................................................................................................ 32
3.12. RAM REGISTERS .................................................................................................................................... 34
3.13. REGISTER RESET VALUES SUMMARY ............................................................................................... 35
4. DETAILED FUNCTIONAL DESCRIPTION ..................................................................................................... 36
2
4.2. I C INTERFACE ....................................................................................................................................... 37
4.2.1. BUS NOT BUSY................................................................................................................................ 37
4.2.2. BIT TRANSFER ................................................................................................................................ 37
4.2.3. START AND STOP CONDITIONS ................................................................................................... 37
4.2.4. DATA VALID ..................................................................................................................................... 38
4.2.5. SYSTEM CONFIGURATION ............................................................................................................ 38
4.2.6. ACKNOWLEDGE .............................................................................................................................. 38
4.2.7. ADDRESSING ................................................................................................................................... 39
4.2.8. WRITE OPERATION......................................................................................................................... 40
4.2.9. READ OPERATION AT SPECIFIC ADDRESS ................................................................................ 40
4.2.10. READ OPERATION .......................................................................................................................... 41
4.3. XT OSCILLATOR ..................................................................................................................................... 41
4.4. RC OSCILLATOR .................................................................................................................................... 41
4.5. RTC COUNTER ACCESS........................................................................................................................ 41
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Extrem Low Power Real Time Clock / Calendar Module
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4.6. HUNDREDTHS SYNCHRONIZATION .................................................................................................... 42
4.7. GENERATING HUNDREDTHS OF A SECOND ..................................................................................... 42
4.8. WATCHDOG TIMER ................................................................................................................................ 42
4.9. DIGITAL CALIBRATION.......................................................................................................................... 43
4.9.1. XT OSCILLATOR DIGITAL CALIBRATION ...................................................................................... 43
4.9.2. RC OSCILLATOR DIGITAL CALIBRATION ..................................................................................... 44
4.10. AUTOCALIBRATION ............................................................................................................................... 46
4.11. BASIC AUTOCALIBRATION OPERATION ............................................................................................ 46
4.11.1. AUTOCALIBRATION OPERATION .................................................................................................. 46
4.11.2. XT AUTOCALIBRATION MODE ....................................................................................................... 47
4.11.3. RC AUTOCALIBRATION MODE ...................................................................................................... 47
4.11.4. AUTOCALIBRATION FREQUENCY AND CONTROL ..................................................................... 47
4.11.5. AUTOCALIBRATION FILTER (Cap_RC) PIN .................................................................................. 48
4.11.6. AUTOCALIBRATION FAIL ................................................................................................................ 48
4.11.7. ACCURACY ERRORS IN RC AUTOCALIBRATION MODE ............................................................ 48
4.11.8. A REAL WORLD EXAMPLE ............................................................................................................. 51
4.11.9. RC AUTOCALIBRATION TIMING ACCURACY EXAMPLE ............................................................. 52
4.11.10.
POWER ANALYSIS ................................................................................................................... 53
4.11.11.
DISANDVANTAGES RELATIVE TO THE XT OSCILLATOR ................................................... 53
4.12. OSCILLATOR FAILURE DETECTION .................................................................................................... 54
4.13. INTERRUPTS ........................................................................................................................................... 54
4.13.1. INTERRUPT SUMMARY .................................................................................................................. 54
4.13.2. ALARM INTERRUPT AIRQ .............................................................................................................. 55
4.13.3. COUNTDOWN TIMER INTERRUPT TIRQ....................................................................................... 55
4.13.4. WATCHDOG TIMER INTERRUPT WIRQ ........................................................................................ 55
4.13.5. BATTERY LOW INTERRUPT BLIRQ ............................................................................................... 55
4.13.6. EXTERNAL INTERRUPT X2IRQ ...................................................................................................... 55
4.13.7. OSCILLATOR FAIL INTERRUPT OFIRQ ......................................................................................... 55
4.13.8. AUTOCALIBRATION FAIL INTERRUPT ACIRQ ............................................................................. 55
4.13.9. SERVICING INTERRUPTS .............................................................................................................. 56
4.14. POWER CONTROL AND SWITCHING ................................................................................................... 56
4.14.1. AUTOMATIC SWITCHOVER SUMMARY ........................................................................................ 57
4.14.2. BATTERY LOW FLAG AND INTERRUPT ........................................................................................ 57
4.14.3. ANALOG COMPARATOR ................................................................................................................ 58
4.14.4. PIN CONTROL AND LEAKAGE MANAGEMENT (POWER CONTROL) ........................................ 58
4.14.5. POWER UP TIMING ......................................................................................................................... 59
4.15. RESET SUMMARY .................................................................................................................................. 59
4.15.1. POWER UP RESET .......................................................................................................................... 60
4.15.2. WATCHDOG TIMER ......................................................................................................................... 60
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Extrem Low Power Real Time Clock / Calendar Module
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4.15.3. SLEEP ............................................................................................................................................... 61
4.16. SOFTWARE RESET ................................................................................................................................ 61
4.17. SLEEP CONTROL STATE MACHINE .................................................................................................... 61
4.17.1. RUN ................................................................................................................................................... 62
4.17.2. SWAIT ............................................................................................................................................... 62
4.17.3. SLEEP ............................................................................................................................................... 62
4.17.4. SLP PROTECTION ........................................................................................................................... 64
4.17.5. OUT2S, OUTB AND LKO2 ............................................................................................................... 64
4.17.6. PIN CONTROL AND LEAKAGE MANAGEMENT (SLEEP CONTROL) .......................................... 64
4.18. SYSTEM POWER CONTROL APPLICATIONS...................................................................................... 65
4.18.1. VSS POWER SWITCHED .................................................................................................................. 65
4.18.2. VDD POWER SWITCHED .................................................................................................................. 66
4.18.3. RESET DRIVEN ................................................................................................................................ 66
4.18.4. INTERRUPT DRIVEN ....................................................................................................................... 67
4.19. TYPICAL SYSTEM IMPLEMENTATION ................................................................................................. 67
4.19.1. ALARMS ............................................................................................................................................ 68
4.19.2. COUNTDOWN TIMER ...................................................................................................................... 68
4.19.3. WAKE BUTTON/SWITCH ................................................................................................................. 68
4.19.4. EXTERNAL DEVICE INPUT ............................................................................................................. 68
4.19.5. ANALOG INPUT................................................................................................................................ 68
4.19.6. BATTERY LOW DETECTION ........................................................................................................... 68
4.19.7. ERRORS ........................................................................................................................................... 68
4.20. SAVING PARAMETERS .......................................................................................................................... 69
4.21. POWER SWITCH ELECTRICAL CHARACTERISTICS ......................................................................... 69
4.22. AVOIDING UNEXPECTED LEAKAGE PATHS ...................................................................................... 69
4.23. SYSTEM POWER ANALYSIS ................................................................................................................. 69
4.23.1. USING AN EXTERNAL RTC WITH POWER MANAGEMENT......................................................... 69
4.23.2. MANAGING MCU ACTIVE POWER ................................................................................................. 70
4.23.3. LOWER COST MCUs ....................................................................................................................... 70
4.23.4. HIGH PERFORMANCE PROCESSORS .......................................................................................... 70
4.24. TRICKLE CHARGER ............................................................................................................................... 70
5. DIGITAL ARCHITECTURE SUMMARY .......................................................................................................... 71
6. ELECTRICAL SPECIFICATIONS.................................................................................................................... 72
6.1. ABSOLUTE MAXIMUM RATINGS .......................................................................................................... 72
6.2. POWER SUPPLY PARAMETERS .......................................................................................................... 72
6.3. OPERATING PARAMETERS .................................................................................................................. 74
6.4. OSCILLATOR PARAMETERS ................................................................................................................ 74
6.5. XT FREQUENCY CHARACTERISTICS .................................................................................................. 76
6.5.1. XT FREQUENCY VS. TEMPERATURE CHARACTERISTICS ........................................................ 76
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6.6. VDD SUPPLY CURRENT .......................................................................................................................... 77
6.7. VBACKUP SUPPLY CURRENT ................................................................................................................... 81
6.8. BREF ELECTRICAL CHARACTERISTICS............................................................................................. 84
2
6.9. I C AC ELECTRICAL CHARACTERISTICS ........................................................................................... 85
6.10. POWER ON AC ELECTRICAL CHARACTERISTICS ............................................................................ 86
6.11. RST AC ELECTRICAL CHARACTERISTICS....................................................................................... 87
7. APPLICATION INFORMATION ....................................................................................................................... 88
7.1. OPERATING RV-1805-C3 ....................................................................................................................... 88
7.2. OPERATING RV-1805-C3 WITH BACKUP BATTERY/SUPERCAP ..................................................... 89
8. RECOMMENDED REFLOW TEMPERATURE (LEADFREE SOLDERING) .................................................. 90
9. PACKAGE ........................................................................................................................................................ 91
9.1. DIMENSIONS AND SOLDERPADS LAYOUT ........................................................................................ 91
9.2. MARKING AND PIN #1 INDEX ................................................................................................................ 91
10. PACKING INFORMATION ............................................................................................................................... 92
10.1. CARRIER TAPE ....................................................................................................................................... 92
10.2. PARTS PER REEL ................................................................................................................................... 92
10.3. REEL 7 INCH FOR 12 mm TAPE ............................................................................................................ 93
10.4. HANDLING PRECAUTIONS FOR CRYSTALS OR MODULES WITH EMBEDDED CRYSTALS ........ 94
11. DOCUMENT REVISION HISTORY.................................................................................................................. 95
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Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
RV-1805-C3
Extreme Low Power Real Time Clock / Calendar Module with I2C Interface
1. OVERVIEW
•
•
•
•
•
•
•
•
•
•
Ultra-low supply current (all at 3V):
- 17 nA with RC oscillator
- 22 nA with RC oscillator and Autocalibration (ACP = 512 sec.)
- 60 nA with crystal oscillator
Baseline timekeeping features:
- 32.768 kHz built-in “Tuning Fork” crystal oscillator with integrated load capacitor/resistor
- Counters for hundredths, seconds, minutes, hours, date, month, year, century, and weekday
- Alarm capability on all counters
- Programmable output clock generation (32.768 kHz to 1/year)
- Countdown timer with repeat function
- Automatic leap year calculation
Advanced timekeeping features:
- Integrated power optimized RC oscillator
- Advanced crystal calibration to ± 2 ppm
- Advanced RC calibration to ± 16 ppm
- Automatic calibration of RC oscillator to crystal oscillator
- Watchdog timer with hardware reset
- Up to 256 bytes of general purpose RAM
Power management features:
- Integrated ~1Ω power switch for off-chip components such as a host MCU
- System sleep manager for managing host processor wake/sleep states
- Reset output generator
- Supercapacitor trickle charger with programmable charging current
- Automatic switchover to VBACKUP
- External interrupt monitor
- Programmable low battery detection threshold
- Programmable analog voltage comparator
2
I C (up to 400 kHz) serial interface
Operating voltage 1.5-3.6 V
Clock and RAM retention voltage 1.5-3.6 V
Operating temperature –40 to +85 °C
All inputs include Schmitt Triggers
Available in small and compact package size, RoHS-compliant and 100% leadfree: C3: 3.7 x 2.5 x 0.9 mm
1.1. GENERAL DESCRIPTION
The RV-1805-C3 Real Time Clock with Power Management provides a groundbreaking combination of ultra-low
power coupled with a highly sophisticated feature set. The power requirement is significantly lower than any other
industry RTC (as low as 17 nA). The RV-1805-C3 includes an on-chip oscillator to provide a minimum power
consumption, full RTC functions including battery backup and programmable counters and alarms for timer and
2
watchdog functions, and either an I C serial interface for communication with a host controller. An integrated power
switch and a sophisticated system sleep manager with counter, timer, alarm, and interrupt capabilities allows the
RV-1805-C3 to be used as a supervisory component in a host microcontroller based system.
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Extrem Low Power Real Time Clock / Calendar Module
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1.2. APPLICATIONS
The RV-1805-C3 RTC module has been specially designed for ultimate low power consumption:
• 60 nA with crystal oscillator (at 3V)
• 17 nA with RC oscillator (at 3V)
• Permits to operate this RTC module several hours at Backup Supply Voltage using low-cost MLCC
These unique features make this product perfectly suitable for many applications:
• Communication: Wireless Sensors and tags, Handsets, Communications equipment
• Automotive:
Navigation & Tracking Systems / Dashboard / Tachometers / Car Audio & Entertainment
Systems
• Metering:
E-Meter / Heating Counter / Smart Meters / PV Converter
• Outdoor:
ATM & POS systems / Ticketing Systems
• Medical:
Glucose Meter / Health Monitoring Systems
• Safety:
Security & Camera Systems / Door Lock & Access Control
• Consumer:
Gambling Machines / TV & Set Top Boxes / White Goods
• Automation:
Data Logger / Home & Factory Automation / Industrial and Consumer Electronics
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Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
2. BLOCK DIAGRAM
Analog
Compare
VBACKUP
VDD
VSS
SCL
SDA
7
1
Power
Control
6
4
5
I2C-BUS
Interface
Calibration Engine
Cap_RC
2
Xtal Osc
Divider
RC Osc
Divider
3
CLK/INT
WDI
RST
PSW
9
10
INPUT
OUTPUT
CONTROL
8
Reset
System Control
logic
Hundredths
Seconds
Minutes
Hours
Date
Months
Years
Weekdays
Hundredths Alarm
Seconds Alarm
Minutes Alarm
Hours Alarm
Date Alarm
Months Alarm
Weekdays Alarm
Status
Control1
Control2
IntMask
SQW
Cal_XT
Sleep Control
Timer Control
Timer
Timer Initial
WDT
Osc. Control
Osc. Status
Trickle Charge
BREF Control
AF Control
Batmode I/O
Analog Status
Output Control
Ext. Ram Addr
User RAM
00
08
0F
10
14
17
1D
20
26
2F
3F
40
FF
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Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
2.1. PINOUT
C3 Package:
#1
VDD
#10
RST
#2
Cap_RC
#9
WDI
#3
CLK / INT
#8
PSW
#4
SCL
#7
VBACKUP
#5
SDA
#6
VSS
1805
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2.2. PIN DESCRIPTION
Symbol
Pin #
VDD
1
Cap_RC
2
Description
Primary power connection. If a single power supply is used, it must be connected to VDD.
Autocalibration filter connection. A 47pF ceramic capacitor should be placed between this pin and VSS for
improved Autocalibration mode timing accuracy.
Clock Output / Interrupt. Primary interrupt output connection. It is an open drain output. CLK / INT may be
configured to generate several signals as a function of the OUT1S field (see CONFIGURATION
REGISTERS, 11h - Control2). CLK / INT is also asserted low on a power up until the RV-1805-C3 has
exited the reset state and is accessible via the I/O interface.
CLK / INT
3
SCL
SDA
VSS
4
5
6
VBACKUP
7
PSW
8
WDI
9
RST
10
1.
CLK / INT can drive the value of the OUT bit.
2.
CLK / INT can drive the inverse of the combined interrupt signal IRQ (see INTERRUPTS).
3.
CLK / INT can drive the square wave output (see CONFIGURATION REGISTERS, 13h – SQW)
if enabled by SQWE.
4.
CLK / INT can drive the inverse of the alarm interrupt signal AIRQ (see INTERRUPTS).
I2C Serial Clock Input. Requires pull-up resistor.
I2C Serial Data. Requires pull-up resistor.
Ground connection
Backup Supply Voltage. If a backup voltage is not present, VBACKUP is normally left floating or grounded, but
it may also be used to provide the analog input to the internal comparator (see ANALOG COMPARATOR).
Requires series resistor. The optimal total series impedance = VBACKUP power source ESR (Equivalent
Series Resistance) + external resistor value = 1.5kΩ.
Power Switch Output. Secondary interrupt output connection. It is an open drain output. PSW may be
configured to generate several signals as a function of the OUT2S field (see CONFIGURATION
REGISTERS, 11h - Control2). This pin will be configured as an ~1 Ω switch if the PWR2 bit is set.
1. PSW can drive the value of the OUTB bit.
2. PSW can drive the square wave output (see CONFIGURATION REGISTERS, 13h - SQW) if
enabled by SQWE.
3. PSW can drive the inverse of the combined interrupt signal IRQ (see INTERRUPTS).
4. PSW can drive the inverse of the alarm interrupt signal AIRQ (see INTERRUPTS).
5. PSW can drive either sense of the timer interrupt signal TIRQ.
6. PSW can function as the power switch output for controlling the power of external devices (see
SLEEP CONTROL).
Watchdog Timer reset input connection. It may also be used to generate an External interrupt with polarity
selected by the EX2P bit if enabled by the EX2E bit. The value of the WDI pin may be read in the WDIN
register bit. This pin does not have an internal pull resistor. It must not be left floating or the RTC may
consume higher current.
Reset Output. It is an open drain output. The polarity is selected by the RSP bit, which will initialize to 0 on
power up to produce an active low output. See AUTOCALIBRATION FAIL INTERRUPT ACIRQ for details
of the generation of RST .
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Extrem Low Power Real Time Clock / Calendar Module
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2.3. FUNCTIONAL DESCRIPTION
The RV-1805-C3 is an extreme low power CMOS Real-Time Clock / Calendar module with built-in “Tuning-Fork”
crystal with the nominal frequency of 32.768 kHz and an on-chip auto-calibrated RC-oscillator; no external
components are required for the oscillator circuitry.
The oscillator frequency on all devices is tested not to exceed a time deviation of ± 100 ppm (parts per million) at
25°C, which equates to about ± 260 seconds per month.
This time accuracy can be further improved to ± 2 ppm (factory calibrated at 25°C) or better by individually
measuring the frequency-deviation in the application at a given temperature and programming a correction value
into the frequency compensation register.
Up to 256 bytes/registers of general purpose ultra-low leakage RAM enable the storage of key parameters when
operating on backup power.
The registers are accessed by selecting a register address and then performing read or write operations. Multiple
reads or writes may be executed in a single access, with the address automatically incrementing after each byte.
2.4. DEVICE PROTECTION DIAGRAM
The following Figure illustrates the internal ESD structure. The ESD Clamp devices are not simple diodes and are
more complex structured. The VDD, VBACKUP and Cap_RC pins have these ESD clamps as well as the internal VSYS
supply, which route a positive ESD discharge to VSS. Note that the VSYS internal supply is switched between the VDD
and VBACKUP supplies dependent upon the mode of operation. In VBACKUP mode (when VDD goes away with a VBACKUP
supply present), the internal VSYS supply is switched to VBACKUP by additional internal circuitry. In VDD mode (when
VDD is present and regardless if a supply is present on VBACKUP or not), the internal VSYS supply is switched to VDD
by additional internal circuitry. Note that VSYS does not directly touch a pin, but all of the positive charge injected
onto the other digital I/O pads ( CLK / INT , SCL, SDA, PSW, WDI and RST ) gets routed to this ESD clamp on
VSYS. In addition, there are simple diodes between VSYS and VSS as well as between the digital I/O pads and VSS as
shown in the diagram. These diodes take care of negative discharges to any of those pads.
Internal ESD structure:
Cap_RC
2
VDD
1
VBACKUP
VSYS (internal supply)
7
ESD
Clamp
ESD
Clamp
ESD
Clamp
ESD
Clamp
ESD
Clamp
All I/Os including:
3 CLK/INT
4 SCL
5 SDA
8 PSW
9 WDI
10 RST
6
VSS
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Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
3. REGISTER ORGANIZATION
Registers are accessed by selecting a register address and then performing read or write operations. Multiple
reads or writes may be executed in a single access, with the address automatically incrementing after each byte.
The following tables Register Definitions (00h to 0Fh) and Register Definitions (10h to FFh) summarize the function
of each register. In the table Register Definitions (00h to 0Fh), the GPx bits (where x is between 0 and 27) are 28
register bits which may be used as general purpose storage. These bits are not described in the sections below. All
of the GPx bits are cleared when the RV-1805-C3 powers up, and they can therefore be used to allow software to
determine if a true Power On Reset has occurred or hold other initialization data.
3.1. REGISTER OVERVIEW
Register Definitions (00h to 0Fh):
Address
00h
01h
02h
03h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Bh
0Ch
0Dh
0Eh
0Fh
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Hundredths
Seconds
Minutes
Hours (24 hour)
Hours (12 hour)
Date
Months
Years
Weekdays
Hundredths Alarm
Seconds Alarm
Minutes Alarm
Hours Alarm (24 hour)
Hours Alarm (12 hour)
Date Alarm
Months Alarm
Weekdays Alarm
Status
80
GP0
GP1
GP3
GP3
GP5
GP8
80
GP13
80
GP14
GP15
GP17
GP17
GP19
GP22
GP27
CB
40
40
40
GP2
GP2
GP4
GP7
40
GP12
40
40
40
GP16
GP16
GP18
GP21
GP26
BAT
20
20
20
20
AM/PM
20
GP6
20
GP11
20
20
20
20
AM/PM
20
GP20
GP25
WDT
10
10
10
10
10
10
10
10
GP10
10
10
10
10
10
10
10
GP24
BL
8
8
8
8
8
8
8
8
GP9
8
8
8
8
8
8
8
GP23
TIM
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
ALM
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
EX2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
EX1
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Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
Register Definitions (10h to FFh):
Address
Function
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
3Fh
40h–7Fh
80h–FFh
Control1
Control2
Interrupt Mask
SQW
Cal_XT
Cal_RC_Hi
Cal_RC_Low
Sleep_Control
Timer Control
Countdown Timer
Timer Initial Value
Watchdog Timer WDT
Osc. Control
Osc. Status
RESERVED
Configuration Key
Trickle
BREF Control
RESERVED
RESERVED
RESERVED
RESERVED
AFCTRL
BATMODE I/O
ID0 (Read only)
ID1 (Read only)
ID2 (Read only)
ID3 (Read only)
ID4 (Read only)
ID5 (Read only)
ID6 (Read only)
ASTAT
OCTRL
Extension Address
RAM
RAM
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
STOP
12/24
OUTB
RS1E
CEB
IM
SQWE
CMDX
CMDR
OUT
RSP
OUT2S
TIE
ARST
SLP
SLRES
EX2P
TE
TM
TRPT
128
64
32
128
64
32
WDS
16
8
OSEL
ACAL
XTCAL
LKO2
TCS
BREF
IOBM
Lot[9]
Lot[8]
BBOD
WDBM
O4BM
BLIE
Bit 1
Bit 0
PWR2
WRTC
OUT1S
EX2E
EX1E
AIE
SQFS
OFFSETX
OFFSETR[13:8]
OFFSETR[7:0]
EX1P
SLST
RPT
16
8
4
16
8
4
4
2
1
AOS
FOS
PWGT
OMODE
RESERVED
Configuration Key
DIODE
SLTO
TFS
2
2
1
1
WRB
OFIE
OF
ACIE
ACF
ROUT
-
RESERVED
RESERVED
RESERVED
RESERVED
AFCTRL
RESERVED
Part Number – MS Byte = 00011000 (18h)
Part Number – LS Byte = 00000101 (05h)
Revision – Major = 00010
Revision – Minor = 011
Lot[7:0]
Unique ID[14:8]
Unique ID[7:0]
Wafer
BMIN
VINIT
EXBM
WDDS
EXDS
RSEN
O4EN
O3EN
O1EN
BPOL
WDIN
EXIN
XADA
XADS
Normal RAM Data
Alternate RAM Data
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Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
3.2. TIME AND DATE REGISTERS
00h - Hundredths
This register holds the count of hundredths of seconds, in two binary coded decimal (BCD) digits. Values will be
from 00 to 99. Note that in order to divide from 32.768 kHz, the hundredths register will not be fully accurate at all
times but will be correct every 500 ms. Maximum jitter of this register will be less than 1 ms. The Hundredths
Counter is not valid if the RC Oscillator is selected.
Address
Function
00h
00h
Hundredths
Reset
Bit
Symbol
7:0
Hundredths
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80
1
40
0
20
0
10
1
8
1
4
0
2
0
1
1
Value
00 to 99
Description
Holds the count of hundredths of seconds, coded in BCD format.
01h - Seconds
This register holds the count of seconds, in two binary coded decimal (BCD) digits. Values will be from 00 to 59.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
01h
Seconds
Reset
GP0
0
40
0
20
0
10
0
8
0
4
0
2
0
1
0
Bit
Symbol
Value
7
6:0
GP0
Seconds
0 or 1
00 to 59
Description
Register bit for general purpose use.
Holds the count of seconds, coded in BCD format.
02h – Minutes
This register holds the count of minutes, in two binary coded decimal (BCD) digits. Values will be from 00 to 59.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
02h
02h
Minutes
Reset
GP1
0
40
0
20
0
10
0
8
0
4
0
2
0
1
0
Bit
Symbol
Value
7
6:0
GP1
Minutes
0 or 1
00 to 59
Description
Register bit for general purpose use.
Holds the count of minutes, coded in BCD format.
14/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
03h - Hours
This register holds the count of hours, in two binary coded decimal (BCD) digits. Values will be from 00 to 23 if the
12/24 bit (see CONFIGURATION REGISTERS, 10h - Control1) is clear. If the 12/24 bit is set, the AM/PM bit will be
0 for AM hours and 1 for PM hours, and hour values will range from 1 to 12.
Hours Register (24 Hour Mode)
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
03h
03h
Hours
Reset
GP3
0
GP2
0
20
0
10
0
8
0
4
0
2
0
1
0
Bit
Symbol
Value
7
6
5:0
GP3
GP2
Hours
0 or 1
0 or 1
00 to 23
Description
Register bit for general purpose use.
Register bit for general purpose use.
Holds the count of hours, coded in BCD format.
Hours Register (12 Hour Mode)
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Hours
Reset
GP3
0
GP2
0
AM/PM
0
10
0
8
0
4
0
2
0
1
0
Bit
Symbol
Value
7
6
5
4:0
GP3
GP2
AM/PM
Hours
0 or 1
0 or 1
0 or 1
1 to 12
03h
03h
Description
Register bit for general purpose use.
Register bit for general purpose use.
0 = AM hours. 1 = PM hours.
Holds the count of hours, coded in BCD format.
04h – Date
This register holds the current day of the month, in two binary coded decimal (BCD) digits. Values will range from
01 to 31. Leap years are correctly handled from 1900 to 2199.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
04h
04h
Date
Reset
GP5
0
GP4
0
20
0
10
0
8
0
4
0
2
0
1
1
Bit
Symbol
Value
7
6
5:0
GP5
GP4
Date
0 or 1
0 or 1
01 to 31
Description
Register bit for general purpose use.
Register bit for general purpose use.
Holds the current day of the month, coded in BCD format.
15/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
05h - Months
This register holds the current month, in two binary coded decimal (BCD) digits. Values will range from 01 to 12.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h
05h
Months
Reset
GP8
0
GP7
0
GP6
0
10
0
8
0
4
0
2
0
1
1
Bit
Symbol
Value
7
6
5
4:0
GP8
GP7
GP6
Months
0 or 1
0 or 1
0 or 1
01 to 12
Description
Register bit for general purpose use.
Register bit for general purpose use.
Register bit for general purpose use.
Holds the current month, coded in BCD format.
06h - Years
This register holds the current year, in two binary coded decimal (BCD) digits. Values will range from 00 to 99.
Address
Function
06h
06h
Years
Reset
Bit
Symbol
7:0
Years
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80
0
40
0
20
0
10
0
8
0
4
0
2
0
1
0
Value
00 to 99
Description
Holds the current year, coded in BCD format.
07h - Weekdays
This register holds the current day of the week. Values will range from 0 to 6.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
07h
07h
Weekdays
Reset
GP13
0
GP12
0
GP11
0
GP10
0
GP09
0
4
0
2
0
1
0
Bit
Symbol
Value
GP13
GP12
GP11
GP10
GP09
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 to 6
7
6
5
4
3
2:0
Weekdays
Description
Register bit for general purpose use.
Register bit for general purpose use.
Register bit for general purpose use.
Register bit for general purpose use.
Register bit for general purpose use.
Holds the weekday counter value.
16/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
3.3. ALARM REGISTERS
08h - Hundredths Alarm
This register holds the alarm value for hundredths of seconds, in two binary coded decimal (BCD) digits. Values will
range from 00 to 99.
Address
Function
08h
08h
Hundredths Alarm
Reset
Bit
Symbol
7:0
Hundredths Alarm
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80
0
40
0
20
0
10
0
8
0
4
0
2
0
1
0
Value
00 to 99
Description
Holds the alarm value for hundredths of seconds, coded in BCD format.
09h - Seconds Alarm
This register holds the alarm value for seconds, in two binary coded decimal (BCD) digits. Values will range from
00 to 59.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
09h
09h
Seconds Alarm
Reset
GP14
0
40
0
20
0
10
0
8
0
4
0
2
0
1
0
Bit
Symbol
Value
7
6:0
GP14
Seconds Alarm
0 or 1
00 to 59
Description
Register bit for general purpose use.
Holds the alarm value for seconds, coded in BCD format.
0Ah - Minutes Alarm
This register holds the alarm value for minutes, in two binary coded decimal (BCD) digits. Values will range from
00 to 59.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ah
0Ah
Minutes Alarm
Reset
GP15
0
40
0
20
0
10
0
8
0
4
0
2
0
1
0
Bit
Symbol
Value
7
6:0
GP15
Minutes Alarm - Tens
0 or 1
00 to 59
Description
Register bit for general purpose use.
Holds the alarm value for minutes, coded in BCD format.
17/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
0Bh - Hours Alarm
This register holds the alarm value for hours, in two binary coded decimal (BCD) digits. Values will range from 00
to 23 if the 12/24 bit (see CONFIGURATION REGISTERS,10h - Control1) is clear. If the 12/24 bit is set, the
AM/PM bit will be 0 for AM hours and 1 for PM hours, and hour values will be from 1 to 12.
Hours Alarm Register (24 Hour Mode)
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh
0Bh
Hours Alarm
Reset
GP17
0
GP16
0
20
0
10
0
8
0
4
0
2
0
1
0
Bit
Symbol
Value
7
6
5:0
GP17
GP16
Hours Alarm
0 or 1
0 or 1
00 to 23
Description
Register bit for general purpose use.
Register bit for general purpose use.
Holds the alarm value for hours, coded in BCD format.
Hours Alarm Register (12 Hour Mode)
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Hours Alarm
Reset
GP17
0
GP16
0
AM/PM
0
10
0
8
0
4
0
2
0
1
0
Bit
Symbol
Value
7
6
5
4:0
GP17
GP16
AM/PM
Hours Alarm
0 or 1
0 or 1
0 or 1
1 to 12
0Bh
0Bh
Description
Register bit for general purpose use.
Register bit for general purpose use.
0 = AM hours. 1 = PM hours.
Holds the alarm value for hours, coded in BCD format.
0Ch - Date Alarm
This register holds the alarm value for the date, in two binary coded decimal (BCD) digits. Values will range from
01 to 31. Leap years are correctly handled from 1900 to 2199.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ch
0Ch
Date Alarm
Reset
GP19
0
GP18
0
20
0
10
0
8
0
4
0
2
0
1
0
Bit
Symbol
Value
7
6
5:0
GP19
GP18
Date Alarm
0 or 1
0 or 1
01 to 31
Description
Register bit for general purpose use.
Register bit for general purpose use.
Holds the alarm value for the date, coded in BCD format.
18/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
0Dh - Months Alarm
This register holds the alarm value for months, in two binary coded decimal (BCD) digits. Values will range from 01
to 12.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Months Alarm
Reset
GP22
0
GP21
0
GP20
0
10
0
8
0
4
0
2
0
1
0
Bit
Symbol
Value
7
6
5
4:0
GP22
GP21
GP20
Months Alarm
0Dh
0Dh
0 or 1
0 or 1
0 or 1
01 to 12
Description
Register bit for general purpose use.
Register bit for general purpose use.
Register bit for general purpose use.
Holds the alarm value for months, coded in BCD format.
0Eh - Weekdays Alarm
This register holds the alarm value for the day of the week. Values will range from 0 to 6.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Eh
0Eh
Weekdays Alarm
Reset
GP27
0
GP26
0
GP25
0
GP24
0
GP23
0
4
0
2
0
1
0
Bit
Symbol
Value
GP27
GP26
GP25
GP24
GP23
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 to 6
7
6
5
4
3
2:0
Weekdays Alarm
Description
Register bit for general purpose use.
Register bit for general purpose use.
Register bit for general purpose use.
Register bit for general purpose use.
Register bit for general purpose use.
Holds the weekdays alarm value.
19/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
3.4. CONFIGURATION REGISTERS
0Fh – Status (Read Only)
This register holds a variety of status bits. The register may be written at any time to clear or set any status flag. If
the ARST bit (see CONFIGURATION REGISTERS,10h - Control1) is set, any read of the Status Register will clear
all of the bits except the CB bit.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CB
0
BAT
0
WDT
0
BL
0
TIM
0
ALM
0
EX2
0
EX1
0
0Fh
0Fh
Status (Read Only)
Reset
Bit
Symbol
Value
7
CB
0 or 1
6
BAT
0 or 1
5
WDT
0 or 1
4
BL
0 or 1
3
TIM
0 or 1
2
ALM
0 or 1
1
EX2
0 or 1
0
EX1
0
Description
Century. This bit will be toggled when the Years register rolls over from 99
to 00 if the CEB bit (see 12h - Interrupt Mask register) is a 1. A 0 assumes
the century is 19xx or 21xx, and a 1 assumes it is 20xx for leap year
calculations.
Set when the system switches to the VBACKUP Power state.
Set when the Watchdog Timer is enabled and is triggered, and the WDS
bit is 0 (see TIMER REGISTERS, 1Bh Watchdog Timer).
Set if the battery voltage VBACKUP crosses the reference voltage selected by
BREF (see ANALOG CONTROL REGISTERS, 21h - BREF Control) in the
direction selected by BPOL (see RAM REGISTERS, 3Fh - Extension RAM
Address).
Set when the Countdown Timer is enabled and reaches zero.
Set when the Alarm function is enabled and all selected Alarm registers
match their respective counters.
Set when an external trigger is detected on the WDI pin. The EX2E bit (see
CONFIGURATION REGISTERS , 12h - Interrupt Mask) must be set in
order for this interrupt to occur, but subsequently clearing EX2E will not
automatically clear this flag.
Unused flag. Always 0.
10h - Control1
This register holds some major control signals.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10h
10h
Control1
Reset
STOP
0
12/24
0
OUTB
0
OUT
1
RSP
0
ARST
0
PWR2
1
WRTC
1
Bit
Symbol
Value
7
STOP
0 or 1
6
12/24
0 or 1
5
OUTB
0 or 1
4
OUT
0 or 1
3
RSP
0 or 1
2
ARST
0 or 1
1
PWR2
0 or 1
0
WRTC
0 or 1
Description
When 1, stops the clocking system. The XT and RC Oscillators are not
stopped. In XT Mode the 32.768 kHz clock output will continue to run. In
RC Mode, the RC clock output will continue to run. Other clock output
selections will produce static outputs. This bit allows the clock system to be
precisely started, by setting it to 1 and back to 0.
When 0, the Hours register operates in 24 hour mode. When 1, the Hours
register operates in 12 hour mode.
A static value which may be driven on the PSW pin. The OUTB bit cannot
be set to 1 if the LKO2 bit is 1 (see OSCILLATOR REGISTERS, 1Dh –
Oscillator Status).
A static value which may be driven on the CLK / INT pin. This bit also
defines the default value for the Square Wave output when SQWE is not
asserted.
Reset Polarity. When 1, the RST pin is asserted high. When 0, the RST
pin is asserted low.
Auto reset enable. When 1, a read of the Status register will cause any
interrupt bits (TIM, BL, ALM, WDT, EX2) to be cleared. When 0, the bits
must be explicitly cleared by writing the Status register.
When 1, the PSW pin is driven by an approximately 1Ω pull-down which
allows the RV-1805-C3 to switch power to other system devices through
this pin. When 0, the PSW pin is a normal open drain output.
Write RTC. This bit must be set in order to write any of the Counter
registers (Hundredths, Seconds, Minutes, Hours, Date, Months, Years or
Weekdays).
20/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
11h - Control2
This register holds additional control and configuration signals for the flexible output pins CLK / INT and PSW.
Note that PSW and CLK / INT are open drain outputs.
Address
Function
11h
11h
11h
Control2
Reset
Set RS1E to 0
Bit
Symbol
7:6
5
RESERVED
RS1E
4:2
OUT2S
1:0
OUT1S
OUT2S Value
000
001
010
011
100
101
110
111
OUT1S Value
00
01
10
11
Bit 7
Bit 6
Bit 5
RESERVED
0
0
Bit 4
Bit 3
1
OUT2S
1
RS1E
1
0
Value
00 to 11
0 or 1
000 to
111
00 to 11
Bit 2
Bit 1
Bit 0
OUT1S
1
0
0
Description
RESERVED
Unused, but has to be 0 to avoid extraneous leakage.
Controls the function of the PSW pin. See OUT2S values below.
Controls the function of the CLK / INT pin. See OUT1S values below.
PSW Pin Control
nIRQ if at least one interrupt is enabled, else OUTB
SQW if SQWE = 1, else OUTB
RESERVED
nAIRQ if AIE is set, else OUTB
TIRQ if TIE is set, else OUTB
nTIRQ if TIE is set, else OUTB
SLEEP
OUTB
CLK/INT Pin Control
nIRQ if at least one interrupt is enabled, else OUT
SQW if SQWE = 1, else OUT
SQW if SQWE = 1, else nIRQ if at least one interrupt is enabled, else OUT
nAIRQ if AIE is set, else OUT
21/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
12h - Interrupt Mask
This register holds the interrupt enable bits and other configuration information.
Address
Function
Bit 7
12h
12h
Interrupt Mask
Reset
CEB
1
Bit
Symbol
Value
CEB
0 or 1
7
6:5
IM
00 to 11
4
BLIE
0 or 1
3
TIE
0 or 1
2
AIE
0 or 1
1
EX2E
0 or 1
0
EX1E
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
BLIE
0
TIE
0
AIE
0
EX2E
0
EX1E
0
IM
1
Description
Century Enable.
0: The CB bit will never be automatically updated.
1: The CB bit will toggle when the Years register rolls over from 99 to 00.
Interrupt Mode.
This controls the duration of the nAIRQ interrupt as shown below. The
interrupt output always goes high when the corresponding flag in the
Status Register is cleared. In order to minimize current drawn by the RV1805-C3 this field should be kept at 3h.
00: Level (static) for both XT mode and RC mode.
01: 1/8192 seconds for XT mode. 1/64 seconds for RC mode.
10: 1/64 seconds for both XT mode and RC mode.
11: 1/4 seconds for both XT mode and RC mode.
Battery Low Interrupt Enable.
0: Disable the battery low interrupt.
1: The battery low detection will generate an interrupt.
Timer Interrupt Enable.
0: Disable the timer interrupt.
1: The Countdown Timer will generate an IRQ interrupt signal and set the
TIM flag when the timer reaches 0.
Alarm Interrupt Enable.
0: Disable the alarm interrupt.
1: A match of all the enabled alarm registers will generate an IRQ interrupt
signal.
External interrupt Enable.
0: Disable the external interrupt.
1: The WDI input pin will generate an external interrupt when the edge
specified by EX2P occurs (see CONFIGURATION REGISTERS, 12h Interrupt Mask).
Unused, but has to be 0 to avoid extraneous leakage.
22/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
13h – SQW
This register holds the control signals for the square wave output. Note that some frequency selections are not
valid if the RC Oscillator is selected.
Address
Function
Bit 7
13h
13h
SQW
Reset
SQWE
0
Bit
Symbol
Value
7
SQWE
0 or 1
6:5
RESERVED
4:0
SQFS
00 to 11
00000
to
11111
Bit 6
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
0
SQFS
1
1
0
Description
When 1, the square wave output is enabled. When 0, the square wave
output is held at the value of OUT.
RESERVED
Selects the frequency of the square wave output, as shown in the following
table. Note that some selections are not valid if the RC oscillator is
selected. Some selections also produce short pulses rather than square
waves, and are intended primarily for test usage.
SQFS Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Bit 5
RESERVED
0
1
Square Wave Output Select
century(2)
1
32.768 kHz(1)
8.192 kHz(1)
4.096 kHz(1)
2.048 kHz(1)
1.024 kHz(1)
512 Hz(1) – Default value
256 Hz(1)
128 Hz(3)
64 Hz – highest calibrated frequency in RC mode
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
½ Hz
¼ Hz
1/8 Hz
1/16 Hz
1/32 Hz
1/60 Hz (1 minute)
16.384 kHz(1) – highest calibrated frequency in XT mode
100 Hz(1)(2)
1 hour(2)
1 day(2)
TIRQ
NOT TIRQ
1 year(2)
1 Hz to Counters(2)
1/32 Hz from Acal(2)
1/8 Hz from Acal(2)
(1) Not
applicable if the RC Oscillator is selected.
for Test Usage.
(3) If the RC Oscillator is selected the frequency is typically 122 Hz.
(2) Pulses
23/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
3.5. CALIBRATION REGISTERS
14h - Calibration XT
This register holds the control signals for the digital calibration function of the XT Oscillator. This register is
initialized with a factory value which calibrates the XT Oscillator. The highest modified frequency is 16.384 kHz.
Address
Function
Bit 7
14h
14h
Calibration XT
Reset
CMDX
0
Bit
Symbol
Value
CMDX
0 or 1
OFFSETX
-64 to
+63
7
6:0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OFFSETX
Preconfigured (Factory Calibrated)
Description
The calibration adjust mode. When 0 (Normal Mode), each adjustment
step is +/- 2 ppm. When 1 (Coarse Mode), each adjustment step is +/- 4
ppm.
The amount to adjust the effective time. This is a two's complement
number with a range of -64 to +63 adjustment steps (Factory Calibrated).
15h - Calibration RC Upper
This register holds the control signals for the fine digital calibration function of the low power RC Oscillator. This
register is initialized with a factory value which calibrates the RC Oscillator. The highest modified frequency is 64
Hz.
Address
Function
Bit 7
15h
15h
Calibration RC Upper
Reset
Bit
Symbol
7:6
CMDR
00 to 11
5:0
OFFSETRU
000000
to
111111
Bit 6
Bit 5
CMDR
Preconfigured
Value
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OFFSETRU
Preconfigured (Factory Calibrated)
Description
The calibration adjust mode for the RC calibration adjustment. CMDR
selects the highest frequency used in the RC Calibration process as shown
in the following table.
The upper 6 bits of the OFFSETR field, which is used to set the amount to
adjust the effective time. OFFSETR is a two's complement number with a
range of -2^13 to +2^13-1 adjustment steps (Factory Calibrated).
CMDR
Calibration Period
Minimal Adjustment Step
Maximum Adjustment
00
01
10
11
8’192 seconds
4’096 seconds
2’048 seconds
1’024 seconds
+/-1.91 ppm
+/-3.82 ppm
+/-7.64 ppm
+/-15.28 ppm
+/-1.56%
+/-3.13%
+/-6.25%
+/-12.5%
16h - Calibration RC Lower
This register holds the lower 8 bits of the OFFSETR field for the digital calibration function of the low power RC
Oscillator. This register is initialized with a factory value which calibrates the RC Oscillator. The highest modified
frequency is 64 Hz.
Address
Function
Bit 7
16h
16h
Calibration RC Lower
Reset
Bit
Symbol
Value
7:0
OFFSETRL
00h to
FFh
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OFFSETRL
Preconfigured (Factory Calibrated)
Description
The lower 8 bits of the OFFSETR field, which is used to set the amount to
adjust the effective time. OFFSETR is a two's complement number with a
range of -2^13 to +2^13-1 adjustment steps (Factory Calibrated).
24/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
3.6. SLEEP CONTROL REGISTER
17h - Sleep Control
This register controls the Sleep function of the Power Control system.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
17h
17h
Sleep Control
Reset
SLP
0
SLRES
0
EX2P
0
EX1P
0
SLST
0
Bit
Symbol
Value
7
SLP
0 or 1
6
SLRES
0 or 1
5
EX2P
0 or 1
4
EX1P
0
3
SLST
0 or 1
2:0
SLTO
0 to 7
Bit 2
Bit 1
Bit 0
0
SLTO
0
0
Description
When 1, the Power Control State Machine (SM) will transition to the
SWAIT state. This bit will be cleared when the SM returns to the RUN
state. If either STOP is 1 or no interrupt is enabled, SLP will remain at 0
even after an attempt to set it to 1.
When 1, assert RST low when the Power Control SM is in the SLEEP
state.
When 1, the external interrupt will trigger on a rising edge of the WDI pin.
When 0, the external interrupt will trigger on a falling edge of the WDI pin.
Unused, but has to be 0 to avoid extraneous leakage.
Set when the RV-1805-C3 enters Sleep Mode. This allows software to
determine if a SLEEP has occurred since the last time this bit was read.
The number of 7.8 ms periods after SLP is set until the Power Control SM
goes into the SLEEP state. If SLTO is not 0, the actual delay is guaranteed
to be between SLTO and (SLTO + 1) periods. If SLTO is 0, the transition
will occur with no delay.
25/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
3.7. TIMER REGISTERS
18h - Countdown Timer Control
This register controls the Countdown Timer function. Note that the TFS = 00 frequency selection is slightly different
depending on whether the 32.768 kHz XT Oscillator or the RC Oscillator is selected. In some RC Oscillator modes,
the interrupt pulse output is specified as RCPLS. In these cases the interrupt output will be a short negative going
pulse which is typically between 100 and 400 µs. This allows control of external devices which require pulses
shorter than the minimum 7.8 ms pulse created directly by the RC Oscillator.
Address
Function
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TE
0
TM
0
TRPT
1
0
RPT
0
0
1
18h
18h
Countdown Timer Control
Reset
Bit
Symbol
Value
7
TE
0 or 1
6
TM
0 or 1
5
TRPT
0 or 1
4:2
RPT
0 to 7
1:0
TFS
00 to
11
RPT
HA
7
7
7
6
5
4
3
2
1
0
FF
F[9-0]
[9-0][9-0]
(*) Once
Bit 7
Bit 0
TFS
1
Description
Timer Enable. When 1, the Countdown Timer will count down. When 0, the
Countdown Timer retains the current value. If TE is 0, the clock to the
Timer is disabled for power minimization.
Timer Interrupt Mode. Along with TRPT, this controls the Timer Interrupt
function as shown in Table 1. A Level Interrupt will cause the nIRQ signal to
be driven low by a Countdown Timer interrupt until the associated flag is
cleared. A Pulse interrupt will cause the nIRQ signal to be driven low for the
time shown in Table 1 or until the flag is cleared.
Along with TM, this controls the repeat function of the Countdown Timer. If
Repeat is selected, the Countdown Timer reloads the value from the Timer
Initial register upon reaching 0, and continues counting. If Single is
selected, the Countdown Timer will halt when it reaches zero. This allows
the generation of periodic interrupts of virtually any frequency.
These bits enable the Alarm Interrupt repeat function, as shown in the
following table. HA is the Hundredths_Alarm register value.
Select the clock frequency and interrupt pulse width of the Countdown
Timer, as defined in Table 1. RCPLS is a 100-400 µs pulse.
Repeat When
(*)
Once per hundredth
Once per tenth (*)
Hundredths match (once per second)
Hundredths and seconds match (once per minute)
Hundredths, seconds and minutes match (once per hour)
Hundredths, seconds, minutes and hours match (once per day)
Hundredths, seconds, minutes, hours and weekday match (once per week)
Hundredths, seconds, minutes, hours and date match (once per month)
Hundredths, seconds, minutes, hours, date and month match (once per year)
Alarm Disabled
per second if RC Oscillator selected
26/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
Table 1: Countdown Timer Function Select
TM
TRPT
TFS
Int
Repeat
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Level
Level
Level
Level
Pulse
Pulse
Pulse
Pulse
Single
Single
Single
Single
Repeat
Repeat
Repeat
Repeat
Single
Single
Single
Single
Repeat
Repeat
Repeat
Repeat
Countdown Timer Frequency
32.768 kHz
RC Oscillator
Oscillator
4.096 kHz
Typ. 122 Hz
64 Hz
64 Hz
1 Hz
1 Hz
1/60 Hz
1/60 Hz
4.096 kHz
Typ. 122 Hz
64 Hz
64 Hz
1 Hz
1 Hz
1/60 Hz
1/60 Hz
4.096 kHz
Typ. 122 Hz
64 Hz
64 Hz
1 Hz
1 Hz
1/60 Hz
1/60 Hz
4.096 kHz
Typ. 122 Hz
64 Hz
64 Hz
1 Hz
1 Hz
1/60 Hz
1/60 Hz
Interrupt Pulse Width
32.768 kHz
RC Oscillator
Oscillator
1/4096 s
Typ. 1/122 s
1/128 s
Typ. 1/122 s
1/64 s
1/64 s
1/64 s
1/64 s
1/4096 s
Typ. 1/122 s
1/128 s
Typ. 1/122 s
1/64 s
1/64 s
1/64 s
1/64 s
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1/4096 s
RCPLS
1/4096 s
RCPLS
1/4096 s
RCPLS
1/4096 s
RCPLS
19h - Countdown Timer
This register holds the current value of the Countdown Timer. It may be loaded with the desired starting value when
the Countdown Timer is stopped.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
19h
19h
Countdown Timer
Reset
128
0
64
0
32
0
16
0
8
0
4
0
2
0
1
0
Bit
Symbol
7:0
Countdown Timer
Value
00h to
FFh
Description
The current value of the Countdown Timer.
1Ah - Timer Initial Value
This register holds the value which will be reloaded into the Countdown Timer when it reaches zero if the TRPT bit
is a 1. This allows for periodic timer interrupts, and a period of (Timer_initial + 1) * (1/ Countdown_frequency).
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1Ah
1Ah
Timer Initial Value
Reset
128
0
64
0
32
0
16
0
8
0
4
0
2
0
1
0
Bit
Symbol
7:0
Timer Initial Value
Value
00h to
FFh
Description
The value reloaded into the Countdown Timer when it reaches zero if the
TRPT bit is a 1.
27/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
1Bh - Watchdog Timer
This register controls the Watchdog Timer function.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
1Bh
1Bh
Watchdog Timer
Reset
WDS
0
16
0
8
0
4
0
2
0
1
0
Bit
Symbol
Value
7
WDS
0 or 1
6:2
BMB
00000
to
11111
1:0
WRB
00 to 11
WRB Value
00
01
10
11
Bit 1
Bit 0
WRB
0
0
Description
Watchdog Steering. When 0, the Watchdog Timer will generate WIRQ
when it times out. When 1, the Watchdog Timer will generate a reset when
it times out.
The number of clock cycles which must occur before the Watchdog Timer
times out. A value of 00000 disables the Watchdog Timer function.
The clock frequency of the Watchdog Timer, as shown in the following
table.
Watchdog Timer Frequency
16 Hz
4 Hz
1 Hz
1/4 Hz
3.8. OSCILLATOR REGISTERS
1Ch - Oscillator Control
This register controls the overall Oscillator function. It may only be written if the Configuration Key register contains
the value A1h. An Autocalibration cycle is initiated immediately whenever this register is written with a value in the
ACAL field which is not zero.
Address
Function
Bit 7
1Ch
1Ch
Oscillator Control
Reset
OSEL
0
Bit
Symbol
Value
7
OSEL
0 or 1
6:5
ACAL
00 to 11
4
AOS
0 or 1
3
FOS
0 or 1
2
PWGT
0 or 1
1
OFIE
0 or 1
0
ACIE
0 or 1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
AOS
0
FOS
0
PWGT
0
OFIE
0
ACIE
0
ACAL
0
Description
When 1, request the RC Oscillator to generate the clock for the timer
circuits (nominal 128 Hz). When 0, request the XT Oscillator to generate a
32.768 kHz clock to the timer circuit. Note that if the XT Oscillator is not
operating, the oscillator switch will not occur. The OMODE field (see
OSCILLATOR REGISTERS,1Dh – Oscillator Status) indicates the actual
oscillator which is selected.
Controls the automatic calibration function (see AUTOCALIBRATION
FREQUENCY AND CONTROL).
When 1, the oscillator will automatically switch to the RC oscillator (RC
Mode according to the ACAL field) when the system is powered from the
battery. When 0, no automatic switching occurs.
When 1, the oscillator will automatically switch to RC oscillator (RC Mode
according to the ACAL field) when an oscillator failure is detected. When 0,
no automatic switching occurs.
When 1, the I/O interface will be disabled when the power switch is active
and disabled (PWR2 is a 1 and the OUT2 output is a 1).
Oscillator Fail interrupt enable. When 1, an Oscillator Failure will generate
an IRQ signal.
When 1, an Autocalibration Failure will generate an interrupt.
28/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
1Dh – Oscillator Status Register
This register holds several miscellaneous bits used to control and observe the oscillators.
Address
Function
Bit 7
1Dh
1Dh
Oscillator Status Register
Reset
Bit
Symbol
Value
7:6
XTCAL
00 to 11
0
5
LKO2
0 or 1
4
OMODE
0 or 1
3:2
RESERVED
Bit 6
XTCAL
00 to 11
1
OF
0 or 1
0
ACF
0 or 1
0
Bit 5
Bit 4
LKO2
1
OMODE
0
Bit 3
Bit 2
RESERVED
0
0
Bit 1
Bit 0
OF
1
ACF
0
Description
Extended Crystal Calibration. This field defines the compensation of a
higher XT oscillator frequency, independent of the normal Crystal
Calibration function controlled by the Calibration XT Register. The
frequency generated by the Crystal Oscillator is slowed by 122 ppm times
the value in the XTCAL field (0, -122, -244 or -366 ppm).
Normally, this field is not used.
Lock OUT2. If this bit is a 1, the OUTB register bit (see CONFIGURATION
REGISTERS, 10h – Control1) cannot be set to 1. This is typically used
when OUT2 is configured as a power switch, and setting OUTB to a 1
would turn off the switch.
(read only) – Oscillator Mode. This bit is a 1 if the RC Oscillator is selected
to drive the internal clocks, and a 0 if the Crystal Oscillator is selected. If
the STOP bit is set, the OMODE bit is invalid.
RESERVED
Oscillator Failure. This bit is set on a power on reset, when both the
system and battery voltages have dropped below acceptable levels. It is
also set if an Oscillator Failure occurs, indicating that the crystal oscillator
is running at less than 8 kHz. It can be cleared by writing a 0 to the bit.
Set when an Autocalibration Failure occurs, indicating that either the RC
Oscillator frequency is too different from 128 Hz to be correctly calibrated
or the XT Oscillator did not start.
3.9. MISCELLANEOUS REGISTERS
1Fh - Configuration Key
This register contains the Configuration Key, which must be written with specific values in order to access some
registers and functions. The Configuration Key is reset to 00h on any register write.
Address
Function
1Fh
1Fh
Configuration Key
Reset
Bit
Symbol
7:0
Configuration Key
Bit 7
Bit 6
Bit 5
0
0
0
Value
00h to
FFh
Bit 4
Bit 3
Configuration Key
0
0
Bit 2
Bit 1
Bit 0
0
0
0
Description
Written with specific values in order to access some registers and
functions.
1. Writing a value of A1h enables write access to the Oscillator Control register
2. Writing a value of 3Ch does not update the Configuration Key register, but generates a Software Reset
(see SOFTWARE RESET).
3. Writing a value of 9Dh enables write access to the Trickle Register (20h), the BREF Register (21h), the
AFCTRL Register (26h), the Batmode I/O Register (27h) and the Output Control Register (30h).
29/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
3.10. ANALOG CONTROL REGISTERS
20h - Trickle
This register controls the Trickle Charger. The Key Register must be written with the value 9Dh in order to enable
access to this register.
Address
Function
Bit 7
20h
20h
Trickle
Reset
Bit
Symbol
7:4
TCS
3:2
DIODE
00 to 11
1:0
ROUT
00 to 11
Bit 6
0
Value
0000 to
1111
0
Bit 4
Bit 3
Bit 2
Bit 1
DIODE
0
0
0
Bit 0
ROUT
0
0
0
Description
A value of 1010 enables the trickle charge function. All other values disable
the Trickle Charger.
Diode Select. A value of 10 inserts a standard diode into the trickle charge
circuit, with a voltage drop of 0.6V. A value of 01 inserts a schottky diode
into the trickle charge circuit, with a voltage drop of 0.3V. Other values
disable the Trickle Charger.
Output Resistor. This selects the output resistor of the trickle charge circuit,
as shown in the following table.
ROUT Value
00
01
10
11
Bit 5
TCS
Series Resistor
Disable
3 kΩ
6 kΩ
11 kΩ
21h - BREF Control
This register controls the reference voltages used in the Wakeup Control system. The Key Register must be written
with the value 9Dh in order to enable access to this register.
Address
Function
Bit 7
21h
21h
BREF Control
Reset
Bit
Symbol
7:4
BREF
0000 to
1111
3:0
RESERVED
0000 to
1111
BREF Value
0111
1011
1101
1111
Bit 6
Bit 5
Bit 4
1
Value
1
1
1
0
Bit 2
Bit 1
RESERVED
0
0
Bit 0
0
Description
This selects the voltage reference which is compared to the battery voltage
VBACKUP to produce the BBOD signal (see ANALOG CONTROL
REGISTERS, 2Fh – Analog Status). Typical values are shown in in the
following table. The valid BREF values are 7h, Bh, Dh, and Fh. The reset
value is Fh. All other values are RESERVED.
RESERVED
VBACKUP Falling Voltage (TYP)
2.5V
2.1V
1.8V
1.4V
Bit 3
BREF
VBACKUP Rising Voltage (TYP)
3.0V
2.5V
2.2V
1.6V
30/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
26h – AFCTRL
This register holds the enable code for the Autocalibration Filter (Cap_RC) filter capacitor connected to the
Cap_RC pin. Writing the value A0h to this register enables the Cap_RC pin. Writing the value 00h to this register
disables the Cap_RC pin. No other value may be written to this register. The Configuration Key Register must be
written with the value 9Dh prior to writing the AFCTRL Register.
Address
Function
26h
26h
AFCTRL
Reset
Bit
Symbol
7:0
AFCTRL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
AFCTRL
0
Value
A0h or
00h
0
0
0
0
Description
If A0h, enable the Cap_RC pin. If 00h, disable the Cap_RC pin.
27h – Batmode IO Register
This register holds the IOBM bit which controls the enabling and disabling of the I/O interface when a Brownout
Detection occurs. It may only be written if the Configuration Key register contains the value 9Dh. All undefined bits
must be written with 0.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
27h
27h
Batmode IO Register
Reset
IOBM
1
0
0
0
RESERVED
0
0
0
0
Bit
Symbol
Value
IOBM
0 or 1
7
6:0
RESERVED
000000
0
Description
If 1, the RV-1805-C3 will not disable the I/O interface even if VDD goes
away and VBACKUP is still present. This allows external access while the RV1805-C3 is powered by VBACKUP.
RESERVED - must write only 0000000.
2Fh – Analog Status Register (Read Only)
This register holds eight status bits which indicate the voltage levels of the VDD and VBACKUP power inputs.
Address
Function
2Fh
Analog Status Register
(Read Only)
Reset
Bit
2Fh
Bit 7
BBOD
Bit 6
BMIN
Bit 5
Bit 4
Bit 3
RESERVED
Bit 2
Bit 1
Bit 0
VINIT
RESER
VED
Symbol
Value
Description
7
BBOD
0 or 1
6
BMIN
If 1, the VBACKUP input voltage is above the BREF threshold.
If 1, the VBACKUP input voltage is above the minimum operating voltage (1.2
V).
5:2
RESERVED
1
0
VINIT
RESERVED
0 or 1
0000 to
1111
0 or 1
0 or 1
RESERVED
If 1, the VDD input voltage is above the minimum power up voltage (1.6 V).
RESERVED
31/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
30h – Output Control Register
This register holds bits which control the behavior of the I/O pins under various power down conditions. The Key
Register must be written with the value 9Dh in order to enable access to this register.
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
30h
30h
30h
Function
Output Control Register
Reset
Set EXDS to 1
WDBM
0
EXBM
0
WDDS
0
EXDS
0
1
RSEN
0
O4EN
0
O3EN
0
O1EN
0
Bit
Symbol
Value
7
WDBM
0 or 1
6
EXBM
0
5
WDDS
0 or 1
4
EXDS
1
3
RSEN
0 or 1
2
O4EN
0
1
O3EN
0
0
O1EN
0 or 1
Description
If 1, the WDI input is enabled when the RV-1805-C3 is powered from
VBACKUP. If 0, the WDI input is disabled when the RV-1805-C3 is powered
from VBACKUP.
Unused, but has to be 0 to avoid extraneous leakage. Disables an internal
input when the RV-1805-C3 is powered from VBACKUP.
If 1, the WDI input is disabled when the RV-1805-C3 is in Sleep Mode. If 0,
the WDI input is enabled when the RV-1805-C3 is in Sleep Mode. If WDI is
disabled, it will appear as a 1 to the internal logic.
Must be set to 1 to avoid extraneous leakage. Disables an internal input
when the RV-1805-C3 is in Sleep Mode.
If 1, the RST output is enabled when the RV-1805-C3 is in Sleep Mode.
If 0, the RST output is completely disconnected when the RV-1805-C3 is
in Sleep Mode.
Unused, but has to be 0 to avoid extraneous leakage. If 0, an internal
output is completely disconnected when the RV-1805-C3 is in Sleep Mode.
Unused, but has to be 0 to avoid extraneous leakage. If 0, an internal
output is completely disconnected when the RV-1805-C3 is in Sleep Mode.
If 1, the CLK / INT output is enabled when the RV-1805-C3 is in Sleep
Mode. If 0, the CLK / INT output is completely disconnected when the RV1805-C3 is in Sleep Mode.
3.11. ID REGISTERS
28h – ID0 - Part Number Upper Register (Read Only)
This register holds the upper eight bits of the part number in BCD format, which is always 18h for the RV-1805-C3.
Address
28h
28h
Function
ID0 - Part Number Upper
Register (Read Only)
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Part Number - Digit 3
0
0
0
Bit 2
Bit 1
Bit 0
Part Number - Digit 2
1
1
0
0
0
29h – ID1 - Part Number Lower Register (Read Only)
This register holds the lower eight bits of the part number in BCD format, which is always 05h for the RV-1805-C3.
Address
29h
29h
Function
ID1 - Part Number Lower
Register (Read Only)
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Part Number - Digit 1
0
0
0
Bit 2
Bit 1
Bit 0
Part Number - Digit 0
0
0
1
0
1
32/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
2Ah – ID2 - Part Revision (Read Only)
This register holds the Revision number of the part.
Address
Function
2Ah
ID2 - Part Revision (Read
Only)
Reset
Bit
Symbol
7:3
MAJOR
2:0
MINOR
2Ah
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
MAJOR
0
Value
00000
to
11111
000 to
111
0
0
Bit 1
Bit 0
MINOR
1
0
0
1
1
Bit 1
Bit 0
Description
This field holds the major revision of the RV-1805-C3.
This field holds the minor revision of the RV-1805-C3.
2Bh – ID3 – Lot Lower (Read Only)
This register holds the lower 8 bits of the manufacturing lot number.
Address
Function
2Bh
ID3 – Lot Lower (Read
Only)
Reset
Bit
Symbol
7:0
Lot[7:0]
2Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Lot[7:0]
Preconfigured Lot Number
Value
00h to
FFh
Description
This field holds the lower 8 bits of the manufacturing lot number.
2Ch – ID4 – Unique ID Upper (Read Only)
This register holds part of the manufacturing information of the part, including bit 9 of the manufacturing lot number
and the upper 7 bits of the unique part identifier. The 15-bit ID field contains a unique value for each RV-1805-C3
part.
Address
Function
Bit 7
2Ch
2Ch
ID4 – ID Upper (Read Only)
Reset
Lot[9]
Bit
Symbol
Value
7
6:0
Lot[9]
ID[14:8]
0 or 1
000000
0 to
111111
1h
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ID[14:8]
Preconfigured Value
Description
This field holds bit 9 of the manufacturing lot number.
This field holds the upper 7 bits of the unique part ID.
2Dh – ID5 – Unique ID Lower (Read Only)
This register holds the lower 8 bits of the unique part identifier. The 15-bit ID field contains a unique value for each
RV-1805-C3 part.
Address
Function
2Dh
ID5 – Unique Lower (Read
Only)
Reset
Bit
Symbol
7:0
ID[7:0]
2Dh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ID[7:0]
Preconfigured Value
Value
00h to
FFh
Description
This field holds the lower 8 bits of the unique part ID.
33/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
2Eh – ID6 – Wafer (Read Only)
Address
2Eh
2Eh
Bit
Function
Bit 7
ID6 – Wafer (Read Only)
Reset
Lot[8]
Symbol
Value
7
Lot[8]
6:1
Wafer
1:0
RESERVED
0 or 1
00000
to
11111
00 to 11
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Wafer
Preconfigured Value
Bit 1
Bit 0
RESERVED
Description
This field holds bit 8 of the manufacturing lot number.
This field holds the manufacturing wafer number.
RESERVED
3.12. RAM REGISTERS
3Fh - Extension RAM Address
This register controls access to the Extension RAM, and includes some miscellaneous control bits.
Address
Bit 7
Bit 6
Bit 5
3Fh
3Fh
Extension RAM Address
Reset
Function
O4BM
0
BPOL
0
WDIN
EXIN
Read Only
Bit
Symbol
Value
7
O4BM
0
6
BPOL
0 or 1
5
4
3
WDIN
EXIN
RSVD
0 or 1
0
0 or 1
2
XADA
0 or 1
1:0
XADS
00 to 11
Bit 4
Bit 3
Bit 2
RSVD
0
XADA
0
Bit 1
Bit 0
XADS
0
0
Description
Unused, but must be set to 0 to avoid extraneous leakage. If 0, an internal
output is completely disconnected when the RV-1805-C3 is powered from
VBACKUP.
BL Polarity. When 0, the Battery Low flag BL is set when the VBACKUP
voltage goes below the BREF threshold. When 1, the Battery Low flag BL
is set when the VBACKUP voltage goes above the BREF threshold.
(read only) – this bit supplies the current level of the WDI pin.
(read only) – Unused
RESERVED
This field supplies the upper bit for addresses to the Alternate RAM
address space.
This field supplies the upper two address bits for the Standard RAM
address space.
40h - 7Fh – Standard RAM
64 bytes of RAM space. The data in the RAM is held when using battery power. The upper 2 bits of the RAM
address are taken from the XADS field, and the lower 6 bits are taken from the address offset, supporting a total
RAM of 256 bytes. The initial values of the RAM locations are undefined.
80h - FFh – Alternate RAM
128 bytes of RAM. The data in the RAM is held when using battery power. The upper bit of the RAM address is
taken from the XADA field, and the lower 7 bits are taken from the address offset, supporting a total RAM of 256
bytes. The initial values of the RAM locations are undefined.
34/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
3.13. REGISTER RESET VALUES SUMMARY
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Fh
20h
21h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
3Fh
Function
Hundredths
Seconds
Minutes
Hours
Date
Months
Years
Weekdays
Hundredths Alarm
Seconds Alarm
Minutes Alarm
Hours Alarm
Date Alarm
Months Alarm
Weekdays Alarm
Status (Read Only)
Control1
Control2
Interrupt Mask
SQW
Calibration XT
Calibration RC Upper
Calibration RC Lower
Sleep Control
Countdown Timer Control
Countdown Timer
Timer Initial Value
Watchdog Timer
Oscillator Control
Oscillator Status Register
Configuration Key
Trickle
BREF Control
AFCTRL
Batmode IO Register
ID0 - Part Number Upper
Register (Read Only)
ID1 - Part Number Lower
Register (Read Only)
ID2 - Part Revision (Read
Only)
ID3 – Lot Lower (Read
Only)
ID4 – Unique ID Upper
(Read Only)
ID5 – Unique ID Lower
(Read Only)
ID6 – Wafer (Read Only)
Analog Status Register
(Read Only)
Output Control Register
Extension RAM Address
Bit 7
Bit 6
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
Preconfigured
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
Bit 0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
Preconfigured (Factory Calibrated)
Preconfigured (Factory Calibrated)
Preconfigured (Factory Calibrated)
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Preconfigured Lot Number
Preconfigured Value
Preconfigured Value
Preconfigured Value
0
0
0
0
0
0
Read Only
0
0
35/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4. DETAILED FUNCTIONAL DESCRIPTION
The RV-1805-C3 serves as a companion part for host processors including microcontrollers, radios, and digital
signal processors. It tracks time as in a typical RTC product and additionally provides unique power management
functionality that makes it ideal for highly energy-constrained applications. To support such operation, the RV1805-C3 includes 3 distinct feature groups: 1) baseline timekeeping features, 2) advanced timekeeping features,
and 3) power management features. Functions from each feature group may be controlled via I/O offset mapped
2
registers. These registers are accessed using the I C serial interface. Each feature group is described briefly below
and in greater detail in subsequent sections.
The baseline timekeeping feature group supports the standard digitally calibrated 32.768 kHz crystal (XT)
oscillation mode for maximum frequency accuracy with an ultra-low current draw of 60 nA. The baseline
timekeeping feature group also includes a standard set of counters monitoring hundredths of a second up through
centuries. A complement of countdown timers and alarms may additionally be set to initiate interrupts or resets on
several of the outputs.
The advanced timekeeping feature group supports two additional oscillation modes: 1) RC oscillator mode, and 2)
Autocalibration mode. At only 17 nA, the temperature-compensated RC oscillator mode provides an even lower
current draw than the XT oscillator for applications with reduced frequency accuracy requirements. A proprietary
calibration algorithm allows the RV-1805-C3 to digitally tune the RC oscillator frequency and the XT oscillator
frequency with accuracy as low as 2 ppm at a given temperature. In Autocalibration mode, the RC oscillator is used
as the primary oscillation source and is periodically calibrated against the digitally tuned XT oscillator.
Autocalibration may be done automatically every 8.5 minutes or 17 minutes and may also be initiated via software.
This mode enables average current draw of only 22 nA with frequency accuracy similar to the XT oscillator. The
advanced timekeeping feature group also includes a rich set of input and output configuration options that enables
the monitoring of external interrupts (e.g., pushbutton signals), the generation of clock outputs, and watchdog timer
functionality.
Power management features built into the RV-1805-C3 enable it to operate as a backup device in both linepowered and battery-powered systems. An integrated power control module automatically detects when main
power (VDD) falls below a threshold and switches to backup power (VBACKUP). Up to 256B of ultra-low leakage RAM
enable the storage of key parameters when operating on backup power.
The RV-1805-C3 is the first RTC to incorporate a number of more advanced power management features. In
particular, the RV-1805-C3 includes a finite State Machine (SM) (integrated with the Power Control block) that can
control a host processor as it transitions between sleep/reset states and active states. Digital outputs can be
configured to control the reset signal or interrupt input of the host controller. The RV-1805-C3 additionally
integrates a power switch with ~1 Ω impedance that can be used to cut off ground current on the host
microcontroller and reduce sleep current to <1 nA. The RV-1805-C3 parts can wake up a sleeping system using
internally generated timing interrupts or externally generated interrupts generated by digital inputs (e.g., using a
pushbutton) or an analog comparator. The aforementioned functionality enables users to seamlessly power down
host processors, leaving only the energy-efficient RV-1805-C3 chip awake. The RV-1805-C3 also includes voltage
detection on the backup power supply.
Each functional block is explained in detail in the remainder of this section. Functional descriptions refer to the
registers shown in the two Tables in Section REGISTER OVERVIEW. A detailed description of all registers can be
found in Section REGISTER ORGANIZATION.
36/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.2. I2C INTERFACE
2
The I C interface is for bidirectional, two-line communication between different ICs or modules. The device is
2
accessed at addresses D2h/D3h, and supports Fast Mode (up to 400 kHz). The I C interface consists of two lines:
one bi-directional data line (SDA) and one clock line (SCL). Both lines are connected to a positive supply via pullup resistors. Data transfer is initiated only when the interface is not busy.
I C termination resistors should be above 2.2 kΩ, and for systems with short I C bus wires/traces and few
connections these terminators can typically be as large as 22 kΩ (for 400 kHz operation) or 56 kΩ (for 100 kHz
operation). Larger resistors will produce lower system current consumption.
2
2
4.2.1.BUS NOT BUSY
Both SDA and SCL remain high.
4.2.2.BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line remains stable during the HIGH
period of the clock pulse, as changes in the data line at this time are interpreted as a control signals. Data changes
should be executed during the LOW period of the clock pulse (see figure below).
Bit transfer:
SDA
SCL
data line
stable;
data valid
change of
data
allowed
4.2.3.START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while
the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH transition of the data line, while the clock
is HIGH, is defined as the STOP condition (P) (see figure below).
Definition of START and STOP conditions:
SDA
SDA
SCL
SCL
S
P
START
condition
STOP
condition
A START condition which occurs after a previous START but before a STOP is called a RESTART condition, and
functions exactly like a normal STOP followed by a normal START.
37/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.2.4.DATA VALID
After a START condition, SDA is stable for the duration of the high period of SCL. The data on SDA may be
changed during the low period of SCL. There is one clock pulse per bit of data. Each data transfer is initiated with a
START condition and terminated with a STOP condition. The number of data bytes transferred between the
START and STOP conditions is not limited. The information is transmitted byte-wide and each receiver
acknowledges with a ninth bit.
4.2.5.SYSTEM CONFIGURATION
2
2
Since multiple devices can be connected with the I C bus, all I C bus devices have a fixed and unique device
number built-in to allow individual addressing of each device.
2
The device that controls the I C bus is the Master; the devices which are controlled by the Master are the Slaves. A
device generating a message is a Transmitter; a device receiving a message is the Receiver. The RV-1805-C3
acts as a Slave-Receiver or Slave-Transmitter.
2
Before any data is transmitted on the I C bus, the device which should respond is addressed first. The addressing
is always carried out with the first byte transmitted after the start procedure. The clock signal SCL is only an input
signal, but the data signal SDA is a bidirectional line.
System configuration:
SDA
SCL
MASTER
TRANSMITTER
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER
RECEIVER
4.2.6.ACKNOWLEDGE
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is
unlimited. Each byte of 8 bits is followed by an acknowledge cycle.
• A slave receiver, which is addressed, must generate an acknowledge cycle after the reception of each byte
• Also a master receiver must generate an acknowledge cycle after the reception of each byte that has been
clocked out of the slave transmitter
• The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that
•
the SDA line is stable LOW during the HIGH period of the related acknowledge clock pulse (set-up and
hold times must be considered)
A master receiver must signal an end of data to the transmitter by not generating an acknowledge cycle on
the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line
HIGH to enable the master to generate a STOP condition
2
Acknowledgement on the I C bus is shown on the figure below.
38/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
2
Acknowledgement on the I C bus:
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL form
master
2
1
8
9
S
START
condition
clock pulse for
acknowledgement
4.2.7.ADDRESSING
2
2
On the I C bus the 7-bit slave address 1101001b is reserved for the RV-1805-C3. The entire I C bus slave address
byte is shown in the table below.
2
I C slave address byte:
Slave address
7
Bit
6
5
4
3
2
1
MSB
1
0
LSB
1
0
1
0
0
1
R/ W
2
After a START condition, the I C slave address has to be sent to the RV-1805-C3 device. The R/ W bit defines the
direction of the following single or multiple byte data transfer. The 7-bit address is transmitted MSB first. If this
address is 1101001b, the RV-1805-C3 is selected, the eighth bit indicate a write (R/ W = 0) or a read (R/ W = 1)
operation (results in D2h or D3h) and the RV-1805-C3 supplies the ACK. The RV-1805-C3 ignores all other
address values and does not respond with an ACK.
In the write operation, a data transfer is terminated by sending either the STOP condition or the START condition of
the next data transfer.
39/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.2.8.WRITE OPERATION
Master transmits to Slave-Receiver at specified address. The Register Address is an 8-bit value that defines which
register is to be accessed next. After reading or writing one byte, the Register Address is automatically incremented
by 1.
1) Master sends out the START condition.
2) Master sends out Slave Address, D2h for the RV-1805-C3; the R/ W bit is a 0 indicating a write operation.
3) Acknowledgement from the RV-1805-C3.
4) Master sends out the Register Address to the RV-1805-C3.
5) Acknowledgement from the RV-1805-C3.
6) Master sends out the Data to write to the specified address in step 4).
7) Acknowledgement from the RV-1805-C3.
8) Steps 6) and 7) can be repeated if necessary. The address will be incremented automatically in the RV1805-C3.
9) Master sends out the STOP Condition.
2
3
S
SLAVE ADDRESS
0 A
4
5
6
7
8
REGISTER ADDRESS
A
DATA
A
DATA
R/W
1
9
A
P
Acknowledge from RV-1805-C3
4.2.9.READ OPERATION AT SPECIFIC ADDRESS
Master reads data after setting Register Address:
1)
2)
3)
4)
5)
6)
7)
8)
Master sends out the START condition.
Master sends out Slave Address, D2h for the RV-1805-C3; the R/ W bit is a 0 indicating a write operation.
Acknowledgement from the RV-1805-C3.
Master sends out the Register Address to the RV-1805-C3.
Acknowledgement from the RV-1805-C3.
Master sends out the RESTART condition (STOP condition followed by START condition)
Master sends out Slave Address, D3h for the RV-1805-C3; the R/ W bit is a 1 indicating a read operation.
Acknowledgement from the RV-1805-C3.
At this point, the Master becomes a Receiver, the Slave becomes the Transmitter.
9) The Slave sends out the Data from the Register Address specified in step 4).
10) Acknowledgement from the Master.
11) Steps 9) and 10) can be repeated if necessary.
The address will be incremented automatically in the RV-1805-C3.
12) The Master, addressed as Receiver, can stop data transmission by not generating an acknowledge on the
last byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the
data line HIGH to enable the Master to generate a STOP condition.
13) Master sends out the STOP condition.
SLAVE ADDRESS
3
0 A
4
5
6
7
REGISTER ADDRESS
A
S
SLAVE ADDRESS
RESTART
Acknowledge from RV-1805-C3
8
1 A
9
10
11
DATA
A
DATA
12 13
A
P
R/W
S
2
R/W
1
Acknowledge from Master
No acknowledge
40/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.2.10. READ OPERATION
Master reads Slave-Transmitter immediately after first byte:
1) Master sends out the START condition.
2) Master sends out Slave Address, D3h for the RV-1805-C3; the R/ W bit is a 1 indicating a read operation.
3) Acknowledgement from the RV-1805-C3.
At this point, the Master becomes a Receiver, the Slave becomes the Transmitter
4) The RV-1805-C3 sends out the Data from the last accessed Register Address incremented by 1.
5) Acknowledgement from the Master.
6) Steps 4) and 5) can be repeated if necessary.
The address will be incremented automatically in the RV-1805-C3.
7) The Master, addressed as Receiver, can stop data transmission by not generating an acknowledge on the
last byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the
data line HIGH to enable the Master to generate a STOP condition.
8) Master sends out the STOP condition.
2
3
S
SLAVE ADDRESS
1 A
4
5
DATA
A
6
DATA
7
8
A
P
R/W
1
Acknowledge from RV-1805-C3
Acknowledge from Master
No acknowledge
4.3. XT OSCILLATOR
The RV-1805-C3 includes a very power efficient crystal (XT) oscillator which runs at 32.768 kHz. This oscillator is
selected by setting the OSEL bit to 0 and includes a low jitter calibration function.
4.4. RC OSCILLATOR
The RV-1805-C3 includes an extremely low power RC oscillator which runs at typically 122 Hz (Fnom = 128 Hz).
This oscillator is selected by setting the OSEL bit to 1. Switching between the XT and RC Oscillators is guaranteed
to produce less than one second of error in the Calendar Counters. The RV-1805-C3 may be configured to
automatically switch to the RC Oscillator when VDD drops below its threshold by setting the AOS bit, and/ or be
configured to automatically switch if an XT Oscillator failure is detected by setting the FOS bit.
4.5. RTC COUNTER ACCESS
When reading any of the counters in the RTC using a burst operation, the 1 Hz and 100 Hz clocks are held off
during the access. This guarantees that a single burst will either read or write a consistent timer value (other than
the Hundredths Counter – see HUNDREDTHS SYNCHRONIZATION). There is a watchdog function to insure that
a very long pause on the interface does not cause the RTC to lose a clock.
On a write to any of the Calendar Counters, the entire timing chain up to 100 Hz (if the XT Oscillator is selected) or
up to 1Hz (if the RC Oscillator is selected) is reset to 0. This guarantees that the Counters will begin counting
immediately after the write is complete, and that in the XT oscillator case the next 100 Hz clock will occur exactly
10 ms later. In the RC Oscillator case, the next 1 Hz clock will occur exactly 1 second later. This allows a burst
write to configure all of the Counters and initiate a precise time start. Note that a Counter write may cause one
cycle of a Square Wave output to be of an incorrect period.
The WRTC bit must be set in order to write to any of the Counter registers. This bit can be cleared to prevent
inadvertent software access to the Counters.
41/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.6. HUNDREDTHS SYNCHRONIZATION
If the Hundredths Counter is read as part of the counter burst, there is a small probability (approximately 1 in 109)
that the Hundredths Counter rollover from 99 to 00 and the Seconds Counter increment will be separated by the
read. In this case, correct read information can be guaranteed by the following algorithm.
1. Read the Counters, using a burst read. If the Hundredths Counter is neither 00 nor 99, the read is correct.
2. If the Hundredths Counter was 00, perform the read again. The resulting value from this second read is
guaranteed to be correct.
3. If the Hundredths Counter was 99, perform the read again.
A. If the Hundredths Counter is still 99, the results of the first read are guaranteed to be correct. Note
that it is possible that the second read is not correct.
B. If the Hundredths Counter has rolled over to 00, and the Seconds Counter value from the second
read is equal to the Seconds Counter value from the first read plus 1, both reads produced correct
values. Alternatively, perform the read again. The resulting value from this third read is guaranteed
to be correct.
C. If the Hundredths Counter has rolled over to 00, and the Seconds Counter value from the second
read is equal to the Seconds Counter value from the first read, perform the read again. The
resulting value from this third read is guaranteed to be correct.
4.7. GENERATING HUNDREDTHS OF A SECOND
The generation of an exact 100 Hz signal for the Hundredths Counter requires a special logic circuit. The 2.048
kHz clock signal is divided by 21 for 12 iterations, and is alternately divided by 20 for 13 iterations. This produces
an effective division of:
(21 * 12 + 20 * 13)/25 = 20.48
producing an exact long-term average 100 Hz output, with a maximum jitter of less than 1 ms. The Hundredths
Counter is not available when the RC Oscillator is selected.
4.8. WATCHDOG TIMER
The RV-1805-C3 includes a Watchdog Timer (WDT), which can be configured to generate an interrupt or a reset if
it times out. The WDT is controlled by the Watchdog Timer Register (see TIMER REGISTERS, 1Bh - Watchdog
Timer). The WRB field selects the frequency at which the timer is decremented, and the BMB field determines the
value loaded into the timer when it is restarted. If the timer reaches a value of zero, the WDS bit determines
whether an interrupt is generated in CLK/ INT (if WDS is 0) or the RST output pin is asserted (if WDS is 1). The
timer reaching zero sets the WDT flag in the Status Register, which may be cleared by setting the WDT flag to
zero. If reset is selected, the RST output pin is asserted within 1/16 second of the timer reaching zero and remains
asserted for 1/16 second.
Two actions will restart the WDT timer:
1. Writing the Watchdog Timer Register with a new watchdog value.
2. A change in the level of the WDI pin.
If the Watchdog Timer generates an interrupt or reset, the Watchdog Timer Register must be written in order to
restart the Watchdog Timer function. If the BMB field is 0, the Watchdog Timer function is disabled.
The BMB field describes the maximum timeout delay. For example, if WRB = 01 so that the clock period is 250 ms,
a BMB value of 9 implies that the timeout will occur between 2000 ms and 2250 ms after writing the Watchdog
Timer Register.
42/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.9. DIGITAL CALIBRATION
4.9.1.XT OSCILLATOR DIGITAL CALIBRATION
In order to improve the accuracy of the XT oscillator, a Distributed Digital Calibration function is included (see
CALIBRATION REGISTERS, 14h - Calibration XT). This function uses a calibration value, OFFSETX, to adjust the
clock period over a 16 second or 32 second calibration period. When the 32.768 kHz XT oscillator is selected, the
clock at the 16.384 kHz level of the divider chain is modified on a selectable interval. Clock pulses are either added
or subtracted to ensure accuracy of the counters. If the CMDX bit is a 0 (normal calibration), OFFSETX cycles of
the 16.384 kHz clock level are gated (negative calibration) or replaced by 32.768 kHz level pulses (positive
calibration) within every 32 second calibration period. In this mode, each step in OFFSETX modifies the clock
frequency by 1.907 ppm, with a maximum adjustment of ~+120/-122 ppm. If the CMDX bit is 1 (coarse calibration),
OFFSETX cycles of the 16.384 kHz clock level are gated or replaced by the 32.768 kHz level pulses within every
16 second calibration period. In this mode, each step in OFFSETX modifies the clock frequency by 3.814 ppm, with
a maximum adjustment of ~+240/-244 ppm. OFFSETX contains a two's complement value, so the possible steps
are from -64 to +63 (7 bits). Note that unlike other implementations, the Distributed Digital Calibration guarantees
that the clock is precisely calibrated every 32 seconds with normal calibration and every 16 seconds when coarse
calibration is selected.
The pulses which are added to or subtracted from the 16.384 kHz clock level are spread evenly over each 16 or 32
second period using the Distributed Calibration algorithm. This insures that in XT mode the maximum cycle-to-cycle
jitter in any clock of a frequency 16.384 kHz or lower caused by calibration will be no more than one 16.384 kHz
period. This maximum jitter applies to all clocks in the RV-1805-C3, including the Calendar Counter, Countdown
Timer and Watchdog Timer clocks and the clock driven onto the CLK / INT pin.
In addition to the normal calibration, the RV-1805-C3 also includes an Extended Calibration field to compensate a
higher XT oscillator frequency. The frequency generated by the Crystal Oscillator may be reduced by 122 ppm
times the value in the XTCAL (see OSCILLATOR REGISTERS, 1Dh – Oscillator Status Register) field (0, -122,
-244 or -366 ppm). The clock is still precisely calibrated in 16 or 32 seconds. Normally, this field is not used.
The XT oscillator calibration value OFFSETX is determined by the following process:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Set the OFFSETX, CMDX and XTCAL register fields to 0 to ensure calibration is not occurring.
Select the XT oscillator by setting the OSEL bit to 0.
Configure a square wave output on the output pin CLK / INT of frequency Fnom = 32’768 Hz.
Measure the frequency Fmeas at the output pin in Hz.
Compute the adjustment value required in ppm: PAdj = ((32’768 – Fmeas)*1’000’000)/32’768
Compute the adjustment value in steps: Adj = PAdj/(1’000’000/2^19) = PAdj/(1.90735)
If Adj < -320, the XT frequency is too high to be calibrated
Else if Adj < -256, set XTCAL = 3, CMDX = 1, OFFSETX = (Adj +192)/2
Else if Adj < -192, set XTCAL = 3, CMDX = 0, OFFSETX = Adj +192
Else if Adj < -128, set XTCAL = 2, CMDX = 0, OFFSETX = Adj +128
Else if Adj < -64, set XTCAL = 1, CMDX = 0, OFFSETX = Adj + 64
Else if Adj < 64, set XTCAL = 0, CMDX = 0, OFFSETX = Adj
Else if Adj < 128, set XTCAL = 0, CMDX = 1, OFFSETX = Adj/2
Else the XT frequency is too low to be calibrated
43/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.9.2.RC OSCILLATOR DIGITAL CALIBRATION
The RC Oscillator has a Distributed Digital Calibration function similar to that of the XT Oscillator (see
CALIBRATION REGISTERS, 14h - Calibration XT). However, because the RC Oscillator has a greater
fundamental variability, the range of calibration is much larger, with four calibration ranges selected by the CMDR
field. When the RC oscillator is selected, the clock at the 64 Hz level of the divider chain is modified on a selectable
interval using the calibration value OFFSETR. Clock pulses are either added or subtracted to ensure accuracy of
the counters. If the CMDR field is 00, OFFSETR cycles of the 64 Hz clock level are gated (negative calibration) or
replaced by 128 Hz level pulses (positive calibration) within every 8’192 second calibration period. In this mode,
each step in OFFSETR modifies the clock frequency by 1.907 ppm, with a maximum adjustment of +15’623/15’625 ppm (+/- 1.56%). If the CMDR field is 01, OFFSETR cycles of the 64 Hz clock level are gated or replaced by
the 128 Hz level pulses within every 4’096 second calibration period. In this mode, each step in OFFSETR modifies
the clock frequency by 3.814 ppm, with a maximum adjustment of +31’246/ -31’250 ppm (+/-3.12%). If the CMDR
field is 10, OFFSETR cycles of the 64 Hz clock level are gated (negative calibration) or replaced by 128 Hz level
pulses (positive calibration) within every 2’048 second calibration period. In this mode, each step in OFFSETR
modifies the clock frequency by 7.64 ppm, with a maximum adjustment of +62’492/-62’500 ppm (+/- 6.25%). If the
CMDR field is 11, OFFSETR cycles of the 64 Hz clock level are gated or replaced by pulses from the 128 Hz clock
level within every 1’024 second calibration period. In this mode, each step in OFFSETR modifies the clock
frequency by 15.28 ppm, with a maximum adjustment of +124’984/-125’000 ppm (+/-12.5%). OFFSETR contains a
two's complement value, so the possible steps are from -8’192 to +8’191 (14 bits).
The pulses which are added to or subtracted from the 64 Hz clock level are spread evenly over each 8’192 second
period using the Distributed Calibration algorithm. This insures that in RC mode the maximum cycle-to-cycle jitter in
any clock of a frequency 64 Hz or lower caused by calibration will be no more than one 64 Hz period. This
maximum jitter applies to all clocks in the RV-1805-C3, including the Calendar Counter, Countdown Timer and
Watchdog Timer clocks and the clock driven onto the CLK / INT pins.
The RC oscillator calibration value OFFSETR is determined by the following process:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Set the OFFSETR and CMDR register fields to 0 to insure calibration is not occurring.
Select the RC oscillator by setting the OSEL bit to 1.
Configure a square wave output on the output pin CLK / INT of frequency Fnom = 128 Hz.
Measure the frequency Fmeas at the output pin.
Compute the adjustment value required in ppm as ((128 – Fmeas)*1’000’000)/Fmeas = PAdj
Compute the adjustment value in steps as PAdj/(1’000’000/2^19) = PAdj/(1.90735) = Adj
If Adj < -65’536, the RC frequency is too high to be calibrated
Else if Adj < -32’768, set CMDR = 3, OFFSETR = Adj/8
Else if Adj < -16’384, set CMDR = 2, OFFSETR = Adj/4
Else if Adj < -8’192, set CMDR = 1, OFFSETR = Adj/2
Else if Adj < 8’192, set CMDR = 0, OFFSETR = Adj
Else if Adj < 16’384, set CMDR = 1, OFFSETR = Adj/2
Else if Adj < 32’768, set CMDR = 2, OFFSETR = Adj/4
Else if Adj < 65’536, set CMDR = 3, OFFSETR = Adj/8
Else the RC frequency is too low to be calibrated
44/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
The following figure shows the modified clock at the 64 Hz level with the achieved time accuracy in ppm after 96
seconds (at TA = 25°C and VDD = 3.0 V).
Modified clock at the 64 Hz level:
130
500
120
400
f average in Hz
300
200
100
100
90
0
80
-100
-200
70
-300
60
-400
50
Accur. in ppm
Time Accuracy in ppm
110
Frequency in Hz
f in Hz
-500
95
95.2
95.4
95.6
Time in s
95.8
96
45/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.10. AUTOCALIBRATION
The RV-1805-C3 includes the capability of using the internal RC Oscillator for all timing functions. For increased
accuracy at a small power penalty, the RC Oscillator may be periodically calibrated to the digitally calibrated Crystal
(XT) Oscillator which is turned on only during this calibration. The overall process is referred to as Autocalibration
and under most conditions produces a clock with long term accuracy essentially indistinguishable from the digitally
calibrated XT Oscillator alone, as shown in the RC/Acal bubble in the following Figure.
Basic Mode Comparison:
XT/Acal
60
VDD = 3.0 V
XT
50
Average
Current
(nA)
TA = 25°C
XT
XT
40
30
20
ACP = 512 sec.
RC/Acal
RC/Acal
RC
ACP = 1024 sec.
10
3
5
100
1'000
10'000
Expected Time Accuracy per Year (ppm)
(1ppm/Year = 31.6 seconds)
4.11. BASIC AUTOCALIBRATION OPERATION
The RV-1805-C3 includes a very powerful automatic calibration feature, referred to as Autocalibration, which allows
the RC Oscillator to be automatically calibrated to the digitally calibrated XT Oscillator. The digitally calibrated XT
Oscillator typically has much better stability than the RC Oscillator, but the RC Oscillator requires significantly less
power. Autocalibration enables many system configurations to achieve accuracy and stability similar to that of the
digitally calibrated XT Oscillator while drawing current similar to that of the RC Oscillator. Autocalibration functions
in two primary modes: XT Autocalibration Mode and RC Autocalibration Mode.
4.11.1. AUTOCALIBRATION OPERATION
The Autocalibration operation counts the number of calibrated XT clock cycles within a specific period as defined
by the RC Oscillator and then loads new values into the Calibration RC Upper and RC Lower registers which will
then adjust the RC Oscillator output to match the digitally calibrated XT frequency. In most cases Autocalibration is
configured by the host controller over the serial interface when the RV-1805-C3 is initialized.
46/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.11.2. XT AUTOCALIBRATION MODE
XT Autocalibration Mode is used when the digitally calibrated XT Oscillator is normally active, but the system is
configured to switch to the RC Oscillator on a failure or a switchover to battery power (see also AUTOMATIC
SWITCHOVER SUMMARY). In XT Autocalibration Mode, the OSEL register bit is set to 0, ACAL is set to 10 or 11
and the RV-1805-C3 uses the XT Oscillator whenever the system power VDD is above the VDDSWF voltage. The RC
Oscillator is periodically automatically calibrated to the XT Oscillator. If the AOS bit is set, when VDD drops below
the VDDSWF threshold the system will switch to using VBACKUP, the clocks will begin using the RC Oscillator (RC
Mode according to the ACAL field) and the XT Oscillator will be disabled to reduce power requirements. Because
the RC Oscillator has been continuously calibrated to the digitally calibrated XT Oscillator, it will be already very
accurate when the switch occurs. When VDD is again above the threshold, the system will switch back to use the XT
Oscillator in the XT Autocalibration Mode. It is possible to gain or lose up to one second during a switchover
between the oscillators.
4.11.3. RC AUTOCALIBRATION MODE
RC Autocalibration Mode is used when the RC Oscillator is always used as the clock but it is desired to maintain
the frequency of the RC Oscillator as close to the digitally calibrated XT Oscillator as possible. In RC
Autocalibration Mode, the OSEL register bit is set to 1, ACAL is set to 10 or 11 and the RV-1805-C3 uses the RC
Oscillator at all times. However, periodically the XT Oscillator is turned on and the RC Oscillator is calibrated to the
XT Oscillator. This allows the system to operate most of the time with the XT Oscillator off but allow continuous
calibration of the RC Oscillator and maintain high accuracy for the RC Oscillator.
4.11.4. AUTOCALIBRATION FREQUENCY AND CONTROL
The Autocalibration function is controlled by the ACAL field in the Oscillator Control register as shown in the
following Table. If ACAL is 00, no Autocalibration occurs. If ACAL is 10 or 11, Autocalibration occurs every 1024 or
512 seconds, which is referred to as the Autocalibration Period (ACP). In RC Autocalibration Mode, an
Autocalibration operation results in the digitally calibrated XT Oscillator being enabled for roughly 50 seconds. The
512 second Autocalibration cycles have the XT Oscillator enabled approximately 10% of the time, while 1024
second Autocalibration cycles have the XT Oscillator enabled approximately 5% of the time.
ACAL Value
00
01
10
11
Autocalibration Mode
No Autocalibration
RESERVED
Autocalibrate every 1024 seconds (~17minutes)
Autocalibrate every 512 seconds (~8.5 minutes)
If ACAL is 00 and is then written with a different value, an Autocalibration cycle is immediately executed. This
allows Autocalibration to be completely controlled by software. As an example, software could choose to execute
an Autocalibration cycle every 2 hours by keeping ACAL at 00, getting a two hour interrupt using the alarm
function, generating an Autocalibration cycle by writing ACAL to 10 or 11, and then returning ACAL to 00.
47/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.11.5. AUTOCALIBRATION FILTER (Cap_RC) PIN
In order to produce the optimal accuracy for the Autocalibrated RC Oscillator, a filter pin Cap_RC is provided. A
47 pF capacitor should be connected between the Cap_RC pin and VSS. In order to enable the filter, the value A0h
must be written to the AFCTRL Register at address 26h (Section ANALOG CONTROL REGISTERS). The Cap_RC
filter is disabled by writing 00h to the AFCTRL Register. No other values should be written to this register. The
Configuration Key Register must be written with the value 9Dh immediately prior to writing the AFCTRL Register.If
the filter capacitor is not connected to the Cap_RC pin or is not enabled, the Autocalibrated RC Oscillator
frequency will typically be between 10 and 50 ppm lower than the digitally calibrated XT Oscillator. If the capacitor
is connected to the Cap_RC pin and enabled, the RC Oscillator frequency will be within the accuracy range
specified in the OSCILLATOR PARAMETERS table of the XT Oscillator.
4.11.6. AUTOCALIBRATION FAIL
If the operating temperature of the RV-1805-C3 exceeds the Autocalibration range specified in the Oscillator
Parameters table or internal adjustment parameters are altered incorrectly, it is possible that the basic frequency of
the RC Oscillator is so far away from the nominal 128 Hz value (off by more than 12%) that the RC Calibration
circuitry does not have enough range to correctly calibrate the RC Oscillator. If this situation is detected during an
Autocalibration operation, the ACF interrupt flag is set, an interrupt is generated if the ACIE register bit is set and
the Calibration RC registers are not updated.
If an Autocalibration failure is detected while running in RC Autocalibration mode, it is advisable to switch into XT
Autocalibration mode to maintain the timing accuracy. This is done by first ensuring a crystal oscillator failure has
not occurred (OF flag = 0) and then clearing the OSEL bit. The ACAL field should remain set to either 11 (512
second period) or 10 (1024 second period). After the switch occurs, the OMODE bit is cleared.
While continuing to operate in XT Autocalibration mode, the following steps can be used to determine when it is
safe to return to RC Autocalibration mode.
1. Clear the ACF flag and ACIE register bit.
2. Setup the Countdown Timer or Alarm to interrupt after the next Autocalibration cycle completes or longer
time period.
3. After the interrupt occurs, check the status of the ACF flag.
4. If the ACF flag is set, it is not safe to return to RC Autocalibration mode. Clear the ACF flag and repeat
steps 2-4.
5. If the ACF flag is still cleared, it is safe to return to RC Autocalibration mode by setting the OSEL bit.
As mentioned in the RC oscillator section, switching between XT and RC oscillators is guaranteed to produce less
than one second of error. However, this error needs to be considered and can be safely managed when
implementing the steps above. For example, switching between oscillator modes every 48 hours will produce less
than 6 ppm of error.
4.11.7. ACCURACY ERRORS IN RC AUTOCALIBRATION MODE
RC Autocalibration Mode is typically the most useful mode, because it allows a dramatic reduction in the power
used by the RV-1805-C3 while maintaining the accuracy of the internal clock. The RC is always used as the
internal clock so that no time errors occur as can be seen with XT Autocalibration Mode and automatic switchover.
RC Autocalibration Mode is the only applicable mode in systems where there is only a single battery supply, which
is very common. Because the RC Oscillator is fundamentally less stable with temperature (typically +/- 1%, or
10’000 ppm, over the full temperature range) than the digitally calibrated XT Oscillator (typically within 150 ppm
over the full temperature range), many applications cannot use the RC Oscillator alone as the timing clock. RC
Autocalibration improves the accuracy of the RC Oscillator by continuously adjusting it to match the calibrated XT
Oscillator.
48/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
Autocalibration maintains the RC Oscillator at a frequency very close to the digitally calibrated XT Oscillator, but
there are obviously small errors which can occur on each cycle. However, as temperature and the raw RC
Oscillator frequency vary, errors typically cancel each other out and produce very low accumulated error. The
following Figure shows a time sequence with varying frequency. The heavy shaded line shows the variation of the
raw RC Oscillator on the 64 Hz level, and the vertical dashed lines indicate the boundaries of Autocalibration
Periods (ACPs, either 512 or 1024 seconds). The RC Oscillator is calibrated within a small number of PPM at the
beginning of each ACP to the digitally calibrated XT Oscillator, so the calibrated RC frequency is the sawtooth
function in the center of the figure, with the accumulated error in each ACP shown by the shaded triangles.
Autocalibration Error Cancellation:
Raw RC frequency
on the 64 Hz level
Autocalibrated
RC frequency
Freq
64 Hz
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Time
Although some error is accumulated in each ACP, it can be seen that the positive errors which occur when the
frequency is rising are cancelled by the negative errors when the frequency is falling. Over any significant period of
time, the net accumulated error is almost completely determined by the frequency difference between the
beginning and end of the period and the rate of change of the frequency with time.
Since the frequencies of both the RC and the XT Oscillators are functions of temperature, and temperature
changes are easy to understand and quantify, accumulated error is measured as a function of the temperature
profile. The behavior of RC Autocalibration has been modeled by varying the temperature in a random way and
simulating the desired period, which in the cases below is one year. The temperature rises or falls at a random rate
between twice the average rate specified and the negative of that value, and is limited to the specified maximum
and minimum temperatures. One thousand simulations were executed, and the specified error is the worst case
result of all iterations. The following Figure shows the maximum accumulated time error relative to the digitally
calibrated XT Oscillator as a function of the maximum temperature range and the average temperature change rate
over a one year period, in seconds (31 seconds in a year = 1 ppm), with an Autocalibration Period of 512 seconds.
Note that even the lowest average change rate of 0.025 equates to one degree C every 40 minutes, which is still
quite fast when averaged over an entire year. At this change rate, the error over the full temperature range is less
than 95 seconds (<3 ppm).
49/95
Micro Crystal
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Autocalibration Time Error relative to the digitally calibrated XT Oscillator, ACP = 512 Seconds:
Time Accuracy for 1 Year in Seconds
ACP = 512 Seconds
300
250
200
-40 to 85
150
-25 to 75
100
-10 to 60
10 to 40
50
0
0
0.1
0.2
0.3
0.4
0.5
Average Temperature Change Rate in °C/min.
The following Figure shows the results when the ACP is 1024 seconds. At high temperature change rates, this
setting produces roughly 3 times the error of the 512 second case, but the errors for low change rates are still
negligible.
Autocalibration Time Error relative to the digitally calibrated XT Oscillator, ACP = 1024 Seconds:
Time Accuracy for 1 Year in Seconds
ACP = 1024 Seconds
1000
900
800
700
600
500
400
300
200
100
0
-40 to 85
-25 to 75
-10 to 60
10 to 40
0
0.4
0.5
0.1
0.2
0.3
Average Temperature Change Rate in °C/min.
50/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
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The deviations in both of the cases above for relatively low temperature change rates are less than the error
introduced by the XT Oscillator itself. The following Figure shows the raw XT error, which is more strongly a
function of the maximum temperature range than the calibrated RC error. The XT error is a similar function of the
temperature change rate but is more influenced by the maximum temperature variation. Errors in the XT Oscillator
are larger when the temperature is further away from the nominal 25 degrees C, and therefore it is expected that
the accumulated error will be greater if the temperature range is larger.
Raw Error, XT Oscillator:
Time Accuracy for 1 Year in Seconds
XT Only Error
1200
1000
800
-40 to 85
600
-25 to 75
400
-10 to 60
10 to 40
200
0
0
0.3
0.4
0.5
0.2
0.1
Average Temperature Change Rate in °C/min.
4.11.8. A REAL WORLD EXAMPLE
Even if the temperature occasionally reaches the extremes of the allowable range and changes relatively quickly, in
most real applications the temperature is reasonably stable. A proposed “real world” temperature profile assumes
that for 30 days per year the temperature has a maximum range of -25 to 75 degrees C and an average change
rate of 1 degree C every 5 minutes (0.2 °C/min.). For the remainder of the year, the maximum temperature range is
10 to 40 degrees C with a maximum change rate of 1 degree C every 40 minutes (0.025 °C/min.). Using this
profile, the accumulated errors over the year (including the XT error in the calibrated RC cases) are shown in
following Table. As can be seen, with an ACP of 512 the clock accuracy using Autocalibration is quite close to the
error achieved by the XT alone. Extending to an ACP of 1024 adds a small incremental error.
Real World Accumulated Errors for 1 Year (1 ppm = 31.6 seconds in a year):
XT Only (0 ppm at 25°C)
Cal RC, ACP = 512
Cal RC, ACP = 1024
Accumulated Error (ppm)
3.3
Accumulated Error (seconds)
104
6.1
8.4
192
245
51/95
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Extrem Low Power Real Time Clock / Calendar Module
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4.11.9. RC AUTOCALIBRATION TIMING ACCURACY EXAMPLE
The RC Oscillator displays relatively high internal jitter caused by pulse addition or subtraction of the
Autocalibration process as well as the inherent thermal noise jitter of the RC Oscillator itself. This jitter introduces
significant time accuracy errors for short time periods.
The following Figure shows a typical Autocalibration mode timing accuracy for the time periods from 1 hour to 1
year relative to the digitally calibrated XT Oscillator, ACP = 512 Seconds. The temperature does not varying. TA =
25°C, VDD = 3.0V.
Autocalibration Mode Timing Accuracy Example:
Timing Accuracy in ppm and seconds
Autocalibration Mode Timing Accuracy, ACP = 512 sec.
1000
TA = 25°C
VDD = 3.0 V
100
Accuracy in ppm
Accuracy in s
10
1
1h
4h
12h
24h 1 week1 month1 year
0.1
52/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.11.10. POWER ANALYSIS
The power comparisons between the various cases are quite straightforward. During an Autocalibration, the XT
Oscillator is powered up for 50 seconds. Therefore if the RV-1805-C3 draws 60 nA when the XT Oscillator is
running and 17 nA when the XT Oscillator is off, the average current for each ACP case is shown in the following
Table. Even the shortest ACP results in a savings of more than 60% of the current.
Autocalibration Current (TA = 25°C, VDD = 3.0V):
Average Current (nA)
XT Only
Cal RC, ACP = 512
Cal RC, ACP = 1024
60
22
19
4.11.11. DISANDVANTAGES RELATIVE TO THE XT OSCILLATOR
Maximum Output Clock Frequency
The primary disadvantage of using the autocalibrated RC Oscillator is that the highest calibrated output clock
frequency which can be generated is 64 Hz (i.e., circa the half of the uncalibrated RC Oscillator frequency). In
applications where a higher frequency clock is required, the XT Oscillator must be used. If such a clock is required
only occasionally, the RV-1805-C3 may be temporarily placed in XT Mode by setting the OSEL bit to 0, and then
returned to RC Mode by setting OSEL back to 1 when the high frequency clock is no longer required. The RV1805-C3 will continue to autocalibrate the RC Oscillator while the XT Oscillator is selected, but the calendar
counters may gain or lose up to 1 second on each of the oscillator switchovers.
Large/Rapid Temperature Fluctuations
The XT Oscillator may also be preferable to Autocalibration when there are frequent, rapid and large temperature
changes. In such a situation, the digitally calibrated XT Oscillator may provide a measurable improvement in
accuracy, although at a significant power penalty relative to using Autocalibration.
Short Term Jitter
A third disadvantage of using the RC Oscillator is that it displays higher internal jitter relative to the XT oscillator.
This jitter is caused by pulse addition or subtraction of the Autocalibration process as well as the inherent thermal
noise jitter of the RC Oscillator itself. This jitter may introduce significant frequency errors over short time periods.
In both cases the mean of the jitter is zero, and the following Table shows the standard deviation of the clock
period for several short time periods including both jitter and temperature effects. A typical worst case metric is 4
standard deviations, which covers approximately 99.99% of all cases.
Short Term Jitter Standard Deviation:
Time Interval
0.5 hours
1 hour
2 hours
4 hours
1 day
2 days
3 days
1 week
Std. Dev. (ppm)
Std. Dev. (ms)
90.9
45.5
32.3
22.5
9.3
6.5
5.3
3.5
163.6
163.8
232.6
324.0
803.5
1123.2
1373.8
2116.8
53/95
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4.12. OSCILLATOR FAILURE DETECTION
If the 32.768 kHz XT Oscillator generates clocks at less than 8 kHz for a period of more than 32 ms, the RV-1805C3 detects an Oscillator Failure. The Oscillator Failure function is controlled by several bits in the OSCILLATOR
REGISTERS (see 1Ch Oscillator Control and 1Dh - Oscillator Status Register). The OF flag is set when an
Oscillator Failure occurs, and is also set when the RV-1805-C3 initially powers up. If the OFIE bit is set, the OF flag
will generate an interrupt on IRQ.
If the FOS bit is set and the RV-1805-C3 is currently using the XT Oscillator, it will automatically switch to the RC
Oscillator on an Oscillator Failure. This guarantees that the system clock will not stop in any case. The OMODE bit
indicates the currently selected oscillator, which will not match the oscillator requested by the OSEL bit if the XT
Oscillator is not running.
The OF flag will be set when the RV-1805-C3 powers up, and will also be set whenever the XT Oscillator is
stopped. This can happen when the STOP bit is set or the OSEL bit is set to 1 to select the RC Oscillator. Since
the XT Oscillator is stopped in RC Autocalibration mode (see RC AUTOCALIBRATION MODE), OF will always be
set in this mode. The OF flag should be cleared whenever the XT Oscillator is enabled prior to enabling the OF
interrupt with OFIE.
4.13. INTERRUPTS
The RV-1805-C3 may generate a variety of interrupts which are ORed into the IRQ signal. This may be driven onto
either the CLK / INT pin or the PSW pin depending on the configuration of the OUT1S and OUT2S fields (see
CONFIGURATION REGISTERS, 11h - Control2).
4.13.1. INTERRUPT SUMMARY
The possible interrupts are summarized in the following Table. All enabled interrupts are ORed into the IRQ signal
when their respective flags are set. Note that most interrupt outputs use the inverse of the interrupt, denoted as e.g.
nIRQ. The fields are:
•
•
•
•
•
Interrupt - the name of the specific interrupt.
Function - the functional area which generates the interrupt.
Enable - the register bit which enables the interrupt. Note that for the Watchdog interrupt, WDS is the
steering bit, so that the flag generates an interrupt if WDS is 0 and a reset if WDS is 1. In either case, the
BMB field must be non-zero to generate the interrupt or reset.
Pulse/Level - some interrupts may be configured to generate a pulse based on the register bits in this
column. "Level Only" implies that only a level may be generated, and the interrupt will only go away when
the flag is reset by software.
Flag - the register bit which indicates that the function has occurred. Note that the flag being set will only
generate an interrupt signal on an external pin if the corresponding interrupt enable bit is also set.
Interrupt
AIRQ
TIRQ
WIRQ
BLIRQ
X2IRQ
OFIRQ
ACIRQ
Function
Alarm Match
Countdown Timer
Watchdog
Battery Low
External Interrupt
Oscillator Fail
Autocal Fail
Enable
AIE
TIM
!WDS
BLIE
EX2E
OFIE
ACIE
Pulse/Level
IM
TM
Level Only
Level Only
Level Only
Level Only
Level Only
Flag
ALM
TIM
WDT
BL
EX2
OF
ACF
54/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
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4.13.2. ALARM INTERRUPT AIRQ
The RV-1805-C3 may be configured to generate the AIRQ interrupt when the values in the Time and Date
Registers match the values in the Alarm Registers. Which register comparisons are required to generate AIRQ is
controlled by the RPT field as described in TIMER REGISTERS, 18h - Countdown Timer Control, allowing software
to specify the interrupt interval. When an Alarm Interrupt is generated, the ALM flag is set and an external interrupt
is generated based on the AIE bit and the pin configuration settings. The IM field controls the period of the external
interrupt, including both level and pulse configurations.
4.13.3. COUNTDOWN TIMER INTERRUPT TIRQ
The RV-1805-C3 may be configured to generate the TIRQ interrupt when the Countdown Timer is enabled by the
TE bit and reaches the value of zero, which will set the TIM flag. The TM, TRPT and TFS fields control the interrupt
timing (see TIMER REGISTERS, 18h - Countdown Timer Control), and the TIE bit and the pin configuration
settings control external interrupt generation.
4.13.4. WATCHDOG TIMER INTERRUPT WIRQ
The RV-1805-C3 may be configured to generate the WIRQ interrupt when the Watchdog Timer reaches its timeout
value. This sets the WDT flag and is described in section WATCHDOG TIMER.
4.13.5. BATTERY LOW INTERRUPT BLIRQ
The RV-1805-C3 may be configured to generate the BLIRQ when the voltage on the VBACKUP pin crosses one of the
thresholds set by the BREF field. The polarity of the detected crossing is set by the BPOL bit.
4.13.6. EXTERNAL INTERRUPT X2IRQ
The RV-1805-C3 may be configured to generate the X2IRQ interrupt when the WDI (X2IRQ) input toggles. The
register bit EX2P control whether the rising or falling transitions generate the respective interrupt. Changing EX2P
may cause an immediate interrupt, so the interrupt flag should be cleared after changing this bit.
The value of the WDI pin may be directly read in the WDIN register bit (see RAM REGISTERS, 3Fh - Extension
RAM Address). By connecting the input such as a pushbutton to WDI, software can debounce the switch input
using software configurable delays.
4.13.7. OSCILLATOR FAIL INTERRUPT OFIRQ
The RV-1805-C3 may be configured to generate the OFIRQ interrupt if the XT oscillator fails (see OSCILLATOR
FAILURE DETECTION).
4.13.8. AUTOCALIBRATION FAIL INTERRUPT ACIRQ
The RV-1805-C3 may be configured to generate the ACIRQ interrupt if an Autocalibration operation fails (see
AUTOCALIBRATION FAIL).
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Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.13.9. SERVICING INTERRUPTS
When an interrupt is detected, software must clear the interrupt flag in order to prepare for a subsequent interrupt.
If only a single interrupt is enabled, software may simply write a zero to the corresponding interrupt flag to clear the
interrupt. However, because all of the flags in the Status register are written at once, it is possible to clear an
interrupt which has not been detected yet if multiple interrupts are enabled. The ARST register bit is provided to
insure that interrupts are not lost in this case. If ARST is a 1, a read of the Status register will produce the current
state of all the interrupt flags and then clear them. An interrupt occurring at any time relative to this read is
guaranteed to either produce a 1 on the Status read, or to set the corresponding flag after the clear caused by the
Status read. After servicing all interrupts which produced 1s in the read, software should read the Status register
again until it returns all zeros in the flags, and service any interrupts with flags of 1.
Note that the OF and ACF interrupts are not handled with this process because they are in the Oscillator Status
register, but error interrupts are very rare and typically do not create any problems if the interrupts are cleared by
writing the flag directly.
4.14. POWER CONTROL AND SWITCHING
The main power supply to the RV-1805-C3 is the VDD pin, which operates over the range specified by the VDDIO
parameter if there are I/O interface operations required, and the range specified by the VDD parameter if only
timekeeping operations are required. The RV-1805-C3 also include a backup supply which is provided on the
VBACKUP pin and must be in the range specified by the VBACKUP parameter in order to supply battery power if VDD is
below VDDSWF. Refer to Table in Section POWER SUPPLY PARAMETERS for the specifications related to the
power supplies and switchover. There are several functions which are directly related to the VBACKUP input. If a
single power supply is used it must be connected to the VDD pin.
The following Figure illustrates the various power states and the transitions between them. There are three power
states:
1. POR – the power on reset state. If the RV-1805-C3 is in this state, all registers including the Counter
Registers are initialized to their reset values.
2. VDD Power – the RV-1805-C3 is powered from the VDD supply.
3. VBACKUP Power – the RV-1805-C3 is powered from the VBACKUP supply.
Initially, VDD is below the VDDST voltage, VBACKUP is below the VBACKUPSW voltage and the RV-1805-C3 is in the POR
state. VDD rising above the VDDST voltage causes the RV-1805-C3 to enter the VDD Power state. If VBACKUP remains
below VBACKUPSW , VDD falling below the VDDRST voltage returns the RV-1805-C3 to the POR state.
Power States:
VDD
V DDST
VBACKUP
Power State
V DDRST
V DDST
V DDSWF
V DDSWR
V DDSWF
V BACKUPSW
POR
VDD Power
V BACKUPRST
POR
VDD Power
VBACKUP Power
VDD Power
VBACKUP Power
POR
If VBACKUP rises above VBACKUPSW in the POR state, the RV-1805-C3 remains in the POR state. This allows the RV1805-C3 to be built into a module with a battery included, and minimal current will be drawn from the battery until
VDD is applied to the module the first time.
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Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
If the RV-1805-C3 is in the VDD Power state and VBACKUP rises above VBACKUPSW, the RV-1805-C3 remains in the
VDD Power state but automatic switchover becomes available. VBACKUP falling below VBACKUPSW has no effect on the
power state as long as VDD remains above VDDSWF. If VDD falls below the VDDSWF voltage while VBACKUP is above
VBACKUPSW the RV-1805-C3 switches to the VBACKUP Power state. VDD rising above VDDSWR returns the RV-1805C3 to the VDD Power state. There is hysteresis in the rising and falling VDD thresholds to insure that the RV-1805C3 does not switch back and forth between the supplies if VDD is near the thresholds. VDDSWF and VDDSWR are
independent of the VBACKUP voltage and allow the RV-1805-C3 to minimize the current drawn from the VBACKUP
supply by switching to VBACKUP only at the point where VDD is no longer able to power the device.
If the RV-1805-C3 is in the VBACKUP Power state and VBACKUP falls below VBACKUPRST, the RV-1805-C3 will return
to the POR state.
Whenever the RV-1805-C3 enters the VBACKUP Power state, the BAT flag (see CONFIGURATION REGISTERS,
2
0Fh - Status (Read Only)) is set and may be polled by software if the I C bus is driven by VBACKUP. If the XT
oscillator is selected and the AOS bit is set (see OSCILLATOR REGISTERS, 1Ch - Oscillator Control), the RV1805-C3 will automatically switch to the RC oscillator in the VBACKUP Power state in order to conserve battery
power (RC mode according to the ACAL field). If the IOBM bit is clear (see ANALOG CONTROL REGISTERS, 27h
2
– Batmode IO Register), the I C interface is disabled in the VBACKUP Power state in order to prevent erroneous
accesses to the RV-1805-C3 if the bus master loses power.
4.14.1. AUTOMATIC SWITCHOVER SUMMARY
Automatic Switchover:
AOS (FOS)
VDD Power state

VBACKUP Power state
AOS = 0 (and/or FOS = 0)
No automatic oscillator
switching occures
RC
RC Autocalibration
XT
XT Autocalibration
=
=
=
=
RC
RC Autocalibration
XT
XT Autocalibration
AOS = 1 (and/or FOS = 1)
Automatic switching to RC
oscillator (RC Mode
according to the ACAL
field)
RC
RC Autocalibration
XT
XT Autocalibration
=
=


RC
RC Autocalibration
RC
RC Autocalibration
4.14.2. BATTERY LOW FLAG AND INTERRUPT
If the VBACKUP voltage drops below the Falling Threshold selected by the BREF field (see ANALOG CONTROL
REGISTERS, 21h – BREF Control), the BL flag (see CONFIGURATION REGISTERS, 0Fh - Status (Read Only)) is
set. If the BLIE interrupt enable bit (see CONFIGURATION REGISTERS, 12h - Interrupt Mask) is set, the IRQ
interrupt is generated. This allows software to determine if a backup battery has been drained. Note that the BPOL
bit must be set to 0. The algorithm in the ANALOG COMPARATOR section should be used when configuring the
BREF value.
If the VBACKUP voltage is above the rising voltage which corresponds to the current BREF setting, BBOD will be set.
At that point the VBACKUP voltage must fall below the falling voltage in order to clear the BBOD bit, set the BAT flag
and generate a falling edge BL interrupt. If BBOD is clear, the VBACKUP voltage must rise above the rising voltage in
order to clear the BBOD bit and generate a rising edge BL interrupt.
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Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.14.3. ANALOG COMPARATOR
If a backup battery is not required, the VBACKUP pin may be used as an analog comparator input. The voltage
comparison level is set by the BREF field. If the BPOL bit is 0, the BL flag will be set when the VBACKUP voltage
crosses from above the BREF Falling Threshold to below it. If the BPOL bit is 1, the BL flag will be set when the
VBACKUP voltage crosses from below the BREF Rising Threshold to above it. The BBOD bit (see ANALOG
CONTROL REGISTERS, 2Fh – Analog Status Register (Read Only)) may be read to determine if the VBACKUP
voltage is currently above the BREF threshold (BBOD = 1) or below the threshold (BBOD = 0).
There is a reasonably large delay tBREF (on the order of seconds) between changing the BREF field and a valid
value of the BBOD bit. Therefore, the algorithm for using the Analog Comparator should comprise the following
steps:
1.
2.
3.
4.
Set the BREF and BPOL fields to the desired values.
Wait longer than the maximum tBREF time.
Clear the BL flag, which may have been erroneously set as BBOD settles.
Check the BBOD bit to insure that the VBACKUP pin is at a level for which an interrupt can occur. If a falling
interrupt is desired (BPOL = 0), BBOD should be 1. If a rising interrupt is desired (BPOL = 1), BBOD should
be 0.
If the comparison voltage on the VBACKUP pin can remain when VDD goes to 0, it is recommended that a Software
Reset be generated to the RV-1805-C3 after power up.
4.14.4. PIN CONTROL AND LEAKAGE MANAGEMENT (POWER CONTROL)
Like most ICs, the RV-1805-C3 may draw unnecessary leakage current if an input pin floats to a value near the
threshold or an output pin is pulled to a power supply. Because external devices may be powered from VDD, extra
care must be taken to insure that any input or output pins are handled correctly to avoid extraneous leakage when
VDD goes away and the RV-1805-C3 is powered from VBACKUP. The 30h – Output Control Register (see ANALOG
CONTROL REGISTERS), the 27h – Batmode IO Register (see ANALOG CONTROL REGISTERS) and the 3Fh Extension RAM Address register (see RAM REGISTERS) include bits to manage this leakage, which should be
used as follows:
1. EXBM is unused, but has to be 0 to avoid extraneous leakage. Disables an internal input when the RV1805-C3 is in the VBACKUP Power state.
2. WDBM should be cleared if the WDI pin is connected to a device which is powered down when the RV1805-C3 is in the VBACKUP Power state.
3. O4BM is unused, but must be set to 0 to avoid extraneous leakage. If 0, an internal output is completely
disconnected when the RV-1805-C3 is in the VBACKUP Power state.
2
4. IOBM should be cleared if the I C bus master is powered down when the RV-1805-C3 is in the VBACKUP
Power state.
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Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.14.5. POWER UP TIMING
When the voltage levels on both the VDD and VBACKUP signals drop below VDDRST, the RV-1805-C3 will enter the
POR state. Once VDD rises above VDDST, the RV-1805-C3 will enter the VDD Power state. The I/O access via the
2
I C interface will be disabled for a period of tVH:CLK. The CLK / INT pin will be low at power up, and will go high when
tVH:CLK expires. Software should poll the CLK / INT value to determine when the RV-1805-C3 may be accessed.
The following Figure illustrates the timing of a power down/up operation.
Power Up Timing:
No I/O Access
VDD
VBACKUP
CLK / INT
State
Oper
Power Down
PwrUp
Oper
t VH:CLK
4.15. RESET SUMMARY
The RV-1805-C3 controls the RST output in a variety of ways, as shown in the following Table. The assertion of
RST is a low signal if the RSP bit is 0, and the assertion is high if RSP is 1. RSP always powers up as a zero so
that on power RST is always asserted low.
Reset Summary:
Function
Power Up
Watchdog
Sleep
Enable
Always Enabled
WDS
SLRES
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Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.15.1. POWER UP RESET
When the RV-1805-C3 powers up (see POWER UP TIMING) CLK / INT and RST will be asserted low until I/O
accesses are enabled. At that point CLK / INT will go high, and RST will continue to be asserted for the delay
tVH:NRST, and will then be deasserted. The following Figure illustrates the reset timing on Power Up. Software should
sample the CLK / INT signal prior to accessing the RV-1805-C3.
Power Up Reset Timing:
No I/O Access
VDD
VBACKUP
CLK / INT
RST
State
Oper
Power Down
PwrUp
Delay
Oper
t VH:CLK
t VH:NRST
4.15.2. WATCHDOG TIMER
If the WDS bit is 1, expiration of the Watchdog Timer (see WATCHDOG TIMER) will cause RST to be asserted for
approximately 60 ms.
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Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.15.3. SLEEP
If the SLRES bit is set, RST will be asserted whenever the RV-1805-C3 is in Sleep Mode (see SLEEP
CONTROL). Once a trigger is received and the RV-1805-C3 exits Sleep Mode, RST will continue to be asserted
for the tVH:NRST delay. The following Figure illustrates the timing of this operation.
Sleep Reset Timing:
PSW
RST
State
Oper
Sleep
Delay
Oper
t VH:NRST
4.16. SOFTWARE RESET
Software may reset the RV-1805-C3 by writing the special value of 3Ch to the Configuration Key register at offset
1Fh. This will provide the equivalent of a power on reset by initializing all of the RV-1805-C3 registers. A software
reset will not cause the RST signal to be asserted.
4.17. SLEEP CONTROL STATE MACHINE
The RV-1805-C3 includes a sophisticated Sleep Control system that allows the RV-1805-C3 to manage power for
other chips in a system. The Sleep Control system provides two outputs which may be used for system power
control:
1. A reset (nRST) may be generated to put any host controller into a minimum power mode and to control
sequencing during power up and power down operations.
2. A power switch signal may be generated (PWR), which allows the RV-1805-C3 to completely power down
other chips in a system by allowing the PSW pin to float. The OUT2S field must be set to a value of 6 to
select the SLEEP output. When using the PWR output, PSW is configured as an open drain pin with
approximately 1 Ω resistance. This allows the RV-1805-C3 to directly switch power with no external
components for small systems, or to control a single external transistor for higher current switching. The
2
low resistance power switch is enabled by setting the PWR2 bit. If the I C master (i.e., the host controller)
is powered down by the power switch, the PWGT bit should be set to insure that a floating bus does not
corrupt the RV-1805-C3.
3. If OUT2S is 6 but the PWR2 bit is not set, PSW will be configured as a high true Sleep output which may
be used as an interrupt.
The Sleep State Machine (SM) in the Figure in Section SLEEP receives several inputs which it uses to determine
the current Sleep State:
1. POR – the indicator that power is valid, i.e. the RV-1805-C3 is in either the VDD Power state or the
VBACKUP Power state.
2. SLP - the Sleep Request signal which is generated by a software access to the Sleep Register.
3. TRIG - the OR of the enabled interrupt request from the Alarm comparison in the RTC, the interrupt signal
from the Countdown Timer in the RTC, the interrupt signal from the Watchdog Timer in the RTC, the
External Interrupt (WDI pin), the Battery Low detection interrupt, the Autocalibration Fail interrupt or the
Oscillator Fail interrupt.
4. TIM - the timeout signal from the Sleep Timeout counter, indicating that it has decremented to 0.
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Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.17.1. RUN
RUN is the normal operating state of the RV-1805-C3. PWR and nRST are not asserted, SLP is 0, and SLST holds
the state of the previous Sleep. SLST should be cleared by software before entering the SWAIT state.
4.17.2. SWAIT
Software can put the chip to sleep by setting the SLP bit, as long as a valid interrupt is enabled (see SLP
PROTECTION) indicated by VAL being asserted. If the SLTO field is between 1 and 7, the SM moves to the
SWAIT state and waits for between SLTO and (SLTO+1) ~8 ms periods. This allows software to perform additional
cleanup functions after setting SLP before the MCU is shut down. Operation is the same in SWAIT as it is in RUN,
and if an enabled operational interrupt occurs (TRIG) the SM returns to the RUN state and clears the SLP bit. PWR
and nRST are not asserted, SLP is 1, and SLST is 0.
If SLTO is set to 0, the SM moves immediately to the SLEEP state. If the MCU is configured to be powered down in
Sleep Mode, the I/O operation to write the Sleep Register must be the last instruction executed by the MCU.
4.17.3. SLEEP
Once the programmed number of periods has elapsed in the SWAIT state, the TIM signal is asserted and the
machine moves to the SLEEP state, putting the RV-1805-C3 into Sleep Mode. In this case the PWR signal is
removed, and nRST is asserted if SLRES is set. Once an enabled operational interrupt occurs (TRIG), the SM
returns to the RUN state, re-enables power and removes reset as appropriate. The SLST register bit in the Sleep
Register is set when the SLEEP state is entered, allowing software to determine if a SLEEP has occurred.
62/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
Sleep State Machine:
!POR
RUN
!SLP +
!VAL
nRST = 1
PWR = 0
SLST = (H)
SLP = 0
TRIG
SLP *
VAL *
SLTO = 0
SLP *
VAL *
SLTO > 0
SWAIT
!TIM *
!TRIG
nRST = 1
PWR = 0
SLST = 0
SLP = 1
TIM *
!TRIG
SLEEP
!TRIG
TRIG
nRST = !(slres)
PWR = 1
SLST = 1
SLP = 1
63/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.17.4. SLP PROTECTION
Since going into Sleep Mode may prevent an MCU from accessing the RV-1805-C3, it is critical to insure that the
RV-1805-C3 can receive a TRIG signal. To guarantee this, the SLP signal cannot be set unless the STOP bit is 0
and at least one of the following conditions exists:
1.
2.
3.
4.
The AIE bit is 1, enabling an Alarm interrupt.
The TIE and the TE bits are 1, enabling a Countdown Timer interrupt.
The EX2E bit is 1, enabling the External interrupt.
The BMB field is not zero and the WDS bit is zero, enabling a Watchdog Interrupt.
In addition, SLP cannot be set if there is an interrupt pending. Software should read the SLP bit after attempting to
set it. If SLP is not asserted, the attempt to set SLP was unsuccessful either because a correct trigger was not
enabled or because an interrupt was already pending. Once SLP is set, software should continue to poll it until the
Sleep actually occurs, in order to handle the case where a trigger occurs before the RV-1805-C3 enters Sleep
Mode.
4.17.5. OUT2S, OUTB AND LKO2
If the OUT2S field is set to the initial value of 7, the PSW pin will be driven with the value of the OUTB bit which is
initially zero. If this pin is used as the power switch, setting OUTB will remove power from the system and may
prevent further access to the RV-1805-C3. In order to insure that this does not happen inadvertently, the LKO2 bit
must be cleared in order to change the OUTB bit to a 1. Note that in this power switch environment the OUT2S
register field must not be written to any value other than 6 or 7, even if the PSW pin would remain at zero, because
it is possible that a short high pulse could be generated on the PSW pin which could create a power down.
4.17.6. PIN CONTROL AND LEAKAGE MANAGEMENT (SLEEP CONTROL)
Like most ICs, the RV-1805-C3 may draw unnecessary leakage current if an input pin floats to a value near the
threshold or an output pin is pulled to a power supply. Because Sleep Mode can power down external devices
connected to the RV-1805-C3, extra care must be taken to insure that any input or output pins are handled
correctly to avoid extraneous leakage. The Output Control register includes bits to manage this leakage, which
should be used as follows:
1. EXDS must be set to 1 to avoid extraneous leakage. Disables an internal input when the RV-1805-C3 is in
Sleep Mode.
2. WDDS should be set if the WDI pin is connected to a device which is powered down in Sleep Mode.
3. O1EN should be cleared if the CLK / INT pin is connected to a device which is powered down in Sleep
Mode.
4. O3EN is unused, but has to be 0 to avoid extraneous leakage. If 0, an internal output is completely
disconnected when the RV-1805-C3 is in Sleep Mode.
5. O4EN is unused, but has to be 0 to avoid extraneous leakage. If 0, an internal output is completely
disconnected when the RV-1805-C3 is in Sleep Mode.
6. RSEN should be cleared if the RST pin is connected to a device which is powered down in Sleep Mode.
2
The Oscillator Control register includes a bit to manage the I C interface:
2
7. The PWGT bit must be set to 1 to avoid extraneous leakage. If 1, the I C interface pins are disabled in
Sleep Mode. This is a particularly important function because there are multiple leakage paths in the I/O
interface.
64/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.18. SYSTEM POWER CONTROL APPLICATIONS
In addition to fundamentally low power RTC operation, the RV-1805-C3 includes the capability to effectively
manage the power of other devices in a system. It allows the creation of extremely power efficient systems with
minimal additional components. This configuration is typically used when the entire system is powered from a
battery.
4.18.1. VSS POWER SWITCHED
The following Figure illustrates the recommended implementation, in which the internal power switch of the RV1805-C3 is used to completely turn off the MCU and/or other system elements. In this case the PSW output is
configured to generate the SLEEP function, the PWR2 bit is asserted and the SLRES bit is set to 0. Under normal
circumstances, the PSW pin is pulled to VSS with approximately 1 Ω of resistance, so that the MCU receives full
power. The MCU initiates a SLP operation, and when the RV-1805-C3 enters the SLEEP state the PSW pin is
opened and power is completely removed from the MCU. This results in significant additional power savings
relative to the other alternatives because even very low power MCUs require more current in their lowest power
state than the RV-1805-C3.
The RV-1805-C3 normally powers up selecting the OUTB register bit to drive the PSW pin, and the default value of
the OUTB bit is zero. This insures that the power switch is enabled at power up. If the power switch function is
used, software should only change the PSW selection between OUTB (111b) and SLEEP (110b) to insure no
glitches occur in the power switching function.
Switched VSS Power Control:
VDD
RV-1805-C3
CLK / INT
VDD
I2C
IRQ
MCU
PSW
VSS
VSS
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Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
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4.18.2. VDD POWER SWITCHED
The following Figure illustrates the application in which an external transistor switch T is used to turn off power to
the MCU. The SLP function operates identically to the VSS switched case above, but this implementation allows
switching higher current and maintains a common ground. R can be on the order of megohms, so that negligible
current is drawn when the circuit is active and PSW is low.
Switched VDD Power Control:
T
R
VDD
VDD
2
IC
RV-1805-C3
IRQ
CLK / INT
MCU
PSW
VSS
VSS
4.18.3. RESET DRIVEN
The following Figure illustrates the application in which the RV-1805-C3 communicates with the system MCU using
the reset function. In this case the MCU sets the SLRES bit so that when the RV-1805-C3 enters the SLEEP state,
it brings RST low to reset the MCU, and initiates a SLP operation. When the trigger occurs, the RV-1805-C3
releases the MCU from reset, and may also generate an interrupt which the MCU can query to determine how reset
was exited. Since some MCUs use much less power when reset, this implementation can save system power.
Reset Driven Power Control:
VDD
RV-1805-C3
RST
VSS
VDD
I2C
MCU
RESET
VSS
One potential issue with this approach is that many MCUs include internal pull-up resistors on their reset inputs,
and the current drawn through that resistor when the reset input is held low is generally much higher than the MCU
would draw in its inactive state. Any pull-up resistor should be disabled and the RST output of the RV-1805-C3
should be configured as a push-pull output.
66/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.18.4. INTERRUPT DRIVEN
The following Figure illustrates the simplest application, in which the RV-1805-C3 communicates with the system
MCU using an interrupt. The MCU can go into standby mode, reducing power somewhat, until the RV-1805-C3
generates an interrupt based on an alarm or a timer function. This produces smaller power savings than other
alternatives, but
allows the MCU to wake in the shortest time.
Interrupt Driven Power Control:
VDD
VDD
I2C
RV-1805-C3
MCU
IRQ
CLK / INT
VSS
VSS
4.19. TYPICAL SYSTEM IMPLEMENTATION
The following Figure is a more detailed view of a typical system using the VSS Power Switched approach. The VSS
pin of the MCU, and potentially other system components, is switched using the PSW pin of the RV-1805-C3. The
CLK / INT pin of the RV-1805-C3 is connected to an interrupt input of the MCU, allowing the MCU to utilize the
RTC interrupt functions of the RV-1805-C3 when it is awake. The RST output of the RV-1805-C3 is connected to
the reset input of the MCU, enabling the RV-1805-C3 to control power on reset and integrate an external MCU
2
reset button RESET. The MCU controls the RV-1805-C3 over the I C I/O channel.
System Example:
VDD
RV-1805-C3
WDI
RST
CLK / INT
VSS
VDD
I2C
MCU
RST
INT
PSW
VSS
RESET or
WAKE
The key value of the RV-1805-C3 in this type of system is the ability to put the MCU into an off state, and providing
a very rich variety of triggers which can cause the RV-1805-C3 to wake the MCU from the off state. There are a
number of different triggers which may be useful.
67/95
Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
RV-1805-C3
4.19.1. ALARMS
The system may require the MCU to wake up at particular times, which is accomplished by configuring the Alarm
Interrupt function of the RV-1805-C3.
4.19.2. COUNTDOWN TIMER
The system may require the MCU to wake up at periodic intervals which do not necessarily correspond to specific
calendar times. The Countdown Timer of the RV-1805-C3 provides highly flexible time interval configuration to
support this function.
4.19.3. WAKE BUTTON/SWITCH
A very common requirement is the capability to wake the system with a manual input such as a pushbutton or
switch, typified by the WAKE button in the System Example above. The external interrupt input WDI may be simply
connected to the button. The WDI input includes a Schmitt trigger circuitry to enable clean interrupts. If additional
debouncing of the input is required, the RV-1805-C3 provides direct access to the interrupt input pin to facilitate
software implementations.
4.19.4. EXTERNAL DEVICE INPUT
In some systems an external device such as a wakeup radio may provide a signal which must wake the MCU. The
RV-1805-C3 external interrupt WDI pin provides this capability.
4.19.5. ANALOG INPUT
Some systems include analog signals, such as light sensors or detectors on radio antennas, which must wake the
MCU. The Analog Comparator function, which allows the voltage on the VBACKUP input of the RV-1805-C3 to be
compared with a configurable voltage threshold and generate an interrupt, can easily be used in this application,
and it allows flexible configuration, both in voltage levels and in transition direction to support different
environments. The Analog Comparator may also be used to provide a second external digital interrupt if necessary
by selecting the proper digital threshold.
4.19.6. BATTERY LOW DETECTION
The Analog Comparator can provide a battery low detection function. In this case the VDD pin would be tied to the
VBACKUP pin, and the thresholds would be adjusted to insure that the Battery Low interrupt occurs prior to any
Brownout Detection on the VDD input. This allows software to prepare for a potential battery failure in advance
without having to poll the battery level.
4.19.7. ERRORS
Any failure interrupt in the RV-1805-C3 may also be configured to wake the MCU. This can be particularly valuable
for an Oscillator Failure detection, when software may need to respond to the error in order to report the problem
quickly.
68/95
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4.20. SAVING PARAMETERS
If the MCU is powered down in Sleep Mode, there is often some data which must be preserved until the next power
up. The internal RAM of the RV-1805-C3 is always available, so software can easily save any necessary
parameters prior to entering Sleep Mode and retrieve them when the MCU wakes up.
4.21. POWER SWITCH ELECTRICAL CHARACTERISTICS
The power switch on the RV-1805-C3 PSW pin has a typical on resistance of 1 ohm over the full temperature
range so that currents up to 50 mA may be handled without appreciable voltage drop. This allows the RV-1805-C3
to switch power to multiple devices in most systems, which can be particularly important for components without
internal Sleep functions. If the PSW pin is not used as a power switch, the maximum leakage current of the ~1 Ω
switch is less than 250 pA at 25 °C.
4.22. AVOIDING UNEXPECTED LEAKAGE PATHS
One potential problem which can occur when the RV-1805-C3 powers other devices down is that unexpected
leakage paths can be created between the powered RV-1805-C3 and the unpowered device. The RV-1805-C3 can
be configured to disable inputs and outputs in Sleep Mode to prevent leakage. In general, any input or output pin
connected to a device which is powered down should be disabled. Any pins which remain powered in Sleep Mode,
such as pushbutton inputs used to wake the system, must not be disabled.
See chapter 4.17.6 PIN CONTROL AND LEAKAGE MANAGEMENT (SLEEP CONTROL)
4.23. SYSTEM POWER ANALYSIS
The RV-1805-C3 can significantly improve the power characteristics of many different types of systems. A specific
example will be presented, and several other generalizations can be made from this. The fundamental advantage
provided by the RV-1805-C3 is that it allows the system designer to essentially ignore the sleep current of other
system components, which allows the utilization of components which have be optimized for other parameters,
such as active power, cost or functionality.
4.23.1. USING AN EXTERNAL RTC WITH POWER MANAGEMENT
The key element in any system power analysis is the usage profile, and for this example we assume the system is
active for Tact and inactive for Tinact. Iact is the current drawn when the system is active, and Iinact is the current drawn
when the system is inactive. The average current Iavg is therefore:
Iavg = (Tact * Iact + Tinact * Iinact )/(Tact + Tinact)
An example will use a PIC16LF1947 MCU, which is highly optimized for low power operation. This MCU draws 80
nA in Sleep Mode, 1.8 uA in Sleep Mode with the internal oscillator and RTC active, and 120 uA in 500 KHz active
mode. Assume a usage profile where the system in active for 1 second every 30 minutes, so that Tact is 1 and Tinact
is 1799. If this MCU is used alone and supplies the RTC functions, the average current for the usage profile is:
Iavg = (1 * 120 uA + 1799* 1.8 uA)/1800 = 1.865 uA
If the RV-1805-C3 is used to provide the RTC functionality in Autocalibrated RC Mode (<20 nA continuous current)
and the PIC is placed into Sleep Mode, the average current for the usage profile is dramatically lower:
Iavg = (1 * 120 uA + 1799* 80 nA)/1800 + 20 nA = 166 nA
This is a significant improvement, but the current can be further reduced by having the RV-1805-C3 switch power
to the MCU. The resulting average current is ~50% lower:
Iavg = (1 * 120 uA + 1799* 0 nA)/1800 + 20 nA = 86 nA
69/95
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4.23.2. MANAGING MCU ACTIVE POWER
In many cases, the duration of the active time is a function of how much processing must be accomplished, and
can therefore be assumed to be a linear function of the MCU clock frequency in active mode. The examples in the
previous section assumed that the MCU ran for 1 second at 500 KHz, so 500’000 cycles of an 8-bit processor were
required. Like most MCUs, the PIC has a relatively constant active current as a function of clock frequency, so
using a higher internal frequency in the same MCU would have little effect on the overall power. However, there
may be other MCUs (such as those with 32-bit processors) which have better active power efficiency but poor
sleep power, and power switching with the RV-1805-C3 eliminates any sleep power considerations.
4.23.3. LOWER COST MCUs
Lower cost MCUs often have poor sleep power characteristics relative to sleep optimized parts. Since the RV1805-C3 eliminates sleep power considerations, these lower cost processors may provide equivalent overall
average power at significant cost savings.
4.23.4. HIGH PERFORMANCE PROCESSORS
In some applications very high performance processors such as DSPs must be used due to real time processing
requirements. These processors are generally not optimized for sleep performance, but they may be used in
applications with low duty cycles. One example of this is fingerprint recognition, which is rarely accessed but must
provide very fast response with complex processing. The RV-1805-C3 power management functions enable a
system design where the processor is powered down the vast majority of the time, providing low average power
combined with very high instantaneous performance.
4.24. TRICKLE CHARGER
The devices supporting the VBACKUP pin include a trickle charging circuit which allows a battery or supercapacitor
connected to the VBACKUP pin to be charged from the power supply connected to the VDD pin. The circuit of the
Trickle Charger is shown in the following Figure. The Trickle Charger configuration is controlled by the 20h - Trickle
register (see ANALOG CONTROL REGISTERS). The Trickle Charger is enabled if a) the TCS field is 1010, b) the
DIODE field is 01 or 10 and c) the ROUT field is not 00. A diode, with a typical voltage drop of 0.6V, is inserted in
the charging path if DIODE is 10. A Schottky diode, with a typical voltage drop of 0.3V, is inserted in the charging
path if DIODE is 01. The series current limiting resistor is selected by the ROUT field as shown in the figure.
Trickle Charger:
Enable
DIODE
ROUT
3k
6k
11 k
70/95
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5. DIGITAL ARCHITECTURE SUMMARY
The following Figure illustrates the overall architecture of the pin inputs and outputs of the RV-1805-C3.
Digital Architecture Summary:
CDT
TIRQ
OUT
analog
VBACKUP
WDI
Calendar
Counters
SQW
Mux
Alarms
AIRQ
Analog
Compare BL
OF
ACF
SQW
IRQ
OUT1
Mux
CLK / INT
OUT2
Mux
PSW
IRQ
OR +
Msk
WDT
OUTB
Sleep
Control
Power
On
Brown
Out
RST
OR +
Msk
RST
71/95
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6. ELECTRICAL SPECIFICATIONS
6.1. ABSOLUTE MAXIMUM RATINGS
The following Table lists the absolute maximum ratings.
Absolute Maximum Ratings:
SYMBOL
PARAMETER
VDD
VBACKUP
VI
VI
VO
VO
II
IO
IOPC
IOPP
Power Supply Voltage
Backup Supply Voltage
Input voltage
Input voltage
Output voltage
Output voltage
Input current
Output current
PSW Output continuous current
PSW Output pulsed current
VESD
ESD Voltage
ILU
TSTG
TOP
TSLD
Latch-up Current
Storage Temperature
Operating Temperature
Lead temperature
TREF
Reflow soldering temperature
(1) CDM
(2) HBM
TEST
MIN
TYP
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-10
-20
VDD Power state
VBACKUP Power state
VDD Power state
VBACKUP Power state
1 second pulse
CDM(1)
HBM(2)
-55
-40
Hand soldering for 10 seconds
Reflow profile per JEDEC JSTD-020D
MAX
UNIT
3.8
3.8
VDD+ 0.3
VBACK+ 0.3
VDD+ 0.3
VBACK+ 0.3
10
20
50
150
±500
±4000
100
125
85
300
V
V
V
V
V
V
mA
mA
mA
mA
V
V
mA
°C
°C
°C
260
°C
– Charged-Device Model
– Human Body Model
6.2. POWER SUPPLY PARAMETERS
The following Figure and Table describe the power supply and switchover parameters. See POWER CONTROL
AND SWITCHING for a detailed description of the operations.
Power Supply Switchover:
VDD
V DDST
VBACKUP
Power State
V DDRST
V DDST
V DDSWF
V DDSWR
V DDSWF
V BACKUPSW
POR
VDD Power
V BACKUPRST
POR
VDD Power
VBACKUP Power
VDD Power
VBACKUP Power
POR
72/95
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For all tables, TA = -40 °C to 85 °C, TYP values at 25 °C.
Power Supply and Switchover Parameters:
SYMBOL
PARAMETER
PWR
TYPE
POWER STATE
TEST
CONDITIONS
Clocks operating
and RAM and
registers retained
I2C operation
MIN
MAX
UNIT
1.5
3.6
V
1.5
3.6
VDD
System Power Voltage
VDD
Static
VDD Power
VDDIO
VDD I/O Interface Voltage
VDD
Static
VDD
Rising
VDD Power
POR -> VDD
Power
VDD
Falling
VDD
Rising
VDD
Falling
VDD
Hyst.
VDD
Falling
VDD Power ->
VBACKUP Power
VDD < VDDSW,MAX
0.7
VBACKUP
Static
VBACKUP Power
Clocks operating
and RAM and
registers retained
1.4
Voltage(1)
VDDST
VDD Start-up
VDDRST
VDD Reset Voltage
VDDSWR
VDDSWF
VDDSWH
VDDFS
VBACKUP
VDD Rising Switch-over
Threshold Voltage
VDD Falling Switch- over
Threshold Voltage
VDD Switchover
Threshold Hysteresis(2)
VDD Falling Slew Rate to
switch to VBACKUP
state(4)
Backup Voltage
VDD Power ->
POR
VBACKUP Power
-> VDD Power
VDD Power ->
VBACKUP Power
VDD Power <->
VBACKUP Power
TYP
1.6
V
V
VBACKUP <
VBACKUP,MIN or no
VBACKUP
1.3
1.5
V
VBACKUP ≥ VBACKRST
1.6
1.7
V
VBACKUP ≥
VBACKSW,MIN
1.2
1.5
V
70
mV
1.4
V/ms
3.6
V
Backup Switchover VoltVDD Power ->
VBACKUP
Static
1.6
3.6
V
VBACKUP Power
age Range(5)
Falling Backup POR
VBACKUP Power
VBACKRST
VBACKUP
Falling
VDD < VDDSWF
1.1
1.4
V
-> POR
Voltage(7)
VBACK Margin above
VBMRG
VBACKUP
Static
VBACKUP Power
200
mV
VDD(3)
VBACK supply series
VBACKESR
VBACKUP
Static
VBACKUP Power
1.0
1.5
kΩ
resistance(6)
(1) V must be above V
DD
DDST to exit the POR state, independent of the VBACKUP voltage.
(2) Difference between V
DDSWR and VDDSWF.
(3) V
BACKUP must be higher than VDD by at least this voltage to insure the RV-1805-C3 remains in the VBACKUP Power state.
(4) Maximum V falling slew rate to guarantee correct switchover to VBACKUP Power state. There is no V falling slew rate
DD
DD
requirement if switching to the VBACKUP power source is not required.
(5) V
BACKUP voltage to guarantee correct transition to VBACKUP Power state when VDD falls.
(6) Total series resistance of the power source attached to the V
BACKUP pin. The optimal value is 1.5kΩ, which may require an external resistor.
VBACKUP power source ESR (Equivalent Series Resistance) + external resistor value = 1.5kΩ.
(7) V
BACKRST is also the static voltage required on VBACKUP for register data retention.
VBACKSW
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6.3. OPERATING PARAMETERS
The following Table lists the operating parameters. For this table, TA = -40 °C to 85 °C, TYP values at 25 °C.
Operating Parameters:
SYMBOL
TEST
CONDITIONS
PARAMETER
VT+
Positive-going Input Threshold Voltage
VT-
Negative-going Input Threshold Voltage
IILEAK
CI
Input leakage current
Input capacitance
RDSON
PSW output resistance to
VDD
IOLEAK
Output leakage current
VDD
3.0V
1.8V
3.0V
1.8V
3.0V
PSW Enabled
MIN
0.8
0.5
1.7V
1.8V
3.0V
3.6V
TYP
MAX
UNIT
1.5
1.1
0.9
0.6
0.02
3
1.7
1.6
1.1
1.05
0.02
2.0
1.25
V
V
80
5.8
5.4
3.8
3.7
80
nA
pF
Ω
nA
6.4. OSCILLATOR PARAMETERS
The following Table lists the oscillator parameters. For this Table, TA = -40 °C to 85 °C unless otherwise indicated.
VDD = 1.7 to 3.6V, TYP values at 25 °C and 3.0V. See also XT FREQUENCY CHARACTERISTICS.
Oscillator Parameters:
SYMBOL
FXT
FOF
FRCC
FRCU
PARAMETER
Crystal Frequency
XT Oscillator failure detection
frequency
Calibrated RC Oscillator
Frequency(1)
Uncalibrated RC Oscillator
Frequency
Uncalibrated RC Oscillator
cycle-to-cycle jitter, |Median|
JRCCC
RC Oscillator cycle-to-cycle
jitter, MIN, MAX
AXT
XT mode digital calibration
accuracy(1)
AAC
Autocalibration mode timing
accuracy, 512 second period,
TA = -10°C to 60°C(1)
TEST CONDITIONS
Factory Calibrated at 25°C,
VDD = 2.8V
Calibration Disabled
(OFFSETR = 0) – 128 Hz level
Calibration Disabled
(OFFSETR = 0) – 128 Hz level
Calibration Disabled
(OFFSETR = 0) – 1 Hz level
128 Hz level at 25°C
128 Hz level, -10°C to 70°C
128 Hz level, -40°C to 85°C
Calibrated at an initial
temperature and voltage.
Factory Calibrated at 25°C,
VDD = 3.0V
24 hour run time
1 week run time
1 month run time
1 year run time
MIN
89
TYP
MAX
UNIT
32.768
kHz
8
kHz
64
Hz
122
220
Hz
2000
ppm
500
1
3.5
10
1
3.5
10
%
-2
2
ppm
35
20
10
3
ppm
Autocalibration mode operating
-10
60
°C
temperature(2)
(1) Timing accuracy is specified at 25°C after digital calibration of the internal RC oscillator and digital calibration of the 32.768 kHz crystal.
The 32.768 kHz tuning fork crystal has a negative temperature coefficient with a parabolic frequency deviation, which can result in a
change of up to 150 ppm across the entire operating temperature range of -40°C to 85°C in XT mode. Autocalibration mode timing
accuracy is specified relative to XT mode timing accuracy from -10°C to 60°C.
(2) Outside of this temperature range, the RC oscillator frequency change due to temperature may be outside of the allowable RC digital
calibration range (+/-12%) for autocalibration mode. When this happens, an autocalibration failure will occur and the ACF interrupt flag is
set. The RV-1805-C3 should be switched to use the XT oscillator as its clock source when this occurs.
Please see the AUTOCALIBRATION FAIL section for more details.
TAC
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The following Figure shows the typical calibrated RC oscillator frequency variation vs. temperature. The RC
oscillator is factory calibrated at 2.8V, 25°C (OFFSETR = Preconfigured reset value).
Factory Calibrated RC Oscillator, Typical Frequency Variation vs. Temperature (64 Hz level is modified):
75
72.5
RC Frequency (Hz)
70
67.5
VDD = 1.8V
65
Autocalibration
mode operating
temperature
(-10 to 60°C)
VDD = 3.0V
62.5
60
-40
-30
-20
57.5
-10
0
10
20
30
40
Temperature (°C)
50
60
70
80
The following Figure shows the typical uncalibrated RC oscillator frequency variation vs. temperature.
Uncalibrated RC Oscillator at 64 Hz level, Typical Frequency Variation vs. Temperature:
72.5
RC Frequency (Hz)
70
67.5
65
VDD = 1.8V
62.5
60
-40
-30
-20
57.5
-10
0
Autocalibration
mode operating
temperature
(-10 to 60°C)
VDD = 3.0V
10
20
30
40
Temperature (°C)
50
60
70
80
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6.5. XT FREQUENCY CHARACTERISTICS
For this Table, TA = -40 °C to 85 °C unless otherwise indicated. VDD = 1.7 to 3.6V, TYP values at 25 °C and 3.0V,
fOSC= 32.768 kHz.
XT Frequency Characteristics:
SYMBOL
PARAMETER
CONDITIONS
TA = +25°C,
Calibration Disabled
(OFFSETX = 0)
ΔF/F
Frequency accuracy
ΔF/FO
Frequency vs. temperature
characteristics
Turnover temperature
Aging first year max.
Oscillator start-up voltage
Oscillator start-up time
T0
ΔF/F
VSTART
TSTART
MIN
TOPR = -40°C to +85°C
TA = +25°C
TA = -40 °C to 85 °C
VDD = 1.7V–3.6V
FCLKOUT = 32.768 kHz
δCLKOUT
CLKOUT duty cycle
TA = +25°C
(1) The XT mode digital calibration accuracy is +/-2 ppm, see OSCILLATOR PARAMETERS.
TYP
MAX
UNIT
±100 (1)
ppm
-0.035ppm/°C2 (TOPR-T0)2 ±10%
ppm
+25 ±5
±3
1.0
°C
ppm
V
s
60 ±10
%
1.6
6.5.1.XT FREQUENCY VS. TEMPERATURE CHARACTERISTICS
20.0
T0 = 25°C (±5°C)
0.0
-20.0
ΔF/F [ppm]
-40.0
-60.0
-0.035 * (T-T0)2 ppm (±10%)
-80.0
-100.0
-120.0
-140.0
-160.0
-180.0
-60
-40
-20
0
20
40
60
80
100
T [°C]
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6.6. VDD SUPPLY CURRENT
The following Table lists the current supplied into the VDD power input under various conditions. For this table, TA =
-40 °C to 85 °C, VBACKUP = 0 V to 3.6 V, TYP values at 25 °C, VDD Power state.
VDD Supply Current:
SYMBOL
PARAMETER
TEST CONDITIONS
2
VDD
IVDD:I2C
VDD supply current during I C
burst read/write
400kHz bus speed, 2.2k pull-up
resistors on SCL/SDA(1)
IVDD:XT
VDD supply current in XT oscillator
mode.
IVDD:RC
VDD supply current in RC oscillator
mode.
IVDD:ACAL
Average VDD supply current in
Autocalibrated RC oscillator
mode.
Time keeping mode with XT
oscillator running(2)
Time keeping mode with only the
RC oscillator running (XT
oscillator is off)(2)
Time keeping mode with only RC
oscillator running and
Autocalibration enabled. ACP =
512 seconds(2)
Time keeping mode with XT
oscillator running, 32.768 kHz
IVDD:CK32
IVDD:CK64
Additional VDD supply current with
CLK / INT at 32.768 kHz.
Additional VDD supply current with
square wave on CLK / INT (3)
All time keeping modes, 64 Hz
CLK / INT at 64 Hz.
square wave on CLK / INT (3)
TYP
MAX
3.0V
1.8V
3.0V
1.8V
3.0V
MIN
6
1.5
60
57
17
10
3
330
290
220
1.8V
14
170
3.0V
22
235
1.8V
18
190
3.0V
0.71
1.8V
0.34
3.0V
1.8V
0.6
0.3
UNIT
µA
nA
nA
nA
µA
nA
(1)
Excluding external peripherals and pull-up resistor current. All other inputs (besides SDA and SCL) are at 0V or VDD.
Test conditions: Continuous burst read/write, 55h data pattern, 25 µs between each data byte, 20 pF load on each bus pin.
(2) All inputs and outputs are at 0V or V .
DD
(3)
All inputs and outputs except CLK / INT are at 0V or VDD. 15pF load on CLK / INT , pull-up resistor current not included.
The following Figure shows the typical VDD power state operating current vs. temperature in XT mode.
Typical VDD Current vs. Temperature in XT Mode:
VDD Power State, XT Mode Current (nA)
130
120
110
100
90
80
VDD = 3.0V
70
60
VDD = 1.8V
50
40
-40
-30
-20
-10
0
10
20
30
40
Temperature (°C)
50
60
70
80
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The following Figure shows the typical VDD power state operating current vs. temperature in RC mode.
Typical VDD Current vs. Temperature in RC Mode:
VDD Power State, RC Mode Current (nA)
75
65
55
45
35
VDD = 3.0V
25
VDD = 1.8V
15
5
-40
-30
-20
-10
10
20
30
40
Temperature (°C)
0
50
60
70
80
The following Figure shows the typical VDD power state operating current vs. temperature in RC Autocalibration
mode.
Typical VDD Current vs. Temperature in RC Autocalibration Mode, ACP = 512 sec.:
VDD Power State, Autocal Mode Current (nA)
55
50
45
40
35
30
VDD = 3.0V
25
20
VDD = 1.8V
15
10
5
-40
-30
-20
-10
0
10
20
30
40
50
60
70
Temperature (°C)
78/95
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The following Figure shows the typical VDD power state operating current vs. voltage for XT Oscillator and RC
Oscillator modes and the average current in RC Autocalibrated mode with ACP = 512 seconds.
Typical VDD Current vs. Voltage, Different Modes of Operation:
70
TA = 25 °C
VDD Power State Current (nA)
60
XT Oscillator Mode
50
40
30
RC Autocalibration Mode, ACP = 512 sec.
20
10
RC Oscillator Mode
0
1.5
2
3
2.5
3.5
VDD Voltage (V)
2
The following Figure shows the typical VDD power state operating current during continuous I C burst read and
write activity. Test conditions: TA = 25 °C, 55h data pattern, 25 µs between each data byte, 20 pF load on each bus
pin, pull-up resistor current not included.
2
Typical VDD Current vs. Voltage, I C Burst Read/Write:
9
TA = 25°C
8
VDD Current (µA)
7
6
5
4
I2C Burst Read/Write
3
2
1
0
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VDD Voltage (V)
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The following Figure shows the typical additional VDD power state operating current with a 32.768 kHz clock output
on the CLK / INT pin. Test conditions: TA = 25 °C. All inputs and outputs except CLK / INT are at 0 V or VDD. 15 pF
capacitive load on the CLK / INT pin, pull-up resistor current not included.
Typical additional VDD Current vs. Voltage, 32.768 kHz Clock Output:
1.0
TA = 25°C
VDD Current (µA)
0.8
0.6
0.4
0.2
0
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VDD Voltage (V)
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6.7. VBACKUP SUPPLY CURRENT
The following Table lists the current supplied into the VBACKUP power input under various conditions. For this table,
TA = -40 °C to 85 °C, TYP values at 25 °C, MAX values at 85 °C, VBACKUP Power state.
VBACKUP Supply Current:
SYMBOL
PARAMETER
TEST CONDITIONS
IVBACK:XT
VBACKUP supply current in XT
oscillator mode.
IVBACK:RC
VBACKUP supply current in RC
oscillator mode.
IVBACK:ACAL
VBACKUP supply current in
Autocalibrated RC oscillator
mode.
IVBACK:VDD
VBACKUP supply current in VDD
powered mode.
(1)
VDD
Time keeping mode with XT
oscillator running(1)
Time keeping mode with only
the RC oscillator running (XT
oscillator is off) (1)
Time keeping mode with the
RC oscillator running and
Autocalibration enabled.
ACP = 512 seconds(1)
VBACK
< VDDSWF
< VDDSWF
< VDDSWF
VDD powered mode(1)
TYP
MAX
3.0V
1.8V
3.0V
63
60
19
330
290
220
1.8V
16
170
3.0V
25
235
1.8V
21
190
0.6
0.5
20
16
3.0V
1.8V
1.7-3.6 V
MIN
-5
-10
UNIT
nA
nA
nA
nA
Test conditions: All inputs and outputs are at 0V or VDD.
The following Figure shows the typical VBACKUP power state operating current vs. temperature in XT mode.
Typical VBACKUP Current vs. Temperature in XT Mode:
VBACKUP Power State, XT Mode Current (nA)
130
120
110
100
90
80
VBACKUP = 3.0V
70
60
VBACKUP = 1.8V
50
40
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature (°C)
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The following Figure shows the typical VBACKUP power state operating current vs. temperature in RC mode.
Typical VBACKUP Current vs. Temperature in RC Mode:
VBACKUP Power State, RC Mode Current (nA)
75
65
55
45
35
VBACKUP = 3.0V
25
VBACKUP = 1.8V
15
5
-40
-30
-20
-10
10
0
20
30
40
50
60
70
80
Temperature (°C)
The following Figure shows the typical VBACKUP power state operating current vs. temperature in RC
Autocalibration mode.
VBACKUP Power State, Autocal Mode Current (nA)
Typical VBACKUP Current vs. Temperature in RC Autocalibration Mode, ACP = 512 sec.:
-40
55
50
45
40
35
30
VBACKUP = 3.0V
25
20
VBACKUP = 1.8V
15
10
5
-30
-20
-10
0
10
20
30
40
50
60
70
Temperature (°C)
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The following Figure shows the typical VBACKUP power state operating current vs. voltage for XT Oscillator and
RC Oscillator modes and the average current in RC Autocalibrated mode with ACP = 512 seconds., VDD = 0 V.
Typical VBACKUP Current vs. Voltage, Different Modes of Operation:
70
TA = 25°C
60
VBACKUP Current (nA)
XT Oscillator Mode
50
40
30
RC Autocalibration Mode, ACP = 512 sec.
20
10
RC Oscillator Mode
0
1.5
2
2.5
3
3.5
VBACKUP Voltage (V)
The following Figure shows the typical VBACKUP current when operating in the VDD power state, VDD = 1.7 V.
Typical VBACKUP Current vs. Voltage in VDD Power State:
0.9
TA = 25°C, VDD = 1.7V
0.8
VBACKUP Current (nA)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.5
2
2.5
VBACKUP Voltage (V)
3
3.5
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6.8. BREF ELECTRICAL CHARACTERISTICS
The following Table lists the parameters of the VBACKUP voltage thresholds. BREF values other than those listed in
the table are not supported. For this table, TA = -20 °C to 70 °C, TYP values at 25 °C, VDD = 1.7 to 3.6V.
BREF Parameters:
SYMBOL
VBRF
PARAMETER
VBACKUP falling threshold
VBRR
VBACKUP rising threshold
VBRH
VBACKUP threshold hysteresis
TBR
VBACKUP analog comparator
recommended operating
temperature range
BREF
MIN
TYP
MAX
0111
1011
1101
1111
0111
1011
1101
1111
0111
1011
1101
1111
2.3
1.9
1.6
2.5
2.1
1.8
1.4
3.0
2.5
2.2
1.6
0.5
0.4
0.4
0.2
3.3
2.8
2.5
All values
-20
2.6
2.1
1.9
3.4
2.9
2.7
UNIT
V
V
V
70
°C
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6.9. I2C AC ELECTRICAL CHARACTERISTICS
2
The following Figure and Table describe the I C AC electrical parameters.
2
I C AC Parameter Definitions:
SDA
t BUF
t LOW
t HD:DAT
t SU:DAT
SCL
t HIGH
t HD:STA
t FALL
t RISE
t SU:STO
t SU:STA
SDA
For the following Table, TA = -40 °C to 85 °C, TYP values at 25 °C.
2
I C AC Electrical Parameters:
SYMBOL
fSCL
tLOW
tHIGH
tRISE
tFALL
tHD:STA
tSU:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
PARAMETER
SCL input clock frequency
Low period of SCL clock
High period of SCL clock
Rise time of SDA and SCL
Fall time of SDA and SCL
START condition hold time
START condition setup time
SDA setup time
SDA hold time
STOP condition setup time
Bus free time before a new transmission
VDD
MIN
1.7V-3.6V
1.7V-3.6V
1.7V-3.6V
1.7V-3.6V
1.7V-3.6V
1.7V-3.6V
1.7V-3.6V
1.7V-3.6V
1.7V-3.6V
1.7V-3.6V
1.7V-3.6V
10
1.3
600
TYP
MAX
UNIT
400
kHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
300
300
600
600
100
0
600
1.3
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6.10. POWER ON AC ELECTRICAL CHARACTERISTICS
The following Figure and Table describe the power on AC electrical characteristics for the CLK / INT pin and XT
oscillator.
Power On AC Electrical Characteristics:
VDD
CLK / INT
t LOW:VDD
VDDRST
VDDST
t VH:CLK
t VL:CLK
t XTST
XT
For the following Table, TA = -40 °C to 85 °C, VBACKUP < 1.2 V
Power On AC Electrical Parameters:
SYMBOL
PARAMETER
VDD
tLOW:VDD
Low period of VDD to insure a valid POR
1.7V-3.6V
tVL:CLK
VDD low to CLK / INT low
1.7V-3.6V
tVH:CLK
VDD high to CLK / INT high
1.7V-3.6V
tXTST
CLK / INT high to XT oscillator start
1.7V-3.6V
TA
85 °C
25 °C
-20 °C
-40 °C
85 °C
25 °C
-20 °C
-40 °C
85 °C
25 °C
-20 °C
-40 °C
85 °C
25 °C
-20 °C
-40 °C
MIN
TYP
0.1
0.1
1.5
10
0.1
0.1
1.5
10
0.4
0.5
3
20
0.4
0.4
0.5
1.5
MAX
UNIT
s
s
s
s
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6.11. RST AC ELECTRICAL CHARACTERISTICS
The following Figure and Table describe the RST AC electrical characteristics.
RST AC Parameter Characteristics:
t LOW:VDD
VDD
RST
VDDRST
VDDST
t VH:NRST
t VL:NRST
For the following Table, TA = -40 °C to 85 °C, VBACKUP < 1.2 V.
RST AC Electrical Parameters:
SYMBOL
PARAMETER
VDD
tLOW:VDD
Low period of VDD to insure a valid POR
1.7V-3.6V
tVL:NRST
VDD low to RST low
1.7V-3.6V
tVH:NRST
VDD high to RST high
1.7V-3.6V
TA
85°C
25°C
-20°C
-40°C
85°C
25°C
-20°C
-40°C
85°C
25°C
-20°C
-40°C
MIN
TYP
0.1
0.1
1.5
10
0.1
0.1
1.5
10
0.5
0.5
3.5
25
MAX
UNIT
s
s
s
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7. APPLICATION INFORMATION
7.1. OPERATING RV-1805-C3
10nF
1
2
VDD
WDI
RV-1805-C3
VBACKUP
SDA
SDA
SCL
SCL
RST
RESET
PSW
47pF
VDD
MCU
VSS
Cap_RC
VSS
CLK / INT
3
1
A 10 nF decoupling capacitor is recommended close to the device.
2
Interface lines SCL, SDA and RST are open drain and require pull-up resistors to VDD.
3
CLK / INT offers selectable frequencies 32.768 kHz to 1/60 Hz for application use. If not used, it is
recommended to disable CLK / INT for optimized current consumption.
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7.2. OPERATING RV-1805-C3 WITH BACKUP BATTERY/SUPERCAP
4
1.5kΩ
Backup
Battery/
Supercap
10nF
10nF
VBACKUP
VDD
RV-1805-C3
47pF
SDA
SDA
SCL
SCL
RST
RESET
PSW
Cap_RC
VSS
4
Main
Battery
VDD
MCU
VSS
CLK / INT
Total battery series impedance = 1.5k ohms, which may require an external resistor.
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8. RECOMMENDED REFLOW TEMPERATURE (LEADFREE SOLDERING)
Maximum Reflow Conditions in accordance with IPC/JEDEC J-STD-020C “Pb-free”
Temperature Profile
Average ramp-up rate
Ramp down Rate
Time 25°C to Peak Temperature
Preheat
Temperature min
Temperature max
Time Tsmin to Tsmax
Soldering above liquidus
Temperature liquidus
Time above liquidus
Peak temperature
Peak Temperature
Time within 5°C of peak temperature
Symbol
(Tsmax to Tp)
Tcool
Tto-peak
Condition
3°C / second max
6°C / second max
8 minutes max
Unit
°C / s
°C / s
min
Tsmin
Tsmax
ts
150
200
60 – 180
°C
°C
sec
TL
tL
217
60 – 150
°C
sec
Tp
tp
260
20 – 40
°C
sec
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9. PACKAGE
9.1. DIMENSIONS AND SOLDERPADS LAYOUT
C3 Package:
Package dimensions (bottom view):
Recommended solderpad layout:
All dimensions in mm typical.
9.2. MARKING AND PIN #1 INDEX
C3 Package:
1805
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10. PACKING INFORMATION
10.1. CARRIER TAPE
12 mm Carrier-Tape:
Material:
Polystyrene / Butadine or Polystyrol black, conductive
Cover Tape:
Base Material:
Adhesive Material:
Polyester, conductive 0.061 mm
Pressure-sensitive Synthetic Polymer
C3 Package:
User Direction of Feed
Tape Leader and Trailer: 300 mm minimum.
All dimensions in mm.
10.2. PARTS PER REEL
C3 Package:
Reels:
Diameter
7”
7”
Material
Plastic, Polystyrol
Plastic, Polystyrol
RTC’s per reel
1’000
3’000
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Micro Crystal
Extrem Low Power Real Time Clock / Calendar Module
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10.3. REEL 7 INCH FOR 12 mm TAPE
Reel:
Diameter
7”
Material
Plastic, Polystyrol
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10.4. HANDLING PRECAUTIONS FOR CRYSTALS OR MODULES WITH EMBEDDED CRYSTALS
The built-in tuning-fork crystal consists of pure Silicon Dioxide in crystalline form. The cavity inside the package is
evacuated and hermetically sealed in order for the crystal blank to function undisturbed from air molecules,
humidity and other influences.
Shock and vibration:
Keep the crystal / module from being exposed to excessive mechanical shock and vibration. Micro Crystal
guarantees that the crystal / module will bear a mechanical shock of 5000g / 0.3 ms.
The following special situations may generate either shock or vibration:
Multiple PCB panels - Usually at the end of the pick & place process the single PCBs are cut out with a router.
These machines sometimes generate vibrations on the PCB that have a fundamental or harmonic frequency
close to 32.768 kHz. This might cause breakage of crystal blanks due to resonance. Router speed should be
adjusted to avoid resonant vibration.
Ultrasonic cleaning - Avoid cleaning processes using ultrasonic energy. These processes can damages
crystals due to mechanical resonance of the crystal blank.
Overheating, rework high temperature exposure:
Avoid overheating the package. The package is sealed with a seal ring consisting of 80% Gold and 20% Tin. The
eutectic melting temperature of this alloy is at 280°C. Heating the seal ring up to >280°C will cause melting of the
metal seal which then, due to the vacuum, is sucked into the cavity forming an air duct. This happens when using
hot-air-gun set at temperatures >300°C.
Use the following methods for rework:
•
•
Use a hot-air- gun set at 270°C.
Use 2 temperature controlled soldering irons, set at 270°C, with special-tips to contact all solder-joints from
both sides of the package at the same time, remove part with tweezers when pad solder is liquid.
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11. DOCUMENT REVISION HISTORY
Date
Revision #
Revision Details
March 2014
1.0
April 2014
1.1
July 2014
1.2
July 2014
2.0
Initial preliminary version
- Added limits and/or temperature range specifications for the following parameters:
VDD,ABSMAX, VBACK,ABSMAX, VDDIO, VDDRST, VDDSWR, VDDSWF, VDDFS, VBACKRST, VT+, VT-, ILEAK, RDSON,
IOLEAK, FRCC, FRCU, TAC, IVDD:I2C, IVDD:XT, IVDD:RC, IVDD:ACAL, IVDD:CK32, IVDD:CLK128, IVBACK:XT, IVBACK:RC,
IVBACK:ACAL, IVBACK:VDD, VBRF, VBRR, VBRH, TBR, tLOW:VDD, tVL:CLK, tVH:CLK, tXTST, tLOW:VDD, tVL:NRST, tVH:NRST
- Removed tBREF parameter
- Additional note on autocalibration operating temperature range in the electrical specification
section
- Added additional description to the Autocalibration Fail section
- Updated RC and XT digital calibration adjustment value equation
- Removed VDDRS parameter as there is no requirement for the VDD rising slew rate
- Added curves to the electrical specification section: VDD Current vs. Voltage in different
operating modes, VDD Current vs. Voltage During I2C burst read/write, VDD Current vs.
Voltage with 32.768kHz Clock Output, VBACKUP Current vs. Voltage in different operating
modes, VBACKUP current vs. Voltage in VDD power state
- Removed typical values at 1.5V and 3.6V in VDD supply current table and replaced with VDD
supply current vs. voltage curves
- Removed typical values at 1.5V and 3.6V in VBACKUP supply current table and replaced with
VBACKUP supply current vs. voltage curve
- Added ID1 - Part Number Lower Register = 0000’0101
- Removed description “low capacitance environments”
- Modified number format for thousand
- Changed 128 Hz to 128 Hz level in section 4.9.2
- Changed 64 Hz to 64 Hz level in section 4.9.2
- Added leakage management for I2C in section 4.17.6.
- Added leakage management in section 4.22
- Corrected calculations in section 4.23.1
- Corrected highest calibrated RC frequency to 64 Hz
- Updated RCPLS value to be consistent across the datasheet
- Corrected current consumption to 17 nA for RC oscillator
- Added term Distributed Digital Calibration
- Added validity of the ACAL field for the RC Oscillator in section 3.8, 4.11.2 and 4.14
- Added section AUTOMATIC SWITCHOVER SUMMARY
- Added section REGISTER RESET VALUES SUMMARY
- Changed document name to Datasheet
- Added register definitions with BCD respectively binary code values
- Added Analog Input VBACKUP to the Digital Architecture Summary
- Added figure with the modified clock at the 64 Hz level
- Corrected frequency in graph Autocalibration Error Cancelation to 64 Hz
- Modified graphs in section 4.11.7 to Accuracy in Seconds
- Added Uncalibrated RC Oscillator cycle-to-cycle jitter, MIN, MAX
- Added highest calibrated frequency in RC mode and XT mode in SQW Register
- Added digitally calibrated XT Oscillator
- Changed Calibration XT register reset value to preconfigurated/factory value
- Modified AXT to Factory Calibrated at 25°C, VDD = 3.0V
- Modified XT Frequency accuracy to ±100 ppm, Calibration Disabled (OFFSETX = 0)
- Added section TIME ACCURACY EXAMPLE
- Corrected TSTART Oscillator start-up time to typ. 1.0 second
- Corrected duty cycle to 60 ±10%
- Modified part number to RV-1805-C3
Released version
Information furnished is believed to be accurate and reliable. However, Micro Crystal assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other
rights of third parties which may result from its use. In accordance with our policy of continuous
development and improvement, Micro Crystal reserves the right to modify specifications mentioned in this
publication without prior notice. This product is not authorized for use as critical component in life support
devices or systems.
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