Ambiq Datasheet

AM08XX Datasheet
AM08XX Real-Time Clock Family
Features
▪ Ultra-low supply current (all at 3V):
- 14 nA with RC oscillator
- 22 nA with RC oscillator and Autocalibration
- 55 nA with crystal oscillator
▪ Baseline timekeeping features:
- 32.768 kHz crystal oscillator with integrated
load capacitor/resistor
- Counters for hundredths, seconds, minutes,
hours, date, month, year, century, and weekday
- Alarm capability on all counters
- Programmable output clock generation
(32.768 kHz to 1/year)
- Countdown timer with repeat function
- Automatic leap year calculation
▪ Advanced timekeeping features:
- Integrated power optimized RC oscillator
- Advanced crystal calibration to ± 2 ppm
- Advanced RC calibration to ± 16 ppm
- Automatic calibration of RC oscillator to crystal
oscillator
- Watchdog timer with hardware reset
- Up to 256 bytes of general purpose RAM
▪ Power management features:
- Automatic switchover to VBAT
- External interrupt monitor
- Programmable low battery detection threshold
- Programmable analog voltage comparator
▪ I2C (up to 400 kHz) and 3-wire or 4-wire SPI (up
to 2 MHz) serial interfaces available
▪ Operating voltage 1.5-3.6 V
▪ Clock and RAM retention voltage 1.5-3.6 V
▪ Operating temperature –40 to 85 °C
▪ All inputs include Schmitt Triggers
▪ 3x3 mm QFN-16 package
Ambiq Micro Inc.
www.ambiqmicro.com
Applications
▪
▪
▪
▪
▪
▪
▪
▪
▪
Smart cards
Wireless sensors and tags
Medical electronics
Utility meters
Data loggers
Appliances
Handsets
Consumer electronics
Communications equipment
Description
The Ambiq Micro AM08XX Real Time Clock family
provides a groundbreaking combination of ultra-low
power coupled with a highly sophisticated feature
set. With power requirements significantly lower than
any other industry RTC (as low as 14 nA), these are
the first semiconductors based on Ambiq Micro’s
innovative SPOTTM (Subthreshold Power Optimized
Technology) CMOS platform. The AM08XX includes
on-chip oscillators to provide minimum power
consumption, full RTC functions including battery
backup and programmable counters and alarms for
timer and watchdog functions, and either an I2C or
SPI serial interface for communication with a host
controller.
303 Camp Craft Road, Suite 350
Westlake Hills, TX 78746
2013 Ambiq Micro, Inc.
October 2013
AM08XX Datasheet
Typical Application Circuit
System Power
1.5k*
VBAT
Battery/
Supercap
XO
XI
VCC
VCC
I2C/SPI
AM08XX
FOUT/nIRQ
MCU
IRQ
VSS
VSS
* Total battery series impedance = 1.5k ohms, which may require an external resistor
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AM08XX Datasheet
Contents
1. Family Summary .......................................................................................................................... 10
2. Package Pins ............................................................................................................................... 11
2.1. Pin Configuration and Connections ...................................................................................... 11
2.2. Pin Descriptions ................................................................................................................... 12
3. Digital Architecture Summary .................................................................................................... 14
4. Electrical Specifications ............................................................................................................. 15
4.1. Absolute Maximum Ratings ................................................................................................. 15
4.2. Power Supply Parameters ................................................................................................... 15
4.3. Operating Parameters .......................................................................................................... 17
4.4. Oscillator Parameters ........................................................................................................... 18
4.5. VCC Supply Current .............................................................................................................. 20
4.6. VBAT Supply Current ............................................................................................................ 24
4.7. BREF Electrical Characteristics ........................................................................................... 27
4.8. I²C AC Electrical Characteristics .......................................................................................... 27
4.9. SPI AC Electrical Characteristics ......................................................................................... 28
4.10. Power On AC Electrical Characteristics ............................................................................. 30
5. Functional Description ................................................................................................................ 31
5.1. I²C Interface ......................................................................................................................... 32
5.1.1. Bus Not Busy .............................................................................................................. 33
5.1.2. Start Data Transfer ..................................................................................................... 33
5.1.3. Stop Data Transfer ..................................................................................................... 33
5.1.4. Data Valid ................................................................................................................... 33
5.1.5. Acknowledge .............................................................................................................. 33
5.1.6. Offset Address Transmission ..................................................................................... 34
5.1.7. Write Operation .......................................................................................................... 34
5.1.8. Read Operation .......................................................................................................... 34
5.2. SPI Interface ........................................................................................................................ 35
5.2.1. Write Operation .......................................................................................................... 35
5.2.2. Read Operation .......................................................................................................... 36
5.3. XT Oscillator ......................................................................................................................... 36
5.4. RC Oscillator ........................................................................................................................ 36
5.5. RTC Counter Access ........................................................................................................... 36
5.6. Hundredths Synchronization ................................................................................................ 37
5.7. Generating Hundredths of a Second .................................................................................... 37
5.8. Watchdog Timer ................................................................................................................... 37
5.9. Digital Calibration ................................................................................................................. 38
5.9.1. XT Oscillator Digital Calibration .................................................................................. 38
5.9.2. RC Oscillator Digital Calibration ................................................................................. 39
5.10. Autocalibration ................................................................................................................... 39
5.10.1. Autocalibration Operation ......................................................................................... 40
5.10.2. XT Autocalibration Mode .......................................................................................... 40
5.10.3. RC Autocalibration Mode .......................................................................................... 40
5.10.4. Autocalibration Frequency and Control .................................................................... 40
5.10.5. Autocalibration Filter (AF) Pin ................................................................................... 41
5.10.6. Autocalibration Fail ................................................................................................... 41
5.11. Oscillator Failure Detection ................................................................................................ 41
5.12. Interrupts ............................................................................................................................ 42
5.12.1. Interrupt Summary .................................................................................................... 42
5.12.2. Alarm Interrupt AIRQ ................................................................................................ 42
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AM08XX Datasheet
5.12.3. Countdown Timer Interrupt TIRQ ............................................................................. 43
5.12.4. Watchdog Timer Interrupt WIRQ .............................................................................. 43
5.12.5. Battery Low Interrupt BLIRQ .................................................................................... 43
5.12.6. External Interrupts X1IRQ and X2IRQ ...................................................................... 43
5.12.7. Oscillator Fail Interrupt OFIRQ ................................................................................. 43
5.12.8. Autocalibration Fail Interrupt ACIRQ ........................................................................ 43
5.12.9. Servicing Interrupts ................................................................................................... 43
5.13. Power Control and Switching ............................................................................................. 44
5.13.1. Battery Low Flag and Interrupt ................................................................................. 45
5.13.2. Analog Comparator .................................................................................................. 45
5.13.3. Pin Control and Leakage Management .................................................................... 45
5.13.4. Power Up Timing ...................................................................................................... 46
5.14. Software Reset ................................................................................................................... 46
5.15. Trickle Charger ................................................................................................................... 46
6. Registers ...................................................................................................................................... 47
6.1. Register Definitions and Memory Map ................................................................................. 48
6.2. Time and Date Registers ..................................................................................................... 50
6.2.1. 0x00 - Hundredths ...................................................................................................... 50
6.2.2. 0x01 - Seconds ........................................................................................................... 50
6.2.3. 0x02 - Minutes ............................................................................................................ 51
6.2.4. 0x03 - Hours ............................................................................................................... 51
6.2.5. 0x04 - Date ................................................................................................................. 52
6.2.6. 0x05 - Months ............................................................................................................. 52
6.2.7. 0x06 - Years ............................................................................................................... 53
6.2.8. 0x07 - Weekday .......................................................................................................... 53
6.3. Alarm Registers .................................................................................................................... 54
6.3.1. 0x08 - Hundredths Alarm ............................................................................................ 54
6.3.2. 0x09 - Seconds Alarm ................................................................................................ 54
6.3.3. 0x0A - Minutes Alarm ................................................................................................. 55
6.3.4. 0x0B - Hours Alarm .................................................................................................... 55
6.3.5. 0x0C - Date Alarm ...................................................................................................... 56
6.3.6. 0x0D - Months Alarm .................................................................................................. 57
6.3.7. 0x0E - Weekday Alarm ............................................................................................... 57
6.4. Configuration Registers ........................................................................................................ 58
6.4.1. 0x0F - Status (Read Only) .......................................................................................... 58
6.4.2. 0x10 - Control1 ........................................................................................................... 59
6.4.3. 0x11 - Control2 ........................................................................................................... 59
6.4.4. 0x12 - Interrupt Mask .................................................................................................. 60
6.4.5. 0x13 - SQW ................................................................................................................ 61
6.5. Calibration Registers ............................................................................................................ 63
6.5.1. 0x14 - Calibration XT .................................................................................................. 63
6.5.2. 0x15 - Calibration RC Upper ...................................................................................... 63
6.5.3. 0x16 - Calibration RC Lower ...................................................................................... 64
6.6. Interrupt Polarity Control Register ........................................................................................ 64
6.6.1. 0x17 - Interrupt Polarity Control .................................................................................. 64
6.7. Timer Registers .................................................................................................................... 65
6.7.1. 0x18 - Countdown Timer Control ................................................................................ 65
6.7.2. 0x19 - Countdown Timer ............................................................................................ 67
6.7.3. 0x1A - Timer Initial Value ........................................................................................... 67
6.7.4. 0x1B - Watchdog Timer .............................................................................................. 67
6.8. Oscillator Registers .............................................................................................................. 68
6.8.1. 0x1C - Oscillator Control ............................................................................................ 68
6.8.2. 0x1D – Oscillator Status Register ............................................................................... 69
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AM08XX Datasheet
6.9. Miscellaneous Registers ...................................................................................................... 69
6.9.1. 0x1F - Configuration Key ............................................................................................ 69
6.10. Analog Control Registers ................................................................................................... 70
6.10.1. 0x20 - Trickle ............................................................................................................ 70
6.10.2. 0x21 - BREF Control ................................................................................................ 71
6.10.3. 0x26 – AFCTRL ........................................................................................................ 71
6.10.4. 0x27 – Batmode IO Register .................................................................................... 72
6.10.5. 0x2F – Analog Status Register (Read Only) ............................................................ 72
6.10.6. 0x30 – Output Control Register ................................................................................ 73
6.11. ID Registers ....................................................................................................................... 73
6.11.1. 0x28 – ID0 - Part Number Upper Register (Read Only) ........................................... 73
6.11.2. 0x29 – ID1 - Part Number Lower Register (Read Only) ........................................... 74
6.11.3. 0x2A – ID2 - Part Revision (Read Only) ................................................................... 74
6.11.4. 0x2B – ID3 – Lot Lower (Read Only) ........................................................................ 74
6.11.5. 0x2C – ID4 – ID Upper (Read Only) ......................................................................... 75
6.11.6. 0x2D – ID5 – Unique Lower (Read Only) ................................................................. 75
6.11.7. 0x2E – ID6 – Wafer (Read Only) .............................................................................. 76
6.12. Ram Registers .................................................................................................................. 76
6.12.1. 0x3F - Extension RAM Address ............................................................................... 76
6.12.2. 0x40 - 0x7F – Standard RAM ................................................................................... 77
6.12.3. 0x80 - 0xFF – Alternate RAM ................................................................................... 77
6.13. Package Mechanical Information ....................................................................................... 78
7. Reflow Profile ............................................................................................................................... 79
8. Ordering Information ................................................................................................................... 80
9. Document Revision History ........................................................................................................ 80
10. Contact Information .................................................................................................................. 81
11. Legal Information and Disclaimers .......................................................................................... 81
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AM08XX Datasheet
List of Figures
Figure 1. Pin Configuration Diagram .................................................................................................. 11
Figure 2. Digital Architecture Summary .............................................................................................. 14
Figure 3. Power Supply Switchover .................................................................................................... 15
Figure 4. Calibrated RC Oscillator Typical Frequency Variation vs. Temperature ............................. 19
Figure 5. Uncalibrated RC Oscillator Typical Frequency Variation vs. Temperature ......................... 19
Figure 6. Typical VCC Current vs. Temperature in XT Mode ............................................................. 21
Figure 7. Typical VCC Current vs. Temperature in RC Mode ............................................................ 21
Figure 8. Typical VCC Current vs. Temperature in RC Autocalibration Mode ................................... 22
Figure 9. Typical VCC Current vs. Voltage, Different Modes of Operation ........................................ 22
Figure 10. Typical VCC Current vs. Voltage, I²C and SPI Burst Read/Write ...................................... 23
Figure 11. Typical VCC Current vs. Voltage, 32.768 kHz Clock Output ............................................. 23
Figure 12. Typical VBAT Current vs. Temperature in XT Mode ......................................................... 24
Figure 13. Typical VBAT Current vs. Temperature in RC Mode ........................................................ 25
Figure 14. Typical VBAT Current vs. Temperature in RC Autocalibration Mode ................................ 25
Figure 15. Typical VBAT Current vs. Voltage, Different Modes of Operation ..................................... 26
Figure 16. Typical VBAT Current vs. Voltage in VCC Power State .................................................... 26
Figure 17. I²C AC Parameter Definitions ............................................................................................ 27
Figure 18. SPI AC Parameter Definitions – Input ............................................................................... 28
Figure 19. SPI AC Parameter Definitions – Output ............................................................................ 29
Figure 20. Power On AC Electrical Characteristics ............................................................................ 30
Figure 21. Detailed Block Diagram ..................................................................................................... 31
Figure 22. Basic I²C Conditions .......................................................................................................... 32
Figure 23. I²C Acknowledge Address Operation ................................................................................ 33
Figure 24. I²C Address Operation ....................................................................................................... 34
Figure 25. I²C Offset Address Transmission ...................................................................................... 34
Figure 26. I²C Write Operation ........................................................................................................... 34
Figure 27. I²C Read Operation ........................................................................................................... 35
Figure 28. SPI Write Operation .......................................................................................................... 36
Figure 29. SPI Read Operation .......................................................................................................... 36
Figure 30. Power States ..................................................................................................................... 44
Figure 31. Power Up Timing ............................................................................................................... 46
Figure 32. Trickle Charger .................................................................................................................. 47
Figure 33. Package Mechanical Diagram ........................................................................................... 78
Figure 34. Reflow Soldering Diagram ................................................................................................. 79
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AM08XX Datasheet
List of Tables
Table 1: Family Summary ................................................................................................................... 10
Table 2: Pin Connections ................................................................................................................... 11
Table 3: Pin Descriptions .................................................................................................................... 12
Table 4: Absolute Maximum Ratings .................................................................................................. 15
Table 5: Power Supply and Switchover Parameters .......................................................................... 16
Table 6: Operating Parameters .......................................................................................................... 17
Table 7: Oscillator Parameters ........................................................................................................... 18
Table 8: VCC Supply Current ............................................................................................................. 20
Table 9: VBAT Supply Current ........................................................................................................... 24
Table 10: BREF Parameters .............................................................................................................. 27
Table 11: I²C AC Electrical Parameters .............................................................................................. 28
Table 12: SPI AC Electrical Parameters ............................................................................................. 29
Table 13: Power On AC Electrical Parameters .................................................................................. 30
Table 14: Autocalibration Modes ........................................................................................................ 40
Table 15: Interrupt Summary .............................................................................................................. 42
Table 16: Register Definitions (0x00 to 0x0F) .................................................................................... 48
Table 17: Register Definitions (0x10 to 0xFF) .................................................................................... 49
Table 18: Hundredths Register ........................................................................................................... 50
Table 19: Hundredths Register Bits .................................................................................................... 50
Table 20: Seconds Register ............................................................................................................... 50
Table 21: Seconds Register Bits ........................................................................................................ 50
Table 22: Minutes Register ................................................................................................................. 51
Table 23: Minutes Register Bits .......................................................................................................... 51
Table 24: Hours Register (12 Hour Mode) ......................................................................................... 51
Table 25: Hours Register Bits (12 Hour Mode) .................................................................................. 51
Table 26: Hours Register (24 Hour Mode) ......................................................................................... 52
Table 27: Hours Register Bits (24 Hour Mode) .................................................................................. 52
Table 28: Date Register ...................................................................................................................... 52
Table 29: Date Register Bits ............................................................................................................... 52
Table 30: Months Register ................................................................................................................. 52
Table 31: Months Register Bits .......................................................................................................... 53
Table 32: Years Register .................................................................................................................... 53
Table 33: Years Register Bits ............................................................................................................. 53
Table 34: Weekdays Register ............................................................................................................ 53
Table 35: Weekdays Register Bits ..................................................................................................... 54
Table 36: Hundredths Alarm Register ................................................................................................ 54
Table 37: Hundredths Alarm Register Bits ......................................................................................... 54
Table 38: Seconds Alarm Register ..................................................................................................... 54
Table 39: Seconds Alarm Register Bits .............................................................................................. 55
Table 40: Minutes Alarm Register ...................................................................................................... 55
Table 41: Minutes Alarm Register Bits ............................................................................................... 55
Table 42: Hours Alarm Register (12 Hour Mode) ............................................................................... 55
Table 43: Hours Alarm Register Bits (12 Hour Mode) ........................................................................ 56
Table 44: Hours Alarm Register (24 Hour Mode) ............................................................................... 56
Table 45: Hours Alarm Register Bits (24 Hour Mode) ........................................................................ 56
Table 46: Date Alarm Register ........................................................................................................... 56
Table 47: Date Alarm Register Bits .................................................................................................... 57
Table 48: Months Alarm Register ....................................................................................................... 57
Table 49: Months Alarm Register Bits ................................................................................................ 57
Table 50: Weekdays Alarm Register .................................................................................................. 57
Table 51: Weekdays Alarm Register Bits ........................................................................................... 58
Table 52: Status Register ................................................................................................................... 58
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AM08XX Datasheet
Table 53: Status Register Bits ............................................................................................................ 58
Table 54: Control1 Register ................................................................................................................ 59
Table 55: Control1 Register Bits ......................................................................................................... 59
Table 56: Control2 Register ................................................................................................................ 59
Table 57: Control2 Register Bits ......................................................................................................... 59
Table 58: nIRQ2 Pin Control .............................................................................................................. 60
Table 59: FOUT/nIRQ Pin Control ...................................................................................................... 60
Table 60: Interrupt Mask Register ...................................................................................................... 60
Table 61: Interrupt Mask Register Bits ............................................................................................... 60
Table 62: SQW Register ..................................................................................................................... 61
Table 63: SQW Register Bits .............................................................................................................. 61
Table 64: Square Wave Function Select ............................................................................................ 62
Table 65: Calibration XT Register ...................................................................................................... 63
Table 66: Calibration XT Register Bits ............................................................................................... 63
Table 67: Calibration RC Upper Register ........................................................................................... 63
Table 68: Calibration RC Upper Register Bits .................................................................................... 63
Table 69: CMDR Function .................................................................................................................. 63
Table 70: Calibration RC Lower Register ........................................................................................... 64
Table 71: Calibration RC Lower Register Bits .................................................................................... 64
Table 72: Interrupt Polarity Control Register ...................................................................................... 64
Table 73: Interrupt Polarity Control Register Bits ............................................................................... 64
Table 74: Countdown Timer Control Register .................................................................................... 65
Table 75: Countdown Timer Control Register Bits ............................................................................. 65
Table 76: Repeat Function ................................................................................................................. 65
Table 77: Countdown Timer Function Select ..................................................................................... 66
Table 78: Countdown Timer Register ................................................................................................. 67
Table 79: Countdown Timer Register Bits .......................................................................................... 67
Table 80: Timer Initial Value Register ................................................................................................ 67
Table 81: Timer Initial Value Register Bits ......................................................................................... 67
Table 82: Watchdog Timer Register ................................................................................................... 67
Table 83: Watchdog Timer Register Bits ............................................................................................ 68
Table 84: Watchdog Timer Frequency Select .................................................................................... 68
Table 85: Oscillator Control Register .................................................................................................. 68
Table 86: Oscillator Control Register Bits ........................................................................................... 68
Table 87: Oscillator Status Register ................................................................................................... 69
Table 88: Oscillator Status Register Bits ............................................................................................ 69
Table 89: Configuration Key Register ................................................................................................. 69
Table 90: Configuration Key Register Bits .......................................................................................... 70
Table 91: Trickle Register ................................................................................................................... 70
Table 92: Trickle Register Bits ............................................................................................................ 70
Table 93: Trickle Charge Output Resistor .......................................................................................... 70
Table 94: BREF Control Register ....................................................................................................... 71
Table 95: BREF Control Register Bits ................................................................................................ 71
Table 96: VBAT Reference Voltage ................................................................................................... 71
Table 97: AFCTRL Register ............................................................................................................... 71
Table 98: AFCTRL Register Bits ........................................................................................................ 72
Table 99: Batmode IO Register .......................................................................................................... 72
Table 100: Batmode IO Register Bits ................................................................................................. 72
Table 101: Analog Status Register ..................................................................................................... 72
Table 102: Analog Status Register Bits .............................................................................................. 72
Table 103: Output Control Register .................................................................................................... 73
Table 104: Output Control Register Bits ............................................................................................. 73
Table 105: 28 – ID0 – Part Number Upper Register .......................................................................... 73
Table 106: 28 – ID1 – Part Number Lower Register .......................................................................... 74
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AM08XX Datasheet
Table 107: 2A – ID2 – Part Revision Register .................................................................................... 74
Table 108: 2A – ID2 – Part Revision Register Bits ............................................................................. 74
Table 109: 2B – ID3 – Lot Lower Register ......................................................................................... 74
Table 110: 2B – ID3 – Lot Lower Register Bits .................................................................................. 74
Table 111: 2C – ID4 – ID Upper Register ........................................................................................... 75
Table 112: 2C – ID4 – ID Upper Register Bits .................................................................................... 75
Table 113: 2D – ID5 – ID Lower Register ........................................................................................... 75
Table 114: 2D – ID5 – ID Lower Register Bits .................................................................................... 75
Table 115: 2E – ID6 – Wafer Register ................................................................................................ 76
Table 116: 2E – ID6 – Wafer Register Bits ......................................................................................... 76
Table 117: 3F – Extension RAM Address Register ............................................................................ 76
Table 118: 3F – Extension RAM Address Register Bits ..................................................................... 76
Table 119: Reflow Soldering Requirements ....................................................................................... 79
Table 120: Ordering Information ......................................................................................................... 80
Table 121: Document Revision History .............................................................................................. 80
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AM08XX Datasheet
1.
Family Summary
The AM08XX family consists of several members (see Table 1). All devices are supplied in a standard 3x3
mm QFN-16 package. Members of the software and pin compatible AM18XX RTC with Power
Management family are also listed.
Table 1: Family Summary
Baseline
Timekeeping
Part #
Advanced Timekeeping
Power Management
XT
Osc
Number
of GP
Outputs
RC
Osc
Calib/
Autocalib
AM0801
■
2
■
■
0
AM0803
■
2
■
■
64
AM0804
■
4
■
■
■
256
AM0805
■
4
■
■
■
256
AM0811
■
2
■
■
0
AM0813
■
2
■
■
64
AM0814
■
3
■
■
■
256
AM0815
■
3
■
■
■
256
Watchdog
RAM
(B)
VBAT
Switch
Reset
Mgmt
Ext
Int
Power
Switch and
Sleep FSM
Interface
I2 C
I2 C
■
■
■
I2 C
■
I2 C
SPI
■
SPI
■
■
SPI
■
SPI
Software and Pin Compatible AM18XX Family Components
AM1801
■
2
■
■
0
AM1803
■
2
■
■
64
AM1804
■
4
■
■
■
256
AM1805
■
4
■
■
■
256
AM1811
■
2
■
■
0
AM1813
■
2
■
■
64
AM1814
■
3
■
■
■
256
AM1815
■
3
■
■
■
256
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■
■
I2 C
■
I2 C
■
■
■
I2 C
■
■
■
I2 C
■
SPI
■
SPI
■
■
■
■
■
■
SPI
■
■
■
SPI
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AM08XX Datasheet
2.
Package Pins
2.1 Pin Configuration and Connections
Figure 1 and Table 2 show the QFN-16 pin configurations for the AM08XX parts. Pins labeled NC must be
left unconnected. The thermal pad, pin 17, on the QFN-16 packages must be connected to VSS.
VCC
XO
Available in AM0803 and AM0805 only, else VSS
(3) Available
in AM0814 and AM0815 only, else NC
(4) Available
in AM0813 and AM0815 only, else VSS
EXTI (3)
SDI
nIRQ2
SCL
(1) CLKOUT/nIRQ3
SDA
(2) VBAT
Available in AM0804 and AM0805 only, else NC
(2)
FOUT/nIRQ
VSS
PAD
NC
VSS
nIRQ2
nCE
(3) WDI
EXTI (1)
AF
XI
FOUT/nIRQ
1
(1)
(3) CLKOUT/nIRQ3
VSS
PAD
NC
NC
SCL
(1) WDI
nTIRQ (1)
SDO
XO
1
(4) VBAT
NC
AM081X
AF
VCC
XI
AM080X
Figure 1. Pin Configuration Diagram
Table 2: Pin Connections
Pin Name
Pin Number in AM08XX
Pin
Type
Function
01
03
04
05
11
13
14
15
5,9,17
9,17
5,9,17
9,17
5,17
17
5,17
17
VSS
Power
Ground
VCC
Power
System power supply
13
13
13
13
13
13
13
13
XI
XT
Crystal input
16
16
16
16
16
16
16
16
XO
XT
Crystal output
15
15
15
15
15
15
15
15
AF
Output
Autocalibration filter
14
14
14
14
14
14
14
14
VBAT
Power
Battery power supply
SCL
Input
I2C or SPI interface clock
SDO
Output
SDI
5
7
7
5
7
7
7
SPI data output
6
6
6
6
Input
SPI data input
9
9
9
9
nCE
Input
SPI chip select
12
12
12
12
SDA
Input
I2C data input/output
EXTI
Input
WDI
6
6
External interrupt input
10
10
10
10
Input
Watchdog reset input
2
2
2
2
FOUT/nIRQ
Output
Int 1/function output
11
11
11
11
11
11
11
11
nIRQ2
Output
Int 2 output
4
4
4
4
4
4
4
4
CLKOUT/nIRQ3
Output
Int 3/clock output
8
8
8
8
nTIRQ
Output
Timer interrupt output
12
12
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6
7
5
7
6
7
5
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AM08XX Datasheet
2.2 Pin Descriptions
Table 3 provides a description of the pin connections.
Table 3: Pin Descriptions
Pin Name
Description
VSS
Ground connection. In the QFN-16 packages the ground slug on the bottom of the package must be
connected to VSS.
VCC
Primary power connection. If a single power supply is used, it must be connected to VCC.
VBAT
Battery backup power connection. If a backup battery is not present, VBAT is normally left floating or
grounded, but it may also be used to provide the analog input to the internal comparator (see AnalogComparator).
XI
Crystal oscillator input connection.
XO
Crystal oscillator output connection.
AF
Autocalibration filter connection. A 47pF ceramic capacitor should be placed between this pin and VSS
for improved Autocalibration mode timing accuracy.
SCL
I/O interface clock connection. It provides the SCL input in both I2C and SPI interface parts.
SDA (only available in
I2C environments)
I/O interface I2C data connection.
SDO (only available in
SPI environments)
I/O interface SPI data output connection.
SDI
I/O interface SPI data input connection.
nCE (only available in
SPI environments)
I/O interface SPI chip select input connection. It is an active low signal. A pull-up resistor is recommended to be connected to this pin to ensure it is not floating. A pull-up resistor also prevents inadvertent writes to the RTC during power transitions.
EXTI
External interrupt input connection. It may be used to generate an External 1 interrupt with polarity
selected by the EX1P bit if enabled by the EX1E bit. The value of the EXTI pin may be read in the EXIN
register bit. This pin does not have an internal pull resistor. It must not be left floating or the RTC may
consume higher current.
WDI
Watchdog Timer reset input connection. It may also be used to generate an External 2 interrupt with
polarity selected by the EX2P bit if enabled by the EX2E bit. The value of the WDI pin may be read in
the WDIN register bit. This pin does not have an internal pull resistor. It must not be left floating or the
RTC may consume higher current.
Primary interrupt output connection. FOUT/nIRQ may be configured to generate several signals as a
function of the OUT1S field (see 0x11 - Control2). FOUT/nIRQ is also asserted low on a power up until
the AM08XX has exited the reset state and is accessible via the I/O interface.
FOUT/nIRQ
nIRQ2
nTIRQ (only available in
I2C environments)
DS0002V1p0
1.
2.
3.
4.
FOUT/nIRQ can drive the value of the OUT bit.
FOUT/nIRQ can drive the inverse of the combined interrupt signal IRQ (see Interrupts).
FOUT/nIRQ can drive the square wave output (see 0x13 - SQW) if enabled by SQWE.
FOUT/nIRQ can drive the inverse of the alarm interrupt signal AIRQ (see Interrupts).
1.
Secondary interrupt output connection. It is an open drain output. nIRQ2 may be configured to
generate several signals as a function of the OUT2S field (see 0x11 - Control2). nIRQ2 can drive
the value of the OUTB bit.
nIRQ2 can drive the square wave output (see 0x13 - SQW) if enabled by SQWE.
nIRQ2 can drive the inverse of the combined interrupt signal IRQ (see Interrupts).
nIRQ2 can drive the inverse of the alarm interrupt signal AIRQ (see Interrupts).
nIRQ2 can drive either sense of the timer interrupt signal TIRQ.
2.
3.
4.
5.
Timer interrupt output connection. It is an open drain output. nTIRQ always drives the active low nTIRQ
signal.
Page 12 of 81
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AM08XX Datasheet
Table 3: Pin Descriptions
Pin Name
CLKOUT/nIRQ3
DS0002V1p0
Description
Square Wave output connection. It is a push-pull output, and may be configured to generate one of two
signals.
1.
2.
CLKOUT/nIRQ3 can drive the value of the OUT bit.
CLKOUT/nIRQ3 can drive the square wave output (see 0x13 - SQW) if enabled by SQWE.
Page 13 of 81
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AM08XX Datasheet
3.
Digital Architecture Summary
Figure 2 illustrates the overall architecture of the pin inputs and outputs of the AM08XX.
TIRQ
CDT
nTIRQ
OUT
Calendar Counters
SQW Mux
Alarms
AIRQ
SQW
IRQ
EXTI
WDI
OF
ACF
BL
CLKOUT/nIRQ3
OUT1 Mux
FOUT/nIRQ
OUT2 Mux
nIRQ2
IRQ OR +
Msk
WDT
OUTB
Power On
Figure 2. Digital Architecture Summary
DS0002V1p0
Page 14 of 81
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AM08XX Datasheet
4.
Electrical Specifications
4.1 Absolute Maximum Ratings
Table 4 lists the absolute maximum ratings.
Table 4: Absolute Maximum Ratings
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC
System Power Voltage
-0.3
3.8
V
VBAT
Battery Voltage
-0.3
3.8
V
VI
Input voltage
VCC Power state
-0.3
VCC+ 0.3
V
VI
Input voltage
VBAT Power state
-0.3
VBAT+ 0.3
V
VO
Output voltage
VCC Power state
-0.3
VCC+ 0.3
V
VO
Output voltage
VBAT Power state
-0.3
VBAT+ 0.3
V
II
Input current
-10
10
mA
IO
Output current
-20
20
mA
VESD
CDM
±500
V
ESD Voltage
HBM
±4000
V
ILU
Latch-up Current
100
mA
TSTG
Storage Temperature
-55
125
°C
TOP
Operating Temperature
-40
85
°C
TSLD
Lead temperature
Hand soldering for 10 seconds
300
°C
TREF
Reflow soldering temperature
Reflow profile per JEDEC JSTD-020D
260
°C
4.2 Power Supply Parameters
Figure 3 and Table 5 describe the power supply and switchover parameters. See Power Control and
Switching for a detailed description of the operations.
VCC
VCCST
VBAT
Power State
VCCRST
VCCST
VCCSWF
VCCSWR
VCCSWF
VBATSW
POR
VCC Power
VBATRST
POR
VCC Power
VBAT Power
VCC Power
VBAT Power
POR
Figure 3. Power Supply Switchover
DS0002V1p0
Page 15 of 81
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AM08XX Datasheet

For Table 5, TA = -40 °C to 85 °C, TYP values at 25 °C.
Table 5: Power Supply and Switchover Parameters
SYMBOL
PARAMETER
PWR
TYPE
POWER STATE
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
VCC
System Power Voltage
VCC
Static
VCC Power
Clocks operating
and RAM and
registers retained
1.5
3.6
V
VCCIO
VCC I/O Interface
Voltage
VCC
Static
VCC Power
I2C or SPI operation
1.5
3.6
V
VCCST
VCC Start-up Voltage(1)
VCC
Rising
POR -> VCC Power
VCCRST
VCC Reset Voltage
VCC
Falling
VCC Power -> POR
VBAT < VBAT,MIN
or no VBAT
1.3
1.5
V
VCCSWR
VCC Rising Switch-over
Threshold Voltage
VCC
Rising
VBAT Power ->
VCC Power
VBAT ≥ VBATRST
1.6
1.7
V
VCCSWF
VCC Falling Switch-over
Threshold Voltage
VCC
Falling
VCC Power ->
VBAT Power
VBAT ≥
VBATSW,MIN
VCC
Hyst.
VCC Power <->
VBAT Power
VCC
Falling
VCC Power ->
VBAT Power
VCC < VCCSW,MAX
0.7
VBAT
Static
VBAT Power
Clocks operating
and RAM and
registers retained
1.4
3.6
V
VBAT
Static
VCC Power ->
VBAT Power
1.6
3.6
V
VBAT
Falling
VBAT Power ->
POR
1.4
V
VBAT
Static
VBAT Power
200
VBAT
Static
VBAT Power
1.0
VCCSWH
VCCFS
VBAT
VBATSW
VBATRST
VBMRG
VBATESR
VCC Switchover Threshold Hysteresis(2)
VCC Falling Slew Rate
to switch to VBAT state(4)
Battery Voltage
Battery Switchover Voltage Range(5)
Falling Battery POR Voltage(7)
VBAT Margin above
VCC(3)
VBAT supply series resistance(6)
1.6
1.2
VCC < VCCSWF
(1)
VCC must be above VCCST to exit the POR state, independent of the VBAT voltage.
(2)
Difference between VCCSWR and VCCSWF.
V
1.5
V
70
mV
1.4
V/ms
1.1
mV
1.5
k
(3)
VBAT must be higher than VCC by at least this voltage to ensure the AM08XX remains in the VBAT Power state.
(4) Maximum VCC falling slew rate to guarantee correct switchover to VBAT Power state. There is no V
CC falling slew
rate
requirement if switching to the VBAT power source is not required.
(5) V
BAT
(6)
voltage to guarantee correct transition to VBAT Power state when VCC falls.
Total series resistance of the power source attached to the VBAT pin. The optimal value is 1.5k, which may require an
external resistor. VBAT power source ESR + external resistor value = 1.5k
(7) V
BATRST
DS0002V1p0
is also the static voltage required on VBAT for register data retention.
Page 16 of 81
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AM08XX Datasheet
4.3 Operating Parameters
Table 6 lists the operating parameters.

For Table 6, TA = -40 °C to 85 °C, TYP values at 25 °C.
Table 6: Operating Parameters
SYMBOL
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX
VT+
Positive-going Input Threshold Voltage
3.0V
1.5
2.0
1.8V
1.1
1.25
VT-
Negative-going Input Threshold Voltage
3.0V
0.8
0.9
1.8V
0.5
0.6
IILEAK
Input leakage current
3.0V
CI
Input capacitance
VOH
High level output voltage on
push-pull outputs
1.7V – 3.6V
VOL
Low level output voltage
1.7V – 3.6V
IOH
IOL
IOLEAK
DS0002V1p0
High level output current on
push-pull outputs
Low level output current
0.02
VOL = 0.2●VCC
80
V
0.2•VCC
-2
-3.8
1.8V
-3
-4.3
3.0V
-7
-11
3.6V
-8.8
-15
1.7V
3.3
5.9
1.8V
6.1
6.9
3.0V
17
19
3.6V
18
20
0.02
Page 17 of 81
nA
pF
0.8•VCC
1.7V
Output leakage current
V
V
3
VOH = 0.8●VCC
UNIT
V
mA
mA
80
nA
2013 Ambiq Micro, Inc.
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AM08XX Datasheet
4.4 Oscillator Parameters
Table 7 lists the oscillator parameters.

For Table 7, TA = -40 °C to 85 °C unless otherwise indicated.
VCC = 1.7 to 3.6V, TYP values at 25 °C and 3.0V.
Table 7: Oscillator Parameters
SYMBOL
PARAMETER
FXT
XI and XO pin Crystal Frequency
FOF
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32.768
kHz
XT Oscillator failure detection
frequency
8
kHz
CINX
Internal XI and XO pin capacitance
1
pF
CEX
External XI and XO pin PCB
capacitance
1
pF
OAXT
XT Oscillation Allowance
320
kΩ
128
Hz
Calibrated RC Oscillator Fre-
At 25°C using a 32.768 kHz
crystal
quency(1)
Factory Calibrated at 25°C,
VCC = 2.8V
FRCU
Uncalibrated RC Oscillator
Frequency
Calibration Disabled (OFFSETR = 0)
JRCCC
RC Oscillator cycle-to-cycle
jitter
FRCC
XT mode digital calibration
AXT
accuracy(1)
AAC
Autocalibration mode timing
accuracy, 512 second period,
TA = -10°C to
89
122
Calibration Disabled (OFFSETR = 0) – 128 Hz
2000
Calibration Disabled (OFFSETR = 0) – 1 Hz
500
Calibrated at an initial temperature and voltage
-2
2
35
1 week run time
20
1 month run time
10
1 year run time
3
-10
ing temperature(2)
220
Hz
ppm
24 hour run time
Autocalibration mode operat-
TAC
(1)
60°C(1)
270
ppm
ppm
60
°C
Timing accuracy is specified at 25°C after digital calibration of the internal RC oscillator and 32.768 kHz crystal. A typical
32.768 kHz tuning fork crystal has a negative temperature coefficient with a parabolic frequency deviation, which can
result in a change of up to 150 ppm across the entire operating temperature range of -40°C to 85°C in XT mode. Autocalibration mode timing accuracy is specified relative to XT mode timing accuracy from -10°C to 60°C.
(2) Outside
of this temperature range, the RC oscillator frequency change due to temperature may be outside of the allowable
RC digital calibration range (+/-12%) for autocalibration mode. When this happens, an autocalibration failure will occur
and the ACF interrupt flag is set. The AMX8XX should be switched to use the XT oscillator as its clock source when this
occurs. Please see the Autocalibration Fail section for more details.
DS0002V1p0
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AM08XX Datasheet
Figure 4 shows the typical calibrated RC oscillator frequency variation vs. temperature. RC oscillator
calibrated at 2.8V, 25°C.
150
TA = 25 °C
145
RC Frequency (Hz)
140
135
VCC = 1.8V
130
VCC = 3.0V
125
120
‐40
‐30
‐20
115
‐10
0
10
20
30
40
Temperature (°C)
50
60
70
80
Figure 4. Calibrated RC Oscillator Typical Frequency Variation vs. Temperature
Figure 5 shows the typical uncalibrated RC oscillator frequency variation vs. temperature.
145
TA = 25 °C
RC Frequency (Hz)
140
135
130
VCC = 1.8V
125
VCC = 3.0V
120
‐40
‐30
‐20
115
‐10
0
10
20
30
40
Temperature (°C)
50
60
70
80
Figure 5. Uncalibrated RC Oscillator Typical Frequency Variation vs. Temperature
DS0002V1p0
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AM08XX Datasheet
4.5 VCC Supply Current
Table 8 lists the current supplied into the VCC power input under various conditions.

For Table 8, TA = -40 °C to 85 °C, VBAT = 0 V to 3.6 V
TYP values at 25 °C, MAX values at 85 °C, VCC Power state
Table 8: VCC Supply Current
SYMBOL
PARAMETER
TEST CONDITIONS
VCC
TYP
MAX
400kHz bus speed, 2.2k pull-up
resistors on SCL/SDA(1)
3.0V
6
10
1.8V
1.5
3
3.0V
8
12
1.8V
4
6
3.0V
23
37
1.8V
13
21
Time keeping mode with XT
3.0V
55
330
oscillator running(3)
1.8V
51
290
Time keeping mode with only
the RC oscillator running (XT
3.0V
14
220
oscillator is off)(3)
1.8V
11
170
Time keeping mode with only
RC oscillator running and Autocalibration enabled. ACP =
3.0V
22
235
1.8V
18
190
Time keeping mode with XT
oscillator running, 32.786 kHz
3.0V
3.6
8
square wave on CLKOUT(4)
1.8V
2.2
5
All time keeping modes, 128 Hz
3.0V
7
35
square wave on CLKOUT(4)
1.8V
2.5
20
IVCC:I2C
VCC supply current during I2C
burst read/write
IVCC:SPIW
VCC supply current during SPI
burst write
2 MHz bus speed (2)
IVCC:SPIR
VCC supply current during SPI
burst read
2 MHz bus speed (2)
IVCC:XT
VCC supply current in XT oscillator mode
IVCC:RC
VCC supply current in RC oscillator mode
IVCC:ACAL
Average VCC supply current in
Autocalibrated RC oscillator
mode
IVCC:CK32
Additional VCC supply current
with CLKOUT at 32.786 kHz
IVCC:CK128
Additional VCC supply current
with CLKOUT at 128 Hz
512 seconds(3)
MIN
UNIT
µA
µA
µA
nA
nA
nA
µA
nA
(1) Excluding
external peripherals and pull-up resistor current. All other inputs (besides SDA and SCL) are at 0V or VCC.
AM080X only. Test conditions: Continuous burst read/write, 0x55 data pattern, 25 s between each data byte, 20 pF load
on each bus pin.
(2) Excluding
external peripheral current. All other inputs (besides SDI, nCE and SCL) are at 0V or VCC. AM081X only. Test
conditions: Continuous burst write, 0x55 data pattern, 25 s between each data byte, 20 pF load on each bus pin.
(3)
All inputs and outputs are at 0 V or VCC.
(4) All
inputs and outputs except CLKOUT are at 0 V or VCC. 15 pF capacitive load on CLKOUT.
DS0002V1p0
Page 20 of 81
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AM08XX Datasheet
Figure 6 shows the typical VCC power state operating current vs. temperature in XT mode.
VCC Power State, XT Mode Current (nA)
130
TA = 25 °C
120
110
100
90
80
VCC = 3.0V
70
60
VCC = 1.8V
50
40
‐40
‐30
‐20
‐10
0
10
20
30
40
Temperature (°C)
50
60
70
80
Figure 6. Typical VCC Current vs. Temperature in XT Mode
Figure 7 shows the typical VCC power state operating current vs. temperature in RC mode.
VCC Power State, RC Mode Current (nA)
75
TA = 25 °C
65
55
45
35
VCC = 3.0V
25
VCC = 1.8V
15
5
‐40
‐30
‐20
‐10
0
10
20
30
40
Temperature (°C)
50
60
70
80
Figure 7. Typical VCC Current vs. Temperature in RC Mode
DS0002V1p0
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AM08XX Datasheet
Figure 8 shows the typical VCC power state operating current vs. temperature in RC Autocalibration mode.
55
VCC Power State, Autocal Mode Current (nA)
TA = 25 °C
50
45
40
35
30
VCC = 3.0V
25
20
VCC = 1.8V
15
10
5
‐40
‐30
‐20
‐10
0
10
20
30
40
50
60
70
Temperature (°C)
Figure 8. Typical VCC Current vs. Temperature in RC Autocalibration Mode
Figure 9 shows the typical VCC power state operating current vs. voltage for XT Oscillator and RC
Oscillator modes and the average current in RC Autocalibrated mode.
70
TA = 25 °C
VCC Power State Current (nA)
60
XT Oscillator Mode
50
40
30
RC Autocalibrated Mode
20
10
RC Oscillator Mode
0
1.5
2
2.5
3
3.5
VCC Voltage (V)
Figure 9. Typical VCC Current vs. Voltage, Different Modes of Operation
DS0002V1p0
Page 22 of 81
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AM08XX Datasheet
Figure 10 shows the typical VCC power state operating current during continuous I2C and SPI burst read
and write activity. Test conditions: TA = 25 °C, 0x55 data pattern, 25 s between each data byte, 20 pF
load on each bus pin, pull-up resistor current not included.
30
TA = 25 °C
VCC Current (µA)
25
20
SPI Burst Read
15
10
SPI Burst Write
5
I2 C Burst Read/Write
0
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC Voltage (V)
Figure 10. Typical VCC Current vs. Voltage, I²C and SPI Burst Read/Write
Figure 11 shows the typical VCC power state operating current with a 32.768 kHz clock output on the
CLKOUT pin. Test conditions: TA = 25 °C, All inputs and outputs except CLKOUT are at 0 V or VCC. 15 pF
capacitive load on the CLKOUT pin.
5
TA = 25 °C
VCC Current (µA)
4
3
2
1
0
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC Voltage (V)
Figure 11. Typical VCC Current vs. Voltage, 32.768 kHz Clock Output
DS0002V1p0
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AM08XX Datasheet
4.6 VBAT Supply Current
Table 9 lists the current supplied into the VBAT power input under various conditions.

For Table 9, TA = -40 °C to 85 °C, TYP values at 25 °C, MAX values at 85 °C, VBAT Power state.
Table 9: VBAT Supply Current
SYMBOL
PARAMETER
IVBAT:XT
VBAT supply current in
XT oscillator mode
IVBAT:RC
VBAT supply current in
RC oscillator mode
IVBAT:ACAL
Average VBAT supply
current in Autocalibrated
RC oscillator mode
IVBAT:VCC
(1)
VBAT supply current in
VCC powered mode
VCC
TEST CONDITIONS
Time keeping mode with
XT oscillator running
(1)
Time keeping mode with
only the RC oscillator running (XT oscillator is off)(1)
Time keeping mode with
the RC oscillator running.
Autocalibration enabled.
ACP = 512 seconds
VBAT
< VCCSWF
< VCCSWF
< VCCSWF
(1)
VCC powered mode(1)
1.7 - 3.6 V
MIN
TYP
MAX
3.0V
56
330
1.8V
52
290
3.0V
16
220
1.8V
12
170
3.0V
24
235
1.8V
20
190
3.0V
-5
0.6
20
1.8V
-10
0.5
16
UNIT
nA
nA
nA
nA
Test conditions: All inputs and outputs are at 0 V or VCC.
Figure 12 shows the typical VBAT power state operating current vs. temperature in XT mode.
VBAT Power State, XT Mode Current (nA)
130
TA = 25 °C
120
110
100
90
80
VBAT = 3.0V
70
60
VBAT = 1.8V
50
40
‐40
‐30
‐20
‐10
0
10
20
30
40
50
60
70
80
Temperature (°C)
Figure 12. Typical VBAT Current vs. Temperature in XT Mode
DS0002V1p0
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AM08XX Datasheet
Figure 13 shows the typical VBAT power state operating current vs. temperature in RC mode.
VBAT Power State, RC Mode Current (nA)
75
TA = 25 °C
65
55
45
35
VBAT = 3.0V
25
VBAT = 1.8V
15
5
‐40
‐30
‐20
‐10
0
10
20
30
40
50
60
70
80
Temperature (°C)
Figure 13. Typical VBAT Current vs. Temperature in RC Mode
Figure 14 shows the typical VBAT power state operating current vs. temperature in RC Autocalibration
mode.
VBAT Power State, Autocal Mode Current (nA)
55
TA = 25 °C
50
45
40
35
30
VBAT = 3.0V
25
20
VBAT = 1.8V
15
10
5
‐40
‐30
‐20
‐10
0
10
20
30
40
50
60
70
Temperature (°C)
Figure 14. Typical VBAT Current vs. Temperature in RC Autocalibration Mode
DS0002V1p0
Page 25 of 81
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AM08XX Datasheet
Figure 15 shows the typical VBAT power state operating current vs. voltage for XT Oscillator and RC
Oscillator modes and the average current in RC Autocalibrated mode, VCC = 0 V.
70
TA = 25 °C
VBAT Current (nA)
60
50
XT Oscillator Mode
40
30
RC Autocalibrated Mode
20
10
RC Oscillator Mode
0
1.5
2
2.5
VBAT Voltage (V)
3
3.5
Figure 15. Typical VBAT Current vs. Voltage, Different Modes of Operation
Figure 16 shows the typical VBAT current when operating in the VCC power state, VCC = 1.7 V.
0.9
TA = 25 °C, VCC = 1.7 V
0.8
VBAT Current (nA)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.5
2
2.5
VBAT Voltage (V)
3
3.5
Figure 16. Typical VBAT Current vs. Voltage in VCC Power State
DS0002V1p0
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AM08XX Datasheet
4.7 BREF Electrical Characteristics
Table 10 lists the parameters of the VBAT voltage thresholds. BREF values other than those listed in the
table are not supported.

For Table 10, TA = -20 °C to 70 °C, TYP values at 25 °C, VCC = 1.7 to 3.6V.
Table 10: BREF Parameters
SYMBOL
VBRF
PARAMETER
VBAT falling threshold
BREF
MIN
TYP
MAX
0111
2.3
2.5
3.3
1011
1.9
2.1
2.8
1101
1.6
1.8
2.5
1111
VBRR
VBRH
TBR
VBAT rising threshold
VBAT threshold hysteresis
VBAT analog comparator recommended operating temperature range
V
1.4
0111
2.6
3.0
3.4
1011
2.1
2.5
2.9
1101
1.9
2.2
2.7
1111
1.6
0111
0.5
1011
0.4
1101
0.4
1111
0.2
All values
UNIT
V
V
-20
70
°C
4.8 I²C AC Electrical Characteristics
Figure 17 and Table 11 describe the I2C AC electrical parameters.
SDA
tBUF
tLOW
tHD:DAT
tSU:DAT
SCL
tHD:STA
tRISE
tFALL
tHIGH
tSU:STO
SDA
tSU:STA
Figure 17. I²C AC Parameter Definitions
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AM08XX Datasheet

For Table 11, TA = -40 °C to 85 °C, TYP values at 25 °C.
Table 11: I²C AC Electrical Parameters
SYMBOL
PARAMETER
VCC
MIN
TYP
MAX
UNIT
400
kHz
fSCL
SCL input clock frequency
1.7V-3.6V
10
tLOW
Low period of SCL clock
1.7V-3.6V
1.3
µs
tHIGH
High period of SCL clock
1.7V-3.6V
600
ns
tRISE
Rise time of SDA and SCL
1.7V-3.6V
300
ns
tFALL
Fall time of SDA and SCL
1.7V-3.6V
300
ns
tHD:STA
START condition hold time
1.7V-3.6V
600
ns
tSU:STA
START condition setup time
1.7V-3.6V
600
ns
tSU:DAT
SDA setup time
1.7V-3.6V
100
ns
tHD:DAT
SDA hold time
1.7V-3.6V
0
ns
tSU:STO
STOP condition setup time
1.7V-3.6V
600
ns
tBUF
Bus free time before a new transmission
1.7V-3.6V
1.3
µs
4.9 SPI AC Electrical Characteristics
Figure 18, Figure 19, and Table 12 describe the SPI AC electrical parameters.
tBUF
nCE
tSU:NCE
tHD:NCE
tLOW
tHIGH
SCL
tSU:SDI
SDI
tSU:CE
tFALL
tHD:SDI
MSB IN
tRISE
LSB IN
Figure 18. SPI AC Parameter Definitions – Input
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AM08XX Datasheet
nCE
SCL
tSU:SDO
tHD:SDO
SDO
tHZ
MSB OUT
LSB OUT
SDI ADDR LSB
Figure 19. SPI AC Parameter Definitions – Output

For Table 12, TA = -40 °C to 85 °C, TYP values at 25 °C.
Table 12: SPI AC Electrical Parameters
SYMBOL
PARAMETER
VCC
MIN
TYP
MAX
UNIT
2
MHz
fSCL
SCL input clock frequency
1.7V–3.6V
0.01
tLOW
Low period of SCL clock
1.7V–3.6V
200
ns
tHIGH
High period of SCL clock
1.7V–3.6V
200
ns
tRISE
Rise time of all signals
1.7V–3.6V
1
µs
tFALL
Fall time of all signals
1.7V–3.6V
1
µs
tSU:NCE
nCE low setup time to SCL
1.7V–3.6V
200
ns
tHD:NCE
nCE hold time to SCL
1.7V–3.6V
200
ns
tSU:CE
nCE high setup time to SCL
1.7V–3.6V
200
ns
tSU:SDI
SDI setup time
1.7V–3.6V
40
ns
tHD:SDI
SDI hold time
1.7V–3.6V
50
ns
tSU:SDO
SDO output delay from SCL
1.7V–3.6V
tHD:SDO
SDO output hold from SCL
1.7V–3.6V
tHZ
SDO output Hi-Z from nCE
1.7V–3.6V
tBUF
nCE high time before a new transmission
1.7V–3.6V
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150
0
ns
250
200
ns
ns
ns
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AM08XX Datasheet
4.10 Power On AC Electrical Characteristics
Figure 20 and Table 13 describe the power on AC electrical characteristics for the FOUT pin and XT
oscillator.
VCC
tLOW:VCC
VCCRST
VCCST
tVH:FOUT
FOUT tVL:FOUT
tXTST
XT
Figure 20. Power On AC Electrical Characteristics

For Table 13, TA = -40 °C to 85 °C, VBAT < 1.2 V
Table 13: Power On AC Electrical Parameters
SYMBOL
tLOW:VCC
tVL:FOUT
tVH:FOUT
tXTST
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PARAMETER
Low period of VCC to ensure a valid POR
VCC low to FOUT low
VCC high to FOUT high
FOUT high to XT oscillator start
VCC
1.7V–3.6V
1.7V–3.6V
1.7V–3.6V
1.7V–3.6V
Page 30 of 81
TA
MIN
TYP
85 °C
0.1
25 °C
0.1
-20 °C
1.5
-40 °C
10
85 °C
0.1
25 °C
0.1
-20 °C
1.5
-40 °C
10
85 °C
0.4
25 °C
0.5
-20 °C
3
-40 °C
20
85 °C
0.4
25 °C
0.4
-20 °C
0.5
-40 °C
1.5
MAX
UNIT
s
s
s
s
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AM08XX Datasheet
5.
Functional Description
Figure 21 illustrates the AM08XX functional design.
VCC VBAT
nCE
SDI
SCL
SDA/O
I2C/SPI
Interface
Power
Control
Analog
Compare
100ths
Seconds
Minutes
Hours
Days
Weekdays
Months
Calibration Engine
Years
XO
XT Osc
Alarms
Timer
Divider
WDT
XI
Control
RC Osc
Divider
RAM
WDI
EXTI
Int/Clock
FOUT/nIRQ
nIRQ2
nTIRQ
CLKOUT/nIRQ3
VSS
Figure 21. Detailed Block Diagram
The AM08XX serves as a full function RTC for host processors such as microcontrollers. The AM08XX
includes 3 distinct feature groups: 1) baseline timekeeping features, 2) advanced timekeeping features,
and 3) basic power management features. Functions from each feature group may be controlled via I/O
offset mapped registers. These registers are accessed using either an I2C serial interface (e.g., in the
AM0805) or a SPI serial interface (e.g., in the AM0815). Each feature group is described briefly below and
in greater detail in subsequent sections.
The baseline timekeeping feature group supports the standard 32.786 kHz crystal (XT) oscillation mode for
maximum frequency accuracy with an ultra-low current draw of 55 nA. The baseline timekeeping feature
group also includes a standard set of counters monitoring hundredths of a second up through centuries. A
complement of countdown timers and alarms may additionally be set to initiate interrupts or resets on
several of the outputs.
The advanced timekeeping feature group supports two additional oscillation modes: 1) RC oscillator mode,
and 2) Autocalibration mode. At only 14 nA, the temperature-compensated RC oscillator mode provides an
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AM08XX Datasheet
even lower current draw than the XT oscillator for applications with reduced frequency accuracy
requirements. A proprietary calibration algorithm allows the AM08XX to digitally tune the RC oscillator
frequency and the XT oscillator frequency with accuracy as low as 2 ppm at a given temperature. In
Autocalibration mode, the RC oscillator is used as the primary oscillation source and is periodically
calibrated against the XT oscillator. Autocalibration may be done automatically every 8.5 minutes or 17
minutes and may also be initiated via software. This mode enables average current draw of only 22 nA
with frequency accuracy similar to the XT oscillator. The advanced timekeeping feature group also
includes a rich set of input and output configuration options that enables the monitoring of external
interrupts (e.g., pushbutton signals), the generation of clock outputs, and watchdog timer functionality.
Power management features built into the AM08XX enable it to operate as a backup device in both linepowered and battery-powered systems. An integrated power control module automatically detects when
main power (VCC) falls below a threshold and switches to backup power (VBAT). Up to 256B of ultra-low
leakage RAM enable the storage of key parameters when operating on backup power. The AM08XX also
includes digitally-tunable voltage detection on the backup power supply. VBAT power switching is included
in the AM0803, AM0813, AM0813 and AM0815 parts only.
Each functional block is explained in detail in the remainder of this section. The functional descriptions
refer to the registers shown in the Register Definitions (0x00 to 0x0F) and Register Definitions (0x10 to
0xFF) tables. A detailed description of all registers can be found in the Registers section of this document.
5.1 I²C Interface
The AM08XX includes a standard I2C interface. The device is accessed at addresses 0xD2/D3, and
supports Fast Mode (up to 400 kHz). The I2C interface consists of two lines: one bi-directional data line
(SDA) and one clock line (SCL). Both the SDA and the SCL lines must be connected to a positive supply
voltage via a pull-up resistor. By definition, a device that sends a message is called the “transmitter”, and
the device that accepts the message is called the “receiver”. The device that controls the message transfer
by driving SCL is called “master”. The devices that are controlled by the master are called “slaves”. The
AM08XX is always a slave device.
I2C termination resistors should be above 2.2 kΩ, and for systems with short I2C bus wires/traces and few
connections these terminators can typically be as large as 22 kΩ (for 400 kHz operation) or 56 kΩ (for 100
kHz operation). Larger resistors will produce lower system current consumption.
The following protocol has been defined:
▪ Data transfer may be initiated only when the bus is not busy.
▪ During data transfer, the data line must remain stable whenever the clock line is high.
▪ Changes in the data line while the clock line is high will be interpreted as control signals.
A number of bus conditions have been defined (see Figure 22) and are described in the following sections.
SDA may
change
Not Busy
SCL
SDA
START
SDA Stable
STOP
Figure 22. Basic I²C Conditions
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5.1.1
Bus Not Busy
Both SDA and SCL remain high.
5.1.2
Start Data Transfer
A change in the state of SDA from high to low, while SCL is high, defines the START condition. A START
condition which occurs after a previous START but before a STOP is called a RESTART condition, and
functions exactly like a normal STOP followed by a normal START.
5.1.3
Stop Data Transfer
A change in the state of SDA from low to high, while SCL is high, defines the STOP condition.
5.1.4
Data Valid
After a START condition, SDA is stable for the duration of the high period of SCL. The data on SDA may be
changed during the low period of SCL. There is one clock pulse per bit of data. Each data transfer is
initiated with a START condition and terminated with a STOP condition. The number of data bytes
transferred between the START and STOP conditions is not limited. The information is transmitted bytewide and each receiver acknowledges with a ninth bit.
5.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge (ACK) bit as shown in Figure 23. This acknowledge
bit is a low level driven onto SDA by the receiver, whereas the master generates an extra acknowledge
related SCL pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, on a read transfer a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges
must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a
stable low during the high period of the acknowledge related SCL pulse. A master receiver must signal an
end-of-data to the slave transmitter by not generating an acknowledge (a NAK) on the last byte that has
been clocked out of the slave. In this case, the transmitter must leave the data line high to enable the
master to generate the STOP condition.
SCL
1
2
8
9
SDA
MSB (bit 7)
Bit 6
Bit 0
ACK
START
Figure 23. I²C Acknowledge Address Operation
Figure 24 illustrates the operation with which the master addresses the AM08XX. After the START
condition, a 7-bit address is transmitted MSB first. If this address is 0b1101001 (0xD2/3), the AM08XX is
selected, the eighth bit indicate a write (RW = 0) or a read (RW = 1) operation and the AM08XX supplies
the ACK. The AM08XX ignores all other address values and does not respond with an ACK
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AM08XX Datasheet
.
SDA
1
1
0
1
0
0
R
W
0
A
SCL
Figure 24. I²C Address Operation
5.1.6
Offset Address Transmission
If the RW bit of the Address Operation indicates a write, the next byte transmitted from the master is the
Offset Address as shown in Figure 25. This value is loaded into the Address Pointer of the AM08XX.
Offset Address
SDA
1
1
0
1
0
0
0
0
A
7
6
5
4
3
2
1
0
A
SCL
Figure 25. I²C Offset Address Transmission
5.1.7
Write Operation
In a write operation the master transmitter transmits to the AM08XX slave receiver. The Address Operation
has a RW value of 0, and the second byte contains the Offset Address as in Figure 25. The next byte is
written to the register selected by the Address Pointer (which was loaded with the Offset Address) and the
Address Pointer is incremented. Subsequent transfers write bytes into successive registers until a STOP
condition is received, as shown in Figure 26.
Byte N
SDA
Addr
W
A
Offset
A
7
Byte N+1
0
A
7
0
Byte N+2
A
7
0
A
SCL
Figure 26. I²C Write Operation
5.1.8
Read Operation
In a read operation, the master first executes an Offset Address Transmission to load the Address Pointer
with the desired Offset Address. A subsequent operation will again issue the address of the AM08XX but
with the RW bit as a 1 indicating a read operation. Figure 27 illustrates this transaction beginning with a
RESTART condition, although a STOP followed by a START may also be used. After the address
operation, the slave becomes the transmitter and sends the register value from the location pointed to by
the Address Pointer, and the Address Pointer is incremented. Subsequent transactions produce
successive register values, until the master receiver responds with a NAK and/or STOP or RESTART to
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AM08XX Datasheet
complete the operation. Because the Address Pointer holds a valid register address, the master may
initiate another read sequence at this point without performing another Offset Address operation.
Byte N
SDA
Addr
W
A
Offset
A
Addr
R
A
7
Byte N+1
0
A
7
0
N
SCL
RESTART
Figure 27. I²C Read Operation
5.2 SPI Interface
The AM08XX includes a standard 4-wire SPI interface. The serial peripheral interface (SPI) bus is intended
for synchronous communication between different ICs. It typically consists of four signal lines: serial data
input (SDI), serial data output (SDO), serial clock (SCL) and an active low chip enable (nCE).
The AM08XX may be connected to a master with a 3-wire SPI interface by tying SDI and SDO together. By
definition, a device that sends a message is called the “transmitter”, and the device that accepts the
message is called the “receiver.” The device that controls the message transfer by driving SCL is called
“master.” The devices that are controlled by the master are called “slaves”. The AM08XX is always a slave
device.
The nCE input is used to initiate and terminate a data transfer. The SCL input is used to synchronize data
transfer between the master and the slave devices via the SDI (master to slave) and SDO (slave to
master) lines. The SCL input, which is generated by the master, is active only during address and data
transfer to any device on the SPI bus.
The AM08XX supports clock frequencies up to 2 MHz, and responds to either (CPOL = 0, CPAH = 0 or
CPOL = 1, CPAH = 1). For these two modes, input data (SDI) is latched in by the low-to-high transition of
clock SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL. There is one clock for
each bit transferred. Address and data bits are transferred in groups of eight bits. Some MCUs specify
CPOL and CPAH in different ways, so care should be taken when configuring the SPI Master.
5.2.1
Write Operation
Figure 28 illustrates a SPI write operation. The operation is initiated when the nCE signal to the AM08XX
goes low. At that point an 8-bit Address byte is transmitted from the master on the SDI line, with the upper
RW bit indicating read (if 0) or write (if 1). In this example the RW bit is a one selecting a write operation,
and the lower 7 bits of the Address byte contain the Offset Address, which is loaded into the Address
Pointer of the AM08XX.
Each subsequent byte is loaded into the register selected by the Address Pointer, and the Address Pointer
is incremented. Because the address is only 7 bits long, only the lower 128 registers of the AM08XX may
be accessed via the SPI interface. The operation is terminated by the master by bringing the nCE signal
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AM08XX Datasheet
high. Note that the SDO line is not used in a write operation and is held in the high impedance state by the
AM08XX.
Offset Address
SDI
X
W
6
5
4
3
2
Data Byte N
1
0
7
6
5
4
3
Data Byte N+1
2
1
0
7
6
5
4
3
2
1
0
X
SDO
SCL
nCE
Figure 28. SPI Write Operation
5.2.2
Read Operation
Figure 29 illustrates a read operation. The address is transferred from the master to the slave just as it is in
a write operation, but in this case the RW bit is a 0 indicating a read. After the transfer of the last address
bit, bit 0, the AM08XX begins driving data from the register selected by the Address Pointer onto the SDO
line, bit 7 first, and the Address Pointer is incremented. The transfer continues until the master brings the
nCE line high.
Offset Address
SDI
X
R
6
5
4
3
2
SDO
Data Byte N
1
Data Byte N+1
0
X
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCL
nCE
Figure 29. SPI Read Operation
5.3 XT Oscillator
The AM08XX includes a very power efficient crystal (XT) oscillator which runs at 32.786 kHz. This
oscillator is selected by setting the OSEL bit to 0 and includes a low jitter calibration function.
5.4 RC Oscillator
The AM08XX includes an extremely low power RC oscillator which runs at 128 Hz. This oscillator is
selected by setting the OSEL bit to 1. Switching between the XT and RC Oscillators is guaranteed to
produce less than one second of error in the Calendar Counters. The AM08XX may be configured to
automatically switch to the RC Oscillator when VCC drops below its threshold by setting the AOS bit, and/
or be configured to automatically switch if an XT Oscillator failure is detected by setting the FOS bit.
5.5 RTC Counter Access
When reading any of the counters in the RTC using a burst operation, the 1 Hz and 100 Hz clocks are held
off during the access. This guarantees that a single burst will either read or write a consistent timer value
(other than the Hundredths Counter – see Hundredths Synchronization). There is a watchdog function to
ensure that a very long pause on the interface does not cause the RTC to lose a clock.
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AM08XX Datasheet
On a write to any of the Calendar Counters, the entire timing chain up to 100 Hz (if the XT Oscillator is
selected) or up to 1Hz (if the RC Oscillator is selected) is reset to 0. This guarantees that the Counters will
begin counting immediately after the write is complete, and that in the XT oscillator case the next 100 Hz
clock will occur exactly 10 ms later. In the RC Oscillator case, the next 1 Hz clock will occur exactly 1
second later. This allows a burst write to configure all of the Counters and initiate a precise time start. Note
that a Counter write may cause one cycle of a Square Wave output to be of an incorrect period.
The WRTC bit must be set in order to write to any of the Counter registers. This bit can be cleared to
prevent inadvertent software access to the Counters.
5.6 Hundredths Synchronization
If the Hundredths Counter is read as part of the counter burst, there is a small probability (approximately 1
in 109) that the Hundredths Counter rollover from 99 to 00 and the Seconds Counter increment will be
separated by the read. In this case, correct read information can be guaranteed by the following algorithm.
1.
2.
3.
Read the Counters, using a burst read. If the Hundredths Counter is neither 00 nor 99, the read is correct.
If the Hundredths Counter was 00, perform the read again. The resulting value from this second read
is guaranteed to be correct.
If the Hundredths Counter was 99, perform the read again.
A. If the Hundredths Counter is still 99, the results of the first read are guaranteed to be correct.
Note that it is possible that the second read is not correct.
B. If the Hundredths Counter has rolled over to 00, and the Seconds Counter value from the second read is equal to the Seconds Counter value from the first read plus 1, both reads produced
correct values. Alternatively, perform the read again. The resulting value from this third read is
guaranteed to be correct.
C. If the Hundredths Counter has rolled over to 00, and the Seconds Counter value from the second read is equal to the Seconds Counter value from the first read, perform the read again. The
resulting value from this third read is guaranteed to be correct.
5.7 Generating Hundredths of a Second
The generation of an exact 100 Hz signal for the Hundredths Counter requires a special logic circuit. The
2.048 kHz clock signal is divided by 21 for 12 iterations, and is alternately divided by 20 for 13 iterations.
This produces an effective division of:
(21 * 12 + 20 * 13)/25 = 20.48
producing an exact long-term average 100 Hz output, with a maximum jitter of less than 1 ms. The
Hundredths Counter is not available when the 128 Hz RC Oscillator is selected.
5.8 Watchdog Timer
The AM08XXincludes a Watchdog Timer (WDT), which can be configured to generate an interrupt or a
reset if it times out. The WDT is controlled by the Watchdog Timer Register (see 0x1B - Watchdog Timer).
The RB field selects the frequency at which the timer is decremented, and the BMB field determines the
value loaded into the timer when it is restarted. If the timer reaches a value of zero, the WDS bit
determines whether an interrupt is generated in nIRQ. The timer reaching zero sets the WDT flag in the
Status Register, which may be cleared by setting the WDT flag to zero.
Two actions will restart the WDT timer:
1.
2.
Writing the Watchdog Timer Register with a new watchdog value.
A change in the level of the WDI pin.
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If the Watchdog Timer generates an interrupt or reset, the Watchdog Timer Register must be written in
order to restart the Watchdog Timer function. If the BMB field is 0, the Watchdog Timer function is disabled.
The BMB field describes the maximum timeout delay. For example, if RB = 01 so that the clock period is
250 ms, a BMB value of 9 implies that the timeout will occur between 2000 ms and 2250 ms after writing
the Watchdog Timer Register.
5.9 Digital Calibration
5.9.1
XT Oscillator Digital Calibration
In order to improve the accuracy of the XT oscillator, a Distributed Digital Calibration function is included
(see 0x14 - Calibration XT). This function uses a calibration value, OFFSETX, to adjust the clock period
over a 16 second or 32 second calibration period. When the 32.786 kHz XT oscillator is selected, the clock
at the 16.384 kHz level of the divider chain is modified on a selectable interval. Clock pulses are either
added or subtracted to ensure accuracy of the counters. If the CMDX bit is a 0 (normal calibration),
OFFSETX cycles of the 16.384 kHz clock are gated (negative calibration) or replaced by 32.786 kHz
pulses (positive calibration) within every 32 second calibration period. In this mode, each step in OFFSETX
modifies the clock frequency by 1.907 ppm, with a maximum adjustment of ~+120/-122 ppm. If the CMDX
bit is 1 (coarse calibration), OFFSETX cycles of the 16.384 kHz clock are gated or replaced by the 32.786
kHz clock within every 16 second calibration period. In this mode, each step in OFFSETX modifies the
clock frequency by 3.814 ppm, with a maximum adjustment of ~+240/-244 ppm. OFFSETX contains a
two's complement value, so the possible steps are from -64 to +63. Note that unlike other implementations,
Distributed Digital Calibration guarantees that the clock is precisely calibrated every 32 seconds with
normal calibration and every 16 seconds when coarse calibration is selected.
In addition to the normal calibration, the AM08XX also includes an Extended Calibration field to
compensate for low capacitance environments. The frequency generated by the Crystal Oscillator may be
slowed by 122 ppm times the value in the XTCAL (see 0x1D – Oscillator Status Register) field (0, -122,244 or -366 ppm). The clock is still precisely calibrated in 16 or 32 seconds. The pulses which are added to
or subtracted from the 16.384 kHz clock are spread evenly over each 16 or 32 second period using the
Ambiq Micro patented Distributed Calibration algorithm. This ensures that in XT mode the maximum cycleto-cycle jitter in any clock of a frequency 16.384 kHz or lower caused by calibration will be no more than
one 16.384 kHz period. This maximum jitter applies to all clocks in the AM08XX, including the Calendar
Counter, Countdown Timer and Watchdog Timer clocks and any clock driven onto the CLKOUT/nIRQ pin.
The XT oscillator calibration value is determined by the following process:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Set the OFFSETX, CMDX and XTCAL register fields to 0 to ensure calibration is not occurring.
Select the XT oscillator by setting the OSEL bit to 0.
Configure a square wave output on one of the output pins of frequency Fnom (for example, 16 Hz).
Measure the frequency Fmeas at the output pin in Hz.
Compute the adjustment value required in ppm as ((32768 – Fmeas)*1000000)/32768 = PAdj
Compute the adjustment value in steps as PAdj/(1000000/2^19) = PAdj/(1.90735) = Adj
If Adj < -320, the XT frequency is too high to be calibrated
Else if Adj < -256, set XTCAL = 3, CMDX = 1, OFFSETX = (Adj +192)/2
Else if Adj < -192, set XTCAL = 3, CMDX = 0, OFFSETX = Adj +192
Else if Adj < -128, set XTCAL = 2, CMDX = 0, OFFSETX = Adj +128
Else if Adj < -64, set XTCAL = 1, CMDX = 0, OFFSETX = Adj + 64
Else if Adj < 64, set XTCAL = 0, CMDX = 0, OFFSETX = Adj
Else if Adj < 128, set XTCAL = 0, CMDX = 1, OFFSETX = Adj/2
Else the XT frequency is too low to be calibrated
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AM08XX Datasheet
5.9.2
RC Oscillator Digital Calibration
The RC Oscillator has a patented Distributed Digital Calibration function similar to that of the XT Oscillator
(see 0x14 - Calibration XT). However, because the RC Oscillator has a greater fundamental variability, the
range of calibration is much larger, with four calibration ranges selected by the CMDR field. When the 128
Hz RC oscillator is selected, the clock at the 64 Hz level of the divider chain is modified on a selectable
interval using the calibration value OFFSETR. Clock pulses are either added or subtracted to ensure
accuracy of the counters. If the CMDR field is 00, OFFSETR cycles of the 64 Hz clock are gated (negative
calibration) or replaced by 128 Hz pulses (positive calibration) within every 8,192 second calibration
period. In this mode, each step in OFFSETR modifies the clock frequency by 1.907 ppm, with a maximum
adjustment of +15,623/-15,625 ppm (+/- 1.56%). If the CMDR field is 01, OFFSETR cycles of the 64 Hz
clock are gated or replaced by the 128 Hz clock within every 4,096 second calibration period. In this mode,
each step in OFFSETR modifies the clock frequency by 3.82 ppm, with a maximum adjustment of +31,246/
-31,250 ppm (+/-3.12%). If the CMDR field is 10, OFFSETR cycles of the 64 Hz clock are gated (negative
calibration) or replaced by 128 Hz pulses (positive calibration) within every 2,048 second calibration
period. In this mode, each step in OFFSETR modifies the clock frequency by 7.64 ppm, with a maximum
adjustment of +62,492/-62,500 ppm (+/- 6.25%). If the CMDR field is 11, OFFSETR cycles of the 64 Hz
clock are gated or replaced by the 128 Hz clock within every 1,024 second calibration period. In this mode,
each step in OFFSETR modifies the clock frequency by 15.28 ppm, with a maximum adjustment of
+124,984/-125,000 ppm (+/-12.5%). OFFSETR contains a two's complement value, so the possible steps
are from -8,192 to +8,191.
The pulses which are added to or subtracted from the 64 Hz clock are spread evenly over each 8,192
second period using the Ambiq Micro patented Distributed Calibration algorithm. This ensures that in RC
mode the maximum cycle-to-cycle jitter in any clock of a frequency 64 Hz or lower caused by calibration
will be no more than one 64 Hz period. This maximum jitter applies to all clocks in the AM08XX including
the Calendar Counter, Countdown Timer and Watchdog Timer clocks and any clock driven onto the
CLKOUT/nIRQ3 or FOUT/nIRQ pins.
The RC oscillator calibration value is determined by the following process:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Set the OFFSETR and CMDR register fields to 0 to ensure calibration is not occurring.
Select the RC oscillator by setting the OSEL bit to 1.
Configure a square wave output on one of the output pins of frequency Fnom (for example, 16 Hz).
Measure the frequency Fmeas at the output pin in Hz.
Compute the adjustment value required in ppm as ((128 – Fmeas)*1000000)/Fmeas = PAdj
Compute the adjustment value in steps as PAdj/(1000000/2^19) = PAdj/(1.90735) = Adj
If Adj < -65,536, the RC frequency is too high to be calibrated
Else if Adj < -32,768, set CMDR = 3, OFFSETR = Adj/8
Else if Adj < -16,384, set CMDR = 2, OFFSETR = Adj/4
Else if Adj < -8,192, set CMDR = 1, OFFSETR = Adj/2
Else if Adj < 8192, set CMDR = 0, OFFSETR = Adj
Else if Adj < 16,384, set CMDR = 1, OFFSETR = Adj/2
Else if Adj < 32,768, set CMDR = 2, OFFSETR = Adj/4
Else if Adj < 65,536, set CMDR = 3, OFFSETR = Adj/8
Else the RC frequency is too low to be calibrated
5.10 Autocalibration
The AM08XX includes a very powerful, patented automatic calibration feature, referred to as
Autocalibration, which allows the RC Oscillator to be automatically calibrated to the XT Oscillator. The XT
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Oscillator typically has much better stability than the RC Oscillator but the RC Oscillator requires
significantly less power. Autocalibration enables many system configurations to achieve accuracy and
stability similar to that of the XT Oscillator while drawing current similar to that of the RC Oscillator.
Autocalibration functions in two primary modes: XT Autocalibration Mode and RC Autocalibration Mode.
See Ambiq Application Note AN0002 – AM08XX Family Autocalibration for more details.
5.10.1 Autocalibration Operation
The Autocalibration operation counts the number of calibrated XT clock cycles within a specific period as
defined by the RC Oscillator and then loads new values into the Calibration RC Upper and RC Lower
registers which will then adjust the RC Oscillator output to match the XT frequency.
5.10.2 XT Autocalibration Mode
In XT Autocalibration Mode, the OSEL register bit is 0 and the AM08XX uses the XT Oscillator whenever
the system power VCC is above the VCCSWF voltage. The RC Oscillator is periodically automatically
calibrated to the XT Oscillator. If the AOS bit is set, when VCC drops below the VCCSWF threshold the
system will switch to using VBAT, the clocks will begin using the RC Oscillator, Autocalibration will be
disabled and the XT Oscillator will be disabled to reduce power requirements. Because the RC Oscillator
has been continuously calibrated to the XT Oscillator, it will be very accurate when the switch occurs.
When VCC is again above the threshold, the system will switch back to use the XT Oscillator and restart
Autocalibration.
5.10.3 RC Autocalibration Mode
In RC Autocalibration Mode, the OSEL register bit is 1 and the AM08XX uses the RC Oscillator at all times.
However, periodically the XT Oscillator is turned on and the RC Oscillator is calibrated to the XT Oscillator.
This allows the system to operate most of the time with the XT Oscillator off but allow continuous
calibration of the RC Oscillator.
5.10.4 Autocalibration Frequency and Control
The Autocalibration function is controlled by the ACAL field in the Oscillator Control register as shown in
Table 14. If ACAL is 00, no Autocalibration occurs. If ACAL is 10 or 11, Autocalibration occurs every 1024
or 512 seconds, which is referred to as the Autocalibration Period (ACXP). In RC Autocalibration Mode, an
Autocalibration operation results in the XT Oscillator being enabled for roughly 50 seconds. The 512
second Autocalibration cycles have the XT Oscillator enabled approximately 10% of the time, while 1024
second Autocalibration cycles have the XT Oscillator enabled approximately 4% of the time.
Table 14: Autocalibration Modes
ACAL Value
Calibration Mode
00
No Autocalibration
01
RESERVED
10
Autocalibrate every 1024seconds (~17minutes)
11
Autocalibrate every 512seconds (~9 minutes)
If ACAL is 00 and is then written with a different value, an Autocalibration cycle is immediately executed.
This allows Autocalibration to be completely controlled by software. As an example, software could choose
to execute an Autocalibration cycle every 2 hours by keeping ACAL at 00, getting a two hour interrupt
using the alarm function, generating an Autocalibration cycle by writing ACAL to 10 or 11, and then
returning ACAL to 00.
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5.10.5 Autocalibration Filter (AF) Pin
In order to produce the optimal accuracy for the Autocalibrated RC Oscillator, a filter pin AF is provided. A
47 pF capacitor should be connected between the AF pin and VSS. In order to enable the filter, the value
0xA0 must be written to the AFCTRL Register at address 0x26 (see 0x26 – AFCTRL). The AF filter is
disabled by writing 0x00 to the AFCTRL Register. No other values should be written to this register. The
Configuration Key Register must be written with the value 0x9D immediately prior to writing the AFCTRL
Register.
If the filter capacitor is not connected to the AF pin or is not enabled, the RC Oscillator frequency will
typically be between 10 and 50 ppm slower than the XT Oscillator. If the capacitor is connected to the AF
pin and enabled, the RC Oscillator frequency will be within the accuracy range specified in the Oscillator
Parameters table of the XT Oscillator.
5.10.6 Autocalibration Fail
If the operating temperature of the AM08XX exceeds the Autocalibration range specified in the Oscillator
Parameters table or internal adjustment parameters are altered incorrectly, it is possible that the basic
frequency of the RC Oscillator is so far away from the nominal 128 Hz value (off by more than 12%) that
the RC Calibration circuitry does not have enough range to correctly calibrate the RC Oscillator. If this
situation is detected during an Autocalibration operation, the ACF interrupt flag is set, an external interrupt
is generated if the ACIE register bit is set and the Calibration RC registers are not updated.
If an Autocalibration failure is detected while running in RC Autocalibration mode, it is advisable to switch
into XT Autocalibration mode to maintain the timing accuracy. This is done by first ensuring a crystal
oscillator failure has not occurred (OF flag = 0) and then clearing the OSEL bit. The ACAL field should
remain set to either 11 (512 second period) or 10 (1024 second period). After the switch occurs, the
OMODE bit is cleared.
While continuing to operate in XT Autocalibration mode, the following steps can be used to determine
when it is safe to return to RC Autocalibration mode.
1.
2.
3.
4.
5.
Clear the ACF flag and ACIE register bit.
Setup the Countdown Timer or Alarm to interrupt after the next Autocalibration cycle completes or longer time period.
After the interrupt occurs, check the status of the ACF flag.
If the ACF flag is set, it is not safe to return to RC Autocalibration mode. Clear the ACF flag and
repeat steps 2-4.
If the ACF flag is still cleared, it is safe to return to RC Autocalibration mode by setting the OSEL bit.
As mentioned in the RC oscillator section, switching between XT and RC oscillators is guaranteed to
produce less than one second of error. However, this error needs to be considered and can be safely
managed when implementing the steps above. For example, switching between oscillator modes every 48
hours will produce less than 6 ppm of error.
5.11 Oscillator Failure Detection
If the 32.786 kHz XT Oscillator generates clocks at less than 8 kHz for a period of more than 32 ms, the
AM08XX detects an Oscillator Failure. The Oscillator Failure function is controlled by several bits in the
Oscillator Control Register (see 0x1C Oscillator Control) and the Oscillator Status Register (see 0x1D Oscillator Status Register). The OF flag is set when an Oscillator Failure occurs, and is also set when the
AM08XX initially powers up. If the OFIE bit is set, the OF flag will generate an interrupt on IRQ.
If the FOS bit is set and the AM08XX is currently using the XT Oscillator, it will automatically switch to the
RC Oscillator on an Oscillator Failure. This guarantees that the system clock will not stop in any case. The
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OMODE bit indicates the currently selected oscillator, which will not match the oscillator requested by the
OSEL bit if the XT Oscillator is not running.
The OF flag will be set when the AM08XX powers up, and will also be set whenever the XT Oscillator is
stopped. This can happen when the STOP bit is set or the OSEL bit is set to 1 to select the RC Oscillator.
Since the XT Oscillator is stopped in RC Autocalibration mode (see RC Autocalibration Mode), OF will
always be set in this mode. The OF flag should be cleared whenever the XT Oscillator is enabled prior to
enabling the OF interrupt with OFIE.
5.12 Interrupts
The AM08XX may generate a variety of interrupts which are ORed into the IRQ signal. This may be driven
onto either the FOUT/nIRQ pin or the nIRQ2 pin depending on the configuration of the OUT1S and OUT2S
fields (see 0x11 - Control2).
5.12.1 Interrupt Summary
The possible interrupts are summarized in Table 15. All enabled interrupts are ORed into the IRQ signal
when their respective flags are set. Note that most interrupt outputs use the inverse of the interrupt (i.e.
nIRQ). The fields are:
▪ Interrupt - the name of the specific interrupt.
▪ Function - the functional area which generates the interrupt.
▪ Enable - the register bit which enables the interrupt. Note that for the Watchdog interrupt, WDS is the
steering bit, so that the flag generates an interrupt if WDS is 0 and a reset if WDS is 1. In either case, the
BMB field must be non-zero to generate the interrupt or reset.
▪ Pulse/Level - some interrupts may be configured to generate a pulse based on the register bits in this
column. "Level Only" implies that only a level may be generated, and the interrupt will only go away
when the flag is reset by software.
▪ Flag - the register bit which indicates that the function has occurred. Note that the flag being set will only
generate an interrupt signal on an external pin if the corresponding interrupt enable bit is also set.
Table 15: Interrupt Summary
Interrupt
Function
Enable
Pulse/Level
Flag
AIRQ
Alarm Match
AIE
IM
ALM
TIRQ
Countdown Timer
TIM
TM
TIM
WIRQ
Watchdog
!WDS
Level Only
WDT
BLIRQ
Battery Low
BLIE
Level Only
BL
X1IRQ
External 1
EX1E
Level Only
EX1
X2IRQ
External 2
EX2E
Level Only
EX2
OFIRQ
Oscillator Fail
OFIE
Level Only
OF
ACIRQ
Autocal Fail
ACIE
Level Only
ACF
5.12.2 Alarm Interrupt AIRQ
The AM08XX may be configured to generate the AIRQ interrupt when the values in the Time and Date
Registers match the values in the Alarm Registers. Which register comparisons are required to generate
AIRQ is controlled by the RPT field as described in the Repeat Function table, allowing software to specify
the interrupt interval. When an Alarm Interrupt is generated, the ALM flag is set and an external interrupt is
generated based on the AIE bit and the pin configuration settings. The IM field controls the period of the
external interrupt, including both level and pulse configurations.
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5.12.3 Countdown Timer Interrupt TIRQ
The AM08XX may be configured to generate the TIRQ interrupt when the Countdown Timer is enabled by
the TE bit and reaches the value of zero, which will set the TIM flag. The TM, TRPT and TFS fields control
the interrupt timing (see 0x18 - Countdown Timer Control), and the TIE bit and the pin configuration
settings control external interrupt generation. The Timer interrupt is always driven onto the nTIRQ pin if it is
available, and may also be driven onto the CLKOUT/nIRQ3 pin by a configuration of the SQFS field (see
0x13 - SQW).
5.12.4 Watchdog Timer Interrupt WIRQ
The AM08XX may be configured to generate the WIRQ interrupt when the Watchdog Timer reaches its
timeout value. This sets the WDT flag and is described in Watchdog Timer.
5.12.5 Battery Low Interrupt BLIRQ
The AM08XX may be configured to generate the BLIRQ when the voltage on the VBAT pin crosses one of
the thresholds set by the BREF field. The polarity of the detected crossing is set by the BPOL bit.
5.12.6 External Interrupts X1IRQ and X2IRQ
The AM08XX may be configured to generate the X1IRQ and X2IRQ interrupts when the EXTI (X1IRQ) or
WDI (X2IRQ) inputs toggle. The register bits EX1P and EX2P control whether the rising or falling
transitions generate the respective interrupt. Changing EX1P or EX2P may cause an immediate interrupt,
so the corresponding interrupt flag should be cleared after changing these bits.
The values of the EXTI and WDI pins may be directly read in the EXIN and WDIN register bits (see 0x3F Extension RAM Address). By connecting an input such as a pushbutton to both EXTI and WDI, software
can debounce the switch input using software configurable delays.
5.12.7 Oscillator Fail Interrupt OFIRQ
The AM08XX may be configured to generate the OFIRQ interrupt if the XT oscillator fails (see Oscillator
Failure Detection).
5.12.8 Autocalibration Fail Interrupt ACIRQ
The AM08XX may be configured to generate the ACIRQ interrupt if an Autocalibration operation fails (see
Autocalibration Fail).
5.12.9 Servicing Interrupts
When an interrupt is detected, software must clear the interrupt flag in order to prepare for a subsequent
interrupt. If only a single interrupt is enabled, software may simply write a zero to the corresponding
interrupt flag to clear the interrupt. However, because all of the flags in the Status register are written at
once, it is possible to clear an interrupt which has not been detected yet if multiple interrupts are enabled.
The ARST register bit is provided to ensure that interrupts are not lost in this case. If ARST is a 1, a read of
the Status register will produce the current state of all the interrupt flags and then clear them. An interrupt
occurring at any time relative to this read is guaranteed to either produce a 1 on the Status read, or to set
the corresponding flag after the clear caused by the Status read. After servicing all interrupts which
produced 1s in the read, software should read the Status register again until it returns all zeros in the flags,
and service any interrupts with flags of 1.
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Note that the OF and ACF interrupts are not handled with this process because they are in the Oscillator
Status register, but error interrupts are very rare and typically do not create any problems if the interrupts
are cleared by writing the flag directly.
5.13 Power Control and Switching
The main power supply to the AM08XX is the VCC pin, which operates over the range specified by the
VCCIO parameter if there are I/O interface operations required, and the range specified by the VCC
parameter if only timekeeping operations are required. Some versions also include a backup supply which
is provided on the VBAT pin and must be in the range specified by the VBAT parameter in order to supply
battery power if VCC is below VCCSWF. Refer to the Power Supply and Switchover Parameters table for the
specifications related to the power supplies and switchover. There are several functions which are directly
related to the VBAT input. If a single power supply is used it must be connected to the VCC pin.
Figure 30 illustrates the various power states and the transitions between them. There are three power
states:
1.
2.
3.
POR – the power on reset state. If the AM08XX is in this state, all registers including the Counter Registers are initialized to their reset values.
VCC Power – the AM08XX is powered from the VCC supply.
VBAT Power – the AM08XX is powered from the VBAT supply.
Initially, VCC is below the VCCST voltage, VBAT is below the VBATSW voltage and the AM08XX is in the
POR state. VCC rising above the VCCST voltage causes the AM08XX to enter the VCC Power state. If
VBAT remains below VBATSW, VCC falling below the VCCRST voltage returns the AM08XX to the POR
state.
VCC
VCCST
VBAT
Power State
VCCRST
VCCST
VCCSWR
VCCSWF
VCCSWF
VBATSW
POR
VCC Power
VBATRST
POR
VCC Power
VBAT Power
VCC Power
VBAT Power
POR
Figure 30. Power States
If VBAT rises above VBATSW in the POR state, the AM08XXremains in the POR state. This allows the
AM08XX to be built into a module with a battery included, and minimal current will be drawn from the
battery until VCC is applied to the module the first time.
If the AM08XX is in the VCC Power state and VBAT rises above VBATSW, the AM08XX remains in the VCC
Power state but automatic switchover becomes available. VBAT falling below VBATSW has no effect on the
power state as long as VCC remains above VCCSWF. If VCC falls below the VCCSWF voltage while VBAT is
above VBATSW the AM08XX switches to the VBAT Power state. VCC rising above VCCSWR returns the
AM08XX to the VCC Power state. There is hysteresis in the rising and falling VCC thresholds to ensure
that the AM08XX does not switch back and forth between the supplies if VCC is near the thresholds.
VCCSWF and VCCSWR are independent of the VBAT voltage and allow the AM08XX to minimize the current
drawn from the VBAT supply by switching to VBAT only at the point where VCC is no longer able to power
the device.
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If the AM08XX is in the VBAT Power state and VBAT falls below VBATRST, the AM08XX will return to the
POR state.
Whenever the AM08XX enters the VBAT Power state, the BAT flag in the Status Register (see 0x0F Status (Read Only)) is set and may be polled by software. If the XT oscillator is selected and the AOS bit
(see 0x1C - Oscillator Control) is set, the AM08XX will automatically switch to the RC oscillator in the
VBAT Power state in order to conserve battery power. If the IOBM bit (see 0x27 – Batmode IO Register) is
clear, the I2C or SPI interface is disabled in the VBAT Power state in order to prevent erroneous accesses
to the AM08XX if the bus master loses power.
5.13.1 Battery Low Flag and Interrupt
If the VBAT voltage drops below the Falling Threshold selected by the BREF field (see 0x21 - BREF
Control), the BL flag in the Status Register (see 0x0F - Status (Read Only)) is set. If the BLIE interrupt
enable bit (see 0x12 - Interrupt Mask) is set, the IRQ interrupt is generated. This allows software to
determine if a backup battery has been drained. Note that the BPOL bit must be set to 0. The algorithm in
the Analog Comparator section should be used when configuring the BREF value.
If the VBAT voltage is above the rising voltage which corresponds to the current BREF setting, BBOD will
be set. At that point the VBAT voltage must fall below the falling voltage in order to clear the BBOD bit, set
the BAT flag and generate a falling edge BL interrupt. If BBOD is clear, the VBAT voltage must rise above
the rising voltage in order to clear the BBOD bit and generate a rising edge BL interrupt.
5.13.2 Analog Comparator
If a backup battery is not required, the VBAT pin may be used as an analog comparator input. The voltage
comparison level is set by the BREF field. If the BPOL bit is 0, the BL flag will be set when the VBAT
voltage crosses from above the BREF Falling Threshold to below it. If the BPOL bit is 1, the BL flag will be
set when the VBAT voltage crosses from below the BREF Rising Threshold to above it. The BBOD bit in
the Analog Status Register (see 0x2F – Analog Status Register (Read Only)) may be read to determine if
the VBAT voltage is currently above the BREF threshold (BBOD = 1) or below the threshold (BBOD = 0).
There is a reasonably large delay (on the order of seconds) between changing the BREF field and a valid
value of the BBOD bit. Therefore, the algorithm for using the Analog Comparator should comprise the
following steps:
1.
2.
Set the BREF and BPOL fields to the desired values.
Wait longer than the maximum tBREF time.
3.
4.
Clear the BL flag, which may have been erroneously set as BBOD settles.
Check the BBOD bit to ensure that the VBAT pin is at a level for which an interrupt can occur. If a falling interrupt is desired (BPOL = 0), BBOD should be 1. If a rising interrupt is desired (BPOL = 1),
BBOD should be 0.
If the comparison voltage on the VBAT pin can remain when VCC goes to 0, it is recommended that a
Software Reset be generated to the AM08XX after power up.
5.13.3 Pin Control and Leakage Management
Like most ICs, the AM08XX may draw unnecessary leakage current if an input pin floats to a value near
the threshold or an output pin is pulled to a power supply. Because external devices may be powered from
VCC, extra care must be taken to ensure that any input or output pins are handled correctly to avoid
extraneous leakage when VCC goes away and the AM08XX is powered from VBAT. The Output Control
register (see 0x30 – Output Control Register), the Batmode IO register (see 0x27 – Batmode IO Register)
and the Extension RAM Address register (see 0x3F - Extension RAM Address) include bits to manage this
leakage, which should be used as follows:
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1.
2.
3.
4.
EXBM should be cleared if the EXTI pin is connected to a device which is powered down when the
AM08XX is in the VBAT Power state.
WDBM should be cleared if the WDI pin is connected to a device which is powered down when the
AM08XX is in the VBAT Power state.
O4BM should be cleared if the CLKOUT/nIRQ3 pin is connected to a device which is powered down
when the AM08XX is in the VBAT Power state.
IOBM should be cleared if the I2C or SPI bus master is powered down when the AM08XX is in the
VBAT Power state.
5.13.4 Power Up Timing
When the voltage levels on both the VCC and VBAT signals drop below VCCRST, the AM08XX will enter the
POR state. Once VCC rises above VCCST, the AM08XX will enter the VCC Power state. I/O accesses via
the I2C or SPI interface will be disabled for a period of tVH:FOUT. The FOUT/nIRQ pin will be low at power
up, and will go high when tVH:FOUT expires. Software should poll the FOUT/nIRQ value to determine when
the AM08XX may be accessed. Figure 31 illustrates the timing of a power down/up operation.
No I/O Access
VCC
VBAT
FOUT/nIRQ
State
Oper
Power Down
PwrUp
Oper
tVH:FOUT
Figure 31. Power Up Timing
5.14 Software Reset
Software may reset the AM08XX by writing the special value of 0x3C to the Configuration Key register at
offset 0x1F. This will provide the equivalent of a power on reset by initializing all of the AM08XX registers.
.
5.15 Trickle Charger
The devices supporting the VBAT pin include a trickle charging circuit which allows a battery or
supercapacitor connected to the VBAT pin to be charged from the power supply connected to the VCC pin.
The circuit of the Trickle Charger is shown in Figure 32. The Trickle Charger configuration is controlled by
the Trickle register (see 0x20 - Trickle). The Trickle Charger is enabled if a) the TCS field is 1010, b) the
DIODE field is 01 or 10 and c) the ROUT field is not 00. A diode, with a typical voltage drop of 0.6V, is
inserted in the charging path if DIODE is 10. A Schottky diode, with a typical voltage drop of 0.3V, is
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inserted in the charging path if DIODE is 01. The series current limiting resistor is selected by the ROUT
field as shown in the figure.
Enable
DIODE
ROUT
3 k 6 k 11 k Figure 32. Trickle Charger
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6.
Registers
Registers are accessed by selecting a register address and then performing read or write operations.
Multiple reads or writes may be executed in a single access, with the address automatically incrementing
after each byte. Table 16 and Table 17 summarize the function of each register. In Table 16, the GPx bits
(where x is between 0 and 27) are 28 register bits which may be used as general purpose storage. These
bits are not described in the sections below. All of the GPx bits are cleared when the AM08XX powers up,
and they can therefore be used to allow software to determine if a true Power On Reset has occurred or
hold other initialization data.
6.1 Register Definitions and Memory Map
Table 16: Register Definitions (0x00 to 0x0F)
Offset
Register
7
6
5
4
3
2
0x00
Hundredths
0x01
Seconds
GP0
Seconds - Tens
Seconds - Ones
0x02
Minutes
GP1
Minutes - Tens
Minutes - Ones
0x03
Hours (24 hour)
GP3
GP2
0x03
Hours (12 hour)
GP3
GP2
0x04
Date
GP5
GP4
0x05
Months
GP8
GP7
0x06
Years
0x07
Weekdays
0x08
Hundredths Alarm
0x09
Seconds Alarm
GP14
Seconds Alarm - Tens
Seconds Alarm - Ones
0x0A
Minutes Alarm
GP15
Minutes Alarm - Tens
Minutes Alarm - Ones
0x0B
Hours Alarm (24 hour)
GP17
GP16
Hours Alarm - Tens
Hours Alarm - Ones
0x0B
Hours Alarm (12 hour)
GP17
GP16
AM/PM
Hours
Alarm Tens
Hours Alarm - Ones
0x0C
Date Alarm
GP19
GP18
Date Alarm - Tens
Date Alarm - Ones
0x0D
Months Alarm
GP22
GP21
GP20
Months
Alarm Tens
0x0E
Weekdays Alarm
GP27
GP26
GP25
GP24
GP23
0x0F
Status
CB
BAT
WDT
BL
TIM
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Seconds - Tenths
1
Seconds - Hundredths
Hours - Tens
AM/PM
Hours - Ones
Hours Tens
Hours - Ones
Date - Tens
GP6
Date - Ones
Months Tens
Months - Ones
Years - Tens
GP13
GP12
Years - Ones
GP11
GP10
Hundredths Alarm - Tenths
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0
GP9
Weekdays
Hundredths Alarm - Hundredths
Months Alarm - Ones
Weekdays Alarm
ALM
EX2
EX1
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All rights reserved.
AM08XX Datasheet
Table 17: Register Definitions (0x10 to 0xFF)
Offset
Register
7
6
5
4
3
2
1
0
OUT
-
ARST
-
WRTC
0x10
Control1
STOP
12/24
OUTB
0x11
Control2
-
-
-
0x12
IntMask
CEB
IM
0x13
SQW
SQWE
-
0x14
Cal_XT
CMDX
0x15
Cal_RC_Hi
0x16
Cal_RC_Low
0x17
Int Polarity
0x18
Timer Control
0x19
Timer
Countdown Timer
0x1A
Timer_Initial
Timer Initial Value
0x1B
WDT
WDS
0x1C
Osc. Control
OSEL
0x1D
Osc. Status
0x1E
RESERVED
0x1F
Configuration Key
0x20
Trickle
0x21
BREF Control
0x22
RESERVED
RESERVED
0x23
RESERVED
RESERVED
0x24
RESERVED
RESERVED
0x25
RESERVED
RESERVED
0x26
AFCTRL
0x27
BATMODE I/O
0x28
ID0 (Read only)
Part Number –MS Byte = 00001000 (0x08)
0x29
ID1 (Read only)
Part Number – LS Byte (e.g. 00000101 for AM0805)
0x2A
ID2 (Read only)
0x2B
ID3 (Read only)
0x2C
ID4 (Read only)
0x2D
ID5 (Read only)
0x2E
ID6 (Read only)
Lot[8]
0x2F
ASTAT
BBOD
BMIN
-
-
-
0x30
OCTRL
WDBM
EXBM
-
-
0x3F
Extension Address
O4BM
BPOL
WDIN
EXIN
OUT2S
BLIE
OUT1S
TIE
AIE
EX1E
-
-
SQFS
OFFSETX
CMDR
OFFSETR[13:8]
OFFSETR[7:0]
-
-
EX2P
TE
TM
TRPT
EX1P
-
-
RPT
TFS
BMB
ACAL
XTCAL
LKO2
WRB
AOS
FOS
-
OFIE
ACIE
OMODE
-
-
OF
ACF
RESERVED
Configuration Key
TCS
DIODE
ROUT
BREF
-
AFCTRL
IOBM
RESERVED
Revision – Major = 00010
Revision – Minor = 011
Lot[7:0]
Lot[9]
Unique ID[14:8]
Unique ID[7:0]
Wafer
–
–
-
VINIT
-
-
-
-
-
-
XADA
0x40–7F
RAM
Normal RAM Data
0x80–FF
RAM
Alternate RAM Data (I2C Mode Only)
DS0002V1p0
EX2E
Page 49 of 81
XADS
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All rights reserved.
AM08XX Datasheet
6.2 Time and Date Registers
6.2.1
0x00 - Hundredths
This register holds the count of hundredths of seconds, in two binary coded decimal (BCD) digits. Values
will be from 00 to 99. Note that in order to divide from 32.786 kHz, the hundredths register will not be fully
accurate at all times but will be correct every 500 ms. Maximum jitter of this register will be less than 1 ms.
The Hundredths Counter is not valid if the 128 Hz RC Oscillator is selected.
Table 18: Hundredths Register
Bit
7
5
4
3
Seconds - Tenths
Name
Reset
6
1
0
2
1
0
Seconds - Hundredths
0
1
1
0
0
1
Table 19: Hundredths Register Bits
Bit
Name
7:4
Seconds Tenths
3:0
Seconds Hundredths
6.2.2
Function
Holds the tenths place in the hundredths counter.
Holds the hundredths place in the hundredths counter.
0x01 - Seconds
This register holds the count of seconds, in two binary coded decimal (BCD) digits. Values will be from 00
to 59.
Table 20: Seconds Register
Bit
7
Name
GP0
Reset
0
6
5
4
3
Seconds - Tens
0
0
2
1
0
Seconds - Ones
0
0
0
0
0
Table 21: Seconds Register Bits
Bit
Name
7
GP0
6:4
Seconds - Tens
Holds the tens place in the seconds counter.
3:0
Seconds Ones
Holds the ones place in the seconds counter.
DS0002V1p0
Function
Register bit for general purpose use.
Page 50 of 81
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AM08XX Datasheet
6.2.3
0x02 - Minutes
This register holds the count of minutes, in two binary coded decimal (BCD) digits. Values will be from 00
to 59.
Table 22: Minutes Register
Bit
7
6
Name
GP1
Reset
0
5
4
3
Minutes - Tens
0
0
2
1
0
Minutes - Ones
0
0
0
0
0
Table 23: Minutes Register Bits
Bit
Name
7
GP1
6:4
Minutes - Tens
Holds the tens place in the minutes counter.
3:0
Minutes - Ones
Holds the ones place in the minutes counter.
6.2.4
Function
Register bit for general purpose use.
0x03 - Hours
This register holds the count of hours, in two binary coded decimal (BCD) digits. Values will be from 00 to
23 if the 12/24 bit (see 0x10 - Control1) is clear. If the 12/24 bit is set, the AM/PM bit will be 0 for AM hours
and 1 for PM hours, and hour values will range from 1 to 12.
Table 24: Hours Register (12 Hour Mode)
Bit
7
6
5
4
Name
GP3
GP2
AM/PM
Hours Tens
Reset
0
0
0
0
3
2
1
0
0
0
Hours - Ones
0
0
Table 25: Hours Register Bits (12 Hour Mode)
Bit
Name
7
GP3
Register bit for general purpose use.
6
GP2
Register bit for general purpose use.
5
AM/PM
4
Hours - Tens
Holds the tens place in the hours counter.
3:0
Hours - Ones
Holds the ones place in the hours counter.
DS0002V1p0
Function
0 = AM hours. 1 = PM hours.
Page 51 of 81
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AM08XX Datasheet
Table 26: Hours Register (24 Hour Mode)
Bit
7
6
Name
GP3
GP2
Reset
0
0
5
4
3
2
Hours - Tens
0
1
0
0
0
Hours - Ones
0
0
0
Table 27: Hours Register Bits (24 Hour Mode)
Bit
Name
7
GP3
Register bit for general purpose use.
6
GP2
Register bit for general purpose use.
5:4
Hours - Tens
Holds the tens place in the hours counter.
3:0
Hours - Ones
Holds the ones place in the hours counter.
6.2.5
Function
0x04 - Date
This register holds the current day of the month, in two binary coded decimal (BCD) digits. Values will
range from 01 to 31. Leap years are correctly handled from 1900 to 2199.
Table 28: Date Register
Bit
7
6
Name
GP5
GP4
Reset
0
0
5
4
3
2
Date - Tens
0
1
0
0
1
Date - Ones
0
0
0
Table 29: Date Register Bits
Bit
Name
7
GP5
Register bit for general purpose use.
6
GP4
Register bit for general purpose use.
5:4
Date - Tens
Holds the tens place in the date counter.
3:0
Date - Ones
Holds the ones place in the date counter.
6.2.6
Function
0x05 - Months
This register holds the current month, in two binary coded decimal (BCD) digits. Values will range from 01
to 12.
Table 30: Months Register
Bit
7
6
5
4
Name
GP8
GP7
GP6
Months Tens
DS0002V1p0
Page 52 of 81
3
2
1
0
Months - Ones
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All rights reserved.
AM08XX Datasheet
Table 30: Months Register
Bit
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
1
Table 31: Months Register Bits
Bit
Name
7
GP8
Register bit for general purpose use.
6
GP7
Register bit for general purpose use.
5
GP6
Register bit for general purpose use.
4
Months - Tens
Holds the tens place in the months counter.
3:0
Months - Ones
Holds the ones place in the months counter.
6.2.7
Function
0x06 - Years
This register holds the current year, in two binary coded decimal (BCD) digits. Values will range from 00 to
99.
Table 32: Years Register
Bit
7
6
4
3
2
Years - Tens
Name
Reset
5
0
0
1
0
0
0
1
0
Years - Ones
0
0
0
0
Table 33: Years Register Bits
Bit
Name
7:4
Years - Tens
Holds the tens place in the years counter.
3:0
Years - Ones
Holds the ones place in the years counter.
6.2.8
Function
0x07 - Weekday
This register holds the current day of the week. Values will range from 0 to 6.
Table 34: Weekdays Register
Bit
7
6
5
4
3
Name
GP13
GP12
GP11
GP10
GP9
Reset
0
0
0
0
0
DS0002V1p0
Page 53 of 81
2
Weekdays
0
0
0
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All rights reserved.
AM08XX Datasheet
Table 35: Weekdays Register Bits
Bit
Name
Function
7
GP13
Register bit for general purpose use.
6
GP12
Register bit for general purpose use.
5
GP11
Register bit for general purpose use.
4
GP10
Register bit for general purpose use.
3
GP9
Register bit for general purpose use.
2:0
Weekdays
Holds the weekday counter value.
6.3 Alarm Registers
6.3.1
0x08 - Hundredths Alarm
This register holds the alarm value for hundredths of seconds, in two binary coded decimal (BCD) digits.
Values will range from 00 to 99.
Table 36: Hundredths Alarm Register
Bit
7
5
4
3
Seconds Alarm - Tenths
Name
Reset
6
0
0
2
1
0
Seconds Alarm - Hundredths
0
0
0
0
0
0
Table 37: Hundredths Alarm Register Bits
Bit
Name
7:4
Seconds Alarm
- Tenths
Holds the tenths place for the hundredths alarm.
3:0
Seconds Alarm
- Hundredths
Holds the hundredths place for the hundredths alarm.
6.3.2
Function
0x09 - Seconds Alarm
This register holds the alarm value for seconds, in two binary coded decimal (BCD) digits. Values will
range from 00 to 59.
Table 38: Seconds Alarm Register
Bit
7
Name
GP14
Reset
0
DS0002V1p0
6
5
4
3
Seconds Alarm - Tens
0
0
2
1
0
Seconds Alarm - Ones
0
Page 54 of 81
0
0
0
0
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All rights reserved.
AM08XX Datasheet
Table 39: Seconds Alarm Register Bits
Bit
Name
7
GP14
6:4
Seconds Alarm
- Tens
Holds the tens place for the seconds alarm.
3:0
Seconds Alarm
- Ones
Holds the ones place for the seconds alarm.
6.3.3
Function
Register bit for general purpose use.
0x0A - Minutes Alarm
This register holds the alarm value for minutes, in two binary coded decimal (BCD) digits. Values will range
from 00 to 59.
Table 40: Minutes Alarm Register
Bit
7
Name
GP15
Reset
0
6
5
4
3
Minutes Alarm - Tens
0
0
2
1
0
Minutes Alarm - Ones
0
0
0
0
0
Table 41: Minutes Alarm Register Bits
Bit
Name
7
GP15
6:4
Minute Alarm Tens
Holds the tens place for the minutes alarm.
3:0
Minutes Alarm
- Ones
Holds the ones place for the minutes alarm.
6.3.4
Function
Register bit for general purpose use.
0x0B - Hours Alarm
This register holds the alarm value for hours, in two binary coded decimal (BCD) digits. Values will range
from 00 to 23 if the 12/24 bit (see 0x10 - Control1) is clear. If the 12/24 bit is set, the AM/PM bit will be 0 for
AM hours and 1 for PM hours, and hour values will be from 1 to 12.
Table 42: Hours Alarm Register (12 Hour Mode)
Bit
7
6
5
4
Name
GP17
GP16
AM/PM
Hours
Alarm Tens
Reset
0
0
0
0
DS0002V1p0
Page 55 of 81
3
2
1
0
Hours Alarm - Ones
0
0
0
0
2013 Ambiq Micro, Inc.
All rights reserved.
AM08XX Datasheet
Table 43: Hours Alarm Register Bits (12 Hour Mode)
Bit
Name
Function
7
GP17
Register bit for general purpose use.
6
GP16
Register bit for general purpose use.
5
AM/PM
4
Hours Alarm Tens
Holds the tens place for the hours alarm.
3:0
Hour Alarm Ones
Holds the ones place for the hours alarm.
0 = AM hours. 1 = PM hours.
Table 44: Hours Alarm Register (24 Hour Mode)
Bit
7
6
Name
GP17
GP16
Reset
0
0
5
4
3
Hours Alarm - Tens
0
0
2
1
0
Hours Alarm - Ones
0
0
0
0
Table 45: Hours Alarm Register Bits (24 Hour Mode)
Bit
Name
7
GP17
Register bit for general purpose use.
6
GP16
Register bit for general purpose use.
5:4
Hours Alarm Tens
Holds the tens place for the hours alarm.
3:0
Hours Alarm Ones
Holds the ones place for the hours alarm.
6.3.5
Function
0x0C - Date Alarm
This register holds alarm value for the date, in two binary coded decimal (BCD) digits. Values will range
from 01 to 31. Leap years are correctly handled from 1900 to 2199.
Table 46: Date Alarm Register
Bit
7
6
Name
GP19
GP18
Reset
0
0
DS0002V1p0
5
4
3
Date Alarm - Tens
0
0
Page 56 of 81
2
1
0
Date Alarm - Ones
0
0
0
0
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All rights reserved.
AM08XX Datasheet
Table 47: Date Alarm Register Bits
Bit
Name
7
GP19
Register bit for general purpose use.
6
GP18
Register bit for general purpose use.
5:4
Date Alarm - Tens
Holds the tens place for the date alarm.
3:0
Date Alarm Ones
Holds the ones place for the date alarm.
6.3.6
Function
0x0D - Months Alarm
This register holds alarm value for months, in two binary coded decimal (BCD) digits. Values will range
from 01 to 12.
Table 48: Months Alarm Register
Bit
7
6
5
4
Name
GP22
GP21
GP20
Months
Alarm Tens
Reset
0
0
0
0
3
2
1
0
Months Alarm - Ones
0
0
0
0
Table 49: Months Alarm Register Bits
Bit
Name
7
GP22
Register bit for general purpose use.
6
GP21
Register bit for general purpose use.
5
GP20
Register bit for general purpose use.
4
Months Alarm Tens
Holds the tens place for the months alarm.
3:0
Months Alarm Ones
Holds the ones place for the months alarm.
6.3.7
Function
0x0E - Weekday Alarm
This register holds the alarm value for the day of the week. Values will range from 0 to 6.
Table 50: Weekdays Alarm Register
Bit
7
6
5
4
3
Name
GP27
GP26
GP25
GP24
GP23
Reset
0
0
0
0
0
DS0002V1p0
Page 57 of 81
2
1
0
Weekdays Alarm
0
0
0
2013 Ambiq Micro, Inc.
All rights reserved.
AM08XX Datasheet
Table 51: Weekdays Alarm Register Bits
Bit
Name
Function
7
GP27
Register bit for general purpose use.
6
GP26
Register bit for general purpose use.
5
GP25
Register bit for general purpose use.
4
GP24
Register bit for general purpose use.
3
GP23
Register bit for general purpose use.
2:0
Weekdays Alarm
Holds the weekdays alarm value.
6.4 Configuration Registers
6.4.1
0x0F - Status (Read Only)
This register holds a variety of status bits. The register may be written at any time to clear or set any status
flag. If the ARST bit is set, any read of the Status Register will clear all of the bits except the CB bit.
Table 52: Status Register
Bit
7
6
5
4
3
2
1
0
Name
CB
BAT
WDT
BL
TIM
ALM
EX2
EX1
Reset
0
0
0
0
0
0
0
0
Table 53: Status Register Bits
Bit
Name
Function
7
CB
Century. This bit will be toggled when the Years register rolls over from 99 to 00 if the CEB bit is a 1.
A 0 assumes the century is 19xx or 21xx, and a 1 assumes it is 20xx for leap year calculations.
6
BAT
Set when the system switches to the VBAT Power state.
5
WDT
Set when the Watchdog Timer is enabled and is triggered, and the WDS bit is 0.
4
BL
Set if the battery voltage VBAT crosses the reference voltage selected by BREF in the direction
selected by BPOL.
3
TIM
Set when the Countdown Timer is enabled and reaches zero.
2
ALM
Set when the Alarm function is enabled and all selected Alarm registers match their respective
counters.
1
EX2
Set when an external trigger is detected on the WDI pin. The EX2E bit must be set in order for this
interrupt to occur, but subsequently clearing EX2E will not automatically clear this flag.
0
EX1
Set when an external trigger is detected on the EXTI pin. The EX1E bit must be set in order for this
interrupt to occur, but subsequently clearing EX1E will not automatically clear this flag.
DS0002V1p0
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AM08XX Datasheet
6.4.2
0x10 - Control1
This register holds some major control signals.
Table 54: Control1 Register
Bit
7
6
5
4
3
2
1
0
Name
STOP
12/24
OUTB
OUT
RESERVED
ARST
RESERVED
WRTC
Reset
0
0
0
1
0
0
0
1
Table 55: Control1 Register Bits
Bit
Name
Function
7
STOP
When 1, stops the clocking system. The XT and RC Oscillators are not stopped. In XT Mode
the 32.786 kHz clock output will continue to run. In RC Mode, the 128 Hz clock output will continue to run. Other clock output selections will produce static outputs. This bit allows the clock
system to be precisely started, by setting it to 1 and back to 0.
6
12/24
When 0, the Hours register operates in 24 hour mode. When 1, the Hours register operates in
12 hour mode.
5
OUTB
A static value which may be driven on the nIRQ2 pin. The OUTB bit cannot be set to 1 if the
LKO2 bit is 1.
4
OUT
A static value which may be driven on the FOUT/nIRQ pin. This bit also defines the default
value for the Square Wave output when SQWE is not asserted.
3
RESERVED
2
ARST
1
RESERVED
0
WRTC
6.4.3
RESERVED
Auto reset enable. When 1, a read of the Status register will cause any interrupt bits (TIM, BL,
ALM, WDT, XT1, XT2) to be cleared. When 0, the bits must be explicitly cleared by writing the
Status register.
RESERVED
Write RTC. This bit must be set in order to write any of the Counter registers (Hundredths, Seconds, Minutes, Hours, Date, Months, Years or Weekdays).
0x11 - Control2
This register holds additional control and configuration signals for the flexible output pins FOUT/nIRQ and
nIRQ2. Note that nIRQ2 and FOUT/nIRQ are open drain outputs.
Table 56: Control2 Register
Bit
7
5
4
RESERVED
Name
Reset
6
0
3
2
1
OUT2S
0
0
0
0
0
OUT1S
0
0
0
Table 57: Control2 Register Bits
Bit
Name
7:5
RESERVED
DS0002V1p0
Function
RESERVED
Page 59 of 81
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AM08XX Datasheet
Table 57: Control2 Register Bits
Bit
Name
Function
4:2
OUT2S
Controls the function of the nIRQ2 pin, as shown in Table 58.
1:0
OUT1S
Controls the function of the FOUT/NIRQ pin, as shown in Table 59.
Table 58: nIRQ2 Pin Control
OUT2S Value
nIRQ2 Pin Function
000
nIRQ if at least one interrupt is enabled, else OUTB
001
SQW if SQWE = 1, else OUTB
010
RESERVED
011
nAIRQ if AIE is set, else OUTB
100
TIRQ if TIE is set, else OUTB
101
nTIRQ if TIE is set, else OUTB
110
RESERVED
111
OUTB
Table 59: FOUT/nIRQ Pin Control
OUT1S Value
6.4.4
FOUT/nIRQ Pin Function
00
nIRQ if at least one interrupt is enabled, else OUT
01
SQW if SQWE = 1, else OUT
10
SQW if SQWE = 1, else nIRQ if at least one interrupt is enabled, else OUT
11
nAIRQ if AIE is set, else OUT
0x12 - Interrupt Mask
This register holds the interrupt enable bits and other configuration information.
Table 60: Interrupt Mask Register
Bit
7
Name
CEB
Reset
1
6
5
IM
1
1
4
3
2
1
0
BLIE
TIE
AIE
EX2E
EX1E
0
0
0
0
0
Table 61: Interrupt Mask Register Bits
Bit
Name
7
CEB
DS0002V1p0
Function
Century Enable.
0: The CB bit will never be automatically updated.
1: The CB bit will toggle when the Years register rolls over from 99 to 00.
Page 60 of 81
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AM08XX Datasheet
Table 61: Interrupt Mask Register Bits
Bit
Name
Function
6:5
IM
Interrupt Mode.
This controls the duration of the nAIRQ interrupt as shown below. The interrupt output always goes
high when the corresponding flag in the Status Register is cleared. In order to minimize current
drawn by the AM08XX this field should be kept at 0x3.
00: Level (static) for both XT mode and RC mode.
01: 1/8192 seconds for XT mode. 1/64 seconds for RC mode.
10: 1/64 seconds for both XT mode and RC mode.
11: 1/4 seconds for both XT mode and RC mode.
4
BLIE
Battery Low Interrupt Enable.
0: Disable the battery low interrupt.
1: The battery low detection will generate an interrupt.
3
TIE
Timer Interrupt Enable.
0: Disable the timer interrupt.
1: The Countdown Timer will generate an IRQ interrupt signal and set the TIM flag when the timer
reaches 0.
2
AIE
Alarm Interrupt Enable.
0: Disable the alarm interrupt.
1: A match of all the enabled alarm registers will generate an IRQ interrupt signal.
1
EX2E
XT2 Interrupt Enable.
0: Disable the XT2 interrupt.
1: The WDI input pin will generate the XT2 interrupt when the edge specified by EX2P occurs.
0
EX1E
XT1 Interrupt Enable.
0: Disable the XT1 interrupt.
1: The EXTI input pin will generate the XT1 interrupt when the edge specified by EX1P occurs.
6.4.5
0x13 - SQW
This register holds the control signals for the square wave output. Note that some frequency selections are
not valid if the 128 Hz RC Oscillator is selected.
Table 62: SQW Register
Bit
7
Name
SQWE
Reset
0
6
5
4
3
RESERVED
0
2
1
0
1
0
SQFS
1
0
0
1
Table 63: SQW Register Bits
Bit
Name
7
SQWE
6:5
RESERVED
4:0
SQFS
DS0002V1p0
Function
When 1, the square wave output is enabled. When 0, the square wave output is held at the
value of OUT.
RESERVED
Selects the frequency of the square wave output, as shown in Table 64. Note that some selections are not valid if the 128 Hz oscillator is selected. Some selections also produce short
pulses rather than square waves, and are intended primarily for test usage.
Page 61 of 81
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All rights reserved.
AM08XX Datasheet
Table 64: Square Wave Function Select
SQFS Value
00000
1 century(2)
00001
32.786 kHz(1)
00010
8.192 kHz(1)
00011
4.096 kHz(1)
00100
2.048 kHz(1)
00101
1.024 kHz(1)
00110
512 Hz(1) – Default value
00111
256 Hz(1)
01000
128 Hz
01001
64 Hz
01010
32 Hz
01011
16 Hz
01100
8 Hz
01101
4 Hz
01110
2 Hz
01111
1 Hz
10000
½ Hz
10001
¼ Hz
10010
1/8 Hz
10011
1/16 Hz
10100
1/32 Hz
10101
1/60 Hz (1 minute)
10110
16.384 kHz (1)
10111
100 Hz (1)(2)
11000
1 hour(2)
11001
1 day(2)
11010
TIRQ
11011
NOT TIRQ
11100
1 year(2)
11101
1 Hz to Counters(2)
11110
1/32 Hz from Acal(2)
11111
1/8 Hz from Acal (2)
(1) NA
(2)
DS0002V1p0
Square Wave Output
if 128 Hz Oscillator selected.
Pulses for Test Usage.
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AM08XX Datasheet
6.5 Calibration Registers
6.5.1
0x14 - Calibration XT
This register holds the control signals for a digital calibration function of the XT Oscillator.
Table 65: Calibration XT Register
Bit
7
6
Name
CMDX
Reset
0
5
4
3
2
1
0
0
0
0
OFFSETX
0
0
0
0
Table 66: Calibration XT Register Bits
Bit
Name
Function
7
CMDX
The calibration adjust mode. When 0 (Normal Mode), each adjustment step is +/- 2 ppm. When
1 (Coarse Mode), each adjustment step is +/- 4 ppm.
6:0
OFFSETX
The amount to adjust the effective time. This is a two's complement number with a range of -64
to +63 adjustment steps.
6.5.2
0x15 - Calibration RC Upper
This register holds the control signals for the fine digital calibration function of the low power RC Oscillator.
This register is initialized with a factory value which calibrates the RC Oscillator to 128 Hz.
Table 67: Calibration RC Upper Register
Bit
7
6
5
4
3
2
Name
CMDR
OFFSETRU
Reset
Preconfigured
Preconfigured
1
0
Table 68: Calibration RC Upper Register Bits
Bit
Name
Function
7:6
CMDR
The calibration adjust mode for the RC calibration adjustment. CMDR selects the highest frequency used in the RC Calibration process, as shown in Table 69.
5:0
OFFSETRU
The upper 6 bits of the OFFSETR field, which is used to set the amount to adjust the effective
time. OFFSETR is a two's complement number with a range of -2^13 to +2^13-1 adjustment
steps.
Table 69: CMDR Function
DS0002V1p0
CMDR
Calibration Period
Minimum Adjustment
Maximum Adjustment
00
8,192 seconds
+/-1.91 ppm
+/-1.56%
01
4,096 seconds
+/-3.82 ppm
+/-3.13%
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AM08XX Datasheet
Table 69: CMDR Function
6.5.3
CMDR
Calibration Period
Minimum Adjustment
Maximum Adjustment
10
2,048 seconds
+/-7.64 ppm
+/-6.25%
11
1,024 seconds
+/-15.28 ppm
+/-12.5%
0x16 - Calibration RC Lower
This register holds the lower 8 bits of the OFFSETR field for the digital calibration function of the low power
RC Oscillator. This register is initialized with a factory value which calibrates the RC Oscillator to 128 Hz.
Table 70: Calibration RC Lower Register
Bit
7
6
5
4
3
Name
OFFSETRL
Reset
Preconfigured
2
1
0
Table 71: Calibration RC Lower Register Bits
Bit
Name
7:0
OFFSETRL
Function
The lower 8 bits of the OFFSETR field, which is used to set the amount to adjust the effective
time. OFFSETR is a two's complement number with a range of -2^13 to +2^13-1 adjustment
steps.
6.6 Interrupt Polarity Control Register
6.6.1
0x17 - Interrupt Polarity Control
This register controls the external interrupt polarity.
Table 72: Interrupt Polarity Control Register
Bit
7
RESERVED
Name
Reset
6
0
5
4
EX2P
EX1P
0
0
0
3
2
1
0
0
0
RESERVED
0
0
Table 73: Interrupt Polarity Control Register Bits
Bit
Name
7:6
RESERVED
5
EX2P
DS0002V1p0
Function
RESERVED
When 1, the external interrupt XT2 will trigger on a rising edge of the WDI pin. When 0, the
external interrupt XT2 will trigger on a falling edge of the WDI pin.
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AM08XX Datasheet
Table 73: Interrupt Polarity Control Register Bits
Bit
Name
Function
4
EX1P
3:0
RESERVED
When 1, the external interrupt XT1 will trigger on a rising edge of the EXTI pin. When 0, the
external interrupt XT1 will trigger on a falling edge of the EXTI pin.
RESERVED
6.7 Timer Registers
6.7.1
0x18 - Countdown Timer Control
This register controls the Countdown Timer function. Note that the 00 frequency selection is slightly
different depending on whether the 32.786 kHz XT Oscillator or the 128 Hz RC Oscillator is selected. In
some RC Oscillator modes, the interrupt pulse output is specified as RCPLS. In these cases the interrupt
output will be a short negative going pulse which is typically between 100 and 400 us. This allows control
of external devices which require pulses shorter than the minimum 7.8 ms pulse created directly by the RC
Oscillator.
Table 74: Countdown Timer Control Register
Bit
7
6
5
Name
TE
TM
TRPT
Reset
0
0
1
4
3
2
1
RPT
0
0
0
TFS
0
1
1
Table 75: Countdown Timer Control Register Bits
Bit
Name
Function
7
TE
Timer Enable. When 1, the Countdown Timer will count down. When 0, the Countdown Timer retains
the current value. If TE is 0, the clock to the Timer is disabled for power minimization.
TM
Timer Interrupt Mode. Along with TRPT, this controls the Timer Interrupt function as shown in Table
28. A Level Interrupt will cause the nIRQ signal to be driven low by a Countdown Timer interrupt until
the associated flag is cleared. A Pulse interrupt will cause the nIRQ signal to be driven low for the
time shown in Table 77 or until the flag is cleared.
5
TRPT
Along with TM, this controls the repeat function of the Countdown Timer. If Repeat is selected, the
Countdown Timer reloads the value from the Timer_Initial register upon reaching 0, and continues
counting. If Single is selected, the Countdown Timer will halt when it reaches zero. This allows the
generation of periodic interrupts of virtually any frequency.
4:2
RPT
These bits enable the Alarm Interrupt repeat function, as shown in Table 76. HA is the Hundredths_Alarm register value.
1:0
TFS
Select the clock frequency and interrupt pulse width of the Countdown Timer, as defined in Table 77.
RCPLS is a 80-120 us pulse.
6
Table 76: Repeat Function
DS0002V1p0
RPT
HA
7
FF
Repeat When
Once per hundredth (*)
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AM08XX Datasheet
Table 76: Repeat Function
RPT
HA
7
F[9-0]
7
[9-0][9-0]
(*)
Repeat When
Once per tenth (*)
Hundredths match (once per second)
6
Hundredths and seconds match (once per minute)
5
Hundredths, seconds and minutes match (once per hour)
4
Hundredths, seconds, minutes and hours match (once per day)
3
Hundredths, seconds, minutes, hours and weekday match (once per week)
2
Hundredths, seconds, minutes, hours and date match (once per month)
1
Hundredths, seconds, minutes, hours, date and month match (once per year)
0
Alarm Disabled
Once per second if 128 Hz Oscillator selected
Table 77: Countdown Timer Function Select
TM
TRPT
TFS
Int
Repeat
Countdown Timer Frequency
Interrupt Pulse Width
32.786 kHz Oscillator
128 Hz Oscillator
32.786 kHz
Oscillator
128 Hz Oscillator
0
0
00
Pulse
Single
4.096 kHz
128 Hz
1/4096 s
1/128 s
0
0
01
Pulse
Single
64 Hz
64 Hz
1/128 s
1/128 s
0
0
10
Pulse
Single
1 Hz
1 Hz
1/64 s
1/64 s
0
0
11
Pulse
Single
1/60 Hz
1/60 Hz
1/64 s
1/64 s
0
1
00
Pulse
Repeat
4.096 kHz
128 Hz
1/4096 s
1/128 s
0
1
01
Pulse
Repeat
64 Hz
64 Hz
1/128 s
1/128 s
0
1
10
Pulse
Repeat
1 Hz
1 Hz
1/64 s
1/64 s
0
1
11
Pulse
Repeat
1/60 Hz
1/60 Hz
1/64 s
1/64 s
1
0
00
Level
Single
4.096 kHz
128 Hz
N/A
N/A
1
0
01
Level
Single
64 Hz
64 Hz
N/A
N/A
1
0
10
Level
Single
1 Hz
1 Hz
N/A
N/A
1
0
11
Level
Single
1/60 Hz
1/60 Hz
N/A
N/A
1
1
00
Pulse
Repeat
4.096 kHz
128 Hz
1/4096 s
RCPLS
1
1
01
Pulse
Repeat
64 Hz
64 Hz
1/4096 s
RCPLS
1
1
10
Pulse
Repeat
1 Hz
1 Hz
1/4096 s
RCPLS
1
1
11
Pulse
Repeat
1/60 Hz
1/60 Hz
1/4096 s
RCPLS
DS0002V1p0
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AM08XX Datasheet
6.7.2
0x19 - Countdown Timer
This register holds the current value of the Countdown Timer. It may be loaded with the desired starting
value when the Countdown Timer is stopped.
Table 78: Countdown Timer Register
Bit
7
6
5
4
2
1
0
0
0
0
Countdown Timer
Name
Reset
3
0
0
0
0
0
Table 79: Countdown Timer Register Bits
Bit
Name
7:0
Countdown
Timer
6.7.3
Function
The current value of the Countdown Timer.
0x1A - Timer Initial Value
This register holds the value which will be reloaded into the Countdown Timer when it reaches zero if the
TRPT bit is a 1. This allows for periodic timer interrupts, and a period of (Timer_initial + 1) * (1/
Countdown_frequency).
Table 80: Timer Initial Value Register
Bit
7
6
5
4
2
1
0
0
0
0
Timer Initial Value
Name
Reset
3
0
0
0
0
0
Table 81: Timer Initial Value Register Bits
Bit
Name
7:0
Timer Initial
Value
6.7.4
Function
The value reloaded into the Countdown Timer when it reaches zero if the TRPT bit is a 1.
0x1B - Watchdog Timer
This register controls the Watchdog Timer function.
Table 82: Watchdog Timer Register
Bit
7
Name
WDS
Reset
0
DS0002V1p0
6
5
4
3
2
1
BMB
0
0
0
Page 67 of 81
0
WRB
0
0
0
0
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AM08XX Datasheet
Table 83: Watchdog Timer Register Bits
Bit
Name
Function
7
WDS
Watchdog Steering. When 0, the Watchdog Timer will generate WIRQ when it times out. When 1,
the Watchdog Timer will generate a reset when it times out.
6:2
BMB
The number of clock cycles which must occur before the Watchdog Timer times out. A value of
00000 disables the Watchdog Timer function.
1:0
WRB
The clock frequency of the Watchdog Timer, as shown in Table 84.
Table 84: Watchdog Timer Frequency Select
WRB Value
Watchdog Timer Frequency
00
16 Hz
01
4 Hz
10
1 Hz
11
1/4 Hz
6.8 Oscillator Registers
6.8.1
0x1C - Oscillator Control
This register controls the overall Oscillator function. It may only be written if the Configuration Key register
contains the value 0xA1. An Autocalibration cycle is initiated immediately whenever this register is written
with a value in the ACAL field which is not zero.
Table 85: Oscillator Control Register
Bit
7
Name
OSEL
Reset
0
6
5
ACAL
0
0
4
3
2
1
0
AOS
FOS
RESERVED
OFIE
ACIE
0
0
0
0
0
Table 86: Oscillator Control Register Bits
Bit
Name
Function
7
OSEL
When 1, request the RC Oscillator to generate a 128 Hz clock for the timer circuits. When 0,
request the XT Oscillator to generate a 32.786 kHz clock to the timer circuit. Note that if the XT
Oscillator is not operating, the oscillator switch will not occur. The OMODE field in the Oscillator
Status register indicates the actual oscillator which is selected.
6:5
ACAL
Controls the automatic calibration function, as described in Autocalibration.
4
AOS
When 1, the oscillator will automatically switch to RC oscillator mode when the system is powered
from the battery. When 0, no automatic switching occurs.
3
FOS
n 1, the oscillator will automatically switch to RC oscillator mode when an oscillator failure is
detected. When 0, no automatic switching occurs.
DS0002V1p0
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AM08XX Datasheet
Table 86: Oscillator Control Register Bits
Bit
Name
2
RESERVED
1
OFIE
Oscillator Fail interrupt enable. When 1, an Oscillator Failure will generate an IRQ signal.
0
ACIE
When 1, an Autocalibration Failure will generate an interrupt.
6.8.2
Function
RESERVED
0x1D – Oscillator Status Register
This register holds several miscellaneous bits used to control and observe the oscillators.
Table 87: Oscillator Status Register
Bit
7
XTCAL
Name
Reset
6
0
0
5
4
LKO2
OMODE
1
0
3
2
RESERVED
0
0
1
0
OF
ACF
1
0
Table 88: Oscillator Status Register Bits
Bit
Name
Function
7:6
XTCAL
Extended Crystal Calibration. This field defines a value by which the Crystal Oscillator is adjusted
to compensate for low capacitance crystals, independent of the normal Crystal Calibration function controlled by the Calibration XT Register. The frequency generated by the Crystal Oscillator
is slowed by 122 ppm times the value in the XTCAL field (0, -122,-244 or -366 ppm).
5
LKO2
Lock OUT2. If this bit is a 1, the OUTB register bit (see Section 7.3.2) cannot be set to 1. This is
typically used when OUT2 is configured as a power switch, and setting OUTB to a 1 would turn off
the switch.
4
OMODE
(read only) – Oscillator Mode. This bit is a 1 if the RC Oscillator is selected to drive the internal
clocks, and a 0 if the Crystal Oscillator is selected. If the STOP bit is set, the OMODE bit is invalid.
3:2
RESERVED
1
OF
0
ACF
RESERVED
Oscillator Failure. This bit is set on a power on reset, when both the system and battery voltages
have dropped below acceptable levels. It is also set if an Oscillator Failure occurs, indicating that
the crystal oscillator is running at less than 8 kHz. It can be cleared by writing a 0 to the bit.
Set when an Autocalibration Failure occurs, indicating that either the RC Oscillator frequency is
too different from 128 Hz to be correctly calibrated or the XT Oscillator did not start.
6.9 Miscellaneous Registers
6.9.1
0x1F - Configuration Key
This register contains the Configuration Key, which must be written with specific values in order to access
some registers and functions. The Configuration Key is reset to 0x00 on any register write.
Table 89: Configuration Key Register
Bit
7
6
5
DS0002V1p0
3
2
1
0
0
0
0
Configuration Key
Name
Reset
4
0
0
0
0
Page 69 of 81
0
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AM08XX Datasheet
Table 90: Configuration Key Register Bits
1.
2.
3.
Bit
Name
7:0
Configuration
Key
Function
Written with specific values in order to access some registers and functions.
Writing a value of 0xA1 enables write access to the Oscillator Control register
Writing a value of 0x3C does not update the Configuration Key register, but generates a Software
Reset (see Software Reset).
Writing a value of 0x9D enables write access to the Trickle Register (0x20), the BREF Register
(0x21), the AFCTRL Register (0x26), the Batmode I/O Register (0x27) and the Output Control Register (0x30).
6.10 Analog Control Registers
6.10.1 0x20 - Trickle
This register controls the Trickle Charger. The Key Register must be written with the value 0x9D in order to
enable access to this register.
Table 91: Trickle Register
Bit
7
6
4
3
TCS
Name
Reset
5
0
0
2
1
DIODE
0
0
0
0
ROUT
0
0
0
Table 92: Trickle Register Bits
Bit
Name
Function
7:4
TCS
3:2
DIODE
Diode Select. A value of 10 inserts a standard diode into the trickle charge circuit, with a voltage
drop of 0.6V. A value of 01 inserts a schottky diode into the trickle charge circuit, with a voltage drop
of 0.3V. Other values disable the Trickle Charger.
1:0
ROUT
Output Resistor. This selects the output resistor of the trickle charge circuit, as shown in Table 93.
A value of 1010 enables the trickle charge function. All other values disable the Trickle Charger.
Table 93: Trickle Charge Output Resistor
DS0002V1p0
ROUT Value
Series Resistor
00
Disable
01
3 KΩ
10
6 KΩ
11
11 KΩ
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AM08XX Datasheet
6.10.2 0x21 - BREF Control
This register controls the reference voltages used in the Wakeup Control system. The Key Register must
be written with the value 0x9D in order to enable access to this register.
Table 94: BREF Control Register
Bit
7
6
4
3
2
BREF
Name
Reset
5
1
1
1
0
0
0
RESERVED
1
1
0
0
Table 95: BREF Control Register Bits
Bit
Name
Function
7:4
BREF
This selects the voltage reference which is compared to the battery voltage VBAT to produce the
BBOD signal. Typical values are shown in Table 96. The valid BREF values are 0x7, 0xB, 0xD,
and 0xF. The reset value is 0xF. All other values are RESERVED.
3:0
RESERVED
RESERVED
Table 96: VBAT Reference Voltage
BREF Value
VBAT Falling Voltage (TYP)
VBAT Rising Voltage (TYP)
0111
2.5V
3.0V
1011
2.1V
2.5V
1101
1.8V
2.2V
1111
1.4V
1.6V
6.10.3 0x26 – AFCTRL
This register holds the enable code for the Autocalibration Filter (AF) filter capacitor connected to the AF
pin. Writing the value 0xA0 to this register enables the AF pin. Writing the value 0x00 to this register
disables the AF pin. No other value may be written to this register. The Configuration Key Register must be
written with the value 0x9D prior to writing the AFCTRL Register.
Table 97: AFCTRL Register
Bit
7
6
5
4
DS0002V1p0
2
1
0
0
0
0
0
AFCTRL
Name
Reset
3
0
0
0
0
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AM08XX Datasheet
Table 98: AFCTRL Register Bits
Bit
Name
7:0
AFCTRL
Function
If 0xA0, enable the AF pin. If 0x00, disable the AF pin.
6.10.4 0x27 – Batmode IO Register
This register holds the IOBM bit which controls the enabling and disabling of the I/O interface when a
Brownout Detection occurs. It may only be written if the Configuration Key register contains the value
0x9D. All undefined bits must be written with 0.
Table 99: Batmode IO Register
Bit
7
Name
IOBM
Reset
1
6
5
4
3
2
1
0
0
0
0
RESERVED
0
0
0
0
Table 100: Batmode IO Register Bits
Bit
Name
Function
7
IOBM
If 1, the AM08XX will not disable the I/O interface even if VCC goes away and VBAT is still present.
This allows external access while the AM08XX is powered by VBAT.
6:0
RESERVED
RESERVED - must write only 0000000.
6.10.5 0x2F – Analog Status Register (Read Only)
This register holds eight status bits which indicate the voltage levels of the VCC and VBAT power inputs.
Table 101: Analog Status Register
Bit
7
6
Name
BBOD
BMIN
5
4
3
RESERVED
2
1
0
VINIT
RESERVED
Reset
Table 102: Analog Status Register Bits
Bit
Name
7
BBOD
If 1, the VBAT input voltage is above the BREF threshold.
6
BMIN
If 1, the VBAT input voltage is above the minimum operating voltage (1.2 V).
DS0002V1p0
Function
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AM08XX Datasheet
Table 102: Analog Status Register Bits
Bit
Name
5:2
RESERVED
1
VINIT
0
RESERVED
Function
RESERVED
If 1, the VCC input voltage is above the minimum power up voltage (1.6 V).
RESERVED
6.10.6 0x30 – Output Control Register
This register holds bits which control the behavior of the I/O pins under various power down conditions.
The Key Register must be written with the value 0x9D in order to enable access to this register.
Table 103: Output Control Register
Bit
7
6
5
Name
WDBM
EXBM
Reset
0
0
4
3
2
1
0
0
0
0
RESERVED
0
0
0
Table 104: Output Control Register Bits
Bit
Name
Function
7
WDBM
If 1, the WDI input is enabled when the AM08XX is powered from VBAT. If 0, the WDI input is disabled when the AM08XX is powered from VBAT.
6
EXBM
If 1, the EXTI input is enabled when the AM08XX is powered from VBAT. If 0, the EXTI input is disabled when the AM08XX is powered from VBAT.
5:0
RESERVED
RESERVED
6.11 ID Registers
6.11.1 0x28 – ID0 - Part Number Upper Register (Read Only)
This register holds the upper eight bits of the part number in BCD format, which is always 0x08 for the
AM08XX family.
Table 105: 28 – ID0 – Part Number Upper Register
Bit
7
DS0002V1p0
5
4
3
Part Number - Digit 3
Name
Reset
6
0
0
0
2
1
0
Part Number - Digit 2
0
Page 73 of 81
1
0
0
0
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AM08XX Datasheet
6.11.2 0x29 – ID1 - Part Number Lower Register (Read Only)
This register holds the lower eight bits of the part number in BCD format.
Table 106: 28 – ID1 – Part Number Lower Register
Bit
7
6
5
4
3
2
1
Name
Part Number - Digit 1
Part Number - Digit 0
Reset
Preconfigured Digit 1
Preconfigured Digit 0
0
6.11.3 0x2A – ID2 - Part Revision (Read Only)
This register holds the Revision number of the part.
Table 107: 2A – ID2 – Part Revision Register
Bit
7
6
4
3
2
MAJOR
Name
Reset
5
0
0
1
0
MINOR
0
1
0
0
1
1
1
0
Table 108: 2A – ID2 – Part Revision Register Bits
Bit
Name
Function
7:3
MAJOR
This field holds the major revision of the AM08XX.
2:0
MINOR
This field holds the minor revision of the AM08XX.
6.11.4 0x2B – ID3 – Lot Lower (Read Only)
This register holds the lower 8 bits of the manufacturing lot number.
Table 109: 2B – ID3 – Lot Lower Register
Bit
7
6
5
4
3
Name
Lot[7:0]
Reset
Preconfigured Lot Number
2
Table 110: 2B – ID3 – Lot Lower Register Bits
Bit
Name
7:0
Lot[7:0]
DS0002V1p0
Function
This field holds the lower 8 bits of the manufacturing lot number.
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AM08XX Datasheet
6.11.5 0x2C – ID4 – ID Upper (Read Only)
This register holds part of the manufacturing information of the part, including bit 9 of the manufacturing lot
number and the upper 7 bits of the unique part identifier. The 15-bit ID field contains a unique value for
each AM08XX part.
Table 111: 2C – ID4 – ID Upper Register
Bit
7
Name
Lot[9]
6
5
4
3
2
1
0
ID[14:8]
Preconfigured Value
Reset
Table 112: 2C – ID4 – ID Upper Register Bits
Bit
Name
Function
7
Lot[9]
This field holds bit 9 of the manufacturing lot number.
1:0
ID[14:8]
This field holds the upper 7 bits of the unique part ID.
6.11.6 0x2D – ID5 – Unique Lower (Read Only)
This register holds the lower 8 bits of the unique part identifier. The 15-bit ID field contains a unique value
for each AM08XX part.
Table 113: 2D – ID5 – ID Lower Register
Bit
7
6
5
4
3
Name
ID]7:0]
Reset
Preconfigured Value
2
1
0
Table 114: 2D – ID5 – ID Lower Register Bits
Bit
Name
7:0
ID[7:0]
DS0002V1p0
Function
This field holds the lower 8 bits of the unique part ID.
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AM08XX Datasheet
6.11.7 0x2E – ID6 – Wafer (Read Only)
Table 115: 2E – ID6 – Wafer Register
Bit
7
6
Name
Lot[8]
5
4
3
2
1
Wafer
0
RESERVED
Preconfigured Value
Reset
Table 116: 2E – ID6 – Wafer Register Bits
Bit
Name
Function
7
Lot[8]
This field holds bit 8 of the manufacturing lot number.
6:2
Wafer
This field holds the manufacturing wafer number.
1:0
RESERVED
RESERVED
6.12 Ram Registers
6.12.1 0x3F - Extension RAM Address
This register controls access to the Extension RAM, and includes some miscellaneous control bits.
Table 117: 3F – Extension RAM Address Register
Bit
7
6
5
4
3
2
Name
O4BM
BPOL
WDIN
EXIN
RSVD
XADA
Reset
0
0
0
0
Read Only
1
0
XADS
0
0
Table 118: 3F – Extension RAM Address Register Bits
Bit
Name
Function
7
O4BM
If 1, the CLKOUT/nIRQ3 output is enabled when the AM08XX is powered from VBAT. If 0, the CLKOUT/nIRQ3 output is completely disconnected when the AM08XX is powered from VBAT.
6
BPOL
BL Polarity. When 0, the Battery Low flag BL is set when the VBAT voltage goes below the BREF
threshold. When 1, the Battery Low flag BL is set when the VBAT voltage goes above the BREF
threshold.
5
WDIN
(read only) – this bit supplies the current level of the WDI pin.
4
EXIN
(read only) – this bit supplies the current level of the EXTI pin.
3
RSVD
RESERVED.
2
XADA
This field supplies the upper bit for addresses to the Alternate RAM address space.
1:0
XADS
This field supplies the upper two address bits for the Standard RAM address space.
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AM08XX Datasheet
6.12.2 0x40 - 0x7F – Standard RAM
64 bytes of RAM space which may be accessed in either I2C or SPI interface mode. The data in the RAM
is held when using battery power. The upper 2 bits of the RAM address are taken from the XADS field, and
the lower 6 bits are taken from the address offset, supporting a total RAM of 256 bytes. The initial values of
the RAM locations are undefined.
6.12.3 0x80 - 0xFF – Alternate RAM
128 bytes of RAM which may be accessed only in I2C interface mode. The data in the RAM is held when
using battery power. The upper bit of the RAM address is taken from the XADA field, and the lower 7 bits
are taken from the address offset, supporting a total RAM of 256 bytes. The initial values of the RAM
locations are undefined.
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AM08XX Datasheet
6.13 Package Mechanical Information
Figure 33 illustrates the package mechanical information.
PACKAGE TOP VIEW
3.00 ± 0.05
3.00 ± 0.05
EXAMPLE PCB LAND PATTERN
2.26
3.30
2.30
3.26
0.30
Pin1
Marking
1.80
x16
1.80
PACKAGE SIDE VIEW
0.52
0.20 REF
0.85 ± 0.05
0.50
Seating Plane
EXAMPLE SOLDER STENCIL
PACKAGE BOTTOM VIEW
0.50
0.25 REF
1.80 ± 0.10
0.50
x16
x16
0.20
1.80 ± 0.10
Thermal Pad
0.26
1
0.20
0.48
0.50
0.35 ± 0.05
0.50 BSC
Drawing Notes:
1. All dimensions are in millimeters.
2. These drawings are subject to change without notice.
3. Quad Flat‐pack, No‐leads (QFN) package configuration.
4. The package thermal pad must be soldered to the board for connectivity and mechanical performance .
5. Customers should contact their board fabricator for minimum solder mask tolerances between signal pads.
Figure 33. Package Mechanical Diagram
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AM08XX Datasheet
7.
Reflow Profile
Figure 34 illustrates the reflow soldering requirements.
Figure 34. Reflow Soldering Diagram
Table 119: Reflow Soldering Requirements
Profile Feature
Preheat/Soak
Temperature Min (Tsmin)
Temperature Max (Tsmax)
Time (ts) from (Tsmin to Tsmax)
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Requirement
150 °C
200 °C
60-120 seconds
Ramp-up rate (TL to Tp)
3 °C/second max.
Liquidous temperature (TL)
Time (tL) maintained above TL
217 °C
60-150 seconds
Peak package body temperature (Tp)
260 °C max.
Time (tp) within 5 °C of Tp
30 seconds max.
Ramp-down rate (Tp to TL)
6 °C/second max.
Time 25 °C to peak temperature
8 minutes max.
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AM08XX Datasheet
8.
Ordering Information
Table 120: Ordering Information
AM18XX Orderable Part Numbers
Package
Temperature
Range
MSL Level(2)
Pb-Free(1) 16-Pin QFN
3 x 3 mm
-40 to +85 °C
1
Device
Standard
Tape and Reel - 3000 pcs.
AM0801
AM0801B3IPS
AM0801B3IT3
AM0803
AM0803B3IPS
AM0803B3IT3
AM0804
AM0804B3IPS
AM0804B3IT3
AM0805
AM0805B3IPS
AM0805B3IT3
AM0811
AM0811B3IPS
AM0811B3IT3
AM0813
AM0813B3IPS
AM0813B3IT3
AM0814
AM0814B3IPS
AM0814B3IT3
AM0815
AM0815B3IPS
AM0815B3IT3
(1) Compliant
and certified with the current RoHS requirements for all 6 substances, including the requirement that lead not
exceed 0.1% by weight in raw homogeneous materials. The package was designed to be soldered at high temperatures
(per reflow profile) and can be used in specified lead-free processes.
(2)
9.
Moisture Sensitivity Level rating according to the JEDEC J-STD-020D industry standard classifications.
Document Revision History
Table 121: Document Revision History
Rev #
Description
0.00
Initial version
0.90
Initial preliminary release
Formating changes. Updated values in electrical specification tables. Added AF pin and description. Added
AM18XX VBAT application example. Removed OUTPP, XTF, and XEN bits. Updated BREF selection tables.
0.91
1.0
Added minimum I2C/SPI bus frequencies. Added tXTST parameter. Added autocalibration temperature range
of operation. Added PSW pulsed current spec. Added AFCTRL register. Added 1.5k ohm VBAT series impedance requirement. Updated trickle charger information to include schottky diode. Added current vs. temperature curves for VCC and VBAT. Added RC frequency vs. temperature curves. Updated orderable part number
information. Updated register reset values.
- Added limits and/or temperature range specifications for the following parameters:
VCC,ABSMAX, VBAT,ABSMAX, VCCIO, VCCRST, VCCSWR, VCCSWF, VCCRS, VCCFS, VBATRST, VT+, VT-, ILEAK, IOH,
IOL, RDSON, IOLEAK, CEX, OAXT, FRCC, FRCU, TAC, IVCC:I2C, IVCC:SPIW, IVCC:SPIR, IVCC:XT, IVCC:RC, IVCC:ACAL,
IVCC:CK32, IVCC:CLK128, IVBAT:XT, IVBAT:RC, IVBAT:ACAL, IVBAT:VCC, VBRF, VBRR, VBRH, TBR, tLOW:VCC, tVL:FOUT,
tVH:FOUT, tXTST, tVL:NRST, tVH:NRST, tRL:NRST, tRH:NRST
- Removed tBREF parameter
- Additional note on autocalibration operating temperature range in the electrical specification section
- Added additional description to the Autocalibration Fail section
- Updated XT digital calibration adjustment value equation
- Removed VCCRS parameter as there is no requirement for the VCC rising slew rate
- Added curves to the electrical specification section: VCC Current vs. Voltage in different operating modes,
VCC Current vs. Voltage During I2C/SPI burst read/write, VCC Current vs. Voltage with 32.768kHz Clock Output, VBAT Current vs. Voltage in different operating modes, VBAT current vs. Voltage in VCC power state
- Removed typical values at 1.5V and 3.6V in VCC supply current table and replaced with VCC supply current
vs. voltage curves
- Removed typical values at 1.5V and 3.6V in VBAT supply current table and replaced with VBAT supply current vs. voltage curve
- Updated orderable part numbers
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AM08XX Datasheet
10. Contact Information
Address
Phone
Website
General Information
Sales
Technical Support
Ambiq Micro, Inc.
303 Camp Craft Road
Westlake Hills, TX 78746
+1 (512) 394-8542
www.ambiqmicro.com
[email protected]
[email protected]
[email protected]
11. Legal Information and Disclaimers
AMBIQ MICRO INTENDS FOR THE CONTENT CONTAINED IN THE DOCUMENT TO BE ACCURATE AND RELIABLE. THIS CONTENT MAY, HOWEVER, CONTAIN TECHNICAL INACCURACIES, TYPOGRAPHICAL ERRORS OR OTHER MISTAKES. AMBIQ MICRO MAY MAKE CORRECTIONS
OR OTHER CHANGES TO THIS CONTENT AT ANY TIME. AMBIQ MICRO AND ITS SUPPLIERS RESERVE THE RIGHT TO MAKE CORRECTIONS,
MODIFICATIONS, ENHANCEMENTS, IMPROVEMENTS AND OTHER CHANGES TO ITS PRODUCTS, PROGRAMS AND SERVICES AT ANY TIME
OR TO DISCONTINUE ANY PRODUCTS, PROGRAMS, OR SERVICES WITHOUT NOTICE.
THE CONTENT IN THIS DOCUMENT IS PROVIDED "AS IS". AMBIQ MICRO AND ITS RESPECTIVE SUPPLIERS MAKE NO REPRESENTATIONS
ABOUT THE SUITABILITY OF THIS CONTENT FOR ANY PURPOSE AND DISCLAIM ALL WARRANTIES AND CONDITIONS WITH REGARD TO
THIS CONTENT, INCLUDING BUT NOT LIMITED TO, ALL IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHT.
AMBIQ MICRO DOES NOT WARRANT OR REPRESENT THAT ANY LICENSE, EITHER EXPRESS OR IMPLIED, IS GRANTED UNDER ANY PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT OF AMBIQ MICRO COVERING OR RELATING TO
THIS CONTENT OR ANY COMBINATION, MACHINE, OR PROCESS TO WHICH THIS CONTENT RELATE OR WITH WHICH THIS CONTENT MAY
BE USED.
USE OF THE INFORMATION IN THIS DOCUMENT MAY REQUIRE A LICENSE FROM A THIRD PARTY UNDER THE PATENTS OR OTHER INTELLECTUAL PROPERTY OF THAT THIRD PARTY, OR A LICENSE FROM AMBIQ MICRO UNDER THE PATENTS OR OTHER INTELLECTUAL PROPERTY OF AMBIQ MICRO.
INFORMATION IN THIS DOCUMENT IS PROVIDED SOLELY TO ENABLE SYSTEM AND SOFTWARE IMPLEMENTERS TO USE AMBIQ MICRO
PRODUCTS. THERE ARE NO EXPRESS OR IMPLIED COPYRIGHT LICENSES GRANTED HEREUNDER TO DESIGN OR FABRICATE ANY INTEGRATED CIRCUITS OR INTEGRATED CIRCUITS BASED ON THE INFORMATION IN THIS DOCUMENT. AMBIQ MICRO RESERVES THE RIGHT
TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN. AMBIQ MICRO MAKES NO WARRANTY, REPRESENTATION
OR GUARANTEE REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR DOES AMBIQ MICRO ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT, AND SPECIFICALLY DISCLAIMS ANY AND ALL
LIABILITY, INCLUDING WITHOUT LIMITATION CONSEQUENTIAL OR INCIDENTAL DAMAGES. “TYPICAL” PARAMETERS WHICH MAY BE PROVIDED IN AMBIQ MICRO DATA SHEETS AND/OR SPECIFICATIONS CAN AND DO VARY IN DIFFERENT APPLICATIONS AND ACTUAL PERFORMANCE MAY VARY OVER TIME. ALL OPERATING PARAMETERS, INCLUDING “TYPICALS” MUST BE VALIDATED FOR EACH CUSTOMER
APPLICATION BY CUSTOMER’S TECHNICAL EXPERTS. AMBIQ MICRO DOES NOT CONVEY ANY LICENSE UNDER NEITHER ITS PATENT
RIGHTS NOR THE RIGHTS OF OTHERS. AMBIQ MICRO PRODUCTS ARE NOT DESIGNED, INTENDED, OR AUTHORIZED FOR USE AS COMPONENTS IN SYSTEMS INTENDED FOR SURGICAL IMPLANT INTO THE BODY, OR OTHER APPLICATIONS INTENDED TO SUPPORT OR SUSTAIN
LIFE, OR FOR ANY OTHER APPLICATION IN WHICH THE FAILURE OF THE AMBIQ MICRO PRODUCT COULD CREATE A SITUATION WHERE
PERSONAL INJURY OR DEATH MAY OCCUR. SHOULD BUYER PURCHASE OR USE AMBIQ MICRO PRODUCTS FOR ANY SUCH UNINTENDED
OR UNAUTHORIZED APPLICATION, BUYER SHALL INDEMNIFY AND HOLD AMBIQ MICRO AND ITS OFFICERS, EMPLOYEES, SUBSIDIARIES,
AFFILIATES, AND DISTRIBUTORS HARMLESS AGAINST ALL CLAIMS, COSTS, DAMAGES, AND EXPENSES, AND REASONABLE ATTORNEY
FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PERSONAL INJURY OR DEATH ASSOCIATED WITH SUCH UNINTENDED
OR UNAUTHORIZED USE, EVEN IF SUCH CLAIM ALLEGES THAT AMBIQ MICRO WAS NEGLIGENT REGARDING THE DESIGN OR MANUFACTURE OF THE PART.
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