80.0 0.5 71.2 66.0(VA) 56.2(AA) 0.6 0.55 13.5Max 8.9 18.3 5.95 5.55 0.7 0.65 16 31.0 K 11.5 40.55 2.5 4- 2.5 PTH 4- 5.0 PAD 75.0 1.6 0.4 A DOT SIZE SCALE 5/1 Co ., 25.2 16.0(VA) 36.0 0.5 1 0.6 Lt d. P2.54*15=38.1 1.8 16- 1.0 PTH 3.55 2.95 2.5 4.95 7.55 12.45 8.0 2 12.55 10.3 5.7 Contour Drawing &Block Diagram LED B/L Com1~16 Controller/Com Driver Y MPU SDA SCL SP D Seg41~80 Seg Driver M CL1 CL2 Vdd,Vss,V1~V5 DI Optional ST AR External contrast adjustment. Bias and Power Circuit VR 10K~20K Seg1~40 N.V. Generator Vdd Vo Vss LA IIC 16X2 LCD Character located DDRAM address DDRAM address 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F W IN Interface Pin Function Pin No. Symbol Level Description 1 V SS 0V Ground 2 V DD 5.0V 3 VO 4 NC － No connection 5 NC － No connection 6 NC － No connection 7 SA0 H/L 8 SA1 H/L 9 NC － No connection 10 NC － No connection 11 NC － No connection Supply Voltage for logic (Variable) Operating voltage for LCD 12 In IIC interface ,DB1(SA1) and DB0(SA0) are used for Slave address, must be connect to VDD or VSS CSB H/L 13 SDA H/L In IIC serial mode, used as chip selection input. When CSB = “Low”, selected When CSB = “High”, not selected. ( Low access enable ) serial input data 14 SCL H/L serial clock input 15 A － LED + 16 K － LED－ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Vss Vdd Vo NC NC NC SA0 SA1 NC NC NC CSB SDA SCL A K