PT16580 General Purpose LCD Driver IC DESCRIPTION PT16580 is an LCD Driver IC which can drive up to 200 segments. It can be used for frequency display in microprocessor-controlled radio receiver and in other display applications. PT16580 supports both 1/3 duty, and 1/4 duty drive. Pin assignment and application circuit are optimized for easy PCB layout and cost saving advantages. APPLICATION • Electronic equipment with LCD display BLOCK DIAGRAM FEATURES • CMOS technology • Up to 153 segments for 1/3 duty and 200 segments for 1/4 duty drive can be displayed • 1/3 Duty - 1/2 Bias and 1/3 Duty - 1/3 Bias drive techniques • 1/4 Duty - 1/2 Bias and 1/4 Duty - 1/3 Bias drive techniques • Power saving mode and all segments OFF function • Direct display of display data without using a decoder • RC oscillation circuit • Power supply voltage: 4.5V to 6V • CMOS/TTL compatible logic input pins • LCD drive bias voltage can be provided internally or externally • On-Chip voltage detection type reset circuit • Programmable PWM signal output pins • Available in 64 pins LQFP Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT16580 APPLICATION CIRCUIT 1 1/2 BIAS (FOR NORMAL PANEL) Notes: 1. 10KΩ ≥ R ≥1KΩ 2. *=Please select the suitable transistor 1/3 BIAS (FOR NORMAL PANELS) Notes: 1. 10KΩ ≥ R ≥1KΩ 2. *=Please select the suitable transistor V1.0 2 May 2011 PT16580 APPLICATION CIRCUIT 2 1/2 BIAS (FOR NORMAL PANEL) Notes: 1. 10KΩ ≥ R ≥1KΩ 2. *=Please select the suitable transistor 1/3 BIAS (FOR NORMAL PANELS) Notes: 1. 10KΩ ≥ R ≥1KΩ 2. *=Please select the suitable transistor V1.0 3 May 2011 PT16580 ORDER INFORMATION Valid Part Number PT16580-LQ Package Type 64 Pins, LQFP Top Code PT16580-LQ PIN CONFIGURATION V1.0 4 May 2011 PT16580 PIN DESCRIPTION Pin Name SG1 to SG50 COM4/SG51 COM3 to COM1 I/O O Active - O - VDD - - VDD1 I - VDD2 I - VSS - - Ground 58 CE I H Chip enable pin 59 CLK I Synchronization clock pin 60 DI I - Transfer data input pin 61 P1 to P3 O H PWM output pins V1.0 Description Pin No. 1 to 50 Segment output pins Common driver output pins 51 to 54 The COM4/ SG51 pin can be used as a segment output in 1/3 duty Power supply 55 Supply voltage in the range 4.5 to 6.0V Used for the 2/3 Bias Voltage when the Bias Voltage is provided externally. 56 Connect to VDD2 when 1/2 bias is used Used for the 1/3 Bias Voltage when the Bias Voltage is provided externally. 57 Connect to VDD1 when 1/2 Bias is used 62 to 64 5 May 2011 PT16580 INPUT/OUTPUT CONFIGURATIONS The schematic diagrams of the input and output circuits of the logic section are shown below: INPUT PINS: CLK, CE, DI OUTPUT PINS: COM1 TO COM3, SG1 TO SG50, COM4/SG51 OUTPUT PINS: P1 TO P3 V1.0 6 May 2011 PT16580 FUNCTION DESCRIPTION LCD SERIAL DATA TRANSFER FORMAT (1/3 DUTY) CONDITION 1: WHEN CLK IS TERMINATED AT “LOW” LEVEL Notes: 1. Address: 41H 2. D1 to D153: Display Data 3. P1 to P3: PWM Output Enable Data 4. DT: 1/3 Duty or 1/4 Duty Drive Selection Data 5. DR: 1/2 or 1/3 Bias Drive Selection Data 6. SC: Segment ON /OFF Control Data 7. BU: Normal Mode/Power-Saving Mode Control Data CONDITION 2: WHEN CLK IS TERMINATED AT “HIGH” LEVEL Notes: 1. Address: 41H 2. D1 to D153: Display Data 3. P1 to P3: PWM Output Enable Data 4. DT: 1/3 Duty or 1/4 Duty Drive Selection Data 5. DR: 1/2 or 1/3 Bias Drive Selection Data 6. SC: Segment ON /OFF Control Data 7. BU: Normal Mode/Power-Saving Mode Control Data V1.0 7 May 2011 PT16580 LCD SERIAL DATA TRANSFER FORMAT (1/4 DUTY) CONDITION 1: WHEN CLK IS TERMINATED AT “LOW” LEVEL Notes: 1. Address: 41H 2. D1 to D200: Display Data 3. P1 to P3: PWM Output Enable Data 4. DT: 1/3 Duty or 1/4 Duty Drive Selection Data 5. DR: 1/2 or 1/3 Bias Drive Selection Data 6. SC: Segment ON /OFF Control Data 7. BU: Normal Mode/Power-Saving Mode Control Data V1.0 8 May 2011 PT16580 CONDITION 2: WHEN CLK IS TERMINATED AT “HIGH” LEVEL Notes: 1. Address: 41H 2. D1 to D200: Display Data 3. P1 to P3: PWM Output Enable Data 4. DT: 1/3 Duty or 1/4 Duty Drive Selection Data 5. DR: 1/2 or 1/3 Bias Drive Selection Data 6. SC: Segment ON /OFF Control Data 7. BU: Normal Mode/Power-Saving Mode Control Data V1.0 9 May 2011 PT16580 SERIAL DATA TRANSFER EXAMPLE 1/3 DUTY SERIAL DATA TRANSFER FOR 105 OR MORE SEGMENTS SERIAL DATA TRANSFER FOR LESS THAN 105 SEGMENTS Under a serial data transfer whereby less than 105 segments are used, 64 or 128 bits of serial data must be transmitted depending on the actual number of segments used. The display data bits D1 to D52 and the control data must always sent. Please refer to the figure below. 1/4 SERIAL DATA TRANSFER FOR 157 OR MORE SEGMENTS SERIAL DATA TRANSFER FOR LESS THAN 157 SEGMENTS Under a serial data transfer whereby less than 157 segments are used, 64, 128 or 192 bits of serial data must be transmitted depending on the actual number of segments used. The display data bits D1 to D52 and the control data must always sent. Please refer to the figure below. V1.0 10 May 2011 PT16580 DISPLAY DATA TO SEGMENT OUTPUT PIN CORRESPONDENCE (1/3 DUTY) Segment Output Pin SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23 SG24 SG25 SG26 COM1 D1 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 D49 D52 D55 D58 D61 D64 D67 D70 D73 D76 COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 D50 D53 D56 D59 D62 D65 D68 D71 D74 D77 COM3 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 D51 D54 D57 D60 D63 D66 D69 D72 D75 D78 Segment Output Pin SG27 SG28 SG29 SG30 SG31 SG32 SG33 SG34 SG35 SG36 SG37 SG38 SG39 SG40 SG41 SG42 SG43 SG44 SG45 SG46 SG47 SG48 SG49 SG50 SG51 COM1 D79 D82 D85 D88 D91 D94 D97 D100 D103 D106 D109 D112 D115 D118 D121 D124 D127 D130 D133 D136 D139 D142 D145 D148 D151 COM2 D80 D83 D86 D89 D92 D95 D98 D101 D104 D107 D110 D113 D116 D119 D122 D125 D128 D131 D134 D137 D140 D143 D146 D149 D152 COM3 D81 D84 D87 D90 D93 D96 D99 D102 D105 D108 D111 D114 D117 D120 D123 D126 D129 D132 D135 D138 D141 D144 D147 D150 D153 For example, the table below lists the segment output states for the SG11 Output Pins Display Data Segment Output Pin (SG11) State D31 D32 D33 0 0 0 The LCD segment corresponding to COM1, COM2 and COM3 are off. 0 0 1 The LCD segment corresponding to COM3 is on. 0 1 0 The LCD segment corresponding to COM2 is on. 0 1 1 The LCD segment corresponding to COM2 and COM3 are on. 1 0 0 The LCD segment corresponding to COM1 is on. 1 0 1 The LCD segment corresponding to COM1 and COM3 are on. 1 1 0 The LCD segment corresponding to COM1 and COM2 are on. 1 1 1 The LCD segment corresponding to COM1, COM2 and COM3 are on. V1.0 11 May 2011 PT16580 DISPLAY DATA AND THE OUTPUT PIN CORRESPONDENCE (1/4 DUTY) Output Pin SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23 SG24 SG25 SG26 SG27 SG28 SG29 SG30 SG31 SG32 SG33 SG34 SG35 SG36 SG37 SG38 SG39 SG40 SG41 SG42 SG43 SG44 SG45 SG46 SG47 SG48 SG49 SG50 V1.0 COM1 D1 D5 D9 D13 D17 D21 D25 D29 D33 D37 D41 D45 D49 D53 D57 D61 D65 D69 D73 D77 D81 D85 D89 D93 D97 D101 D105 D109 D113 D117 D121 D125 D129 D133 D137 D141 D145 D149 D153 D157 D161 D165 D169 D173 D177 D181 D185 D189 D193 D197 COM2 D2 D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46 D50 D54 D58 D62 D66 D70 D74 D78 D82 D86 D90 D94 D98 D102 D106 D110 D114 D118 D122 D126 D130 D134 D138 D142 D146 D150 D154 D158 D162 D166 D170 D174 D178 D182 D186 D190 D194 D198 12 COM3 D3 D7 D11 D15 D19 D23 D27 D31 D35 D39 D43 D47 D51 D55 D59 D63 D67 D71 D75 D79 D83 D87 D91 D95 D99 D103 D107 D111 D115 D119 D123 D127 D131 D135 D139 D143 D147 D151 D155 D159 D163 D167 D171 D175 D179 D183 D187 D191 D195 D199 COM4 D4 D8 D12 D16 D20 D24 D28 D32 D36 D40 D44 D48 D52 D56 D60 D64 D68 D72 D76 D80 D84 D88 D92 D96 D100 D104 D108 D112 D116 D120 D124 D128 D132 D136 D140 D144 D148 D152 D156 D160 D164 D168 D172 D176 D180 D184 D188 D192 D196 D200 May 2011 PT16580 For example, the table below lists the segment output states for the SG11 output pin. Display Data Segment Output Pin (SG11) State D41 D42 D43 D44 0 0 0 0 The LCD segments corresponding to COM1, COM2, COM3 and COM4 are off. 0 0 0 1 The LCD segment corresponding to COM4 is on. 0 0 1 0 The LCD segment corresponding to COM3 is on. 0 0 1 1 The LCD segments corresponding to COM3 and COM4 are on. 0 1 0 0 The LCD segment corresponding to COM2 is on. 0 1 0 1 The LCD segments corresponding to COM2 and COM4 are on. 0 1 1 0 The LCD segments corresponding to COM2 and COM3 are on. 0 1 1 1 The LCD segments corresponding to COM2, COM3 and COM4 are on. 1 0 0 0 The LCD segment corresponding to COM1 is on. 1 0 0 1 The LCD segments corresponding to COM1 and COM4 are on. 1 0 1 0 The LCD segments corresponding to COM1 and COM3 are on. 1 0 1 1 The LCD segments corresponding to COM1, COM3 and COM4 are on. 1 1 0 0 The LCD segments corresponding to COM1 and COM2 are on. 1 1 0 1 The LCD segments corresponding to COM1, COM2 and COM4 are on. 1 1 1 0 The LCD segments corresponding to COM1, COM2 and COM3 are on. 1 1 1 1 The LCD segments corresponding to COM1, COM2, COM3 and COM4 are on. V1.0 13 May 2011 PT16580 1/3 DUTY, 1/2 BIAS DRIVE WAVEFORMS V1.0 14 May 2011 PT16580 1/3 DUTY, 1/3 BIAS DRIVE WAVEFORMS V1.0 15 May 2011 PT16580 1/4 DUTY, 1/2 BIAS DRIVE WAVEFORMS V1.0 16 May 2011 PT16580 1/4 DUTY, 1/3 BIAS DRIVE WAVEFORMS V1.0 17 May 2011 PT16580 PWM SERIAL DATA TRANSFER FORMAT CONDITION 1: WHEN CLK IS TERMINATED AT “LOW” LEVEL CONDITION 2: WHEN CLK IS TERMINATED AT “HIGH” LEVEL Notes: 1. Address: 42H 2. D0 to D7: PWM control data PWM INSTRUCTION Instruction D7 D6 D5 D4 * * a Frame frequency set 0 0 b P1 PWM data set P2 PWM data set P3 PWM data set 0 1 1 1 0 1 Code D3 * D2 D1 D0 * * fPWM PWM data PWM data PWM data Description Frame frequency set fPWM = 0: fosc/(256) fPWM = 1: fosc/(512) 6-bit PWM data is set. Note: *=Don’t care V1.0 18 May 2011 PT16580 PWM OUTPUT FUNCTION DESCRIPTION PWM signals are outputted through P1 to P3 port. The duty cycle variation of PWM signal from 0 to 100% is divided into 33 steps. The different PWM data can be set to each separately. PWM data v.s. Duty cycle Duty Cycle of 128 125 100 75 50 25 0 0 4 8 12 16 20 24 28 32 PWM Data The relationship between PWM duty cycle and the register value is shown as below: PWM Data 0, 0, 0, 0, 0, 0 0, 0, 0, 0, 0, 1 0, 0, 0, 0, 1, 0 0, 0, 0, 0, 1, 1 0, 0, 0, 1, 0, 0 0, 0, 0, 1, 0, 1 0, 0, 0, 1, 1, 0 0, 0, 0, 1, 1, 1 0, 0, 1, 0, 0, 0 0, 0, 1, 0, 0, 1 0, 0, 1, 0, 1, 0 0, 0, 1, 0, 1, 1 0, 0, 1, 1, 0, 0 0, 0, 1, 1, 0, 1 0, 0, 1, 1, 1, 0 0, 0, 1, 1, 1, 1 0, 1, 0, 0, 0, 0 Duty 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 PWM Data 0, 1, 0, 0, 0, 1 0, 1, 0, 0, 1, 0 0, 1, 0, 0, 1, 1 0, 1, 0, 1, 0, 0 0, 1, 0, 1, 0, 1 0, 1, 0, 1, 1, 0 0, 1, 0, 1, 1, 1 0, 1, 1, 0, 0, 0 0, 1, 1, 0, 0, 1 0, 1, 1, 0, 1, 0 0, 1, 1, 0, 1, 1 0, 1, 1, 1, 0, 0 0, 1, 1, 1, 0, 1 0, 1, 1, 1, 1, 0 0, 1, 1, 1, 1, 1 1, 0, 0, 0, 0, 0 Duty 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124 128 The LED brightness can be selected from 33 levels (0 to 32). V1.0 19 May 2011 PT16580 VOLTAGE DETECTION TYPE RESET CIRCUIT (VDET) The Voltage Detection Type Reset Circuit generates an output signal and resets the system when power is applied for the first time and when voltage drops (that is, for example, the power supply voltage is less than or equal to the power down detection voltage (VDET = 3.0V typ.). To ensure that this reset function works properly, it is recommended that a capacitor must be connected to the power supply line so that both the power supply voltage (VDD) rise time when power is first applied and the power supply voltage (VDD) fall time when the voltage drops are at least 1ms. SYSTEM RESET If the supply voltage (VDD) rise time when power is first applied is at least 1ms, then the VDET output signal will initiate a system reset when the supply voltage is increased. Likewise, if the supply voltage (VDD) fall time when power drops is at least 1ms, then the VDET output signal will initiate a system reset when the supply voltage is decreased. It must be noted that the reset function is cleared at the point when all the serial data (Display Data- D1 to D153 in 1/3 duty or D1 to D200 in 1/4 duty and the control data) have been completely transferred. Please refer to the figure below. Power supply voltage VDD rise time: t1 > 1ms Power supply voltage VDD fall time: t2 > 1ms During the reset period, the internal states of the various blocks of PT16580 are enumerated below. It should be noted that the Address Detector, Shift Register and RGB Program Register Blocks are not reset during this period since serial data transfer is possible. (Please also refer to the Block Diagram Section) CLOCK GENERATOR BLOCK When the reset function is applied, the base clock is terminated. COMMON DRIVER, SEGMENT DRIVER, LATCH BLOCKS & PWM DRIVER When the reset function is applied, the display and P1 to P3 pin are turned OFF. It should be noted, however, that the display and PWM control data may be inputted to the latch circuit during the reset period. ADDRESS DETECTOR, SHIFT REGISTER & RGB PROGRAM REGISTER Since serial data transfer is possible, these circuits are not reset. V1.0 20 May 2011 PT16580 POWER ON SET When PT16580 is initialized, the internal status after power supply has been reset as the following table. Instruction At Reset Condition LCD bias DR = 1: 1/2 bias LCD display SC = 1: OFF P1 to P3 pin P1, P2, P3 = 0, 0, 0: all disable Power mode BU = 1: Power saving mode LCD duty DT = 0: 1/4duty PWM frequency D0 = 0: fosc/(256) PWM duty D5, D4, D3, D2, D1, D0 = 0, 0, 0, 0, 0, 0: 0/128 V1.0 21 May 2011 PT16580 ABSOLUTE MAXIMUM RATINGS (Unless otherwise specified, Ta = 25℃, Vss = 0V) Parameter Symbol Condition Maximum supply voltage VDDMAX VDD VIN1 CE, CLK, DI Input voltage VIN2 VDD1, VDD2 SG1 to SG50, COM4/SG51, Output voltage VOUT COM1 to COM3, P1 to P3 IOUT1 SG1 to SG51 Output current IOUT2 COM1 to COM4 IOUT3 P1 to P3 Ta = 85℃ Allowable power dissipation PDMAX Operating temperature Topr Storage temperature Tstg - Rating -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 Unit V -0.3 to VDD +0.3 V 300 3 10 200 -40 to +85 -65 to +150 μA mA mA mW ℃ ℃ V ALLOWABLE OPERATING RANGE (Unless otherwise specified, Ta = 25oC, Vss = 0V) Parameter Symbol Condition Supply voltage VDD VDD VDD1 VDD1 Input voltage VDD2 VDD2 High level input voltage VIH CE, CLK, DI Low level input voltage VIL CE, CLK, DI Data setup time tds CLK, DI (see Notes) Data hold time tdh CLK, DI (see Notes) CE wait time tcp CE, CLK (see Notes) CE setup time tcs CE, CLK (see Notes) CE hold time tch CE, CLK (see Notes) High level clock pulse width CLK (see Notes) tΦH Low level clock pulse width CLK (see Notes) tΦL Rise time tr CE, CLK, DI (see Notes) Fall time tf CE, CLK, DI (see Notes) V1.0 22 Min. 4.5 2.4 0 160 160 160 160 160 160 160 - Typ. 2/3VDD 1/3VDD 160 160 Max. 6.0 VDD VDD VDD 0.7 - Unit V V V V V ns ns ns ns ns ns ns ns ns May 2011 PT16580 Notes: 1. When CLK is terminated at “LOW” level 2. When CLK is terminated at “HIGH” level V1.0 23 May 2011 PT16580 ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta = 25℃, Vss = 0V, VDD = 5V) Parameter Symbol Conditions Hysteresis VH CE, CLK, DI Power-on detection voltage VDET CE, CLK, DI High level input current IIH VI = VDD CE, CLK, DI Low level input current IIL VI = 0V SG1 to SG50 VOH1 Io = -20µA COM1 to COM4 VOH2 High level output voltage Io = -100µA P1 to P3 VOH3 IO = -10mA SG1 to SG50 VOL1 Io = 20µA COM1 to COM4 Low level output voltage VOL2 Io = 100µA P1 to P3 VOL3 Io = 10mA COM1 to COM4 VMID1 1/2 Bias, Io = ±100µA SG1 to SG51 VMID2 1/3 Bias, Io = ±20µA Middle level output voltage SG1 to SG51 VMID3 (See Note 1) 1/3 Bias, Io = ±20µA COM1 to COM4 VMID4 1/3 Bias, Io = ±100µA COM1 to COM4 VMID5 1/3 Bias, Io = ±100µA Oscillation frequency Fosc OSC IDD1 Current drain IDD2 IDD3 Power Saving Mode VDD = 6V Outputs Open, 1/2 Bias VDD = 6V Outputs Open, 1/3 Bias Min. 2.5 Typ. 0.1VDD 3.0 Max. 3.5 Unit V V - - 5.0 μA -5.0 - - μA VDD-1.0 - - V VDD-1.0 - - V VDD-1.0 - - V - - 1.0 V - - 1.0 V - - 1.0 V 1/2VDD-1.0 - 1/2VDD+1.0 V 2/3VDD-1.0 - 2/3VDD+1.0 V 1/3VDD-1.0 - 1/3VDD+1.0 V 2/3VDD-1.0 - 2/3VDD+1.0 V 1/3VDD-1.0 - 1/3VDD+1.0 V 280 400 520 KHz - - 200 μA - 300 1000 μA - 375 1200 μA Note: Excluding the bias voltage generation divider resistors built in the VDD1 and VDD2. (See below) V1.0 24 May 2011 PT16580 PACKAGE INFORMATION 64 PINS, LQFP PACKAGE (BODY SIZE: 10MM X 10MM, PITCH: 0.50MM, THK BODY: 1.40MM) Symbol A A1 A2 b c D D1 E E1 e L L1 Min. 0.05 1.35 0.17 0.09 θ 0° 0.45 Nom. 1.40 0.22 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC 0.50 BSC 0.60 1.00 REF Max. 1.60 0.15 1.45 0.27 0.20 3.5° 7° 0.75 Notes: 1. Refer to JEDEC MS-026BCD. 2. All dimensions are in millimeter. V1.0 25 May 2011 PT16580 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.0 26 May 2011