KODENSHI KK0065

TECHNICAL DATA
KK0065
40 Channel Segment / Common Driver
For Dot Matrix LCD
The KK0065 is a LCD driver LSI which is fabricated by low power CMOS technology. Basically this LSI consists of
20 × 2 bit bi-directional shift register, 20 × 2 bit data latch and 20 × 2 bit driver. This LSI can be used a common or
segment driver.
FEATURES
FUNCTIONS
• Dot matrix LCD driver with 40-channel output.
• Selectable function to use common/segment drivers
simultaneously.
• Input / Output signal
- output: 20 × 2 channel waveform for LCD driving
- input: - Serial display data and control pulse from
the controller LSI.
• Bias voltage (V1-V6)
• Display driving bias: static -1/5
• Power supply voltage: +5V ± 10%, +3V ± 10%
• Supply voltage for display: 0 ~ -5V(VEE)
• Interface
driver(cascade connection)
Other KK0065
controller
IZ0066
KS0066
HD44780
SED1278
• CMOS Process
• Bare chip available
ABSOLUTE MAXIMUM RATING (Ta = 25oC)
Characteristic
Symbol
Value
Unit
Operating Voltage
VDD
-0.3 ~ 7.0
V
Driver Supply Voltage
VLCD
VDD - 13.5 ~ VDD + 0.3
V
Input Voltage 1
VIN1
- 0.3 ~ VDD + 0.3
V
Input Voltage 2 (V1-V6)
VIN2
VDD + 0.3 ~ VEE - 0.3
Operating Temperature
Storage Temperature
TOPR
TSTG
V
-30 ~ +85
o
-55 ~ +125
o
C
C
Voltage greater than above may damage to then circuit.
VEE: connect protection resistor (220Ω ± 5%)
1
KK0065
ELECTRICAL CHARACTERISTICS
DC characteristics (VDD=2.7~5.5V, VDD - VEE =3~13V, VSS=0V, Ta=-30 ~ +85OC )
Characteristic
Symbol
Test Condition
Min
Max
Unit
Applicable pin
Operating Current *
IDD
fCL2=400KHz
-
1
mA
-
Supply Current *
IEE
fCL1=1KHz
-
10
µA
Input High Voltage
VIH
-
0.7VDD
VDD
V
Input Low Voltage
VIL
0
0.3VDD
Input Leakage Current
ILKG
VIN =0-VDD
-5
5
Output High Voltage
VOH
IOH = -0.4mA
VDD0.4
-
Output Low Voltage
VOL
IOL = +0.4mA
-
0.4
Voltage Descending
VD1
ION=0.1mA for one of
SC1-SC40
-
1.1
VD2
ION=0.5mA for each
SC1-SC40
-
1.5
IV
VIH= VDD~ VEE
-10
10
Leakage Current
CL1, CL2, DL1,
DL2,
DR1, DR2,
µA
SHL1, SHL2, M,
FCS
DL1, DL2, DR1,
DR2
V
V(V1-V6),
SC(SC1-SC40)
µA
V1-V6
(Output SC1SC40:floating)
* VDD-VEE=4V
AC characteristics (VDD=2.7~5.5V, VDD - VEE =3~13V, VSS=0V, Ta=-30 ~ +85OC )
Characteristic
Symbol
Test Condition
Min
Max
Unit
Applicable pin
fCL
-
-
400
KHz
CL2
Clock High Level Width
tWCKH
-
800
-
CL1, CL2
Clock Low Level Width
tWCKL
-
800
-
CL2
tLS
from CL2 to CL1
500
-
tLS
from CL1 to CL2
500
-
Clock Rise/Fall Time
tR/tF
-
-
200
Data Set-up Time
tSU
-
300
-
DL1, DL2, DR1,
DR2,
Data Hold Time
tDH
-
300
-
FLM
Data Delay Time
tD
CL=15pF
-
500
Data Shift Frequency
Clock Set-up Time
ns
CL1, CL2
DL1, DL2, DR1,
DR2
Input/Output current excluded; When input is at the intermediate level with CMOS, excessive current flows through the
input circuit to the power supply,To avoid this, input level must be fixed at «H» or «L».
2
KK0065
BLOCK DIAGRAM
S S
C C
1 2
S
C
1
9
S
C
2
0
S
C
2
1
S
C
2
2
S
C
3
9
S
C
4
0
PART 2
PART 1
V1
V1
V2
V2
V3
LCD DRIVER
LCD DRIVER
V4
V5
V6
DATA LATCH
(20 bit)
DATA LATCH
(20 bit)
VDD
Vss
VEE
BIDIRECTIONAL
SHIFT REGISTER
(20bit)
BIDIRECTIONAL
SHIFT REGISTER
(20bit)
M
SW
CL1
CONTR
LOGIC
CL2
F
C
S
D
L
1
S
H
L
1
D
R
1
D
L
2
S
H
L
2
D
R
2
3
KK0065
PIN DESCRIPTION
PIN №
INP/
OUTP
VDD (24)
GND (34) Power
VEE (31)
NAME
DESCRIPTION
Operating Voltage
For logical circuit (+5 V ± 10%, +3 V ± 10%)
0 V (GND)
For LCD driver circuit (-5 V)
Negative Supply
Voltage
Bias Voltage
Input
Bias voltage level for LCD drive (select level)
V1 V2
(44,45)
LCD driver
LCD driver output
SC1÷SC20 Output
Input PART 1 Bias Voltage
Bias voltage level for LCD drive (nonselect level)
V3 V4
(46,47)
Input
Data interface Selection of the shift direction of Part 1 shift register
SHL1
(41)
SHL1
DL1
DR1
VDD
out
in
VSS
in
out
DL1,DR1 Input/
(35,36) Output
SC21÷
SC40
V5 V6
(48,49)
SHL2
(42)
Data input/output of Part 1 shift register
Output
Input
Input
PART 2
M
(40)
CL1,CL2
(32,33)
FCS
(43)
Input
LCD driver output
Bias Voltage
Bias voltage level for LCD drive (nonselect level)
Data interface Selection of the shift direction of Part 2 shift register
SHL2
DL2
DR2
VDD
out
in
VSS
in
out
Data input/output of Part 2 shift register
Alternated
signal for LCD
Input
driver output
Data shift / latch clock
Input
Mode selection
PART
1
2
FCS
VSS
VDD
VSS
VDD
CL1
latch clock
(
)
shift clock
)
(
CL2
shift clock
(
)
latch clock
)
(
Power
LCD
Power
VDD
or
VSS
Controller
or
KK0065
LCD driver
DL2,DR2 Input/
(37,38) Output
INTERFACE
Power
Supply
Power
VDD
or
VSS
Controller
or
KK0065
M
polarity
M
Controller
_
M
Shift/latch clock of display data and polarity of M signal
are changed by FCS signal.
By setting FCS to VDD level , user can select the function
that use Part 1 as segment driver and Part 2 as common
driver simultaneously.
NC(39)
No connection pin
N.C
4
KK0065
APPLICATION CIRCUIT
COM1~ COM16
DL1
FCS
SHL1
SC1 ~ SC40
KK0065
BT1510
DL2
DR1
DR2
CL1
CL2
LCD Panel
DL1
FCS
SHL1
SC1 ~ SC40
KK0065
BT1510
DL2
DR1
DR2
CL1
CL2
DL1
FCS
SHL1
SC1 ~ SC40
KK0065
BT1510
DL2
DR1
CL1
DR2
CL2
SHL2
M
VSS
VDD
V6 V5 V4 V3 V2 V1 VEE
V1
SHL2
M
VSS
VDD
V6 V5 V4 V3 V2 V1 VEE
V1
V2
SHL2
M
VSS
VDD
V6 V5 V4 V3 V2 V1 VEE
V2
V3
VDD
V3
VLCD (1/5 bia s)
GNDor
other voltage
V5
V4
V5
V4
VDD
CLK2
CLK1
M
VSS
OSC2
OSC1
D
SEG1~ SEG40
KK44780
BT1578
DB0 ~ DB7
To MPU
5
KK0065
PAD DIAGRAM
47
48
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
49
31
30
50
KK0065 (CHIP)
29
51
28
52
Y
27
53
26
X
54
25
(0,0)
55
24
56
23
Chip size:3240×2740
Pad size:100×100
Unit
:µm
57
58
22
21
59
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
PAD LOCATION
Pad
№
1
2
3
Pad
Name
VEE
CL1
CL2
X
Y
-1384
-1344
-1190
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VSS
DL1
DR1
DL2
DR2
M
SHL1
SHL2
FCS
V1
V2
V3
V4
V5
V6
SC40
SC39
-1002
-852
-702
-552
-402
-252
-102
48
198
482
632
782
932
1082
1232
1382
1381
Pad
Name
SC38
SC37
SC36
X
Y
-840
-1140
-1140
Pad
№
21
22
23
1381
1381
1381
-627.5
-477.5
-327.5
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-777.5
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SC35
SC30
SC31
SC32
SC33
SC34
SC29
SC28
SC27
SC26
SC25
SC24
SC23
SC22
SC21
SC20
SC19
1381
1381
1381
1381
1381
1381
1381
1380
1232
1082
932
782
632
482
332
115
-35
-177.5
-29.5
120.5
270.5
420.5
570.5
720.5
1135
1135
1135
1135
1135
1135
1135
1135
1135
1135
Pad
№
41
42
43
Pad
Name
SC18
SC17
SC16
X
Y
-185
-335
-485
1135
1135
1135
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
SC15
SC14
SC13
SC12
SC9
SC10
SC11
SC8
SC7
VDD
SC6
SC5
SC4
SC3
SC2
SC1
-635
-785
-1033
-1183
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
1135
1135
1135
1135
970
820
670
520
370
220
70
-80
-230
-380
-528
-678
6