Electronics, Inc. 750 North Mary Ave. ϖ Sunnyvale, CA 94085 U.S.A. Tel: 408-732-5000 Fax: 408-732-5055 http://www.atpinc.com Rev. Date: Jul. 22, 2011 A T P A Q5 6 M 7 2 D 8 B KH9 S 2GB DDR3-1333 UNBUFFERED ECC DIMM DESCRIPTION The ATP AQ56M72D8BKH9S is a high performance 2GB DDR3-1333 Unbuffered ECC SDRAM memory module. It is organized as 256M x 72 in a 240-pin Dual-In-Line Memory Module (DIMM) package. The module utilizes nine 256Mx8 DDR3 SDRAMs in FBGA package. The module consists of a 256-byte serial EEPROM, which contains the module configuration information. KEY FEATURES • High Density: 2GB (256M x 72) • DIMM Rank: 1 Rank • Cycle Time: 1.5ns (667MHz) • CAS Latency: 9 • Power supply: 1.5V ± 0.075V • Internal self calibration through ZQ • Burst lengths: 8 • Auto & Self refresh Part No. AQ56M72D8BKH9S • • • • • • 7.8 μs refresh interval at lower than TCASE 85°C, 3.9μs refresh interval at 85°C < TCASE < 95 °C Dynamic On Die Termination Fly-by topology PCB Height: 1.18 inches Asynchronous Reset RoHS compliant Max Freq 667MHz (1.5ns@CL=9) x2 Interface SSTL_1.5 PIN DESCRIPTION Pin Name Description Pin Name Description A0~A9, A11~A14 A10/AP BA0~BA2 SDRAM Address Bus Address Input/Auto precharge SDRAM Bank Select Column Address Strobe DIMM ECC Check bits Clock Inputs, positive line Clock Inputs, negative line Clock Enables Data Masks Temperature sensor Event output Data Input/Output Data strobes/ high data strobes Data strobes(negative line) ODT0 VTT RAS RESET WE CS0 SA0~SA2 SCL SDA RSVD VDD VDDQ VDDSPD On die termination SDRAM I/O termination supply Row Address Strobe Set DRAMs to Known State Write Enable Chip Selects I2C serial bus data line for EEPROM I2C serial bus clock for EEPROM I2C slave address select for EEPROM Reserved for Future Use Core Power I/O Driver Power SPD Power Input/Output Reference supply Command/address reference supply No Connect VSS Ground Memory bus test tool (Not Connect and Not Useable on DIMMs) CAS CB0~CB7 CK0 CK0 CKE0 DM0~DM8 Event DQ0~DQ63 DQS0~DQS8 DQS0 ~ DQS8 VREFDQ VREFCA NC TEST Your Ultimate Memory Solution! Page 1 of 7 ATP AQ56M72D8BKH9S PIN ASSIGNMENT No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 KEY 49 50 51 52 53 54 55 56 57 58 59 60 Designation No. Designation VREFDQ VSS DQ0 DQ1 VSS 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 154 155 156 157 158 159 160 161 162 VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC 94 95 96 97 98 99 100 101 102 163 164 165 166 167 168 VSS CB6 CB7 VSS NC (TEST) 169 170 171 172 173 174 175 176 177 178 179 180 NC VDD NC A14 VDD A12 A9 VDD A8 A6 VDD A3 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8 DQS8 VSS CB2 CB3 VSS NC NC CKE0 VDD BA2 NC VDD A11 A7 VDD A5 A4 VDD RESET No. Designation A2 VDD NC NC VDD VDD VREFCA NC VDD A10/AP BA0 VDD WE CAS VDD NC NC VDD NC VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT Your Ultimate Memory Solution! 750 North Mary Ave, Sunnyvale, CA 94085, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 2 of 7 No. Designation 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 A1 VDD VDD CK0 CK0 VDD EVENT A0 VDD BA1 VDD RAS CS0 VDD ODT0 A13 VDD NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC 214 215 216 217 218 219 220 221 222 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 NC 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT ATP AQ56M72D8BKH9S FUNCTIONAL BLOCK DIAGRAM CKE0 ODT0 CS0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQS8 DQS8 DM8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQS DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 VDDSPD DQS4 DQS4 DM4 CS ODT CKE U1 ZQ DQS5 DQS5 DM5 CS ODT CKE U3 ZQ DQS6 DQS6 DM6 CS ODT CKE U5 ZQ DQS7 DQS7 DM7 CS ODT CKE U7 ZQ CS ODT CKE U9 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 BA0-BA2 SDRAMS U1-U9 A0-A14 RAS SDRAMS U1-U9 CAS SDRAMS U1-U9 WE CK0 SDRAMS U1-U9 SDRAMS U1-U9 CK0 SDRAMS U1-U9 CS ODT CKE U2 ZQ CS ODT CKE U4 ZQ CS ODT CKE U6 ZQ CS ODT CKE U8 SDRAMS U1-U9 ZQ SPD VDD/VDDQ SDRAMS U1-U9 VREFDQ SDRAMS U1-U9 VSS SDRAMS U1-U9 VREFCA SDRAMS U1-U9 Serial PD w/ integrated Thermal sensor Integrated Thermal sensor in SPD SCL EVENT Your Ultimate Memory Solution! 750 North Mary Ave, Sunnyvale, CA 94085, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 3 of 7 SDA EVENT A0 A1 A2 SA0 SA1 SA2 ZQ ATP AQ56M72D8BKH9S ABSOLUTE MAXIMUM DC RATINGS Item Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Operating Temperature Symbol Rating Units Notes VDD VDDQ VIN, VOUT TSTG TCASE -0.4V ~ 1.975V -0.4V ~ 1.975V -0.4V ~ 1.975V -55 to +100 0 to +95 V V V o C o C 1,3 1,3 1 1,2 1,2 Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. It is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6xVDDQ, When VDD and VDDQ are less than500mV; VREF may be equal to or less than 300mV. AC & DC OPERATING CONDITIONS (SSTL- 1.5) Recommended operating conditions Item Symbol Min. Typical Max. Units Notes Supply Voltage Supply Voltage for Output VREFDQ(DC) VREFCA(DC) Input High Voltage (DC) Input High Voltage (AC) Input Low Voltage (DC) Input Low Voltage (AC) VDD VDDQ I/O I/O VIH (DC) VIH (AC) VIL (DC) VIL (AC) 1.425 1.425 0.49 * VDD 0.49 * VDD VREF + 0.100 VREF + 0.150 VSS - 1.5 1.5 0.50 * VDD 0.50 * VDD - 1.575 1.575 0.51 * VDD 0.51 * VDD VDD VREF - 0.100 VREF - 0.150 V V V V V V V V 1,2 1,2 4,5 4,5 3 3 3 3 Notes: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. For DQ and DM, VREF = VREFDQ. For input only pins except RESET, or VREF = VREFCA 4. The ac peak noise on VREF may not allow VREF to deviate from VREF (DC) by more than ± 1% VDD (for reference: approx. ± 15mV) 5. For reference: approx. VDD/2 ± 15mV RELIABILITY MTBF @25 oC (Hours) 1 FIT @ 25 oC 2 MTBF @40 oC (Hours) 1 FIT @ 40 oC2 11,978,000 83 6,615,000 151 Notes: 1. The Mean Time between Failures (MTBF) is calculated using a prediction methodology, Bellcore Prediction, which based on reliability data of the individual components in the module. It assumes nominal voltage, with all other parameters within specified range. 2. Failures per Billion Device-Hours Your Ultimate Memory Solution! 750 North Mary Ave, Sunnyvale, CA 94085, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 4 of 7 ATP AQ56M72D8BKH9S IDD SPECIFICATION PARAMETER & POWER CONSUMPTION (IDD values are for full operating range of Voltage and Temperature) Symbol Proposed Conditions Value Units 360 mA 450 mA 110 mA 140 mA 180 mA 230 mA 180 mA 150 mA 320 mA 680 mA 720 mA 1,040 mA 110 mA 1,220 mA 1,280 mW Operating one bank active-precharge current; IDD0 CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Timing table ; BL: 8; AL: 0;/ CS: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Operating one bank active-read-precharge current; IDD1 CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Timing table ; BL: 8; AL: 0; /CS: High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Precharge Power-Down Current Slow Exit IDD2P0 CKE: Low; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pre-charge Power Down Mode: Slow Exit Precharge Power-Down Current Fast Exit IDD2P1 CKE: Low; External clock: On; tCK, CL: see Timing table; BL: 81); AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Pre-charge Power Down Mode: Fast Exit Precharge standby current; IDD2N CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-gling; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; IDD2NT CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-gling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers Precharge Standby ODT Current Precharge quiet standby current; IDD2Q CKE: High; External clock: On; tCK, CL: see Timing table; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 IDD3P CKE: Low; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 Active Power-Down Current Active Standby Current IDD3N CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-gling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Operating Burst Read Current IDD4R CKE: High; External clock: On; tCK, CL: see Timing table; BL: 8; AL: 0; /CS: High between RD; Command, Address, Bank Address Inputs: par-tially toggling ; Data IO: seamless read data burst with different data between one burst and the next one; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Operating Burst Write Current IDD4W CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: par-tially toggling ; Data IO: seamless write data burst with different data between one burst and the next one; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at HIGH; Burst Refresh Current IDD5B CKE: High; External clock: On; tCK, CL, nRFC: see Timing table ; BL: 8; AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Self Refresh Current: Normal Temperature Range TCASE: 0 - 85°C; IDD6 Auto Self-Refresh (ASR): Disabled; Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Timing table ; BL: 8; AL: 0; /CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self- Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING Operating Bank Interleave Read Current IDD7 PDIMM CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Timing table ; BL: 8; AL: CL-1; /CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling; Data IO: read data bursts with different data between one burst and the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Power Consumption per DIMM System is operating at 667 MHz clock with VDD = 1.5V. This parameter is calculated at a common loading. Your Ultimate Memory Solution! 750 North Mary Ave, Sunnyvale, CA 94085, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 5 of 7 ATP AQ56M72D8BKH9S TIMING PARAMETER Parameter Symbol Clock cycle time at CL=7.0, CWL=6.0 Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACTIVE to PRECHARGE command period Average high pulse width Average low pulse width DQS, DQS to DQ skew, per group, per access DQ output hold time from DQS, DQS DQ low-impedance time from CK, CK DQ high-impedance time from CK, CK Data setup time to DQS, DQS referenced to Vih(ac)Vil(ac) levels Data hold time to DQS, DQS referenced to Vih(ac)Vil(ac) levels DQS, DQS READ Preamble DQS, DQS differential READ Postamble DQS, DQS output high time DQS, DQS output low time DQS, DQS WRITE Preamble DQS, DQS WRITE Postamble DQS, DQS rising edge output access time from rising CK， CK DQS, DQS low-impedance time (Referenced from RL-1) DQS, DQS high-impedance time (Referenced from RL+BL/2) DQS, DQS differential input low pulse width DQS, DQS differential input high pulse width DQS, DQS rising edge to CK, CK rising edge DQS, DQS falling edge setup time to CK, CK rising edge DQS, DQS falling edge hold time to CK, CK rising edge DLL locking time Internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register Set command cycle time Mode Register Set command update delay CAS to CAS command delay Auto precharge write recovery + precharge time Multi-Purpose Register Recovery Time ACTIVE to ACTIVE command period for 1KB page size ACTIVE to ACTIVE command period for 2KB page size Four activate window for 1KB page size Four activate window for 2KB page size Command and Address setup time to CK, CK referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK referenced to Vih(ac) / Vil(ac) levels Power-up and RESET calibration time Normal operation Full calibration time Normal operation short calibration time Exit Reset from CKE HIGH to a valid command Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Asynchronous RTT turn-on delay (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) ODT turn-on RTT_NOM and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew 2Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval Average periodic refresh interval (0°C ≤ TCASE ≤ 85 °C) Average periodic refresh interval (85°C ≤ TCASE ≤ 95 °C) Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL Power Down Entry to Exit Timing Write leveling output delay Write leveling output error *Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges. Your Ultimate Memory Solution! 750 North Mary Ave, Sunnyvale, CA 94085, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 6 of 7 tCK tAA tRCD tRP tRC tRAS tCH(avg) tCL(avg) tDQSQ tQH tLZ(DQ) tHZ(DQ) tDS(base) tDH(base) tRPRE tRPST tQSH tQSL tWPRE tWPST tDQSCK tLZ(DQS) tHZ(DQS) tDQSL tDQSH tDQSS tDSS tDSH tDLLK tRTP tWTR tWR tMRD tMOD tCCD tDAL tMPRR tRRD tRRD tFAW tFAW tIS(base) tIH(base) tZQinitI tZQoper tZQCS tXPR tXP tAONPD tAOFPD tAON tAOF tADC tRFC tREFI tREFI tXS tXSDLL tPD tWLO tWLOE DDR3-1333 min 1.5 13.125 13.125 13.125 49.125 36 0.47 0.47 0.38 -500 Max 1.875 20 9*tREFI 0.53 0.53 125 250 250 30 65 0.9 0.3 0.4 0.4 0.9 0.3 -255 255 -500 250 250 0.45 0.55 0.45 0.55 -0.25 0.25 0.2 0.2 512 max(4nCK,7.5ns) max (4nCK,7.5ns) 15 4 max(12nCK,15ns) 4 tWR + roundup (tRP / tCK) 1 max(4nCK,6ns) max (4nCK,7.5ns) 30 45 65 140 512 256 64 max(5nCK, tRFC+ 10ns) Units ns ns ns ns ns ns tCK tCK ps tCK ps ps ps ps tCK tCK tCK tCK tCK tCK ps ps ps tCK tCK tCK tCK tCK nCK* ns nCK* nCK* nCK* nCK* ns ns ps ps tCK tCK tCK max(3nCK,6ns) 2 2 -250 0.3 0.3 160 7.8 3.9 max(5nCK,tRFC+10ns) tDLLK(min) tCK(min) 0 0 8.5 8.5 250 0.7 0.7 7.8 3.9 ns ns ps tCK tCK ns us us 9*tREFI 9 2 tCK tCK ns ns ATP AQ56M72D8BKH9S PHYSICAL DIMENSIONS (UNITS IN INCHES) (Drawing not to scale) 240-pin DIMM Front Back Disclaimer: No part of this document may be copied or reproduced in any form or by any means, or transferred to any third party, without the prior written consent of an authorized representative of ATP Electronics (“ATP”). The information in this document is subject to change without notice. ATP assumes no responsibility for any errors or omissions that may appear in this document, and disclaims responsibility for any consequences resulting from the use of the information set forth herein. ATP makes no commitments to update or to keep current information contained in this document. The information set forth in this document is considered to be “Proprietary” and “Confidential” property owned by ATP. Your Ultimate Memory Solution! 750 North Mary Ave, Sunnyvale, CA 94085, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 7 of 7