HANBit HDD16M64B8 DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref. SO-DIMM Part No. HDD16M64B8 GENERAL DESCRIPTION The HDD16M64B8 is a 16M x 64 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module. The module consists of eight CMOS 16M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 200-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD16M64B8 is a SO-DIMM(Small Outline Dual in line Memory Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible. FEATURES • Part Identification HDD16M64B8 – 10A : 100MHz (CL=2) HDD16M64B8 – 13A : 133MHz (CL=2) HDD16M64B8 – 13B : 133MHz (CL=2.5) • 128MB(16Mx64) Unbuffered DDR SO-DIMM based on 16Mx8 DDR SDRSM • 2.5V ± 0.2V VDD and VDDQ power supply • Auto & self refresh capability (4096 Cycles/64ms) • All input and output are compatible with SSTL_2 interface • Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock • All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock • MRS cycle with address key programs - Latency (Access from column address) : 2, 2.5 - Burst length : 2, 4, 8 - Data scramble : Sequential & Interleave • Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock • All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock • The used device is 4M x 8bit x 4Banks DDR SDRAM URL : www.hbe.co.kr REV 1.0 (August. 2002) 1 HANBit Electronics Co.,Ltd. HANBit HDD16M64B8 PIN ASSIGNMENT PIN Front PIN Back PIN Frontl PIN Back PIN Front PIN Back 1 VREF 2 VREF 67 DQ27 68 DQ31 133 DQS4 134 DM4 3 VSS 4 VSS 69 VDD 70 VDD 135 DQ34 136 DQ38 5 DQ0 6 DQ4 71 NC 72 NC 137 VSS 138 VSS 7 DQ1 8 DQ5 73 NC 74 NC 139 DQ35 140 DQ39 9 VDD 10 VDD 75 Vss 76 Vss 141 DQ40 142 DQ44 11 DQS0 12 DM0 77 NC 78 143 VDD 144 VDD 13 DQ2 14 DQ6 79 NC 80 NC 145 DQ41 146 DQ45 15 VSS 16 VSS 81 VDD 82 VDD 147 DQS5 148 DM5 17 DQ3 18 DQ7 83 NC 84 NC 149 VSS 150 VSS 19 DQ8 20 DQ12 85 NC 86 NC (/RESET) 151 DQ42 152 DQ46 21 VDD 22 VDD 87 VSS 88 VSS 153 DQ43 154 DQ47 23 DQ9 24 DQ13 89 CK2 90 VSS 155 VDD 156 VDD 25 DQS1 26 DM1 91 /CK2 92 VDD 157 VDD 158 /CK1 27 VSS 28 VSS 93 VDD 94 VDD 159 VSS 160 CK1 29 DQ10 30 DQ14 95 CKE1 96 CKE0 161 VSS 162 VSS 31 DQ11 32 DQ15 97 NC(A13) 98 NC (BA2) 163 DQ48 164 DQ52 33 VDD 34 VDD 99 NC (A12) 100 A11 165 DQ49 166 DQ53 35 CK0 36 VDD 101 A9 102 A8 167 VDD 168 VDD 37 /CK0 38 VSS 103 VSS 104 VSS 169 DQS6 170 DM6 39 VSS 40 VSS 105 A7 106 A6 171 DQ50 172 DQ54 41 DQ16 42 DQ20 107 A5 108 A4 173 VSS 174 VSS 43 DQ17 44 DQ21 109 A3 110 A2 175 DQ51 176 DQ55 45 VDD 46 VDD 111 A1 112 A0 177 DQ56 178 DQ60 47 DQS2 48 DM2 113 VDD 114 VDD 179 VDD 180 VDD 49 DQ18 50 DQ22 115 A10/AP 116 BA1 181 DQ57 182 DQ61 51 VSS 52 VSS 117 BA0 118 /RAS 183 DQS7 184 DM7 53 DQ19 54 DQ23 119 /WE 120 /CAS 185 VSS 186 VSS 55 DQ24 56 DQ28 121 /CS0 122 NC 187 DQ58 188 DQ62 57 VDD 58 VDD 123 NC 124 NC 189 DQ59 190 DQ63 59 DQ25 60 DQ29 125 VSS 126 VSS 191 VDD 192 VDD 61 DQS3 62 DM3 127 DQ32 128 DQ36 193 *SDA 194 *SA0 63 VSS 64 VSS 129 DQ33 130 DQ37 195 *SCL 196 *SA1 65 DQ26 66 DQ30 131 VDD 132 VDD 197 *VSPD 198 *SA2 199 VDDID 200 NC NC *These pins should be NC in the system which does not support SPD PIN PIN DESCRIPTION PIN PIN DESCRIPTION A0~A11 Address input VDD Power supply(2.5V) BA0~BA1 Bank Select Address VDDQ Power supply for DQs(2.5V) DQ0~DQ63 Data input/output VREF Power supply for reference DQS0~DQS7 Data Strobe input/output VSPD Serial EEPROM Power supply(3.3) DM0~DM7 Data-in Mask VSS Ground CK0~CK2,/CK0~/CK2 Clock input SA0~SA2 Address in EEPROM CKE0~CKE1 Clock enable input SDA Serial data I/O /CS0 Chip Select input SCL Serial clock /RAS, /CAS Row / Column Address strobe WP Write protection NC No connection VDDID VDD identification flag URL : www.hbe.co.kr REV 1.0 (August. 2002) 2 HANBit Electronics Co.,Ltd. HANBit HDD16M64B8 FUNCTIONAL BLOCK DIAGRAM /CS0 V SPD A11 URL : www.hbe.co.kr REV 1.0 (August. 2002) A11 3 HANBit Electronics Co.,Ltd. HANBit HDD16M64B8 PIN FUNCTION DESCRIPTION Pin CK, /CK Name Input Function CK and CK are differential clock inputs. All address and control input signals are sam-pled on the positive edge of CK and negative edge of CK. Output (read) data Clock is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all CKE Clock Enable functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognizean LVCMOS LOW level prior to VREF being stable on power-up. CS enables(registered LOW) and disables(registered HIGH) the command decoder. /CS All commands are masked when CS is registered HIGH. CS provides for external Chip Select bank selection on systems with multiple banks. CS is considered part of the command code. Row/column addresses are multiplexed on the same pins. A0 ~ A11 Address BA0 ~ BA1 Bank select address /RAS Row address strobe /CAS Column strobe /WE Write enable DQS0 ~ 7 Data Strobe Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE command is being applied. Latches row addresses on the positive going edge of the CLK with /RAS low. address Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from /CAS, /WE active. Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled DM0~7 Input Data Mask on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-ing. DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. VDDQ Supply DQ Power Supply : +2.5V ± 0.2V. VDD Supply Power Supply : +2.5V ± 0.2V (device specific). VSS Supply DQ Ground. VREF Supply SSTL_2 reference voltage. VSPD Supply Serial EEPROM Power Supply : 3.3v VDDID URL : www.hbe.co.kr REV 1.0 (August. 2002) VDD identification Flag 4 HANBit Electronics Co.,Ltd. HANBit HDD16M64B8 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNTE VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V Voltage on VDDQ supply relative to Vss VDDQ -0.5 ~ 3.6 V Storage temperature TSTG -55 ~ +150 °C PD 8.0 W Voltage on any pin relative to Vss Power dissipation Short circuit current IOS 50 Notes: Operation at above absolute maximum rating can adversely affect device reliability mA DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) ) PARAMETER SYMBOL MIN MAX UNIT VDD 2.3 2.7 V VDDQ 2.3 2.7 V I/O Reference Voltage VREF 1.15 1.35 V 1 I/O Termination Voltage(system) VTT VREF – 0.04 VREF + 0.04 V 2 Input High Voltage VIH (DC) VREF + 0.15 VREF + 0.3 V Input Low Voltage VIL (DC) -0.3 VREF - 0.15 V Input Voltage Level, CK and /CK inputs VIN (DC) -0.3 VDDQ + 0.3 V Input Differential Voltage, CK and /CK inputs VID (DC) 0.3 VDDQ + 0.6 V Input leakage current I LI -2 2 uA Output leakage current I OZ -5 5 uA Output High current (VOUT = 1.95V) I OH -16.8 Supply Voltage I/O Supply Voltage 3 mA Output Low current (VOUT = 0.35V) I OL 16.8 Notes : 1.Typically, the value of VREF is expected to be about 0.5* VDD of the transmitting device. VREF is expected to track variation in VDDQ . 2. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). 3. VTT of the transmitting device must track VREF of the receiving device. CAPACITANCE NOTE mA (VDD = min to max, VDDQ = 2.5V to 2.7V, TA = 25°C, f = 100MHz) DESCRIPTION SYMBO MIN MAX UNITS L Input capacitance(A0~A11, BA0~BA1, /RAS, /CAS,/WE) CIN1 36 44 pF Input capacitance(CKE0,CKE1) CIN2 36 44 pF Input capacitance(/CS0) CIN3 34 42 pF Input capacitance(CK0~CK2, /CK0~/CK2) CIN4 34 38 pF Input capacitance(DM0~DM7) CIN5 8 9 pF COUT1 8 9 pF Data input/output capacitance (DQ0 ~ DQ63, DQS0~DQS7) URL : www.hbe.co.kr REV 1.0 (August. 2002) 5 HANBit Electronics Co.,Ltd. HANBit HDD16M64B8 DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, VDD = 2.5V, T =25°C) TEST PARAMETER VERSION SYMBOL UNIT CONDITION -10A -13A -13B 720 800 800 mA 24 28 28 mA 104 104 104 mA 240 240 240 mA 328 360 360 mA 1040 1200 1200 mA 1040 1240 1240 mA 1200 1440 1440 mA 16 16 16 mA 80 8 8 NOTE Burst length = 2 Operating current IDD1 (One bank active) Precharge standby tRC ≥ tRC(min), CL=2.5 IOUT = 0mA, Active-Read-Presharge CKE ≤ VIL(max) current in IDD2P tCK = tCK(min), All banks idle power-down mode Precharge standby CKE ≥ VIH(min) current in non power-down IDD2N /CS≥ VIH(min), tCK = tCK(min) mode All banks idle, CKE ≤ VIL(max), Active standby current in IDD3P power-down mode tCK = tCK(min) Active standby current Onel banks, in non power-down mode IDD3N (One bank active) Active-Read-Presharge, tRC = tRAS(max), tCK = tCK(min) Burst length = 2 Operating current (Read) Operating current(Write) Auto refresh current IDD4R CL=2.5 tRC = tRC(min), IOUT = 0mA, CL=2 Burst length = 2 CL=2.5 tRC = tRC(min) CL=2 IDD4W IDD5 tRC ≥ tREF(min) Normal Self refresh Low IDD6 CKE ≤ 0.2V mA current Power Notes: Operation at above absolute maximum rating can adversely affect device reliability AC OPERATING CONDITIONS PARAMETER STMBOL MIN MAX UNIT Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH (AC) VREF + 0.35 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL (AC) VREF - 0.35 V Input Differential Voltage, CK and CK inputs VID (AC) 0.7 VDDQ+0.6 V 1 Input Crossing Point Voltage, CK and CK inputs VIX (AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 NOTE Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same URL : www.hbe.co.kr REV 1.0 (August. 2002) 6 HANBit Electronics Co.,Ltd. HANBit HDD16M64B8 AC OPERATING TEST CONDITIONS PARAMETER VALUE UNIT Input reference voltage for Clock 0.5 * VDDQ V Input signal maximum peak swing 1.5 V Input signal minimum slew rate 1.0 V VREF+0.35/VREF V Input timing measurement reference level VREF V Output timing measurement reference level VTT V See Load Circuit V Input Levels(VIH/VIL) Output load condition NOTE AC CHARACTERISTICS (These AC charicteristics were tested on the Component) PARAMETER DDR200 DDR266A DDR266B -10A -13A -13B SYMBOL MIN MAX MIN MAX MIN UNIT NOTE MAX Row cycle time tRC 70 65 65 ns 1 Refresh row cycle time tRFC 80 75 75 ns 1,2 Row active time tRAS 48 ns 1,2 /RAS to /CAS delay tRCD 20 20 20 ns 3 Row precharge time tRP 20 20 20 ns 3 Row active to Row active delay tRRD 15 15 15 ns 3 Write recovery time tWR 2 2 2 tCK 3 Last data in to Read command tCDLR 1 1 1 tCK 2 Col. address to Col. address delay tCCD 1 1 1 tCK CL=2.0 Clock cycle time 120K 10 URL : www.hbe.co.kr REV 1.0 (August. 2002) 120K 45 120K 12 7.5 12 10 12 ns 12 7.5 12 7.5 12 ns 0.55 0.45 0.55 0.45 0.55 tCK tCK CL=2.5 Clock high level width 45 tCH 0.45 7 HANBit Electronics Co.,Ltd. HANBit Clock low level width HDD16M64B8 tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tDQSCK -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns Output data access time from CK/CK tAC -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to ouput data edge tDQSQ - +0.6 - +0.5 - +0.5 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK tHZQ -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 ns DQS-in hold time tWPREH 0.25 0.25 0.25 tCK tDSS 0.2 0.2 0.2 tCK tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 tCK DQS-in cycle time tDSC 0.9 Address and Control Input setup time tIS 1.1 0.9 0.9 ns Address and Control Input hold time tIH 1.1 0.9 0.9 ns Mode register set cycle time tMRD 16 15 15 ns DQ & DM setup time to DQS tDS 0.6 0.5 0.5 ns DQ & DM hold time to DQS tDH 0.6 0.5 0.5 ns DQ & DM input pulse width tDIPW 2 1.75 1.75 ns Power down exit time tPDEX 10 10 10 ns Exit self refresh to write command tXSW 116 95 tXSA 80 Exit self refresh to read command tXSR 200 200 200 Cycle Refresh interval time TREF 15.6 15.6 15.6 us Output DQS valid window TQH 0.35 0.35 0.35 tCK DQS write postamble time TWPST 0.25 0.25 0.25 tCK DQS-out access time from CK/CK Data out high impedence time from 2 CK-/CK 3 DQS-in falling edge to CK rising-setup time DQS-in falling edge to CK rising hold time 1.1 Exit self refresh to bank active 0.9 75 1.1 0.9 1.1 tCK ns 75 ns command Notes : 1. 2. Maximum burst refresh of 8. tHZQ transitions occurs in the same assess time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving. 3. The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. URL : www.hbe.co.kr REV 1.0 (August. 2002) 8 HANBit Electronics Co.,Ltd. 1 4 HANBit 4. HDD16M64B8 The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. SIMPLIFIED TRUTH TABLE COMMAND CK E n-1 CK E n /CS /R A S /C A S /WE DM X L L L L X OP code 1,2 X L L L L X OP code 1,2 L L L H X X L H H H H X X X L L H H Register Extended MRS H Register Mode register set H Auto refresh Refresh Self refresh Entry Exit Bank active & row addr. Read & Auto column disable address Auto precharge eable H H X X L H L precharge Bank selection e All banks Clock suspend or Precharge power down mode X X X L H L V V H X X Entry H L Exit L H Entry H L Exit L H DM H No operation command H L H H L L L H L H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 3 3 Address V 4 (A0 ~A9) 4 Column 4 Address X X 3 Column L (A0 ~ A9) H X NOTE Row address L X A11 A9~A0 X L H Precharg active power down X H H enable Burst Stop H A10/ AP H precharge Auto address L H disable column L precharge Auto Write & H H BA 0,1 X V L X H 4,6 7 X 5 X X X X X V X X X 8 (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. URL : www.hbe.co.kr REV 1.0 (August. 2002) 9 HANBit Electronics Co.,Ltd. HANBit 7. HDD16M64B8 DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0) PACKAGING INFORMATION Unit : mm Front – Side PCB 두 께 : 1.0 ± 0.1mm URL : www.hbe.co.kr REV 1.0 (August. 2002) 10 HANBit Electronics Co.,Ltd. HANBit HDD16M64B8 ORDERING INFORMATION Part Number Density Org. HDD16M64B8-10A 128MByte 16M x 64 HDD16M64B8-13A 128MByte 16M x 64 HDD16M64B8-13B 128MByte 16M x 64 URL : www.hbe.co.kr REV 1.0 (August. 2002) Package 200PIN SO-DIMM 200PIN SO-DIMM 200PIN SO-DIMM 11 Ref. Vcc MODE MAX.frq 4K 2.5V DDR 100MHz/CL2 4K 2.5V DDR 133MHz/CL2 4K 2.5V DDR 133MHz/CL2.5 HANBit Electronics Co.,Ltd.