Datasheet

260Pin DDR4 2133 SO-DIMM
4GB Based on 512Mx8
AQD-SD4U4GN21-SG
Advantech
AQD-SD4U4GN21-SG
Datasheet
Rev. 1.0
2015-03-13
1
260Pin DDR4 2133 SO-DIMM
4GB Based on 512Mx8
AQD-SD4U4GN21-SG
Description
Pin Identification
DDR4 SO-DIMMs are high-speed and low power memory
Symbol
A0–A14
BA0, BA1
BG0, BG1
RAS_n
CAS_n
WE_n
CS0_n, CS1_n
CKE0, CKE1
modules that use 512Mx8bits DDR4 SDRAM in FBGA
package and a 4K-bit serial EEPROM on a 260-pin
printed circuit board. DDR4 SO-DIMMs are dual In-Line
memory modules and are intended for mounting into
260-pin edge connector sockets.
The synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
ODT0, ODT1
possible on both edges of DQS. The large range of
ACT_n
DQ0–DQ63
CB0–CB7
operation frequencies and programmable latencies allow
the same device to be useful for a variety of high
bandwidth
and
high
performance memory system
DM_n/DBI_n/
applications.
DQS0_t–DQS8_t
Features
 RoHS compliant
DQS0_c–DQS8_c
 JEDEC standard 1.2V ± 0.06V power supply
CK0_t, CK1_t
 VDDQ=1.2V ± 0.06V
 Clock Freq: 1067MHZ for 2133Mb/s/Pin.
CK0_c, CK1_c
 Programmable CAS Latency: 10,11,12,13,14,15,16
PARITY
VDD
 Programmable Additive Latency (Posted /CAS):
0,CL-2 or CL-1 clock
VREFCA
 Programmable /CAS Write Latency (CWL)
VSS
= 11, 14(DDR4-2133)
VDDSPD
 8 bit pre-fetch
 Burst Length: 4, 8
SCL
 Bi-directional Differential Data-Strobe
SDA
 On Die Termination with ODT pin
 Serial presence detect with EEPROM
SA0–SA2
 On DIMM Thermal Sensor
ALERT_n
VPP
RESET_n
 Asynchronous reset
EVENT_n
VTT
RFU
2
Function
SDRAM address bus
SDRAM bank select
SDRAM bank group select
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
DIMM Rank Select Lines
SDRAM clock enable lines
SDRAM on-die termination control
lines
SDRAM activate
DIMM memory data bus
DIMM ECC check bits
Input data mask and data bus
inversion
SDRAM data strobes
(positive line of differential pair)
SDRAM data strobes
(negative line of differential pair)
SDRAM clocks
(positive line of differential pair)
SDRAM clocks
(negative line of differential pair)
SDRAM parity input
SDRAM I/O and core power supply
SDRAM command/address
reference supply
Power supply return (ground)
Serial SPD EEPROM positive
power supply
2
I C serial bus clock for EEPROM
2
I C serial bus data line for
EEPROM
2
I C slave address select for
EEPROM
SDRAM ALERT_n
SDRAM Supply
Set DRAMs to a Known State
SPD signals a thermal event has
occurred
SDRAM I/O termination supply
Reserved for future use
260Pin DDR4 2133 SO-DIMM
4GB Based on 512Mx8
AQD-SD4U4GN21-SG
Dimensions (Unit: millimeter)
Note:1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.
3
260Pin DDR4 2133 SO-DIMM
4GB Based on 512Mx8
AQD-SD4U4GN21-SG
Pin Assignments
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
01
VSS
89
VSS
177
DQS4_c
02
VSS
90
VSS
178
03
05
DQ5
VSS
91
93
CB1/NC
VSS
179
181
DQS4_t
VSS
04
06
DQ4
VSS
92
94
180
182
07
DQ1
95
DQS8_c
183
DQ38
08
DQ0
96
184
VSS
09
VSS
97
DQS8_t
185
VSS
10
98
186
DQ35
11
DQS0_c
99
VSS
187
DQ34
12
100
CB6/NC
188
VSS
13
15
17
19
21
DQS0_t
VSS
DQ7
VSS
DQ3
101
103
105
107
109
CB2/NC
VSS
CB3/NC
VSS
CKE0
189
191
193
195
197
14
16
18
20
22
102
104
106
108
110
VSS
CB7/NC
VSS
RESET_n
CKE1
190
192
194
196
198
DQ45
VSS
DQ41
VSS
DQS5_c
23
VSS
111
VDD
199
24
DQ12
112
VDD
200
DQS5_t
25
27
29
31
113
115
117
119
BG1
BG0
VDD
A12
201
203
205
207
26
28
30
32
VSS
DQ8
VSS
DQS1_c
114
116
118
120
ACT_n
ALERT_n
VDD
A11
202
204
206
208
VSS
DQ47
VSS
DQ43
121
A9
209
VSS
34
DQS1_t
122
A7
210
VSS
35
37
39
41
DQ13
VSS
DQ9
VSS
DM1_n/
DBI_n
VSS
DQ15
VSS
DQ10
VSS
DQ44
VSS
DQ40
VSS
DM5_n/
DBI5_n
VSS
DQ46
VSS
DQ42
VSS
DM0_n/
DBI0_n
VSS
DQ6
VSS
DQ2
VSS
CB0/NC
VSS
DM8_n/
DBI_n/NC
VSS
DM4_n/
DBI4_n
VSS
DQ39
123
125
127
129
VDD
A8
A6
VDD
211
213
215
217
DQ52
VSS
DQ49
VSS
36
38
40
42
VSS
DQ14
VSS
DQ11
124
126
128
130
VDD
A5
A4
VDD
212
214
216
218
43
VSS
131
A3
219
DQS6_c
44
VSS
132
A2
220
DQ53
VSS
DQ48
VSS
DM6_n/
DBI6_n
45
DQ21
133
A1
221
DQS6_t
46
DQ20
134
47
49
51
VSS
DQ17
VSS
135
137
139
VDD
CK0_t
CK0_c
223
225
227
VSS
DQ55
VSS
48
50
52
136
138
140
53
DQS2_c
141
VDD
229
DQ51
54
142
55
57
59
61
DQS2_t
VSS
DQ23
VSS
143
145
147
149
231
233
235
237
VSS
DQ61
VSS
DQ56
56
58
60
62
144
146
148
150
63
DQ19
151
PARITY
BA1
VDD
CS0_n
WE_n/
A14
VSS
DQ16
VSS
DM2_n/
DBI2_n
VSS
DQ22
VSS
DQ18
EVENT_n,
NF
VDD
CK1_t/NF
CK1_c/NF
239
VSS
64
VSS
152
65
VSS
153
VDD
241
DM7_n/
DBI7_n
66
DQ28
154
67
DQ29
155
ODT0
243
VSS
68
VSS
156
69
71
VSS
DQ25
157
159
CS1_n
VDD
245
247
DQ62
VSS
70
72
DQ24
VSS
158
160
73
VSS
161
ODT1
249
DQ58
74
DQS3_c
162
75
DM3_n/
DBI3_n
163
VDD
251
VSS
76
DQS3_t
164
77
VSS
165
253
SCL
78
VSS
79
81
83
85
87
DQ30
VSS
DQ26
VSS
CB5/NC
167
169
171
173
175
255
257
259
-
VDDSPD
VPP
VPP
-
80
82
84
86
88
DQ31
VSS
DQ27
VSS
CB4/NC
33
C1, CS3_n,
NC
VSS
DQ37
VSS
DQ33
VSS
Note: 1. NC for Non ECC SO-DIMM.
4
Pin
Name
222
VSS
224
226
228
DQ54
VSS
DQ50
VDD
230
VSS
A0
A10/AP
VDD
BA0
RAS_n/
A16
232
234
236
238
DQ60
VSS
DQ57
VSS
240
DQS7_c
VDD
242
DQS7_t
CAS_n/
A15
A13
VDD
C0/
CS2_n/NC
244
VSS
246
248
DQ63
VSS
250
DQ59
VREFCA
252
VSS
166
SA2
254
SDA
168
170
172
174
176
VSS
DQ36
VSS
DQ32
VSS
256
258
260
-
SA0
VTT
SA1
-
260Pin DDR4 2133 SO-DIMM
4GB Based on 512Mx8
AQD-SD4U4GN21-SG
Block Diagram
4GB, 512Mx64 Module (1 Rank x8)
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes
in specifications at any time without prior notice.
5
260Pin DDR4 2133 SO-DIMM
4GB Based on 512Mx8
AQD-SD4U4GN21-SG
Operating Temperature Condition
Parameter
Symbol
Rating
Unit
Note
Operating Temperature
TOPER
0 to 85
C
1,2
Note: Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
At 0 - 85C, operation temperature range is the temperature which all DRAM specification will be supported.
Absolute Maximum DC Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on VDD relative to Vss
VDD
-0.3 ~ 1.5
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
-0.3 ~ 1.5
V
1
Voltage on VPP pin relative to Vss
VPP
-0.3 ~ 3.0
V
3
Voltage on any pin relative to Vss
VIN, VOUT
-0.3 ~ 1.5
V
1
Storage temperature
TSTG
-55~+100
C
1,2
Note: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
VPP must be equal or greater than VDD/VDDQ at all times.
AC & DC Operating Conditions
Recommended DC operating conditions (SSTL –1.5)
Rating
Parameter
Symbol
Min
Typ.
Unit
Note
s
V
V
V
1, 2
1, 2
3
Max
Supply voltage
VDD
1.14
1.2
1.26
Supply voltage for Output
VDDQ
1.14
1.2
1.26
Wordline supply voltage
VPP
2.375
2.5
2.75
Note: Under all conditions VDDQ must be less than or equal to VDD.
VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together.
DC bandwidth is limited to 20MHz
Single-ended AC & DC input levels for Command and Address
DDR4-1600/1866/2133
Parameter
Symbol
Unit Note
Min
Max
I/O Reference Voltage (CMD/ADD)
VREFCA(DC)
0.49*VDDQ
0.51*VDDQ
V
1,2
DC Input Logic High
VIH(DC)
VREF+0.075
VDD
V
DC Input Logic Low
VIL(DC)
VSS
VREF-0.075
V
AC Input Logic High
VIH(AC)
VREF+0.1
Note 1
V
AC Input Logic Low
VIL(AC)
Note 1
VREF-0.1
V
Note: The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD
(for reference: approx. ± 12mV)
For reference: approx. VDD/2 ± 12mV
6
260Pin DDR4 2133 SO-DIMM
4GB Based on 512Mx8
AQD-SD4U4GN21-SG
Differential AC and DC Input Levels
DDR4-1600/1866/2133
Parameter
Symbol
Unit Note
Min
Max
differential input high DC
VIHdiff(DC)
+0.150
NOTE 3
V
1
differential input low DC
VILdiff(DC)
NOTE 3
-0.150
V
1
differential input high AC
VIHdiff(AC)
2 x (VIH(AC) - VREF)
NOTE 3
V
2
differential input low AC
VILdiff(AC)
NOTE 3
2 x (VIL(AC) -VREF) V
2
Note: Used to define a differential signal slew-rate.
For CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA;
These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective
limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot
and undershoot.
Single-ended AC & DC output levels
Parameter
Symbol
DDR4-1600/1866/2133
Unit Note
DC output high measurement level
VOH(DC)
1.1 x VDDQ
V
DC output mid measurement level
VOM(DC)
0.8 x VDDQ
V
DC output low measurement level
VOL(DC)
0.5 x VDDQ
V
AC output high measurement level
VOH(AC)
(0.7 + 0.15) x VDDQ
V
1
AC output low measurement level
VOL(AC)
(0.7 - 0.15) x VDDQ
V
1
Note: The swing of ± 0.15 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak
swing with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ.
Differential AC & DC output levels
Parameter
Symbol
DDR4-1600/1866/2133
Unit Note
AC differential output high
VOHdiff(AC)
+0.3 x VDDQ
V
1
measurement level
AC differential output low
VOLdiff(AC)
-0.3 x VDDQ
V
1
measurement level
Note: The swing of ± 0.3 × VDDQ is based on approximately 50% of the static differential output peak-to-peak swing
with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ at each of the
differential outputs.
7
260Pin DDR4 2133 SO-DIMM
4GB Based on 512Mx8
AQD-SD4U4GN21-SG
IDD Specification parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
4GB, 512Mx64 Module (1 Rank x8)
Parameter
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC =
tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid
commands;Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL
= 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS =
tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is
HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Symbol
DDR4 2133 CL15
Unit
IDD0
480
mA
IDD1
520
mA
IDD2P
240
mA
IDD2Q
312
mA
IDD2N
368
mA
IDD3P
352
mA
IDD3N
504
mA
IDD4R
1200
mA
IDD4W
1280
mA
IDD5
1520
mA
IDD6
160
mA
IDD7
1480
mA
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Active power - down current; All banks open; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Active standby current; All banks open; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads,
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL
= 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R
Burst refresh current; tCK = tCK(IDD); Refresh command at every
tRFC(IDD) interval; CKE is HIGH, /CS is HIGH between valid commands; Other
control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads,
IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK =
tCK(IDD), Trc = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between valid commands;Address bus inputs are STABLE
during DESELECTs; Data pattern is same as IDD4R;
Note:
Module IDD was calculated on the specific brand DRAM(3Xnm) component IDD and can be differently
measured according to DQ loading capacitor.
8
260Pin DDR4 2133 SO-DIMM
4GB Based on 512Mx8
AQD-SD4U4GN21-SG
Timing Parameters & Specifications
Speed
Parameter
Average Clock Period
CK high-level width
CK low-level width
DQS_t,DQS_c to DQ skew, per group, per
access
DQS_t,DQS_c to DQ Skew determin-istic,
per group, per access
DDR4 2133
Unit
Symbol
tCK
tCH
tCL
Min
0.938
0.48
0.48
Max
<1.071
0.52
0.52
ns
tCK
tCK
tDQSQ
-
TBD
tCK/2
tDQSQ
-
TBD
tCK/2
tQH
TBD
-
tCK/2
tQH
TBD
-
UI
tDQSQ
-
TBD
UI
tQH
TBD
-
UI
tDQSQ
TBD
TBD
UI
tRPRE
0.9
TBD
tCK
DQS_t, DQS_c differential READ Postamble
tRPST
TBD
TBD
tCK
DQS_t, DQS_c differential WRITE Preamble
tWPRE
0.9
-
tCK
DQS_t, DQS_c differential WRITE Postamble
tWPST
TBD
TBD
tCK
tLZ(DQS)
-360
180
ps
tHZ(DQS)
-
180
ps
tDQSL
0.46
0.54
tCK
tDQSH
0.46
0.54
tCK
tDQSS
-0.27
0.27
tCK
tDSS
0.18
-
tCK
tDSH
0.18
-
tCK
tWTR_S
Max(2nCK, 2.5ns)
-
tWTR_L
Max(4nCK,7.5ns)
-
tWR
15
-
ns
tMRD
8
-
nCK
DQ output hold time from DQS_t,DQS_c
DQ output hold time deterministic from
DQS_t, DQS_c
DQS_t,DQS_c to DQ Skew total, per group,
per access; DBI enabled
DQ output hold time total from DQS_t,
DQS_c; DBI enabled
DQ to DQ offset , per group, per ac-cess
referenced to DQS_t, DQS_c
DQS_t, DQS_c differential READ Pre-amble
(2 clock preamble)
DQS_t and DQS_c low-impedance time
(Referenced from RL-1)
DQS_t and DQS_c high-impedance time
(Referenced from RL+BL/2)
DQS_t, DQS_c differential input low pulse
width
DQS_t, DQS_c differential input high pulse
width
DQS_t, DQS_c rising edge to CK_t, CK_c
rising edge (1 clock preamble)
DQS_t, DQS_c falling edge setup time to
CK_t, CK_c rising edge
DQS_t, DQS_c falling edge hold time from
CK_t, CK_c rising edge
Delay from start of internal write trans-action
to internal read command for different bank
group
Delay from start of internal write trans-action
to internal read command for same bank
group
WRITE recovery time
Mode Register Set command cycle time
9
260Pin DDR4 2133 SO-DIMM
4GB Based on 512Mx8
AQD-SD4U4GN21-SG
CAS_n to CAS_n command delay for same
bank group
Speed
Parameter
CAS_n to CAS_n command delay for
different bank group
Auto precharge write recovery + precharge
time
ACTIVATE to ACTIVATE Command delay to
different bank group for 2KB page size
ACTIVATE to ACTIVATE Command delay to
different bank group for 1KB page size
ACTIVATE to ACTIVATE Command delay to
different bank group for 1/ 2KB page size
ACTIVATE to ACTIVATE Command delay to
same bank group for 2KB page size
ACTIVATE to ACTIVATE Command delay to
same bank group for 1KB page size
ACTIVATE to ACTIVATE Command delay to
same bank group for 1/2KB page size
tCCD_L
6
Symbol
Min
Max
tCCD_S
4
-
DDR4 2133
tDAL
nCK
Unit
nCK
nCK
tWR+tRP/tCK
tRRD_S(2K)
Max(4nCK,5.3ns)
-
nCK
tRRD_S(1K)
Max(4nCK,3.7ns)
-
nCK
tRRD_S
(1/ 2K)
Max(4nCK,3.7ns)
-
nCK
tRRD_L(2K)
Max(4nCK,6.4ns)
-
nCK
tRRD_L(1K)
Max(4nCK,5.3ns)
-
nCK
tRRD_L
(1/ 2K)
Max(4nCK,5.3ns)
-
nCK
Four activate window for 2KB page size
tFAW_2K
Max(28nCK, 30ns)
-
ns
Four activate window for 1KB page size
tFAW_1K
Max(20nCK, 21ns)
-
ns
tFAW_1/2K
Max(16nCK, 15ns)
-
ns
Power-up and RESET calibration time
tZQinit
1024
-
nCK
Normal operation Full calibration time
tZQoper
512
-
nCK
tZQCS
128
-
nCK
tXS
tRFC(min)+ 10ns
-
tXSDLL
tDLLK(min)
-
tRTP
Max(4nCK,7.5ns)
-
tCKESR
tCKE(min)+1nCK
-
tXP
Max (4nCK,6ns)
-
tCKE
Max (3nCK,5ns)
-
tAONAS
1.0
9.0
ns
tAOFAS
1.0
9.0
ns
tADC
0.3
0.7
tCK
Four activate window for 1/2KB page size
Normal operation short calibration time
Exit Self Refresh to commands not re-quiring
a locked DLL
Exit Self Refresh to commands requir-ing a
locked DLL
Internal READ Command to PRE-CHARGE
Command delay
Minimum CKE low width for Self re-fresh
entry to exit timing
Exit Power Down with DLL on to any valid
command;Exit Precharge Power Down with
DLL frozen to commands not requiring a
locked DLL
CKE minimum pulse width
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
RTT dynamic change skew
10
260Pin DDR4 2133 SO-DIMM
4GB Based on 512Mx8
AQD-SD4U4GN21-SG
SERIAL PRESENCE DETECT SPECIFICATION
AQD-SD4U4GN21-SG Serial Presence Detect
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15-16
17
18
19
20-23
24
25
26
27
28
29
30-31
32-33
34-35
36-37
38
39
40
41-59
Function Described
Number of Bytes Used / Number of Bytes in SPD
Device / CRC Coverage
SPD Revision
Key Byte / DRAM Device Type
Key Byte / Module Type
SDRAM Density and Banks
SDRAM Addressing
SDRAM Package Type
SDRAM Optional Features
SDRAM Thermal and Refresh Options
Other SDRAM Optional Features
Reserved
Module Nominal Voltage, VDD
Module Organization
Module Memory Bus Width
Module Thermal Sensor
Reserved
Timebases
SDRAM Minimum Cycle Time (tCKAVGmin)
SDRAM Maximum Cycle Time (tCKAVGmax)
CAS Latencies Supported
Minimum CAS Latency Time (tAAmin)
Minimum RAS to CAS Delay Time (tRCDmin)
Minimum Row Precharge Delay Time (tRPmin)
Upper Nibbles for tRASmin and tRCmin
Minimum Active to Precharge Delay Time (tRASmin),
Least Significant Byte
Minimum Active to Active/Refresh Delay Time
(tRCmin), Least Significant Byte
Minimum Refresh Recovery Delay Time (tRFC1min)
Minimum Refresh Recovery Delay Time (tRFC2min)
Minimum Refresh Recovery Delay Time (tRFC4min)
Minimum Four Activate Window Delay Time
(tFAWmin)
Minimum Activate to Activate Delay Time
(tRRD_Smin), different bank group
Minimum Activate to Activate Delay Time
(tRRD_Lmin), same bank group
Minimum CAS to CAS Delay Time (tCCD_Lmin),
same bank group
Reserved
11
Standard Specification
CRC:0-255Byte
SPD Byte use: 512Byte
SPD Byte total: 512Byte
DDR4 SDRAM
SO-DIMM
4Gb, 16banks
ROW:15, Column:10
1.2V
1Rank, 8bits
Non-ECC, 64bits
Support
0.938ns
1.5ns
10, 11, 12, 13, 14, 15, 16
13.5ns
13.5ns
13.5ns
-
Vendor Part
33ns
08
46.5ns
74
260ns
160ns
110ns
20,08
00,05
70,03
21ns
00,A8
3.7ns
1E
5.3ns
2B
5.355ns
2B
-
00
23
0C
03
84
19
00
03
01
03
80
00
00
08
0C
6C
6C
6C
11
260Pin DDR4 2133 SO-DIMM
4GB Based on 512Mx8
AQD-SD4U4GN21-SG
60-77
78-116
-
00
-
83
-
B5
-
CE
-
00
-
00
122
Connector to SDRAM Bit Mapping
Reserved
Fine Offset for Minimum CAS to CAS Delay Time
(tCCD_Lmin), same bank group
Fine Offset for Minimum Activate to Activate Delay
Time (tRRD_Lmin), same bank group
Fine Offset for Minimum Activate to Activate Delay
Time (tRRD_Smin), different bank group
Fine Offset for Minimum Active to Active/Refresh
Delay Time (tRCmin)
Fine Offset for Minimum Row Precharge Delay Time
(tRPmin)
Fine Offset for Minimum RAS to CAS Delay Time
(tRCDmin)
-
00
123
Fine Offset for Minimum CAS Latency Time (tAAmin)
-
00
-
00
-
C2
30mm
Planar Double Sides
Revision 0, Raw card A
Standard
Transcend
Taipei
-
0F
11
00
00
00
00
01,4F
54
00
00
51 44 2D
34 55 34
32 31 2D
20 20 20
00
Variable
00
Variable
00
-
117
118
119
120
121
124
125
126-127
128
129
130
131
132-253
254-255
256-319
320-321
322
323-324
325-328
Fine Offset for SDRAM Maximum Cycle Time
(tCKAVGmax)
Fine Offset for SDRAM Minimum Cycle Time
(tCKAVGmin)
Cyclical Redundancy Code
Raw Card Extension, Module Nominal Height
Module Maximum Thickness
Reference Raw Card Used
Address Mapping from Edge Connector to DRAM
Reserved
Cyclical Redundancy Code (CRC)
Reserved
Module Manufacturer ID Code
Module Manufacturing Location
Module Manufacturing Date
Module Serial Number
329-348 Module Part Number
349
350-351
352
353-381
382-383
384-551
AQD-SD4U4GN21-SG
Module Revision Code
DRAM Manufacturer ID Code
DRAM Stepping
Manufacturer Specific Data
Reserved
End User Programmable
By Manufacturer
By Manufacturer
-
12
41
44
4E
47
53
47
53
20