Datasheet

240Pin DDR3 1333 UDIMM
1GB Based on 128Mx8
AQD-D31GN13-SX
Advantech
AQD-D31GN13-SX
Datasheet
Rev. 1.1
2013-09-24
1
240Pin DDR3 1333 UDIMM
1GB Based on 128Mx8
AQD-D31GN13-SX

Description
Pin Identification
 Pin Identification
AQD-D31GN13-SX is a DDR3 Unbuffered, non-ECC
high-speed, low power memory module that use 8 pcs of
Symbol
Function
128Mx8bits DDR3 SDRAM in FBGA package and a 2048
A0~A13, BA0~BA2
Address/Bank input
bits serial EEPROM on a 240-pin printed circuit board.
DQ0~DQ63
Bi-direction data bus.
DQS0~DQS7
Data strobes
/DQS0~/DQS7
Differential Data strobes
CK0, /CK0,CK1, /CK1
Clock Input. (Differential pair)
use of system clock. Data I/O transactions are possible
CKE0, CKE1
Clock Enable Input.
on both edges of DQS. Range of operation frequencies,
ODT0, ODT1
On-die termination control line
programmable latencies allow the same device to be
/S0, /S1
DIMM rank select lines.
useful for a variety of high bandwidth, high performance
/RAS
Row address strobe
/CAS
Column address strobe
/WE
Write Enable
DM0~DM7
Data masks/high data strobes
VDD
Core power supply
 VDDQ=1.5V ± 0.075V
VDDQ
I/O driver power supply
 Clock Freq: 667MHZ for 1333Mb/s/Pin.
VREFDQ
I/O reference supply
AQD-D31GN13-SX is a Dual In-Line Memory Module and
is intended for mounting into 240-pin edge connector
sockets.
Synchronous design allows precise cycle control with the
memory system applications.
Features
 RoHS compliant products.
 JEDEC standard 1.5V ± 0.075V Power supply
 Programmable CAS Latency: 6, 7, 8, 9
Command/address reference
VREFCA
 Programmable Additive Latency (Posted /CAS):
0,CL-2 or CL-1 clock
VDDSPD
 Programmable /CAS Write Latency (CWL)
supply
SPD EEPROM power supply
I2C serial bus address select for
= 7(DDR3-1333)
SA0~SA2
EEPROM
 8 bit pre-fetch
 Burst Length: 4, 8
SCL
I2C serial bus clock for EEPROM
 Bi-directional Differential Data-Strobe
SDA
I2C serial bus data for EEPROM
 Internal calibration through ZQ pin
VSS
Ground
 On Die Termination with ODT pin
/RESET
Set DRAMs Known State
VTT
SDRAM I/O termination supply
NC
No Connection
 Serial presence detect with EEPROM
 Asynchronous reset
2
240Pin DDR3 1333 UDIMM
1GB Based on 128Mx8
AQD-D31GN13-SX
Dimensions (Unit: millimeter)
Note:1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.
3
240Pin DDR3 1333 UDIMM
1GB Based on 128Mx8
AQD-D31GN13-SX
Pin Assignments
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
No
Name
No
Name
No
Name
No
Name
No
Name
No
01 VREFDQ 41
VSS
81
DQ32
121
VSS
161
NC
201
02
VSS
42
NC
82
DQ33
122
DQ4
162
NC
202
03
DQ0
43
NC
83
VSS
123
DQ5
163
VSS
203
04
DQ1
44
VSS
84
/DQS4
124
VSS
164
NC
204
05
VSS
45
NC
85
DQS4
125
DM0
165
NC
205
06
/DQS0
46
NC
86
VSS
126
NC
166
VSS
206
07
DQS0
47
VSS
87
DQ34
127
VSS
167
NC
207
08
VSS
48
NC
88
DQ35
128
DQ6
168 /RESET 208
09
DQ2
49
NC
89
VSS
129
DQ7
169 CKE1,NC 209
10
DQ3
50
CKE0
90
DQ40
130
VSS
170
VDD
210
11
VSS
51
VDD
91
DQ41
131
DQ12
171
NC
211
12
DQ8
52
BA2
92
VSS
132
DQ13
172
NC
212
13
DQ9
53
NC
93
/DQS5
133
VSS
173
VDD
213
14
VSS
54
VDD
94
DQS5
134
DM1
174
A12
214
15
/DQS1
55
A11
95
VSS
135
NC
175
A9
215
16
DQS1
56
A7
96
DQ42
136
VSS
176
VDD
216
17
VSS
57
VDD
97
DQ43
137
DQ14
177
A8
217
18
DQ10
58
A5
98
VSS
138
DQ15
178
A6
218
19
DQ11
59
A4
99
DQ48
139
VSS
179
VDD
219
20
VSS
60
VDD
100
DQ49
140
DQ20
180
A3
220
21
DQ16
61
A2
101
VSS
141
DQ21
181
A1
221
22
DQ17
62
VDD
102
/DQS6
142
VSS
182
VDD
222
23
VSS
63
CK1,NC 103
DQS6
143
DM2
183
VDD
223
24
/DQS2
64
/CK1,NC 104
VSS
144
NC
184
CK0
224
25
DQS2
65
VDD
105
DQ50
145
VSS
185
/CK0
225
26
VSS
66
VDD
106
DQ51
146
DQ22
186
VDD
226
27
DQ18
67 VREFCA 107
VSS
147
DQ23
187
NC
227
28
DQ19
68
NC
108
DQ56
148
VSS
188
A0
228
29
VSS
69
VDD
109
DQ57
149
DQ28
189
VDD
229
30
DQ24
70
A10/AP
110
VSS
150
DQ29
190
BA1
230
31
DQ25
71
BA0
111
/DQS7
151
VSS
191
VDD
231
32
VSS
72
VDD
112
DQS7
152
DM3
192
/RAS
232
33
/DQS3
73
/WE
113
VSS
153
NC
193
/S0
233
34
DQS3
74
/CAS
114
DQ58
154
VSS
194
VDD
234
35
VSS
75
VDD
115
DQ59
155
DQ30
195
ODT0
235
36
DQ26
76
/S1,NC
116
VSS
156
DQ31
196
A13
236
37
DQ27
77
117
SA0
157
VSS
197
VDD
237
ODT1,NC
38
VSS
78
VDD
118
SCL
158
NC
198
NC
238
39
NC
79
NC
119
SA2
159
NC
199
VSS
239
40
NC
80
VSS
120
VTT
160
VSS
200
DQ36
240
/S1,ODT1,CKE1：Used for dual-rank UDIMMs; NC on single-rank UDIMMs.
CK1 and /CK1：Used for dual-rank UDIMMs; not used on single-rank UDIMMs but terminated.
4
Pin
Name
DQ37
VSS
DM4
NC
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5
NC
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
NC
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DM7
NC
VSS
DQ62
DQ63
VSS
VDDSPD
SA1
SDA
VSS
VTT
Blo
ck
Dia
gra
m
1GB
,
128
Mx6
4
Mod
ule(
1
Ran
k
x8)
240Pin DDR3 1333 UDIMM
1GB Based on 128Mx8
AQD-D31GN13-SX
This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make changes
in specifications at any time without prior notice.
Operating Temperature Condition
Parameter
Symbol
5
Rating
Unit
Note
240Pin DDR3 1333 UDIMM
1GB Based on 128Mx8
AQD-D31GN13-SX
Operating Temperature
TOPER
0 to 85
C
Note:
Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
1,2
Absolute Maximum DC Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on VDD relative to Vss
VDD
-0.4 ~ 1.975
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
-0.4 ~ 1.975
V
1
Voltage on any pin relative to Vss
VIN, VOUT
-0.4 ~ 1.975
V
1
Storage temperature
TSTG
-55~+100
C
1,2
1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
Note:
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC operating conditions (SSTL –1.5)
Rating
Parameter
Symbol
Unit
Min
Typ.
Note
Max
Supply voltage
VDD
1.425
1.5
1.575
V
Supply voltage for Output
VDDQ
1.425
1.5
1.575
V
I/O Reference Voltage (DQ)
VREFDQ(DC) 0.49*VDDQ 0.50*VDDQ
0.51*VDDQ
V
I/O Reference Voltage (CMD/ADD)
VREFCA(DC)
0.49*VDDQ 0.50*VDDQ
0.51*VDDQ
V
AC Input Logic High
VIH(AC)
VREF+0.175
V
AC Input Logic Low
VIL(AC)
VREF-0.175
V
DC Input Logic High
VIH(DC)
VREF+0.1
VDD
V
DC Input Logic Low
VIL(DC)
VSS
VREF-0.1
V
Note: There is no specific device VDD supply voltage requirement for SSTL-1.5 compliance.
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together.
3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD.
1, 2
1, 2
3
3
AC Input Level for Differential Signals
Parameter
Differential Input Logical High
Differential Input Logical Low
Symbol
VIHdiff
VILdiff
6
Value
+200
-200
Unit
mV
Note
240Pin DDR3 1333 UDIMM
1GB Based on 128Mx8
AQD-D31GN13-SX
IDD Specification parameters Definition
( IDD values are for full operating range of Voltage and Temperature)
1GB, 128Mx64 Module(1 Rank x8)
Parameter
Symbol
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD),
tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;Address bus
IDD0
DDR3 1333 CL9
Unit
280
mA
IDD1
336
mA
IDD2P
96
mA
IDD2Q
120
mA
IDD2N
120
mA
IDD3P
control and address bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
= tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control and
IDD3N
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
IDD4R
CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL
= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is
HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data IDD4W
bus inputs are SWITCHING IDD4R
120
mA
160
mA
560
mA
560
mA
IDD5
720
mA
IDD6
80
mA
IDD7
1040
mA
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL =
CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other
control and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is
HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA;
BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD),
tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid
commands;Address bus inputs are STABLE during DESELECTs; Data pattern is same
as IDD4R;
Note:
1.Module IDD was calculated on the specific brand DRAM component IDD and can be differently measured
according to DQ loading capacitor.
7
240Pin DDR3 1333 UDIMM
1GB Based on 128Mx8
AQD-D31GN13-SX
2GB, 256Mx64 Module(2 Rank x8)
Parameter
Symbol
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD),
tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;Address bus
IDD0
DDR3 1333 CL9
Unit
400
mA
IDD1
456
mA
IDD2P
192
mA
IDD2Q
240
mA
IDD2N
240
mA
IDD3P
240
mA
IDD3N
280
mA
IDD4R
680
mA
IDD4W
680
mA
IDD5
840
mA
IDD6
160
mA
IDD7
1160
mA
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL =
CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other
control and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is
HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other
control and address bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
= tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL
= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is
HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING IDD4R
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA;
BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD),
tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid
commands;Address bus inputs are STABLE during DESELECTs; Data pattern is same
as IDD4R;
Note:
1.Module IDD was calculated on the specific brand DRAM component IDD and can be differently measured
according to DQ loading capacitor.
8
240Pin DDR3 1333 UDIMM
1GB Based on 128Mx8
AQD-D31GN13-SX
Timing Parameters & Specifications
Speed
Parameter
DDR3 1333
Unit
Symbol
Min
Max
Average Clock Period
tCK
1.5
<1.875
ns
CK high-level width
tCH
0.47
0.53
tCK
CK low-level width
tCL
0.47
0.53
tCK
tDQSQ
-
125
ps
DQ output hold time from DQS, /DQS
tQH
0.38
-
tCK
DQ low-impedance time from CK, /CK
tLZ(DQ)
-500
250
ps
DQ high-impedance time from CK, /CK
tHZ(DQ)
-
250
ps
tDS
30
-
ps
tDH
65
-
DQ and DM input pulse width for each input
tDIPW
400
-
ps
DQS, /DQS Read preamble
tRPRE
0.9
-
tCK
DQS, /DQS differential Read postamble
tRPST
0.3
-
tCK
DQS, /DQS Write preamble
tWPRE
0.9
-
tCK
DQS, /DQS Write postamble
tWPST
0.3
-
tCK
DQS, /DQS low-impedance time
tLZ(DQS)
-500
250
ps
DQS, /DQS high-impedance time
tHZ(DQS)
-
250
ps
DQS, /DQS differential input low pulse width
tDQSL
0.45
0.55
tCK
DQS, /DQS differential input high pulse width
tDQSH
0.45
0.55
tCK
DQS, /DQS rising edge to CK, /CK rising edge
tDQSS
-0.25
+0.25
tCK
tDSS
0.2
-
tCK
tDSH
0.2
-
tCK
tWTR
Max
(4tck, 7.5ns)
-
tWR
15
-
ns
Mode register set command cycle time
tMRD
4
-
tCK
/CAS to /CAS command delay
tCCD
4
-
nCK
Auto precharge write recovery + precharge time
tDAL
Active to active command period for 1KB page
tRRD
DQS, /DQS to DQ skew, per group, per access
Data setup time to DQS, /DQS reference to
Vih(ac)Vil(ac) levels
Data hold time to DQS, /DQS reference to
Vih(ac)Vil(ac) levels
DQS, /DQS falling edge setup time to CK, /CK
rising edge
DQS, /DQS falling edge hold time to CK, /CK
rising edge
Delay from start of Internal write transaction to
Internal read command
Write recovery time
tWR+tRP/tck
Max
(4tck, 6ns)
9
ps
nCK
-
240Pin DDR3 1333 UDIMM
1GB Based on 128Mx8
AQD-D31GN13-SX
Active to active command period for 2KB page
tRRD
Max
(4tck, 7.5ns)
-
Four Activate Window for 1KB page size products
tFAW
30
-
Symbol
Min
Max
tFAW
45
-
ns
Power-up and RESET calibration time
tZQinitl
512
-
tCK
Normal operation Full calibration time
tZQoper
256
-
tCK
tZQcs
64
-
tCK
tXS
Max
(5tCK, tRFC+10)
-
tXSDLL
tDLL(min)
-
Speed
Parameter
Four Activate Window for 2KB page size products
Normal operation short calibration time
Exit self refresh to commands not requiring a
locked DLL
Exit self refresh to commands requiring a locked
DLL
Internal read to precharge command delay
DDR3 1333
Max
tRTP
(4tCK, 7.5ns)
Minimum CKE low width for Self refresh entry to
exit timing
tCKESR
Exit power down with DLL to any valid command:
Exit Precharge Power Down with DLL
tXP
CKE minimum pulse width (high and low pulse
width)
tCK(min)+1tCK
Max
(3tCK, 6ns)
ns
Unit
tCK
-
tCKE
Max
(3tCK,5.625ns)
-
tAONPD
2
8.5
ns
tAOFPD
2
8.5
ns
ODT turn-on
tAON
-250
250
ps
ODT turn-off
tAOF
0.3
0.7
tCK
Asynchronous RTT turn-on delay (Power-Down
mode)
Asynchronous RTT turn-off delay (Power-Down
mode)
10
240Pin DDR3 1333 UDIMM
1GB Based on 128Mx8
AQD-D31GN13-SX
SERIAL PRESENCE DETECT SPECIFICATION
AQD-CD31G13N-SX Serial Presence Detect
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32-59
Function Described
Standard Specification
CRC:0-116Byte
Number of SPD Bytes written / SPD device size / CRC
SPD
Byte use: 176Byte
coverage during module production
SPD Byte total: 256Byte
SPD Revision
Version 1.0
Key Byte / DRAM Device Type
DDR3 SDRAM
Key Byte / Module Type
UDIMM
SDRAM Density and Banks
1GB 8banks
SDRAM Addressing
ROW:14, Column:10
Reserved
Module Organization
1Rank / x8
Module Memory Bus Width
Non ECC, 64bit
Fine Timebase Dividend and Divisor
2.5ps
Medium Timebase Dividend
0.125ns
Medium Timebase Divisor
0.125ns
SDRAM Minimum Cycle Time (tCKmin)
1.5ns
Reserved
CAS Latencies Supported, Least Significant Byte
6, 7, 8, 9
CAS Latencies Supported, Most Significant Byte
Minimum CAS Latency Time (tAAmin)
13.125ns
Minimum Write Recovery Time (tWRmin)
15ns
Minimum /RAS to /CAS Delay Time (tRCDmin)
13.125ns
Minimum Row Active to Row Active Delay Time
6ns
(tRRDmin)
Minimum Row Precharge Time (tRPmin)
13.125ns
Upper Nibble for tRAS and tRC
Minmum Active to Precharge Time (tRASmin)
36ns
Minmum Active to Active/Refresh Time (tRCmin)
49.125ns
Minmum Refresh Recovery Time (tRFCmin), Least
110ns
Significant Byte
Minmum Refresh Recovery Time (tRFCmin), Most
110ns
Significant Byte
Minmum Internal Write to Read Command Delay Time
7.5ns
(tWTmin)
Minimum Internal Read to Precharge Command Delay
7.5ns
Time (tRTPmin)
Upper Nibble for tFAW
30ns
Minmum Four Active Window Delay Time (tFAWmin)
30ns
DLL off Mode,
SDRAM Optional Features
RZQ/6, RZQ/7
SDRAM Thermal and Refresh Options
No ODTs, Support ASR
Reserved
11
Vendor Part
92
10
0B
02
02
11
00
01
03
52
01
08
0C
00
3C
00
69
78
69
30
69
11
20
89
70
03
3C
3C
00
F0
83
05
00
240Pin DDR3 1333 UDIMM
1GB Based on 128Mx8
AQD-D31GN13-SX
60
61
62
63
64-116
117
118
119
120-121
122-125
126-127
Module Nominal Height
Module Max Thickness
Reference Raw Card Used
Address Mapping from Edge Connector to DRAM
Reserved
Module Manufacturer ID Code, Least Significant Byte
Module Manufacturer ID Code, Most Significant Byte
Module Manufacturing Location
Module Manufacturing Date
Module Serial Number
Cyclical Redundancy Code
30mm
Planar Single Sides
R/C A
Standard
Transcend
Transcend
Taipei-
0F
01
00
00
00
01
4F
54
00
00
C8, EF
41 51 44 2D 44
128-145 Module Part Number
AQD-D31GN13-SX
31 47 4E 31 33 2D
53 58 20 20 20
146-147
148-149
150-175
176-255
Revision Code
DRAM Manufacturer ID Code
Manufacturer Specific Data
Open for customer use
By Manufacturer
By Manufacturer
Undefined
12
33
00
Variable
Variable
00
20