The following document contains information on Cypress products. FUJITSU MICROELECTRONICS DATA SHEET DS07-13743-5E 16-Bit Proprietary Microcontroller CMOS F2MC-16LX MB90880 Series MB90882(S)/F882A(S)/F883B(S)/F883BH(S)/F883C(S)/ MB90F884B(S)/F884BH(S)/F884C(S)/V880A-101/102 ■ DESCRIPTION The MB90880 series is a general-purpose 16-bit microcontroller, designed by FUJITSU MICROELECTRONICS, for process control of devices such as consumer appliances, which require high-speed real-time processing capabilities. The instruction set of the F2MC-16LX CPU core retains the same AT architecture as the F2MC* family, with further refinements including high-level language instructions, an expanded addressing mode, enhanced multiplierdivider instructions and bit processing. In addition, a 32-bit accumulator is built in to enable long word processing. As its peripheral resources, the MB90880 series has a 16-bit PPG, multi-function serial interface (software switch over enabled for SIO, UART and I2C) , 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up-down counter, base timer (software switch over enabled for 16-bit reload timer, PWC timer, PPG timer and PWM timer), DTP / external interrupt and chip select pins. *: F2MC is the abbreviation of FUJITSU Flexible Microcontroller. For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ Copyright©2006-2010 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2010.2 MB90880 Series ■ FEATURES • Clock Minimum instruction execution time : 30.3 ns / 4.125 MHz source oscillation × eight times (in internal operation : 33 MHz) PLL clock multiplication system • Maximum memory space 16 Mbytes • Instruction set optimized for control applications Supported data types : bit, byte, word and long word Standard addressing modes : 23 types Enhanced high-precision calculation realized by 32-bit accumulator Signed multiplication/division instructions and extended RETI instruction functions • Instruction set supporting high-level language (C language) and multi-task operations Introduction of system stack pointer Symmetrical instruction set and barrel shift instructions • Improved execution speed 4-byte queue • Powerful interrupt functions Eight priority levels programmable; External interrupts : 24 • Data transfer functions (μDMAC) Up to 16 channels • Built-in ROM Flash memory product : 256, 384 and 512 Kbytes; Mask ROM product : 256 Kbytes only • Built-in RAM Flash memory product : 16, 24 and 30 Kbytes; Mask ROM product : 16 Kbytes only • General-purpose ports Dual clock product : up to 81 channels; Single clock product : up to 83 channels • A/D converter RC successive approximation conversion type : 20 channels (Resolution : 8 or 10 bits) • Multi-function serial interface 7 channels (software switchable between for SIO, UART and I2C) • 16-bit PPG 8 channels • 8/16-bit up-down counter/timer Event input pins : 6 8-bit up-down counters : 2 8-bit reload/compare registers : 2 • Base timer 4 channels (software switchable between 16-bit reload timer, PWC timer, PPG timer, and PWM timer) • 16-bit I/O timer Input capture × 2 channels, output compare × 6 channels, free run timer × 1 channel • Built-in dual clock generator • Low power consumption modes Stop mode, sleep mode, CPU intermittent operation mode, watch timer, time base timer mode • Package QFP-100/LQFP-100 • Process CMOS technology • Power supply voltage 3V : Single power supply operation 2 DS07-13743-5E MB90880 Series ■ PRODUCT LINEUP Part number MB90882(S) MB90F883B(S)/ MB90F883BH(S)/ MB90F883C(S) MB90F882A(S) MB90F884B(S)/ MB90F884BH(S)/ MB90F884C(S) MB90V880A-101/ MB90V880A-102 Parameter Type MASK ROM product ROM size 256 Kbytes 256 Kbytes 384 Kbytes 512 Kbytes ⎯ RAM size 16 Kbytes 16 Kbytes 24 Kbytes 30 Kbytes 30 Kbytes Flash memory product Evaluation product CPU functions Number of instructions : 351 Instruction bit length : 8 bits, 16 bits Instruction length : 1 to 7 bytes Data bit length : 1 bit, 8 bits, 16 bits Minimum execution time : 30.3 ns (machine clock : 33 MHz) The maximum operating frequency of MB90F883B(S), MB90F884B(S) is 25 MHz. Ports General-purpose I/O ports : up to 81 for dual clock model, up to 83 for single clock model Pins X0A and X1A cannot be used as I/O ports in dual clock model General-purpose I/O ports (CMOS output) Multi-function serial interface 7 channels (software switchable between SIO, UART and I2C) 16-bit PPG timer 8 channels 8/16-bit up-down counter/timer Event input pins : 6 8-bit up-down counters : 2 8-bit reload/compare registers : 2 16-bit I/O timer 16-bit free run timer Number of channels : 1 Overflow interrupt Output compare (OCU) Number of channels : 6 Pin input source : Match signal of compare register Input capture (ICU) Number of channels : 2 Rewriting register by pin input (rising, falling or both edges) DTP/external interrupt circuit External interrupt pins : 24 channels (edge/level support) Base timer 4 channels (software switchable between 16-bit reload timer, PWC timer, PPG timer, and PWM timer) Time base timer 18-bit counter Interrupt interval : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (source oscillation : 4 MHz) A/D converter Conversion accuracy : 8 or 10 bits can be switched Single conversion mode (Selected channel converted only once) Scan conversion mode (Multiple successive channels converted) Successive conversion mode (Selected channel converted repeatedly) Stop conversion mode (Selected channel converted and stopped repeatedly) Watchdog timer Reset generation interval : 3.58 ms, 14.33 ms, 57.23ms, 458.75 ms (source oscillation : 4 MHz, minimum value) (Continued) DS07-13743-5E 3 MB90880 Series (Continued) Part number MB90882(S) MB90F882A(S) MB90F883B(S)/ MB90F883BH(S)/ MB90F883C(S) MB90F884B(S)/ MB90F884BH(S)/ MB90F884C(S) MB90V880A-101/ MB90V880A-102 Parameter Low power consumption (standby) modes Flash memory Process Emulatorspecific power supply* Sleep, stop, CPU intermittent operation, watch timer, time base timer ⎯ Flash security function/ accidental write prevention function (not available in MB90F883B(S), MB90F884B(S), MB90F883BH(S), MB90F884BH(S)) ⎯ CMOS technology ⎯ Yes * : It is setting of Jumper switch (TOOL VCC) when emulator is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details. 4 DS07-13743-5E MB90880 Series ■ PIN ASSIGNMENTS P22/A18/PPG2 P21/A17/PPG1 P20/A16/PPG0 P17/AD15/D15/IN1 P16/AD14/D14/IN0 P15/AD13/D13/OUT5 X0 X1 VSS VCC P14/AD12/D12/OUT4 P13/AD11/D11/OUT3 P12/AD10/D10/OUT2 P11/AD09/D09/OUT1 P10/AD08/D08/OUT0 P07/AD07/D07/IRQ7 P06/AD06/D06/IRQ6 P05/AD05/D05/IRQ5 P04/AD04/D04/IRQ4 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 P23/A19/PPG3 (TOP VIEW) P24/A20/TIO0 1 80 P03/AD03/D03/IRQ3 P25/A21/TIO1 2 79 P02/AD02/D02/IRQ2 P26/A22/TIO2 3 78 P01/AD01/D01/IRQ1 P27/A23/TIO3 4 77 P00/AD00/D00/IRQ0 P30/A00/ZIN0/UI1 5 76 P57/CLK/PPG7 P31/A01/AIN0/UO1/(SDA1) 6 75 P56/RDY/PPG6 P32/A02/BIN0/UCK1/(SCL1) 7 74 P55/HAK/PPG5 P33/A03/UI2 8 73 P54/HRQ/PPG4 P34/A04/UO2/(SDA2) 9 72 P53/WRH/IRQ23 P35/A05/ZIN1/UCK2/(SCL2) 10 71 P52/WRL P36/A06/AIN1/IRQ8 11 70 P51/RD P37/A07/BIN1/IRQ9 12 69 P50/ALE P40/A08/X0A* 13 68 PA3/(PPG7)/IRQ22 P41/A09/X1A* 14 67 PA2/(PPG6)/IRQ21 VCC 15 66 DVSS VSS 16 65 DVCC C 17 64 PA1/(PPG5)/IRQ20 P42/A10/UI3 18 63 PA0/(PPG4)/IRQ19 P43/A11/UO3/(SDA3) 19 62 P87/IRQ18/ADTG P44/A12/UCK3/(SCL3) 20 61 P86/UCK0/(SCL0) P45/A13/UI4 21 60 P85/UO0/(SDA0) P46/A14/UO4/(SDA4) 22 59 P84/UI0 P47/A15/UCK4/(SCL4) 23 58 P83/IRQ17 P90/CS0/AN8 24 57 P82/IRQ16/UCK6/(SCL6) P91/CS1/AN9 25 56 P81/UO6/(SDA6) P92/CS2/AN10 26 55 P80/IRQ15/UI6 P93/CS3/AN11 27 54 RST P94/AN12 28 53 MD0 P95/(UI3)/AN13 29 52 MD1 P96/AN14/(UO3)/(SDA3) 30 51 MD2 P76/IRQ14/UCK5/(SCL5) P67/AN7 50 43 P66/AN6 P75/UO5/(SDA5) 42 P65/AN5 49 41 P64/AN4 48 40 P63/AN3 P74/IRQ13/UI5 39 P62/AN2 47 38 P61/AN1 P73/IRQ12/AN19/(UCK4)/(SCL4) 37 P60/AN0 46 36 P72/IRQ11/AN18/(UO4)/(SDA4) 35 AVSS 45 34 P70/AN16 44 33 AVRH VSS 32 AVCC P71/(UI4)/IRQ10/AN17 31 P97/AN15/(UCK3)/(SCL3) QFP-100 (FPT-100P-M06) * : Dual clock product is sub clock oscillation pin. Single clock product is P40/A08 and P41/A09 pins. DS07-13743-5E 5 MB90880 Series P25/A21/TIO1 P24/A20/TIO0 P23/A19/PPG3 P22/A18/PPG2 P21/A17/PPG1 P20/A16/PPG0 P17/AD15/D15/IN1 P16/AD14/D14/IN0 P15/AD13/D13/OUT5 X0 X1 VSS VCC P14/AD12/D12/OUT4 P13/AD11/D11/OUT3 P12/AD10/D10/OUT2 P11/AD09/D09/OUT1 P10/AD08/D08/OUT0 P07/AD07/D07/IRQ7 P06/AD06/D06/IRQ6 P05/AD05/D05/IRQ5 P04/AD04/D04/IRQ4 P03/AD03/D03/IRQ3 P02/AD02/D02/IRQ2 P01/AD01/D01/IRQ1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (TOP VIEW) P26/A22/TIO2 1 75 P00/AD00/D00/IRQ0 P27/A23/TIO3 2 74 P57/CLK/PPG7 P30/A00/ZIN0/UI1 3 73 P56/RDY/PPG6 P31/A01/AIN0/UO1/(SDA1) 4 72 P55/HAK/PPG5 P32/A02/BIN0/UCK1/(SCL1) 5 71 P54/HRQ/PPG4 P33/A03/UI2 6 70 P53/WRH/IRQ23 P34/A04/UO2/(SDA2) 7 69 P52/WRL P35/A05/ZIN1/UCK2/(SCL2) 8 68 P51/RD P36/A06/AIN1/IRQ8 9 67 P50/ALE P37/A07/BIN1/IRQ9 10 66 PA3/(PPG7)/IRQ22 P40/A08/X0A* 11 65 PA2/(PPG6)/IRQ21 P41/A09/X1A* 12 64 DVSS VCC 13 63 DVCC VSS 14 62 PA1/(PPG5)/IRQ20 C 15 61 PA0/(PPG4)/IRQ19 P42/A10/UI3 16 60 P87/IRQ18/ADTG P43/A11/UO3/(SDA3) 17 59 P86/UCK0/(SCL0) P44/A12/UCK3/(SCL3) 18 58 P85/UO0/(SDA0) P45/A13/UI4 19 57 P84/UI0 P46/A14/UO4/(SDA4) 20 56 P83/IRQ17 P47/A15/UCK4/(SCL4) 21 55 P82/IRQ16/UCK6/(SCL6) P90/CS0/AN8 22 54 P81/UO6/(SDA6) P91/CS1/AN9 23 53 P80/IRQ15/UI6 P92/CS2/AN10 24 52 RST P93/CS3/AN11 25 51 MD0 39 40 41 42 43 44 45 46 47 48 49 50 P65/AN5 P66/AN6 P67/AN7 VSS P71/(UI4)/IRQ10/AN17 P72/IRQ11/AN18/(UO4)/(SDA4) P73/IRQ12/AN19/(UCK4)/(SCL4) P74/IRQ13/UI5 P75/UO5/(SDA5) P76/IRQ14/UCK5/(SCL5) MD2 MD1 34 P60/AN0 38 33 AVSS P64/AN4 32 P70/AN16 37 31 AVRH P63/AN3 30 AVCC 36 29 P97/AN15/(UCK3)/(SCL3) P62/AN2 28 P96/AN14/(UO3)/(SDA3) 35 27 P61/AN1 26 P94/AN12 P95/(UI3)/AN13 LQFP-100 (FPT-100P-M20) * : Dual clock product is sub clock oscillation pin. Single clock product is P40/A08 and P41/A09 pins. 6 DS07-13743-5E MB90880 Series ■ PIN DESCRIPTIONS Pin no. LQFP *1 QFP *2 Pin name I/O circuit type*3 P26 1 2 3 3 4 5 A22 General-purpose I/O port D Base timer I/O pin (ch.2) P27 General-purpose I/O port A23 D Base timer I/O pin (ch.3) P30 General-purpose I/O port A00 ZIN0 E P31 General-purpose I/O port A01 External address pin in non-multiplex mode. 8/16-bit up-down counter/timer input pin (ch.0) E Multi-function serial output pin This pin operates as UO1 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). P32 General-purpose I/O port A02 External address pin in non-multiplex mode. 7 8/16-bit up-down counter/timer input pin (ch.0) E UCK1/ (SCL1) P33 7 8/16-bit up-down counter/timer input pin (ch.0) Multi-function serial input pin 6 8 External address pin in non-multiplex mode. UI1 BIN0 6 Higher address output pin (A23) when corresponding bit in external address output control register (HACR) is set to "0". TIO3 UO1/ (SDA1) 5 Higher address output pin (A22) when corresponding bit in external address output control register (HACR) is set to "0". TIO2 AIN0 4 Function A03 Multi-function serial clock I/O pin This pin operates as UCK1 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SCL1 when it is used in an I2C (operation mode 4). General-purpose I/O port E External address pin in non-multiplex mode. UI2 Multi-function serial input pin P34 General-purpose I/O port A04 External address pin in non-multiplex mode. 9 E UO2/ (SDA2) Multi-function serial output pin This pin operates as UO2 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). (Continued) DS07-13743-5E 7 MB90880 Series Pin no. LQFP *1 QFP *2 Pin name I/O circuit type*3 P35 General-purpose I/O port A05 External address pin in non-multiplex mode. ZIN1 8 10 8/16-bit up-down counter/timer input pin (ch.1) E UCK2/ (SCL2) P36 9 10 11 11 12 13 A06 AIN1 Multi-function serial clock I/O pin This pin operates as UCK2 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SCL2 when it is used in an I2C (operation mode 4). General-purpose I/O port D External address pin in non-multiplex mode. 8/16-bit up-down counter/timer input pin (ch.1) IRQ8 External interrupt input pin P37 General-purpose I/O port A07 BIN1 D External address pin in non-multiplex mode. 8/16-bit up-down counter/timer input pin (ch.1) IRQ9 External interrupt input pin P40 General-purpose I/O port (Only for single clock model) A08 A/D External address pin in non-multiplex mode. (Only for single clock model) X0A 32 kHz oscillator connecting pin (Only for dual clock model) P41 General-purpose I/O port (Only for single clock model) A/D External address pin in non-multiplex mode. (Only for single clock model) 12 14 A09 13 15 VCC ⎯ Power supply pin 14 16 VSS ⎯ Power supply pin (GND) 15 17 C ⎯ Regulator stabilization capacity connecting pin It should be connected to a 0.47μF ceramic capacitor. X1A 32 kHz oscillator connecting pin (Only for dual clock model) P42 16 17 18 A10 General-purpose I/O port E External address pin in non-multiplex mode. UI3 Multi-function serial input pin P43 General-purpose I/O port A11 External address pin in non-multiplex mode. 19 E UO3/ (SDA3) 8 Function Multi-function serial output pin This pin operates as UO3 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). (Continued) DS07-13743-5E MB90880 Series Pin no. LQFP *1 QFP *2 18 Pin name I/O circuit type*3 P44 General-purpose I/O port A12 External address pin in non-multiplex mode. 20 E UCK3/ (SCL3) P45 19 20 21 A13 E Multi-function serial input pin P46 General-purpose I/O port A14 External address pin in non-multiplex mode. 22 E General-purpose I/O port A15 External address pin in non-multiplex mode. E P90 23 24 25 26 CS0 H Analog input pin P91 General-purpose I/O port CS1 H 28 Analog input pin P92 General-purpose I/O port CS2 H CS3 P94 AN12 29 AN13 (UI3) Chip select 2 output pin Analog input pin General-purpose I/O port H Chip select 3 output pin Analog input pin H P95 27 Chip select 1 output pin AN9 AN11 26 Chip select 0 output pin AN8 P93 27 Multi-function serial clock I/O pin This pin operates as UCK4 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SCL4 when it is used in an I2C (operation mode 4). General-purpose I/O port AN10 25 Multi-function serial output pin This pin operates as UO4 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). P47 23 24 External address pin in non-multiplex mode. UI4 UCK4/ (SCL4) 22 Multi-function serial clock I/O pin This pin operates as UCK3 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SCL3 when it is used in an I2C (operation mode 4). General-purpose I/O port UO4/ (SDA4) 21 Function General-purpose I/O port Analog input pin General-purpose I/O port K Analog input pin Multi-function serial input pin (when the P95FS bit in P9FSR register is “1”) (Continued) DS07-13743-5E 9 MB90880 Series Pin no. LQFP *1 QFP *2 Pin name I/O circuit type*3 P96 General-purpose I/O port AN14 28 30 Analog input pin K (UO3)/ (SDA3) P97 31 Multi-function serial output pin This pin operates as UO3 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). (when the P96FS bit in P9FSR register is “1”) General-purpose I/O port AN15 29 Function Analog input pin K (UCK3)/ (SCL3) Multi-function serial clock I/O pin This pin operates as UCK3 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SCL3 when it is used in an I2C (operation mode 4). (when the P97FS bit in P9FSR register is “1”) 30 32 AVCC ⎯ A/D converter power supply pin 31 33 AVRH ⎯ Reference voltage input pin for A/D converter This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVCC. 32 34 33 35 34 36 35 37 36 38 37 39 38 40 39 41 40 42 41 43 P70 AN16 AVSS P60 AN0 P61 AN1 P62 AN2 P63 AN3 P64 AN4 P65 AN5 P66 AN6 P67 AN7 H H H H H H H H H General-purpose I/O port Analog input pin A/D converter analog GND pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin (Continued) 10 DS07-13743-5E MB90880 Series Pin no. LQFP *1 QFP *2 Pin name 42 44 VSS 43 44 45 I/O circuit type*3 ⎯ General-purpose I/O port IRQ10 External interrupt input pin AN17 K Multi-function serial input pin (when the P71FS bit in P7FSR register is “1”) P72 General-purpose I/O port IRQ11 External interrupt input pin AN18 Analog input pin 46 K General-purpose I/O port IRQ12 External interrupt input pin AN19 Analog input pin K P74 47 48 49 Multi-function serial output pin This pin operates as UO4 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). (when the P72FS bit in P7FSR register is “1”) P73 47 48 Analog input pin (UI4) (UCK4)/ (SCL4) 46 Power supply pin (GND) P71 (UO4)/ (SDA4) 45 Function IRQ13 Multi-function serial clock I/O pin This pin operates as UCK4 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SCL4 when it is used in an I2C (operation mode 4). (when the P73FS bit in P7FSR register is “1”) General-purpose I/O port G External interrupt input pin UI5 Multi-function serial input pin P75 General-purpose I/O port UO5/ (SDA5) G Multi-function serial output pin This pin operates as UO5 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). P76 General-purpose I/O port IRQ14 External interrupt input pin 50 G Multi-function serial clock I/O pin This pin operates as UCK5 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SCL5 when it is used in an I2C (operation mode 4). UCK5/ (SCL5) 49 51 MD2 M Operation mode specification input pin 50 52 MD1 L Operation mode specification input pin (Continued) DS07-13743-5E 11 MB90880 Series Pin no. I/O circuit type*3 LQFP *1 QFP *2 Pin name 51 53 MD0 L Operation mode specification input pin 52 54 RST B Reset input pin P80 53 54 55 55 56 IRQ15 General-purpose I/O port G Multi-function serial input pin P81 General-purpose I/O port UO6/ (SDA6) G 57 59 General-purpose I/O port IRQ16 External interrupt input pin G P83 IRQ17 P84 UI0 I G P85 58 60 UO0/ (SDA0) 61 UCK0/ (SCL0) G 62 IRQ18 G I IRQ19 (PPG4) General-purpose I/O port Multi-function serial input pin Multi-function serial output pin This pin operates as UO0 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial clock I/O pin This pin operates as UCK0 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SCL0 when it is used in an I2C (operation mode 4). External interrupt input pin External trigger input pin, when A/D converter is used. PA0 63 External interrupt input pin General-purpose I/O port ADTG 61 General-purpose I/O port General-purpose I/O port P87 60 Multi-function serial clock I/O pin This pin operates as UCK6 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SCL6 when it is used in an I2C (operation mode 4). General-purpose I/O port P86 59 Multi-function serial output pin This pin operates as UO6 when it is used in a UART/CSIO/LINUART (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). P82 UCK6/ (SCL6) 58 External interrupt input pin UI6 57 56 Function General-purpose I/O port J External interrupt input pin PPG timer output pin (when the PA0FS bit in PAFSR register is “1”) (Continued) 12 DS07-13743-5E MB90880 Series Pin no. LQFP *1 QFP *2 Pin name I/O circuit type*3 PA1 62 64 IRQ20 Function General-purpose I/O port J (PPG5) External interrupt input pin PPG timer output pin (when the PA1FS bit in PAFSR register is "1") 63 65 DVCC ⎯ PA port power supply pin 64 66 DVSS ⎯ PA port power supply pin (GND) PA2 65 67 IRQ21 General-purpose I/O port J (PPG6) PPG timer output pin (when the PA2FS bit in PAFSR register is "1") PA3 66 68 IRQ22 General-purpose I/O port J (PPG7) 67 69 68 70 P50 ALE P51 RD 71 WRL F F 71 72 73 WRH F F General-purpose I/O port Read strobe output (RD) pin in external bus mode. Lower data write strobe output (WRL) pin in external bus mode, and serves as a general-purpose I/O port when WRE bit in EPCR register is "0". Higher data write strobe output (WRH) pin in external bus mode with 16-bit bus width, and serves as a general-purpose I/O port when WRE bit in EPCR register is "0". IRQ23 External interrupt input pin P54 General-purpose I/O port HRQ F HAK PPG5 Hold request input (HRQ) pin in external bus mode, and serves as a general-purpose I/O port when HDE bit in EPCR register is "0". PPG timer output pin P55 74 Address latch enable signal (ALE) pin in external bus mode. General-purpose I/O port PPG4 72 General-purpose I/O port General-purpose I/O port P53 70 External interrupt input pin PPG timer output pin (when the PA3FS bit in PAFSR register is "1") P52 69 External interrupt input pin General-purpose I/O port F Hold acknowledge output (HAK) pin in external bus mode, and serves as a general-purpose I/O port when HDE bit in EPCR register is "0". PPG timer output pin (Continued) DS07-13743-5E 13 MB90880 Series Pin no. LQFP *1 QFP *2 Pin name I/O circuit type*3 P56 73 75 RDY General-purpose I/O port F PPG6 76 CLK General-purpose I/O port F PPG7 76 77 78 79 77 78 79 80 81 AD00/ D00 Machine cycle clock output (CLK) pin in external bus mode, and serves as a general-purpose I/O port when CKE bit in EPCR register is "0". PPG timer output pin P00 75 External ready input (RDY) pin in external bus mode, and serves as a general-purpose I/O port when RYE bit in EPCR register is "0". PPG timer output pin P57 74 Function General-purpose I/O port C Lower external address/data bus I/O pin (AD00) in multiplex mode. Lower external data bus output pin (D00) in non-multiplex mode. IRQ0 External interrupt input pin P01 General-purpose I/O port AD01/ D01 C External address/lower data bus I/O pin (AD01) in multiplex mode. Lower external data bus output pin (D01) in non-multiplex mode. IRQ1 External interrupt input pin P02 General-purpose I/O port AD02/ D02 C External address/lower data bus I/O pin (AD02) in multiplex mode. Lower external data bus output pin (D02) in non-multiplex mode. IRQ2 External interrupt input pin P03 General-purpose I/O port AD03/ D03 C External address/lower data bus I/O pin (AD03) in multiplex mode. Lower external data bus output pin (D03) in non-multiplex mode. IRQ3 External interrupt input pin P04 General-purpose I/O port AD04/ D04 IRQ4 C Lower external address/data bus I/O pin (AD04) in multiplex mode. Lower external data bus output pin (D04) in non-multiplex mode. External interrupt input pin (Continued) 14 DS07-13743-5E MB90880 Series Pin no. LQFP *1 QFP *2 Pin name I/O circuit type*3 P05 80 81 82 83 82 83 84 85 AD05/ D05 General-purpose I/O port C P06 General-purpose I/O port AD06/ D06 C Lower external data bus output pin (D06) in non-multiplex mode. External interrupt input pin P07 General-purpose I/O port AD07/ D07 C Lower external address/data bus I/O pin (AD07) in multiplex mode. Lower external data bus output pin (D07) in non-multiplex mode. IRQ7 External interrupt input pin P10 General-purpose I/O port AD08/ D08 C AD09/ D09 AD10/ D10 OUT2 Higher external address/data bus I/O pin (AD08) in multiplex mode. Higher external data output pin (D08) in non-multiplex mode. Output compare event output pin General-purpose I/O port C Higher external address/data bus I/O pin (AD09) in multiplex mode. Higher external data output pin (D09) in non-multiplex mode. Output compare event output pin P12 87 Lower external address/data bus I/O pin (AD06) in multiplex mode. IRQ6 OUT1 85 Lower external data bus output pin (D05) in non-multiplex mode. External interrupt input pin P11 86 Lower external address/data bus I/O pin (AD05) in multiplex mode. IRQ5 OUT0 84 Function General-purpose I/O port C Higher external address/data bus I/O pin (AD10) in multiplex mode. Higher external data output pin (D10) in non-multiplex mode. Output compare event output pin (Continued) DS07-13743-5E 15 MB90880 Series Pin no. LQFP *1 QFP *2 Pin name I/O circuit type*3 P13 86 88 AD11/ D11 General-purpose I/O port C OUT3 89 AD12/ D12 Higher external address/data bus I/O pin (AD11) in multiplex mode. Higher external data output pin (D11) in non-multiplex mode. Output compare event output pin P14 87 Function General-purpose I/O port C OUT4 Higher external address/data bus I/O pin (AD12) in multiplex mode. Higher external data output pin (D12) in non-multiplex mode. Output compare event output pin 88 90 VCC ⎯ Power supply pin 89 91 VSS ⎯ Power supply pin (GND) 90 92 X1 A Main oscillator connecting pin 91 93 X0 A Main oscillator connecting pin P15 92 94 AD13/ D13 General-purpose I/O port C OUT5 94 95 95 96 97 AD14/ D14 Higher external data output pin (D13) in non-multiplex mode. Output compare event output pin P16 93 Higher external address/data bus I/O pin (AD13) in multiplex mode. General-purpose I/O port C Higher external address/data bus I/O pin (AD14) in multiplex mode. Higher external data output pin (D14) in non-multiplex mode. IN0 Trigger input pin for input capture ch.0 P17 General-purpose I/O port AD15/ D15 C Higher external address/data bus I/O pin (AD15) in multiplex mode. Higher external data output pin (D15) in non-multiplex mode. IN1 Trigger input pin for input capture ch.1 P20 General-purpose I/O port A16 PPG0 D Higher address output pin (A16) when corresponding bit in external address output control register (HACR) is set to "0". PPG timer output pin (Continued) 16 DS07-13743-5E MB90880 Series (Continued) Pin no. LQFP *1 QFP *2 Pin name I/O circuit type*3 P21 96 98 A17 General-purpose I/O port D PPG1 99 A18 General-purpose I/O port D PPG2 100 A19 General-purpose I/O port D PPG3 100 1 2 A20 Higher address output pin (A19) when corresponding bit in external address output control register (HACR) is set to "0". PPG timer output pin P24 99 Higher address output pin (A18) when corresponding bit in external address output control register (HACR) is set to "0". PPG timer output pin P23 98 Higher address output pin (A17) when corresponding bit in external address output control register (HACR) is set to "0". PPG timer output pin P22 97 Function General-purpose I/O port D Higher address output pin (A20) when corresponding bit in external address output control register (HACR) is set to "0". TIO0 Base timer I/O pin (ch.0) P25 General-purpose I/O port A21 TIO1 D Higher address output pin (A21) when corresponding bit in external address output control register (HACR) is set to "0". Base timer I/O pin (ch.1) *1 : LQFP : FPT-100P-M20 *2 : QFP : FPT-100P-M06 *3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”. DS07-13743-5E 17 MB90880 Series ■ I/O CIRCUIT TYPE Type Circuit Remarks A X1, X1A P-ch N-ch • Oscillation feedback resistance X1, X0 : approx. 1 MΩ X1A, X0A : approx. 10 MΩ • Standby control provided Xout X0, X0A Standby control signal B Hysteresis input with pull-up resistor R R Hysteresis input C Pull-up control signal P-ch P-ch N-ch • • • • Input pull-up resistor control provided CMOS level output Hysteresis input CMOS input (in external bus mode) R CMOS input Hysteresis input Standby control for input shutdown D • CMOS level output • Hysteresis input P-ch N-ch R Hysteresis input Standby control for input shutdown E • CMOS level output • Hysteresis input • I2C level hysteresis input P-ch N-ch R Hysteresis input I2C level hysteresis input Standby control for input shutdown (Continued) 18 DS07-13743-5E MB90880 Series Type Circuit Remarks F • CMOS level output • Hysteresis input • CMOS input (in external bus mode) P-ch N-ch R CMOS input Hysteresis input Standby control for input shutdown G P-ch Open-drain control signal N-ch • CMOS level output (Open-drain control provided) • 5 V tolerant • Hysteresis input • I2C level hysteresis input R Hysteresis input I2C level hysteresis input Standby control for input shutdown H • CMOS level output • Hysteresis input • Analog input P-ch N-ch R Hysteresis input Standby control for input shutdown Analog input I P-ch Open-drain control signal N-ch • CMOS level output (Open-drain control provided) • 5 V tolerant • Hysteresis input R Hysteresis input Standby control for input shutdown (Continued) DS07-13743-5E 19 MB90880 Series Type Circuit Remarks J • CMOS/level output (high-current type) • Hysteresis input P-ch N-ch R Hysteresis input Standby control for input shutdown K • • • • P-ch N-ch CMOS level output Hysteresis input Analog input I2C level hysteresis input R Hysteresis input I2C level Hysteresis input Standby control for input shutdown Analog input L Flash memory product • CMOS level input • High-voltage control for flash test provided Flash memory product N-ch N-ch Control signal N-ch N-ch R Mode input Diffused resistor MASK ROM product Hysteresis input MASK ROM product R Hysteresis input (Continued) 20 DS07-13743-5E MB90880 Series (Continued) Type M Circuit Remarks Flash memory product • CMOS level input • High-voltage control for flash test provided Flash memory product N-ch N-ch Control signal N-ch N-ch R Mode input Diffused resistor MASK ROM product, Evaluation product R With pull-down resistor Hysteresis input Hysteresis input Pull-down resistor DS07-13743-5E 21 MB90880 Series ■ HANDLING DEVICES 1. Maximum rated voltages for the prevention of latch-up Be cautious not to exceed the absolute maximum rating. CMOS ICs may cause latch-up, when a voltage higher than VCC or lower than VSS is applied to input or output pins other than medium-to-high resistant pins, or when a voltage exceeding the rating is applied between VCC and VSS pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Take the utmost care not to let it occur. Likewise, care must be taken not to allow the analog power supply (AVCC, AVRH) and analog input to exceed the digital power supply (VCC) when turning on or off any analog system. 2. Handling unused pins Leaving unused input pins open may cause a malfunction or latch-up which leads to fatal damage to the device. Therefore, they must be pulled up or down through at least 2 kΩ resistance. Also, any unused I/O pin should be left open in the output state, or set to the input state and handled in the same way as an unused input pin. 3. Notes on using external clock Even when an external clock is being used, oscillation stabilization wait time is required for a power-on reset or release from sub clock mode or stop mode. The following diagram shows an example of using an external clock. X0(X0A) Open X1(X1A) 4. Handling power supply pins (VCC/VSS) When multiple VCC and VSS pins supply pins are used, all the power supply pins must be connected to external power and ground lines due to the device design, to reduce latch-up and unwanted radiation, prevent abnormal operation of strobe signals caused by the rise in the ground level and to conform to the total output current rating. Make sure to connect the VCC and VSS pins of this device via lowest impedance to power lines. It is recommended that a bypass capacitor of around 0.1 μF be placed between the VCC and VSS pins near the device. 5. Crystal oscillator circuit Noises around X0/X1 or X0A/X1A pins may cause abnormal operations. It is strongly recommended to provide bypass capacitors via shortest distance from X0/X1, X0A/X1A pins, crystal oscillator (or ceramic oscillator) and ground lines and also not to allow the lines of the oscillation circuit to cross the lines of other circuits. This will ensure stable operations of the printed circuit boards. Please ask each crystal maker to evaluate the oscillational characteristics of the crystal and this device. 6. Notes on PLL clock mode operation If an oscillator comes off or clock input stops during PLL clock mode operation, this microcontroller may continue its operation using a free-running frequency from a self-excited oscillation circuit within PLL. This is not a guaranteed operation. 22 DS07-13743-5E MB90880 Series 7. Power-on and power-off sequence of A/D converter and analog input Turn on the A/D converters (AVCC, AVRH) and analog inputs (AN0 to AN19) after turning on the digital power supply (VCC) . During power-off, turn off the digital power supply (VCC) after turning off the A/D converters and analog inputs (AN0 to AN19) . In this case, make sure that AVRH does not exceed AVCC during the power-on/power-off procedure. Also make sure that the input voltage does not exceed AVCC when a pin which is also used as an analog input is used as an input port. 8. Handling power supply pins on A/D converter-mounted models Make sure to achieve "AVCC = AVRH = VCC" and "AVSS = VSS" in connecting the circuits, even when not using the A/D converter function. 9. Note on power-up To prevent the internal regulator from malfunctioning, maintain the voltage rise time at 50 μs (between 0.2V and 2.7V) or more during power-up. 10. Stabilization of power supply Even when the VCC power supply voltage is within the specified operating range, it may still cause the device to malfunction, if the power supply changes rapidly. For stabilization reference, it is recommended to control the supply voltage so that VCC ripple variations (P-P values) at commercial frequencies (50/60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching. 11. Note of MB90F883B(S), MB90F884B(S) • Maximum operating frequency is 25 MHz. • MB90F883B(S) and MB90F884B(S) do not contain the flash security function or protect function against erroneous write operation. 12. Note of MB90F883BH(S), MB90F884BH(S) MB90F883BH(S) and MB90F884BH(S) do not contain the flash security function or protect function against erroneous write operation. 13. Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of receiving wrong data due to the noise. 14. When Using Dual Clock Products as Single Clock Products Use the X0A pin connected to Vss, and use the X1A pin as open. DS07-13743-5E 23 MB90880 Series ■ BLOCK DIAGRAM X0, X1, RST X0A, X1A MD0 to MD2 CPU F2MC-16LX series core Clock control circuit RAM Interrupt controller ROM μDMAC 16-bit PPG UI0 to UI6 UO0 to UO6 UCK0 to UCK6 F2MC-16LX bus Multifunction serial SIO/UART/I2C mode switching enabled 8/16-bit up-down counter/timer PPG0 to PPG7 AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 I/O timer AVCC AVRH AVSS ADTG AN0 to AN19 16-bit input capture × 2 channels 8/10-bit A/D converter 24 IRQ0 to IRQ23 16-bit output compare × 6 channels 16-bit free-run timer 16-bit base timer External interrupt IN0, IN1 OUT0 to OUT5 TIO0 to TIO3 Reload timer/PWM/PWC/ PPG mode switching enabled I/O port 8 8 8 8 8 8 8 7 8 8 4 P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P76 P80 to P87 P90 to P97 PA0 to PA3 Note : The I/O ports shown in the diagram above are shared by other built-in function blocks. They cannot be used as I/O ports when used as pins for a built-in module. 24 DS07-13743-5E MB90880 Series ■ MEMORY MAP Single chip mode Internal ROM external bus ROM area ROM area External ROM external bus FFFFFFH Address #1 010000H Address #2 007900H ROM area ROM area Image of FF bank Image of FF bank Peripheral area Peripheral area Peripheral area Address #3 RAM Register RAM Register RAM Register 000100H 0000F0H 000000H Peripheral area : Internal Parts No. MB90882 (S) MB90F882A (S) MB90F883B (S) / MB90F883BH (S)/ MB90F883C(S) MB90F884B (S) / MB90F884BH (S)/ MB90F884C(S) MB90V880A-101/102 Address #1 FC0000H FC0000H Peripheral area : External Address #2 Peripheral area : Access prohibited Address #3 004100H 004100H 006100H FA0000H 008000H fixed F80000H 007900H (F80000H) 007900H Note : The image of the ROM data in the FF bank appears at the top of the 00 bank in order to enable efficient use of the C compiler small memory model. The lower 16-bit address for the FF bank will be assigned to the same address as that for the 00 bank, so that tables in ROM can be referenced without declaring a "far" indication with the pointer. For example, when accessing the address 00C000H, the actual access is to address FFC000H in ROM. Here the FF bank ROM area exceeds 32 Kbytes, it is not possible to show the entire area in the 00 bank image. Therefore, the ROM data in FF8000H to FFFFFFH can be seen in the 00 bank image, while the data in FF0000H to FF7FFFH can only be seen in the FF bank. For MB90F883B(S)/F883BH(S)/F883C(S), the areas of 006100H to 0078FFH and F80000H to F9FFFFH cannot be used as an external area. DS07-13743-5E 25 MB90880 Series ■ F2MC-16LX CPU PROGRAMMING MODEL • Dedicated register AH Accumulator AL USP User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program counter bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional data bank register 8 bits 16 bits 32 bits • General-purpose register MSB LSB 16 bits 000180H + RP × 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R0 RW4 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 RL3 • Processor status bit 15 PS 26 bit 13 bit 12 ILM bit 8 bit 7 RP bit 0 CCR DS07-13743-5E MB90880 Series ■ I/O MAP Address Register abbreviation 000000H PDR0 000001H Register name R/W Resource Initial value Port 0 data register R/W Port 0 XXXXXXXXB PDR1 Port 1 data register R/W Port 1 XXXXXXXXB 000002H PDR2 Port 2 data register R/W Port 2 XXXXXXXXB 000003H PDR3 Port 3 data register R/W Port 3 XXXXXXXXB 000004H PDR4 Port 4 data register R/W Port 4 XXXXXXXXB 000005H PDR5 Port 5 data register R/W Port 5 XXXXXXXXB 000006H PDR6 Port 6 data register R/W Port 6 XXXXXXXXB 000007H PDR7 Port 7 data register R/W Port 7 XXXXXXXXB 000008H PDR8 Port 8 data register R/W Port 8 XXXXXXXXB 000009H PDR9 Port 9 data register R/W Port 9 XXXXXXXXB 00000AH PDRA Port A data register R/W Port A XXXXXXXXB 00000BH UDER Up-down timer input enable register R/W Up-down timer input control XX000000B 00000CH ILSR0 Serial input level selection register 0 R/W 00000DH ILSR1 Serial input level selection register 1 R/W 00000EH ILSR2 Serial input level selection register 2 R/W 00000FH 00000000B Multi-function serial control 00000000B ---00000B Disabled 000010H DDR0 Port 0 direction register R/W Port 0 00000000B 000011H DDR1 Port 1 direction register R/W Port 1 00000000B 000012H DDR2 Port 2 direction register R/W Port 2 00000000B 000013H DDR3 Port 3 direction register R/W Port 3 00000000B 000014H DDR4 Port 4 direction register R/W Port 4 00000000B 000015H DDR5 Port 5 direction register R/W Port 5 00000000B 000016H DDR6 Port 6 direction register R/W Port 6 00000000B 000017H DDR7 Port 7 direction register R/W Port 7 -0000000B 000018H DDR8 Port 8 direction register R/W Port 8 00000000B 000019H DDR9 Port 9 direction register R/W Port 9 00000000B 00001AH DDRA Port A direction register R/W Port A ----0000B 00001BH ADER0 Analog input enable register 0 R/W Port 6, A/D 11111111B 00001CH ADER1 Analog input enable register 1 R/W Port 9, A/D 11111111B 00001DH ADER2 Analog input enable register 2 R/W Port 7, A/D ----1111B 00001EH RDR0 Port 0 input resistance register R/W Port 0 (pull-up resistance control) 00000000B 00001FH RDR1 Port 1 input resistance register R/W Port 1 (pull-up resistance control) 00000000B (Continued) DS07-13743-5E 27 MB90880 Series Address Register abbreviation 000020H SMR0 000021H SCR0/IBCR0 Register name R/W Resource Initial value Serial bus mode register ch.0 R/W $$$$$$$$B SCR0/IBCR0 serial bus control register/I2C bus control register ch.0 R/W $$$$$$$$B Extended communication control register/I2C bus status register ch.0 R/W $$$$$$$$B Serial status register ch.0 R/W $$$$$$$$B 000022H ESCR0/ IBSR0 000023H SSR0 000024H RDR00/ TDR00 Transmission/reception data register 0 ch.0 R,W 000025H RDR10/ TDR10 Transmission/reception data register 1 ch.0 R,W $$$$$$$$B 000026H BGR00 Baud rate generator register 0 ch.0 R/W $$$$$$$$B 000027H BGR10 Baud rate generator register 1 ch.0 R/W $$$$$$$$B 000028H ISBA0 7-bit slave address register ch.0 R/W 00000000B 000029H ISMK0 7-bit slave address mask register ch.0 R/W 01111111B 00002AH SMR1 Serial bus mode register ch.1 R/W $$$$$$$$B Serial bus control register / I2C bus control register ch.1 R/W $$$$$$$$B Extended communication control register / I2C bus status register ch.1 R/W $$$$$$$$B Serial status register ch.1 R/W $$$$$$$$B 00002BH SCR1/IBCR1 Multi-function serial ch.0 $$$$$$$$B 00002CH ESCR1/ IBSR1 00002DH SSR1 00002EH RDR01/ TDR01 Transmission/reception data register 0 ch.1 R,W 00002FH RDR11/ TDR11 Transmission/reception data register 1 ch.1 R,W $$$$$$$$B 000030H BGR01 Baud rate generator register 0 ch.1 R/W $$$$$$$$B 000031H BGR11 Baud rate generator register 1 ch.1 R/W $$$$$$$$B 000032H ISBA1 7-bit slave address register ch.1 R/W 00000000B 000033H ISMK1 7-bit slave address mask register ch.1 R/W 01111111B 000034H ADCSL Lower A/D control status register R/W 00011110B 000035H ADCSH Higher A/D control status register R/W 00000000B 000036H ADCRL Lower A/D data register R XXXXXXXXB 000037H ADCRH Higher A/D data register R 000038H ADSRL Lower A/D conversion channel setting register R/W 00000000B 000039H ADSRH Higher A/D conversion channel setting register R/W 00000000B 00003AH Multi-function serial ch.1 A/D Converter $$$$$$$$B 111111XXB Reserved (Continued) 28 DS07-13743-5E MB90880 Series Address Register abbreviation 00003BH PACSR1 00003CH Register name R/W Resource Initial value Address detection control status register 1 R/W Address match detection function 00000000B OLSR0 Output level selection register 0 R/W Port 7 (N-ch open-drain control) -000----B 00003DH OLSR1 Output level selection register 1 R/W Port 8 (N-ch open-drain control) 00000000B 00003EH SMR2 Serial bus mode register ch.2 R/W $$$$$$$$B Serial bus control register / I C bus control register ch.2 R/W $$$$$$$$B Extended communication control register / I2C bus status register ch.2 R/W $$$$$$$$B Serial status register ch.2 R/W $$$$$$$$B 2 00003FH SCR2/IBCR2 000040H ESCR2/ IBSR2 000041H SSR2 000042H RDR02/ TDR02 Transmission/reception data register 0 ch.2 R,W 000043H RDR12/ TDR12 Transmission/reception data register 1 ch.2 R,W $$$$$$$$B 000044H BGR02 Baud rate generator register 0 ch.2 R/W $$$$$$$$B 000045H BGR12 Baud rate generator register 1 ch.2 R/W $$$$$$$$B 000046H ISBA2 7-bit slave address register ch.2 R/W 00000000B 000047H ISMK2 7-bit slave address mask register ch.2 R/W 01111111B 000048H SMR3 Serial bus mode register ch.3 R/W $$$$$$$$B Serial bus control register / I2C bus control register ch.3 R/W $$$$$$$$B Extended communication control register / I2C bus status register ch.3 R/W $$$$$$$$B Serial status register ch.3 R/W $$$$$$$$B 000049H SCR3/IBCR3 Multi-function serial ch.2 $$$$$$$$B 00004AH ESCR3/ IBSR3 00004BH SSR3 00004CH RDR03/ TDR03 Transmission/reception data register 0 ch.3 R,W 00004DH RDR13/ TDR13 Transmission/reception data register 1 ch.3 R,W $$$$$$$$B 00004EH BGR03 Baud rate generator register 0 ch.3 R/W $$$$$$$$B 00004FH BGR13 Baud rate generator register 1 ch.3 R/W $$$$$$$$B 000050H ISBA3 7-bit slave address register ch.3 R/W 00000000B 000051H ISMK3 7-bit slave address mask register ch.3 R/W 01111111B 000052H SMR4 Serial bus mode register ch.4 R/W 2 000053H SCR4/IBCR4 Serial bus control register / I C bus control register ch.4 R/W Multi-function serial ch.3 $$$$$$$$B $$$$$$$$B Multi-function serial ch.4 $$$$$$$$B (Continued) DS07-13743-5E 29 MB90880 Series Address Register abbreviation 000054H ESCR4/ IBSR4 000055H SSR4 000056H Register name R/W Resource Initial value Extended communication control register / I2C bus status register ch.4 R/W $$$$$$$$B Serial status register ch.4 R/W $$$$$$$$B RDR04/ TDR04 Transmission/reception data register 0 ch.4 R,W $$$$$$$$B 000057H RDR14/ TDR14 Transmission/reception data register 1 ch.4 R,W 000058H BGR04 Baud rate generator register 0 ch.4 R/W $$$$$$$$B 000059H BGR14 Baud rate generator register 1 ch.4 R/W $$$$$$$$B 00005AH ISBA4 7-bit slave address register ch.4 R/W 00000000B 00005BH ISMK4 7-bit slave address mask register ch.4 R/W 01111111B 00005CH SMR5 Serial bus mode register ch.5 R/W $$$$$$$$B Serial bus control register / I C bus control register ch.5 R/W $$$$$$$$B Extended communication control register / I2C bus status register ch.5 R/W $$$$$$$$B Serial status register ch.5 R/W $$$$$$$$B Multi-function serial ch.4 $$$$$$$$B 2 00005DH SCR5/IBCR5 00005EH ESCR5/ IBSR5 00005FH SSR5 000060H RDR05/ TDR05 Transmission/reception data register 0 ch.5 R,W 000061H RDR15/ TDR15 Transmission/reception data register 1 ch.5 R,W $$$$$$$$B 000062H BGR05 Baud rate generator register 0 ch.5 R/W $$$$$$$$B 000063H BGR15 Baud rate generator register 1 ch.5 R/W $$$$$$$$B 000064H ISBA5 7-bit slave address register ch.5 R/W 00000000B 000065H ISMK5 7-bit slave address mask register ch.5 R/W 01111111B 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH OCCP0 OCCP1 OCCP2 OCCP3 00006EH 00006FH Lower output compare register (ch.0) Higher output compare register (ch.0) Lower output compare register (ch.1) Higher output compare register (ch.1) Lower output compare register (ch.2) Higher output compare register (ch.2) Lower output compare register (ch.3) Higher output compare register (ch.3) Multi-function serial ch.5 00000000B R/W R/W R/W $$$$$$$$B 00000000B 00000000B 16-bit I/O timer output compare (ch.0 to ch.5) 00000000B 00000000B 00000000B 00000000B R/W 00000000B Reserved ROMM ROM mirror function selection register R/W ROM mirror function -------1B (Continued) 30 DS07-13743-5E MB90880 Series Address 000070H 000071H 000072H 000073H Register abbreviation OCCP4 OCCP5 Register name R/W Lower output compare register (ch.4) Higher output compare register (ch.4) Lower output compare register (ch.5) Higher output compare register (ch.5) Resource Initial value 00000000B R/W 00000000B 00000000B R/W 00000000B Lower output compare control register (ch.0, ch.1) R/W 000075H Higher output compare control register (ch.0, ch.1) R/W 000076H Lower output compare control register (ch.2, ch.3) R/W 0000--00B 000077H Higher output compare control register (ch.2, ch.3) R/W ---00000B 000078H Lower output compare control register (ch.4, ch.5) R/W 0000--00B 000079H Higher output compare control register (ch.4, ch.5) R/W ---00000B 00007AH Lower input capture data register (ch.0) R XXXXXXXXB Higher input capture data register (ch.0) R XXXXXXXXB Lower input capture data register (ch.1) R IPCP1 Higher input capture data register (ch.1) R 00007EH ICS01 Input capture control status register 00007FH ICE01 Input capture edge register 000080H TCDT 000081H 000074H OCS01 OCS23 OCS45 00007BH IPCP0 00007CH 00007DH 0000--00B 16-bit I/O timer output compare (ch.0 to ch.5) 16-bit I/O timer input capture (ch.0, ch.1) ---00000B XXXXXXXXB XXXXXXXXB R/W 00000000B R ------XXB Lower timer counter data register R/W 00000000B TCDT Higher timer counter data register R/W 00000000B 000082H TCCS Timer control status register R/W 000083H TCCS Timer control status register R/W 000084H 000085H CPCLR Lower compare clear register 00000000B XX-00000B XXXXXXXXB R/W Higher compare clear register 000086H to 00009AH 16-bit I/O timer free-run timer XXXXXXXXB Reserved 00009BH DCSR DMAC descriptor channel specification register R/W DMAC 00000000B 00009CH DSRL DMAC lower status register R/W DMAC 00000000B 00009DH DSRH DMAC higher status register R/W DMAC 00000000B (Continued) DS07-13743-5E 31 MB90880 Series Address Register abbreviation 00009EH PACSR0 00009FH DIRR 0000A0H LPMCR Low power consumption mode control register W, R/W 0000A1H CKSCR Clock selection register R, R/W Register name R/W Resource Initial value Address detection control status register 0 R/W Address match detection function 00000000B Delayed interrupt source generation/ release register R/W Delayed interrupt generation module -------0B 0000A2H, 0000A3H Low power consumption 00011000B 11111100B Reserved 0000A4H DSSR DMAC stop status register 0000A5H ARSR Auto ready function selection register W 0000A6H HACR External address output control register W 0000A7H EPCR Bus control signal selection register W 0000A8H WDTC Watchdog timer control register R, W Watchdog timer XXXXX111B 0000A9H TBTC Time base timer control register W, R/W Time base timer 1XX00100B 0000AAH WTC Watch timer control register R, R/W Watch timer 10001000B 0000ABH R/W DMAC 00000000B 0011--00B External bus ********B 1000*10-B Reserved 0000ACH DERL DMAC lower enable register R/W 0000ADH DERH DMAC higher enable register R/W 0000AEH FMCS Flash memory control status register 0000AFH W, R/W DMAC Flash memory I/F 00000000B 00000000B 000X0000B Prohibited 0000B0H ICR00 Interrupt control register 00 W, R/W 00000111B 0000B1H ICR01 Interrupt control register 01 W, R/W 00000111B 0000B2H ICR02 Interrupt control register 02 W, R/W 00000111B 0000B3H ICR03 Interrupt control register 03 W, R/W 00000111B 0000B4H ICR04 Interrupt control register 04 W, R/W 00000111B 0000B5H ICR05 Interrupt control register 05 W, R/W 00000111B 0000B6H ICR06 Interrupt control register 06 W, R/W 0000B7H ICR07 Interrupt control register 07 W, R/W 0000B8H ICR08 Interrupt control register 08 W, R/W 00000111B 0000B9H ICR09 Interrupt control register 09 W, R/W 00000111B 0000BAH ICR10 Interrupt control register 10 W, R/W 00000111B 0000BBH ICR11 Interrupt control register 11 W, R/W 00000111B 0000BCH ICR12 Interrupt control register 12 W, R/W 00000111B 0000BDH ICR13 Interrupt control register 13 W, R/W 00000111B Interrupt control 00000111B 00000111B (Continued) 32 DS07-13743-5E MB90880 Series Address Register abbreviation 0000BEH ICR14 Interrupt control register 14 W, R/W 0000BFH ICR15 Interrupt control register 15 W, R/W 0000C0H CMR0 Chip select area MASK register 0 R/W 00001111B 0000C1H CAR0 Chip select area register 0 R/W 11111111B 0000C2H CMR1 Chip select area MASK register 1 R/W 00001111B 0000C3H CAR1 Chip select area register 1 R/W 11111111B 0000C4H CMR2 Chip select area MASK register 2 R/W 0000C5H CAR2 Chip select area register 2 R/W 0000C6H CMR3 Chip select area MASK register 3 R/W 00001111B 0000C7H CAR3 Chip select area register 3 R/W 11111111B 0000C8H CSCR Chip select control register R/W ----000*B 0000C9H CALR Chip select active level register R/W ----0000B Register name 0000CAH to 0000CEH R/W Resource Interrupt control Bus interface Initial value 00000111B 00000111B 00001111B 11111111B Reserved 0000CFH PLLOS 0000D0H BAPL DMA buffer address pointer (low) R/W XXXXXXXXB 0000D1H BAPM DMA buffer address pointer (middle) R/W XXXXXXXXB 0000D2H BAPH DMA buffer address pointer (high) R/W XXXXXXXXB 0000D3H DMACS DMA control register R/W 0000D4H IOAL DMAI/O register address pointer (low) R/W 0000D5H IOAH DMAI/O register address pointer (high) R/W XXXXXXXXB 0000D6H DCTL DMA data counter (low) R/W XXXXXXXXB 0000D7H DCTH DMA data counter (high) R/W XXXXXXXXB 00000000B 0000D8H to 0000DFH PLL output selection register W PLL DMAC ------X0B XXXXXXXXB XXXXXXXXB Reserved 0000E0H ENIR0 Interrupt/DTP enable register 0 R/W 0000E1H EIRR0 Interrupt/DTP source register 0 R/W Request level setting register 0 R/W Request level setting register 0 R/W 00000000B 00000000B 0000E2H 0000E3H ELVR0 0000E4H ENIR1 Interrupt/DTP enable register 1 R/W 0000E5H EIRR1 Interrupt/DTP source register 1 R/W Request level setting register 1 R/W Request level setting register 1 R/W 0000E6H 0000E7H ELVR1 DTP / external interrupt DTP / external interrupt XXXXXXXXB 00000000B XXXXXXXXB 00000000B 00000000B (Continued) DS07-13743-5E 33 MB90880 Series Address Register abbreviation 0000E8H ENIR2 Interrupt/DTP enable register 2 R/W 0000E9H EIRR2 Interrupt/DTP source register 2 R/W Request level setting register 2 R/W Request level setting register 2 R/W 0000EAH 0000EBH ELVR2 Register name R/W Resource XXXX0000B DTP / external interrupt Reserved 0000F0H to 0000FFH External area 000100H to 00017FH RAM area/extended intelligent I/O service (EI2OS) 000180H to #H* RAM area PCNTL0 PPG0 lower control status register R/W 007901H PCNTH0 PPG0 higher control status register R/W 007902H PCNTL1 PPG1 lower control status register R/W 007903H PCNTH1 PPG1 higher control status register R/W 007904H PCNTL2 PPG2 lower control status register R/W 007905H PCNTH2 PPG2 higher control status register R/W 007906H PCNTL3 PPG3 lower control status register R/W 007907H PCNTH3 PPG3 higher control status register R/W 007908H PCNTL4 PPG4 lower control status register R/W 007909H PCNTH4 PPG4 higher control status register R/W 00790AH PCNTL5 PPG5 lower control status register R/W 00790BH PCNTH5 PPG5 higher control status register R/W 00790CH PCNTL6 PPG6 lower control status register R/W 00790DH PCNTH6 PPG6 higher control status register R/W 00790EH PCNTL7 PPG7 lower control status register R/W 00790FH PCNTH7 PPG7 higher control status register R/W 007910H PPGDIV PPG0 output division setting register R/W 007911H XXXXXXXXB 00000000B 00000000B 0000ECH to 0000EFH 007900H Initial value 16-bit PPG0 16-bit PPG1 16-bit PPG2 16-bit PPG3 16-bit PPG4 16-bit PPG5 16-bit PPG6 16-bit PPG7 16-bit PPG0 00000000B 00000001B 00000000B 00000001B 00000000B 00000001B 00000000B 00000001B 00000000B 00000001B 00000000B 00000001B 00000000B 00000001B 00000000B 00000001B 11111100B Reserved 007912H PDCRL0 007913H PDCRH0 007914H PCSRL0 007915H PCSRH0 PPG0 down counter register 11111111B R 16-bit PPG0 PPG0 period setting register W 11111111B 11111111B 11111111B (Continued) 34 DS07-13743-5E MB90880 Series Address Register abbreviation 007916H PUDUTL0 007917H PUDUTH0 Register name PPG0 duty setting register 007918H Disabled 007919H Disabled 00791AH PDCRL1 00791BH PDCRH1 00791CH PCSRL1 00791DH PCSRH1 00791EH PUDUTL1 00791FH PUDUTH1 W PPG1 duty setting register W Disabled PDCRH2 007924H PCSRL2 007925H PCSRH2 007926H PUDUTL2 007927H PUDUTH2 PPG2 down counter register R PPG2 period setting register W PPG2 duty setting register W 007928H Disabled 007929H Disabled 00792AH PDCRL3 00792BH PDCRH3 00792CH PCSRL3 00792DH PCSRH3 00792EH PUDUTL3 00792FH PUDUTH3 PPG3 down counter register R PPG3 period setting register W PPG3 duty setting register W 007930H Disabled 007931H Disabled 007932H PDCRL4 007933H PDCRH4 007934H PCSRL4 007935H PCSRH4 007936H PUDUTL4 007937H PUDUTH4 16-bit PPG0 PPG1 period setting register 007921H 007923H W R Disabled PDCRL2 Resource PPG1 down counter register 007920H 007922H R/W PPG4 down counter register R PPG4 period setting register W PPG4 duty setting register W Initial value 00000000B 00000000B 11111111B 11111111B 16-bit PPG1 11111111B 11111111B 00000000B 00000000B 11111111B 11111111B 16-bit PPG2 11111111B 11111111B 00000000B 00000000B 11111111B 11111111B 16-bit PPG3 11111111B 11111111B 00000000B 00000000B 11111111B 11111111B 16-bit PPG4 11111111B 11111111B 00000000B 00000000B (Continued) DS07-13743-5E 35 MB90880 Series Address Register abbreviation Register name R/W 007938H Disabled 007939H Disabled 00793AH PDCRL5 00793BH PDCRH5 00793CH PCSRL5 00793DH PCSRH5 00793EH PUDUTL5 00793FH PUDUTH5 PPG5 down counter register R PPG5 period setting register W PPG5 duty setting register W 007940H Disabled 007941H Disabled 007942H PDCRL6 007943H PDCRH6 007944H PCSRL6 007945H PCSRH6 007946H PUDUTL6 007947H PUDUTH6 PPG6 down counter register R PPG6 period setting register W PPG6 duty setting register W 007948H Disabled 007949H Disabled 00794AH PDCRL7 00794BH PDCRH7 00794CH PCSRL7 00794DH PCSRH7 00794EH PUDUTL7 00794FH PUDUTH7 PPG7 down counter register R PPG7 period setting register W PPG7 duty setting register W 007950H Disabled 007951H Disabled 007952H 007953H 007954H TMCR0 Timer control register ch.0 R/W STC0 Status control register ch.0 R/W 007955H Resource 11111111B 11111111B 16-bit PPG5 11111111B 11111111B 00000000B 00000000B 11111111B 11111111B 16-bit PPG6 11111111B 11111111B 00000000B 00000000B 11111111B 11111111B 16-bit PPG7 11111111B 11111111B 00000000B 00000000B 00000000B Base timer ch.0 00000000B 00000000B Disabled 007956H TMR0 007957H Initial value Timer register ch.0 R/W Base timer ch.0 00000000B/ XXXXXXXXB 00000000B/ XXXXXXXXB (Continued) 36 DS07-13743-5E MB90880 Series Address 007958H 007959H 00795AH 00795BH 00795CH 00795DH 00795EH Register abbreviation PCSR0/ PRLL0 Register name R/W Period/L-width setting register ch.0 Resource XXXXXXXXB R/W XXXXXXXXB Base timer ch.0 PDUT0/ PRLH0/ DTBF0 Duty/H-width/data buffer register ch.0 R/W TMCR1 Timer control register ch.1 R/W STC1 Status control register ch.1 R/W 00795FH 00000000B Base timer ch.1 Disabled TMR1 007964H 007965H 007966H 007967H 007968H Timer register ch.1 R/W PCSR1/ PRLL1 Period/L-width setting register ch.1 R/W PDUT1/ PRLH1/ DTBF1 Duty/H-width/data buffer register ch.1 R/W TMCR2 Timer control register ch.2 R/W STC2 Status control register ch.2 R/W 007969H 00000000B/ XXXXXXXXB 00000000B/ XXXXXXXXB Base timer ch.1 00000000B Base timer ch.2 00796FH 007970H 007971H 007972H 00000000B 00000000B Disabled TMR2 00796EH XXXXXXXXB XXXXXXXXB/ 00000000B 00000000B/ XXXXXXXXB Timer register ch.2 R/W Period/L-width setting register ch.2 R/W 00000000B/ XXXXXXXXB 00796BH 00796DH XXXXXXXXB XXXXXXXXB/ 00000000B 00796AH 00796CH 00000000B 00000000B 007961H 007963H XXXXXXXXB/ 00000000B XXXXXXXXB/ 00000000B 007960H 007962H Initial value PCSR2/ PRLL2 PDUT2/ PRLH2/ DTBF2 Duty/H-width/data buffer register ch.2 R/W TMCR3 Timer control register ch.3 R/W STC3 Status control register ch.3 R/W Base timer ch.2 XXXXXXXXB XXXXXXXXB XXXXXXXXB/ 00000000B XXXXXXXXB/ 00000000B 00000000B Base timer ch.3 00000000B 00000000B (Continued) DS07-13743-5E 37 MB90880 Series Address Register abbreviation Register name R/W 007973H Resource Disabled 00000000B/ XXXXXXXXB 007974H TMR3 Timer register ch.3 R/W Period/L-width setting register ch.3 R/W 00000000B/ XXXXXXXXB 007975H 007976H 007977H 007978H Initial value PCSR3/ PRLL3 Base timer ch.3 XXXXXXXXB XXXXXXXXB XXXXXXXXB/ 00000000B Duty/H-width/data buffer register ch.3 007979H PDUT3/ PRLH3/ DTBF3 00797AH UDCR0 Up-down count register (ch.0) R 00000000B 00797BH UDCR1 Up-down count register (ch.1) R 00000000B 00797CH RCR0 Reload/compare register (ch.0) W 00000000B 00797DH RCR1 Reload/compare register (ch.1) W R/W XXXXXXXXB/ 00000000B 00000000B 8/16-bit up-down counter/timer 00797EH CCRL0 Lower counter control register (ch.0) W, R/W 00797FH CCRH0 Higher counter control register (ch.0) R/W 00000000B 007980H CCRL1 Lower counter control register (ch.1) W, R/W XX00X000B 007981H CCRH1 Higher counter control register (ch.1) R/W -0000000B 007982H CSR0 R, R/W 00000000B Counter status register (ch.0) 007983H 007984H Reserved CSR1 Counter status register (ch.1) 007985H to 00798FH 007990H XX00X000B R, R/W 8/16-bit up-down counter/timer 00000000B Reserved SMR6 007991H SCR6/IBCR6 Serial bus mode register ch.6 R/W $$$$$$$$B Serial bus control register / I2C bus control register ch.6 R/W $$$$$$$$B Extended communication control register / I2C bus status register ch.6 R/W $$$$$$$$B Serial status register ch.6 R/W 007992H ESCR6/ IBSR6 007993H SSR6 007994H RDR06/ TDR06 Transmission/reception data register 0 ch.6 R,W $$$$$$$$B 007995H RDR16/ TDR16 Transmission/reception data register 1 ch.6 R,W $$$$$$$$B 007996H BGR06 Baud rate generator register 0 ch.6 R/W $$$$$$$$B 007997H BGR16 Baud rate generator register 1 ch.6 R/W $$$$$$$$B Multi-function serial ch.6 $$$$$$$$B (Continued) 38 DS07-13743-5E MB90880 Series Address Register abbreviation 007998H ISBA6 007999H Register name R/W Resource Initial value 7-bit slave address register ch.6 R/W 00000000B ISMK6 7-bit slave address mask register ch.6 R/W Multi-function serial ch.6 00799AH PAFSR PPG pin assignment switching register R/W PPG pin switching control ----0000B 00799BH PMSSR PPG multi-channel start register R/W PPG multi-start control 00000000B R/W Multi-function serial pin control -----000B 00799CH 00799DH 01111111B Reserved P9FSR Serial pin switching register 1 00799CH to 0079A1H Reserved 0079A2H P7FSR Serial pin switching register 0 R/W Multi-function serial pin control ----000XB 0079A3H LSYNS LIN SYNCH FIELD switching register R/W Input capture input control 10001000B 0079A4H, 0079A5H Reserved 0079A6H FWR0 Flash memory write control register 0 R/W 0079A7H FWR1 Flash memory write control register 1 R/W 0079A8H to 0079DFH Detection address register 0 (low) PADR0 Detection address register 0 (middle) 0079E2H Detection address register 0 (high) 0079E3H Detection address register 1 (low) 0079E4H PADR1 Detection address register 1 (middle) 0079E5H Detection address register 1 (high) 0079E6H Detection address register 2 (low) 0079E7H PADR2 0079E8H 00000000B Detection address register 2 (middle) XXXXXXXXB R/W Address match detection function XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W Address match detection function XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W Address match detection function Detection address register 2 (high) 0079E9H to 0079EFH XXXXXXXXB XXXXXXXXB Reserved Detection address register 3 (low) 0079F0H 0079F1H 00000000B Reserved 0079E0H 0079E1H Flash memory I/F PADR3 0079F2H Detection address register 3 (middle) Detection address register 3 (high) XXXXXXXXB R/W Address match detection function XXXXXXXXB XXXXXXXXB (Continued) DS07-13743-5E 39 MB90880 Series (Continued) Address Register abbreviation 0079F3H 0079F4H Register name Resource R/W Address match detection function Detection address register 4 (low) PADR4 Detection address register 4 (middle) 0079F5H Detection address register 4 (high) 0079F6H Detection address register 5 (low) 0079F7H R/W PADR5 0079F8H 0079F9H to 007FFFH Detection address register 5 (middle) Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W Address match detection function Detection address register 5 (high) XXXXXXXXB XXXXXXXXB Reserved Explanation on R/W R/W : Readable/Writable R : Read only W : Write only Explanation on initial value 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. : This bit is not used. * : The initial value of this bit is “1” or “0”. It varies depending on the mode pin (MD2, MD1 or MD0 pin) . + : The initial value of this bit is “1” or “0”. $ : The initial value of this bit varies depending on the operation mode of the resource. #H* : Varies depending on the RAM area of the device. 40 DS07-13743-5E MB90880 Series ■ INTERRUPT SOURCES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS Interrupt source μDMAC Clearing channel of EI2OS no. Interrupt vector Interrupt control register No. Address No. Address Reset × ⎯ #08 FFFFDCH ⎯ ⎯ INT9 instruction × ⎯ #09 FFFFD8H ⎯ ⎯ Exception × ⎯ #10 FFFFD4H ⎯ ⎯ INT0 (IRQ0/1) 0 #11 FFFFD0H INT0 (IRQ2 to IRQ7) ⎯ #12 FFFFCCH ICR00 0000B0H INT0 (IRQ8 to IRQ15) ⎯ #13 FFFFC8H INT0 (IRQ16 to IRQ23) ⎯ #14 FFFFC4H ICR01 0000B1H Base timer ch.0 (source 0,1) 1 #15 FFFFC0H Base timer ch.1 (source 0,1) 2 #16 FFFFBCH ICR02 0000B2H Base timer ch.2 (source 0,1) 3 #17 FFFFB8H Base timer ch.3 (source 0,1) 4 #18 FFFFB4H ICR03 0000B3H PPG0/PPG4 counter borrow 5 #19 FFFFB0H PPG1/PPG5 counter borrow 6 #20 FFFFACH ICR04 0000B4H PPG2/PPG6 counter borrow 7 #21 FFFFA8H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH PPG3/PPG7 counter borrow × 8 #22 FFFFA4H 8/16-bit up-down counter/timer (ch.0/1) compare / underflow / overflow / up-down inversion × ⎯ #23 FFFFA0H Input capture retrieval (ch.0/1) ⎯ #24 FFFF9CH Output compare (ch.0/1/2) match ⎯ #25 FFFF98H Output compare (ch.3/4/5) match ⎯ #26 FFFF94H A/D converter ⎯ #27 FFFF90H Overflow in 16-bit free-run timer / compare clear / multi-function serial ch.4/5/6 status 9 #28 FFFF8CH Multi-function serial ch.4 reception 10 #29 FFFF88H Multi-function serial ch.4 transmission 11 #30 FFFF84H Multi-function serial ch.5 reception 12 #31 FFFF80H Multi-function serial ch.5 transmission 13 #32 FFFF7CH Multi-function serial ch.6 reception 14 #33 FFFF78H Multi-function serial ch.6 transmission 15 #34 FFFF74H Multi-function serial ch.0/1 reception / status ⎯ #35 FFFF70H Multi-function serial ch.0/1 transmission ⎯ #36 FFFF6CH Multi-function serial ch.2 reception / status ⎯ #37 FFFF68H Multi-function serial ch.2 transmission ⎯ #38 FFFF64H (Continued) DS07-13743-5E 41 MB90880 Series (Continued) Interrupt source μDMAC Clearing channel 2 of EI OS no. Interrupt vector No. Address Multi-function serial ch.3 reception / status ⎯ #39 FFFF60H Multi-function serial ch.3 transmission ⎯ #40 FFFF5CH Flash writing/deletion, time base timer, watch timer* × ⎯ #41 FFFF58H Delayed interrupt generation module × ⎯ #42 FFFF54H × Interrupt control register No. Address ICR14 0000BEH ICR15 0000BFH : The interrupt request flag is not cleared by the interrupt clear signal. : The interrupt request flag is cleared by the interrupt clear signal. : The interrupt request flag is cleared by the interrupt clear signal. Stop request function provided at receiving only. * : Flash writing/deletion, the time base timer and watch timer cannot be used simultaneously. Note : If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the EI2OS/μDMAC interrupt clear signal. Therefore, when either of the two sources for the EI2OS/ μDMAC function is used, the other interrupt function can not be used. In this case, set the interrupt request enable bit to “0” in the appropriate resource and take measures by software polling. 42 DS07-13743-5E MB90880 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute maximum ratings Parameter Symbol Rating Unit Remarks Min Max VCC VSS − 0.3 VSS + 4.0 V DVCC VSS − 0.3 VSS + 4.0 V DVcc = Vcc*2 AVCC VSS − 0.3 VSS + 4.0 V *2 AVRH VSS − 0.3 VSS + 4.0 V *2 VSS − 0.3 VSS + 4.0 V *3 VSS − 0.3 VSS + 7.0 V *3, *8 VSS − 0.3 VSS + 4.0 V *3 VSS − 0.3 VSS + 7.0 V *3, *8 ICLAMP − 2.0 +2.0 mA *7 Total maximum clamp current Σ⏐ICLAMP⏐ ⎯ 20 mA *7 “L” level maximum output current IOL1 ⎯ 10 mA *4 IOL2 ⎯ 20 mA PA0 to PA3*4 IOLAV1 ⎯ 3 mA *5 IOLAV2 ⎯ 10 mA PA0 to PA3*5 ΣIOL1 ⎯ 60 mA ΣIOL2 ⎯ 80 mA PA0 to PA3 ΣIOLAV1 ⎯ 30 mA *6 ΣIOLAV2 ⎯ 40 mA PA0 to PA3*6 IOH1 ⎯ −10 mA *4 IOH2 ⎯ −20 mA PA0 to PA3*4 IOHAV1 ⎯ −3 mA *5 IOHAV2 ⎯ −10 mA PA0 to PA3*5 ΣIOH1 ⎯ −60 mA ΣIOH2 ⎯ −80 mA PA0 to PA3 ΣIOHAV1 ⎯ −30 mA *6 ΣIOHAV2 ⎯ −40 mA PA0 to PA3*6 Power consumption PD ⎯ 320 mW Operating temperature TA −40 +85 °C Tstg −55 +150 °C Power supply voltage*1 Input voltage*1 VI Output voltage*1 VO Maximum clamp current “L” level average output current “L” level maximum total output current “L” level average total output current “H” level maximum output current “H” level average output current “H” level maximum total output current “H” level average total output current Storage temperature *1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V. *2 : Set AVCC, DVCC and AVRH to the same voltage. AVCC and DVCC must not exceed VCC. Also, AVRH must not exceed AVCC. *3 : VI and VO must not exceed 0.3V. When the maximum current to/from an input is limited by using an external component, the ICLAMP rating supersedes the VI rating. *4 : The maximum output current is defined as the peak value of the current of any one of the corresponding pins. (Continued) DS07-13743-5E 43 MB90880 Series (Continued) *5 : The average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins. *6 : The average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins. *7 : • Relevant pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P76, P80 to P87, P90 to P97, PA0 to PA3 • Use within recommended operating conditions. • Use with DC voltage (current) . • The + B signal should always be applied with a limiting resistance placed between the + B signal and the microcontroller. • Set the limiting resistor value, whether instantaneous or stationary, so that the current to be input to the microcontroller pin does not exceed the rating during the input of the + B signal. • Note that when the microcontroller drive current is low, such as in the power saving modes, the + B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a + B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the + B input pin open. • Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept + B signal input. • Sample recommended circuit : • Input/Output equivalent circuit Protective diode VCC Limiting resistance P-ch + B input (0V to 16V) N-ch R *8 : P74 to P76 and P80 to P87 can be used as 5V I/F pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed any of these ratings. 44 DS07-13743-5E MB90880 Series 2. Recommended operating conditions (VSS = AVSS = 0.0 V) Parameter Power supply voltage “H” level input voltage “L” level input voltage Symbol Value Unit Remarks Min Max VCC DVcc 2.7 3.6 V In normal operation 1.8 3.6 V Hold stop status VIH 0.7 VCC VCC + 0.3 V All pins other than VIH2, VIHS, VIHM and VIHX VIH2 0.7 VCC VSS + 5.8 V P74 to P76, P80 to P87 VIHS 0.8 VCC VCC + 0.3 V Hysteresis input pins VIHS2 0.7 VCC VCC + 0.3 V Hysteresis input pins (multi-function serial pins) VIHS3 0.7 VCC VCC + 0.3 V CMOS input pins (external bus mode input pins) VIHM VCC − 0.3 VCC + 0.3 V MD pin input VIHX 0.8 VCC VCC + 0.3 V X0A and X1A pins VIL VSS − 0.3 0.3 VCC V All pins other than VILS, VILM and VIHX VILS VSS − 0.3 0.2 VCC V Hysteresis input pins VILS2 VSS − 0.3 0.3 VCC V Hysteresis input pins (multi-function serial pins) VILS3 VSS − 0.3 0.3 VCC V CMOS input pins (external bus mode pins) VILM VSS − 0.3 VSS + 0.3 V MD pin input VILX VSS − 0.3 0.2 Vcc V X0A and X1A pins Smoothing capacitor CS Operating temperature TA 0.1 1.0 μF Use a ceramic capacitor or comparable capacitor of the AC characteristics. Bypass capacitor at the VCC pin should be greater than this capacitor. −40 +85 °C In ordinary operation. 0 +70 °C When external bus is in operation. • C Pin Connection Diagram C CS DS07-13743-5E 45 MB90880 Series WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 46 DS07-13743-5E MB90880 Series 3. DC characteristics (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol “H” level output voltage “L” level output voltage VOH VOL Input leak current Pull-up resistance Pull-down resistance Open-drain output current IIL RPULL RDOWN Ileak Pin name Conditions Value Min Typ Max Unit Remarks All pins except P74 to P76, P80 to P87 and PA0 to PA3 VCC = 3.0 V, IOH = −4.0 mA VCC − 0.5 ⎯ ⎯ V P74 to P76, P80 to P87 VCC = 3.0 V, IOH = −2.0 mA VCC − 0.5 ⎯ ⎯ V PA0 to PA3 DVCC = 3.0 V, IOH = −10.0 mA DVCC − 0.6 ⎯ ⎯ V All pins except P74 to P76, P80 to P87 and PA0 to PA3 VCC = 3.0 V, IOL = 4.0 mA ⎯ ⎯ 0.4 V P74 to P76, P80 to P87 VCC = 3.0 V, IOH = −2.0 mA ⎯ ⎯ 0.4 V PA0 to PA3 DVCC = 3.0 V, IOL = 10.0 mA ⎯ ⎯ 0.5 V All input pins VCC = 3.3 V, VSS < VI < VCC −10 ⎯ +10 μA 25 50 100 kΩ Evaluation product ⎯ MD2 P31, P32, P34, P35, P43, P44, P46, P47, P72 to P76, P80 to P87, P96, P97 15 33 66 kΩ Flash memory product / MASK ROM product 25 50 100 kΩ Evaluation product 40 100 200 kΩ MASK ROM product ⎯ 0.1 10 μA ⎯ ⎯ ⎯ (Continued) DS07-13743-5E 47 MB90880 Series (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Conditions VCC = 3.3 V, Internal 25 MHz operation at normal operation Power supply current ICC ⎯ VCC = 3.3 V, Internal 33 MHz operation at normal operation VCC = 3.3 V, Internal 25 MHz operation, flash write VCC = 3.3 V, Internal 33 MHz operation, flash write Value Unit Remarks Min Typ Max ⎯ 15 23 mA MB90882(S) ⎯ 20 28 mA MB90F882A(S) ⎯ 27 37 mA MB90F883C(S), MB90F884C(S) ⎯ 30 40 mA MB90F883B(S)/BH(S), MB90F884B(S)/BH(S) ⎯ 22 30 mA MB90882(S) ⎯ 28 38 mA MB90F882A(S) ⎯ 35 45 mA MB90F883C(S), MB90F884C(S) ⎯ 40 52 mA MB90F883BH(S), MB90F884BH(S) ⎯ 30 40 mA MB90F882A(S) ⎯ 37 47 mA MB90F883C(S), MB90F884C(S) ⎯ 40 50 mA MB90F883B(S)/BH(S), MB90F884B(S)/BH(S) ⎯ 40 52 mA MB90F882A(S) ⎯ 45 57 mA MB90F883C(S), MB90F884C(S) ⎯ 50 62 mA MB90F883BH(S), MB90F884BH(S) (Continued) 48 DS07-13743-5E MB90880 Series (Continued) Parameter Symbol Value Unit Typ Max VCC = 3.3 V, Internal 25 MHz operation, sleep mode ⎯ 6 12 mA VCC = 3.3 V, Internal 33 MHz operation, sleep mode ⎯ 10 20 mA ⎯ VCC = 3.3 V, Internal 2 MHz, operation, Time-base timer ⎯ 0.25 0.9 mA ⎯ VCC = 3.3 V, External 32 kHz, internal 8 kHz operation, sub-operation (TA = + 25 °C) ⎯ 80 200 μA ⎯ VCC = 3.3 V, External 32 kHz, Internal 8 kHz operation, sub sleep mode (TA = + 25 °C) ⎯ 50 160 μA ICCT ⎯ VCC = 3.3 V, External 32 kHz, internal 8 kHz operation, watch operation (TA = + 25 °C) ⎯ 20 110 μA ICCH ⎯ TA = + 25 °C, Stop mode, VCC = 3.3 V ⎯ 15 100 μA ⎯ 5 15 pF ICTS ICCL ICCLS Input capacitance Conditions Min ICCS Power supply current Pin name CIN ⎯ All pins except AVCC, AVSS, AVCC, AVSS, VCC, DVCC, VSS, VCC, DVCC, DVSS VSS, DVSS Remarks Note : P74 to P76 and P80 to P87 are N-ch open-drain pins with controls and normally used at the CMOS level. DS07-13743-5E 49 MB90880 Series 4. AC characteristics (1) Clock timing ratings (VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name FCH Clock frequency Clock cycle time Input clock pulse width Input clock rise/fall time Internal operating clock frequency Internal operating clock cycle time X0, X1 Value Conditions Min Typ Max ⎯ 3 ⎯ 25 External crystal oscillation ⎯ 3 ⎯ 50 External clock input ⎯ 4 ⎯ 25 ⎯ 3 ⎯ 16.5 ⎯ 3 ⎯ 11 ⎯ 3 ⎯ 8.25 Unit Remarks PLL1 multiplication MHz PLL2 multiplication PLL3 multiplication PLL4 multiplication ⎯ 3 ⎯ 5.5 PLL6 multiplication ⎯ 3 ⎯ 4.125 PLL8 multiplication FCL X0A, X1A ⎯ ⎯ 32.768 ⎯ kHz tC X0, X1 ⎯ 20 ⎯ 333 ns *1 tCL X0A, X1A ⎯ ⎯ 30.5 ⎯ μs PWH PWL X0 ⎯ 5 ⎯ ⎯ ns PWLH PWLL X0A ⎯ ⎯ 15.2 ⎯ μs *2 tcr tcf X0 ⎯ ⎯ ⎯ 5 ns External clock in use fCP ⎯ ⎯ 1.5 ⎯ 33 MHz *1 fCPL ⎯ ⎯ ⎯ 8.192 ⎯ kHz tCP ⎯ ⎯ 30.3 ⎯ 666 ns tCPL ⎯ ⎯ ⎯ 122.1 ⎯ μs *1 *1 : The maximum operating frequency is 25 MHz in MB90F883B (S), MB90F884B (S). The maximum operating frequency is 25 MHz in all models when external bus is in operation. *2 : Input it at a duty ratio of 50% ±3%. • X0, X1 clock timing tC 0.8 VCC X0 0.2 VCC PWH PWL tcf tcr • X0A, X1A clock timing tCL 0.8 VCC X0A 0.2 VCC PWLH PWLL tcf 50 tcr DS07-13743-5E MB90880 Series • PLL warranted operating range Internal operating clock frequency vs. Supply voltage 3.6 Supply voltage VCC (V) PLL warranted operating range 3.0 2.7 Normal operating range 1.5 16 4 33 Internal clock fCP (MHz) * * : The maximum operating frequency of MB90F883B(S),MB90F884B(S) is 25 MHz. Notes: • Use the fCP at 4 MHz or higher only for PLL1 multiplication. • For A/D operating frequencies, refer to “5. A/D Converter electrical characteristics”. Source oscillator frequency vs. Internal operating clock frequency 33 Internal clock fCP (MHz) * 8 Multiplication 25 24 3 Multiplication 6 Multiplication No multiplication 2 Multiplication 20 18 16 12 1 Multiplication 4 Multiplication 9 8 6 4 1.5 3 4 5 6 8 10 12.5 16 20 25 32 40 50 Source oscillator clock FCH (MHz) * : The maximum operating frequency of MB90F883B(S),MB90F884B(S) is 25 MHz. Setting correspondence for the registers PLLOS, CKSCR between the PLL multiple and the source oscillator clock/internal clock frequencies PLL multiple DIV2 PLL2 CS1 CS0 Source oscillator clock Internal clock 1 1 2 2 2 2 3 3 4 4 4 6 8 0 1 0 0 1 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 4 MHz to 25 MHz 8 MHz to 25 MHz 3 MHz to 12.5 MHz 4 MHz to 16.5 MHz 6 MHz to 12.5 MHz 6 MHz to 16.5 MHz 3 MHz to 8.33 MHz 6 MHz to 11 MHz 3 MHz to 6.25 MHz 3 MHz to 8.25 MHz 6 MHz to 8.25 MHz 3 MHz to 5.5 MHz 3 MHz to 4.125 MHz 4 MHz to 25 MHz 8 MHz to 25 MHz 6 MHz to 25 MHz 8 MHz to 33 MHz 12 MHz to 25 MHz 12 MHz to 33 MHz 9 MHz to 25 MHz 18 MHz to 33 MHz 12 MHz to 25 MHz 12 MHz to 33 MHz 24 MHz to 33 MHz 18 MHz to 33 MHz 24 MHz to 33 MHz DS07-13743-5E 51 MB90880 Series AC characteristics are determined using the following measurement reference voltage values. • Input signal waveform Hysteresis input pins • Output signal waveform Output pins 0.8 VCC 2.4 V 0.2 VCC 0.8 V Pins other than hysteresis input/MD input pins 0.7 VCC 0.3 VCC 52 DS07-13743-5E MB90880 Series (2) Clock output timing (VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Cycle time CLK↑ → CLK↓ Symbol Pin name Conditions tCYC CLK ⎯ tCHCL CLK Value Min Max tCP* ⎯ Unit Remarks ns VCC = 3.0 V to 3.6 V tCP* / 2 − 15 tCP* / 2 + 15 ns fCP = 25 MHz VCC = 2.7 V to 3.3 V tCP* / 2 − 20 tCP* / 2 + 20 ns fCP = 16 MHz VCC = 2.7 V to 3.3 V tCP* / 2 − 64 tCP* / 2 + 64 ns fCP = 5 MHz * : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. tCYC tCHCL 2.4 V CLK DS07-13743-5E 2.4 V 0.8 V 53 MB90880 Series (3) Reset input ratings (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Reset input time Symbol tRSTL Pin name Value Conditions ⎯ RST Min Max 16 tCP*1 ⎯ Unit Remarks ns In normal operation Oscillator oscillation time*2 + 100 μs + 16 tCP*1 ⎯ ms In sub clock, sub-sleep, watch and stop modes 100 ⎯ μs In time base timer mode *1 : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. *2 : Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several tens of ms; for a ceramic oscillator, this is several hundred ms to a few ms, and for an external clock this is 0 ms. • In sub clock, sub-sleep, watch and stop modes tRSTL RST 0.2 VCC 0.2 VCC 90% of amplitude X0 Internal operation clock 100 μs + 16 tCP Oscillator oscillation time Internal reset Oscillation stabilization wait time Execution of instruction • Measurement conditions for AC ratings CL : Load capacitance applied to pin during testing Pin CL 54 CLK, ALE : CL = 30 pF AD15 to AD00 (Address, data bus) , RD, WR, A23 to A00/D15 to D00 : CL = 30 pF DS07-13743-5E MB90880 Series (4) Power-on ratings (Power-on reset) (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Power rise time Power cutoff time tR VCC tOFF VCC Conditions ⎯ Value Unit Remarks Min Max 0.05 30 ms * 1 ⎯ ms For continuous operation * : During the power rise time, VCC must be less than 0.2V. Notes : • The above ratings are values used for power-on reset. • A power-on reset should be applied by restarting the power supply inside the device. tR 2.7 V VCC 0.2 V 0.2 V 0.2 V tOFF A sudden change in the supply voltage may activate a power-on reset. As shown in the following figure, it is recommended to apply a smooth voltage rise with suppressed fluctuation when changing the supply voltage during operation. Main power voltage VCC Sub supply voltage VSS DS07-13743-5E RAM data held A rise slope of 50mV/ms or less is recommended. 55 MB90880 Series (5) Bus read timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C, fcp ≤ 25 MHz) Parameter ALE pulse width Symbol Pin name tLHLL ALE Conditions ⎯ Value Unit Remarks ⎯ ns 16 MHz < fCP ≤ 25 MHz tCP* / 2 − 20 ⎯ ns 8 MHz < fCP ≤ 16 MHz tCP* / 2 − 35 ⎯ ns fCP ≤ 8 MHz tCP* / 2 − 17 ⎯ ns tCP* / 2 − 40 ⎯ ns Min Max tCP* / 2 − 15 Valid address → ALE↓ time tAVLL Address, ALE ⎯ ALE ↓ → valid address time tLLAX ALE, address ⎯ tCP* / 2 − 15 ⎯ ns valid address → RD↓ Time tAVRL RD, address ⎯ tCP* − 25 ⎯ ns Valid address → valid data input tAVDV Address / data ⎯ ⎯ 5 tCP* / 2 − 55 ns ⎯ 5 tCP* / 2 − 80 ns fCP ≤ 8 MHz 3 tCP* / 2 − 25 ⎯ ns 16 MHz < fCP ≤ 25 MHz 3 tCP* / 2 − 20 ⎯ ns 8 MHz < fCP ≤ 16 MHz ⎯ 3 tCP* / 2 − 55 ns ⎯ 3 tCP* / 2 − 80 ns RD pulse width tRLRH RD ⎯ RD↓ → valid data input tRLDV RD, data ⎯ RD↑→ data hold time tRHDX RD, data ⎯ 0 ⎯ ns RD↑ → ALE↑ time tRHLH RD, ALE ⎯ tCP* / 2 − 15 ⎯ ns RD↑ → valid address time tRHAX Address, RD ⎯ tCP* / 2 − 10 ⎯ ns Valid address → CLK↑ time tAVCH Address, CLK ⎯ tCP* / 2 − 17 ⎯ ns RD↓ → CLK↑ time tRLCH RD, CLK ⎯ tCP* / 2 − 17 ⎯ ns ALE↓ → RD↓ time tLLRL RD, ALE ⎯ tCP* / 2 − 15 ⎯ ns fCP ≤ 8 MHz fCP ≤ 8 MHz * : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. 56 DS07-13743-5E MB90880 Series tAVCH tRLCH 2.4 V 2.4 V CLK tRHLH ALE 2.4 V 2.4 V tLHLL 2.4 V 0.8 V tRLRH 2.4 V RD tAVLL tLLAX 0.8 V tLLRL Multiplex mode tAVRL A23 to A16 tRLDV tRHAX 2.4 V 2.4 V 0.8 V 0.8 V tAVDV 2.4 V 2.4 V tRHDX 0.7 VCC 0.8 V 0.8 V 0.7 VCC Read data Address AD15 to AD00 0.3 VCC 0.3 VCC tRHAX Non-multiplex mode A23 to A00 2.4 V 2.4 V 0.8 V 0.8 V tRLDV tRHDX tAVDV 0.7 VCC 0.3 VCC DS07-13743-5E 0.7 VCC Read data D15 to D00 0.3 VCC 57 MB90880 Series (6) Bus write timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C, fcp ≤ 25 MHz) Parameter Valid address → WR ↓ time WR pulse width Valid data output → WR↑ time WR↑ → data hold time Value Symbol Pin name Conditions Min Max tAVWL Address, WR ⎯ tCP* − 15 ⎯ ns ⎯ 3 tCP* / 2 − 25 ⎯ ns 16 MHz < fCP ≤ 25 MHz ⎯ 3 tCP* / 2 − 20 ⎯ ns 8 MHz < fCP ≤ 16 MHz ⎯ 3 tCP* / 2 − 15 ⎯ ns ⎯ 10 ⎯ ns 16 MHz < fCP ≤ 25 MHz ⎯ 20 ⎯ ns 8 MHz < fCP ≤ 16 MHz ⎯ 30 ⎯ ns fCP ≤ 8 MHz tWLWH tDVWH tWHDX WR (WRL, WRH) Data, WR WR, data Unit WR↑ → valid address time tWHAX WR, address ⎯ tCP* / 2 − 10 ⎯ ns WR↑ → ALE↑ time tWHLH WR, ALE ⎯ tCP* / 2 − 15 ⎯ ns WR↓ → CLK↑ time tWLCH WR, CLK ⎯ tCP* / 2 − 17 ⎯ ns Remarks * : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. 58 DS07-13743-5E MB90880 Series tWLCH 2.4 V CLK tWHLH 2.4 V ALE tWLWH 2.4 V WR (WRL, WRH) 0.8 V Multiplex mode tAVWL A23 to A16 tWHAX 2.4 V 2.4 V 0.8 V 0.8 V tDVWH 2.4 V Address AD15 to AD00 2.4 V 2.4 V Write data 0.8 V 0.8 V 0.8 V tWHAX Non-multiplex mode A23 to A00 2.4 V 2.4 V 0.8 V 0.8 V tDVWH D15 to D00 DS07-13743-5E tWHDX 2.4 V 0.8 V tWHDX 2.4 V Write data 0.8 V 59 MB90880 Series (7) Ready input timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C, fcp ≤ 25 MHz) Parameter Symbol RDY setup time tRYHS RDY hold time tRYHH Pin name RDY Conditions Value Unit Min Max ⎯ 35 ⎯ ns ⎯ 70 ⎯ ns ⎯ 0 ⎯ ns 2.4 V Remarks fCP = 8 MHz 2.4 V CLK ALE RD/WR tRYHS tRYHH When RDY wait is not applied When RDY wait is applied (1 cycle) 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tRYHS 60 DS07-13743-5E MB90880 Series (8) Hold timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C, fcp ≤ 25 MHz) Parameter Symbol Pin name Pin floating → HAK↓ time tXHAL HAK HAK↓ → valid pin time tHAHV HAK Conditions ⎯ Value Unit Min Max 30 tCP* ns tCP* 2 tCP* ns * : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. Note : It takes one or more cycles from when the HRQ pin is read to when HAK changes. HAK 2.4 V 0.8 V tXHAL Pins 2.4 V 0.8 V DS07-13743-5E tHAHV High-Z 2.4 V 0.8 V 61 MB90880 Series (9) Multi-function serial timing (UART, SIO) (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Serial clock cycle time tSCYC ⎯ UCK↓ → UO delay time tSLOV ⎯ Valid UI → UCK↑ tIVSH ⎯ UCK↑ → valid UI hold time tSHIX Serial clock “H” pulse width Value Conditions Unit Min Max 4 tCP*2 ⎯ ns −50 +50 ns 50 ⎯ ns ⎯ 0 ⎯ ns tSHSL ⎯ 2 tCP*2 ⎯ ns Serial clock “L” pulse width tSLSH ⎯ 2 tCP*2 ⎯ ns UCK↓ → UO delay time tSLOV ⎯ ⎯ 50 ns Valid UI → UCK↑ tIVSH ⎯ 50 ⎯ ns UCK↑ → valid UI hold time tSHIX ⎯ 50 ⎯ ns Internal shift clock mode output pin : CL*1 = 80 pF + 1 TTL External shift clock mode output pin : CL*1 = 80 pF + 1 TTL *1 : CL is the load capacitance applied to pins during testing. *2 : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. Note : The above AC characteristics are for CLK synchronous mode operation. • Internal shift clock mode tSCYC UCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V UO 0.8 V tIVSH UI tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL UCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V UO 0.8 V tIVSH UI 62 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC DS07-13743-5E MB90880 Series (10) Multi-function serial timing (I2C) a. Master mode operation Parameter (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Conditions Standard mode High-speed mode*3 Min Max Min Max Unit SCL clock frequency fSCL 0 100 0 400 kHz SCL clock “L” width tLOW 4.7 ⎯ 1.3 ⎯ μs SCL clock “H” width tHIGH 4.0 ⎯ 0.6 ⎯ μs Bus-free time between “stop” condition and “start” condition tBUS 4.7 ⎯ 1.3 ⎯ μs 4.7 ⎯ 0.6 ⎯ μs 4.0 ⎯ 0.6 ⎯ μs Repeat “start” condition setup time SCL↑ → SDA↓ tSUSTA (Repeat) “start” condition hold time SDA↓ → SCL↓ tHDSTA “Stop” condition setup time SCL↑ → SDA↑ tSUSTO 4.0 ⎯ 0.6 ⎯ μs Data hold time SCL↓ → SDA↓↑ tHDDAT 2tcp*1 ⎯ 2tcp*1 ⎯ μs Data setup time SDA↓↑ → SCL↑ tSUDAT 250 ⎯ 100*2 ⎯ ns DS07-13743-5E R=1kΩ C=50pF*4 63 MB90880 Series b. Slave mode operation (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Conditions Standard mode High-speed mode *3 Min Max Min Max Unit SCL clock frequency fSCL 0 100 0 400 kHz SCL clock “L” width tLOW 4.7 ⎯ 1.3 ⎯ μs SCL clock “H” width tHIGH 4.0 ⎯ 0.6 ⎯ μs Bus-free time between “stop” condition and “start” condition tBUS 4.7 ⎯ 1.3 ⎯ μs 4.7 ⎯ 0.6 ⎯ μs 4.0 ⎯ 0.6 ⎯ μs Repeat “start” condition setup time SCL↑ → SDA↓ tSUSTA (Repeat) “start” condition hold time SDA↓ → SCL↓ tHDSTA “Stop” condition setup time SCL↑ → SDA↑ tSUSTO 4.0 ⎯ 0.6 ⎯ μs Data hold time SCL↓ → SDA↓↑ tHDDAT 2tcp*1 ⎯ 2tcp*1 ⎯ μs Data setup time SDA↓↑ → SCL↑ tSUDAT 250 ⎯ 100*2 ⎯ ns R=1kΩ C=50pF*4 *1 : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. *2 : The high-speed mode I2C bus device can be used in a standard mode I2C bus system. However, the device must satisfy the required condition “tSUDAT ≥ 250 ns”. If the device does not extend the “L” period of the SCL signal, the succeeding data must be output to the SDA line before a period of 1250 ns (the maximum time of SDA/SCL rise + tSUDAT) in which the SCL line is open. *3 : Set the internal operation clock to 6MHz or higher when using this over 100kHz. *4 : “R” and “C” are the pull-up resistance and load capacitance of the SCL/SDA lines. • Timing definition SDA tBUS tLOW tHDSTA tSUDAT SCL tHDSTA 64 tHIGH tHDDAT fSCL tSUSTA tSUSTO DS07-13743-5E MB90880 Series (11) Timer input timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Conditions Input pulse width tTIWH tTIWL IN0, IN1, TIO0 to TIO3 ⎯ Value Min Max 4 tCP* ⎯ Unit ns *: tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. IN0, IN1 TIO0 to TIO3 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tTIWL tTIWH (12) Timer output timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter CLK↑ → change time PPG0 to PPG7 change time OUT0 to OUT5 change time CLK PPG0 to PPG7 OUT0 to OUT5 TIO0 to TIO3 Symbol Pin name Conditions tTO PPG0 to PPG7, OUT0 to OUT5, TIO0 to TIO3 Load condition : 80 pF Value Min Max 30 ⎯ Unit ns 0.7 VCC 0.7 VCC 0.3 VCC tTO DS07-13743-5E 65 MB90880 Series (13) Trigger input timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Conditions Input pulse width tTRGH tTRGL ADTG, IRQ0 to IRQ7 ⎯ Value Unit Remarks ⎯ ns In normal operation ⎯ μs In stop mode Min Max 5 tCP* 1 *: tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. IRQ0 to IRQ7 ADTG 0.8 VCC 0.8 VCC 0.2 VCC tTRGH 66 0.2 VCC tTRGL DS07-13743-5E MB90880 Series (14) Chip select output timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C, fcp ≤ 25 MHz) Parameter Symbol Pin name Conditions Chip select output valid time → RD↓ tSVRL CS0 to CS3, RD Chip select output valid time → WR↓ tSVWL RD↑ → Chip select output valid time WR↑ → Chip select output valid time Value Unit Min Max ⎯ tCP* / 2 − 7 ⎯ ns CS0 to CS3, WRH, WRL ⎯ tCP* / 2 − 7 ⎯ ns tRHSV RD, CS0 to CS3 ⎯ tCP* / 2 − 17 ⎯ ns tWHSV WRH, WRL, CS0 to CS3 ⎯ tCP* / 2 − 17 ⎯ ns *: tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. tSVRL 2.4 V RD 0.8 V tRHSV A23 to A16 CS0 to CS3 2.4 V 0.8 V 2.4 V D15 to D00 Read data 0.8 V tSVWL tWHSV 2.4 V WRH, WRL 0.8 V D15 to D00 Undefined Write data Note : The chip select output signal changes simultaneously due to the internal bus configuration; therefore, this may generate a bus wait. AC cannot be warranted between the ALE output signal and the chip select output signal. DS07-13743-5E 67 MB90880 Series 5. A/D converter electrical characteristics (VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V ≤ AVRH, TA = −40 °C to +85 °C) Value Symbol Pin name Min Standard Max Resolution ⎯ ⎯ ⎯ ⎯ 10 bit Total error ⎯ ⎯ ⎯ ⎯ ±3.0 LSB Linear error ⎯ ⎯ ⎯ ⎯ ±2.5 LSB Differential linear error ⎯ ⎯ ⎯ ⎯ ±1.9 LSB Zero transition voltage VOT AN0 to AN19 AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB V Full-scale transition voltage VFST AN0 to AN19 AVRH − 3.5 LSB AVRH − 1.5 LSB AVRH + 0.5 LSB V Sampling time tSMP ⎯ 1.2 ⎯ ⎯ μs *1 Compare time tCMP ⎯ 1.8 ⎯ ⎯ μs *1 Conversion time tCNV ⎯ 3.0 ⎯ ⎯ μs *1 Analog port input current IAIN AN0 to AN19 − 3.0 ⎯ + 3.0 μA Analog input voltage VAIN AN0 to AN19 AVSS ⎯ AVRH V ⎯ AVRH AVSS + 2.2 ⎯ AVCC V IA AVCC ⎯ 1.9 3.7 mA IAH AVCC ⎯ ⎯ *2 5 μA Parameter Reference voltage Supply current Unit Remarks Reference voltage supply current IR AVRH ⎯ 520 720 μA IRH AVRH ⎯ ⎯ 5*2 μA Inter-channel variation ⎯ AN0 to AN19 ⎯ ⎯ 4 LSB *1 : Time per channel *2 : Current when the A/D converter is not in operation and the CPU is stopped (VCC = AVCC = AVRH = 3.0 V ) 68 DS07-13743-5E MB90880 Series • External impedance and sampling time for analog input This is an A/D converter with a sample hold function. If high external impedance is preventing it from securing sufficient sampling time, a sufficient analog voltage will not be charged in the internal sample hold capacitor, affecting the accuracy of the A/D conversion. In order to satisfy the A/D conversion accuracy specifications, adjust the register values and operating frequency or decrease the external impedance so that the sampling time becomes longer than the minimum value, based on the relationship between the external impedance and the minimum sampling time. If a sufficient sampling time cannot be secured, connect a capacitor with a capacitance of approximately 0.1 μF to the analog input pin. Model diagram of analog input circuit R Analog input Comparator C Turned on during sampling ON R C 12.2 kΩ (Max) 8.5 pF (Max) Note : These are reference values. • Relation between external impedance and minimum sampling time [External impedance = 0 kΩ to 20 kΩ] [External impedance = 0 kΩ to 100 kΩ] Flash memory device MASK ROM device 100 20 90 18 External impedance [kΩ] External impedance [kΩ] Flash memory device MASK ROM device 80 70 60 50 40 30 20 16 14 12 10 10 8 6 4 2 0 0 0 5 10 15 20 25 30 35 Minimum sampling time [μs] 0 1 2 3 4 5 6 7 8 Minimum sampling time [μs] • Errors : As | AVRH⎯AVSS | decreases, the absolute error increases. DS07-13743-5E 69 MB90880 Series 6. Definition of A/D Converter Terms Resolution Non linearity error Differential linearity error Total error : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” ) and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion characteristics. : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. : Difference between an actual value and a theoretical value. A total error includes zero transition error, full-scale transition error, and linear error. Total error 3FFH 3FEH 1.5 LSB Actual conversion characteristics Digital output 3FDH {1 LSB × (N − 1) + 0.5 LSB} 004H VNT (Actual measurement value) 003H Actual conversion characteristics 002H Ideal characteristics 001H 0.5 LSB AVSS AVRH Analog input VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVRH − AVSS 1 LSB (Ideal value) = [V] 1024 Total error of digital output “N” = [LSB] VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVRH − 1.5 LSB [V] VNT : A voltage at which digital output transits from (N − 1) H, NH. (Continued) 70 DS07-13743-5E MB90880 Series (Continued) Linearity error Differential linearity error Ideal characteristics 3FFH Actual conversion characteristics Digital output 3FDH (N + 1)H {1 LSB × (N − 1) + VOT } 004H 003H VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Digital output 3FEH Actual conversion characteristics NH V (N + 1) T (actual measurement value) (N − 1)H VNT (actual measurement value) Actual conversion characteristics 002H 001H Ideal characteristics (N − 2)H VOT (actual measurement value) AVSS AVRH AVSS AVRH Analog input Analog input Non linearity error of digital output N = Differential linearity error of digital output N = 1 LSB = VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N+1) T − VNT 1 LSB VFST − VOT 1022 [LSB] −1 LSB [LSB] [V] VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” DS07-13743-5E 71 MB90880 Series • Flash memory write/erase characteristics Parameter Conditions Unit Remarks 3.6 s Excludes internal write time before erase operation. 6.2 ⎯ s Excludes internal write time before erase operation. ⎯ 23 ⎯ μs Excludes overhead time at system level. ⎯ 10000 ⎯ ⎯ cycle Average TA = +85 °C 100000 ⎯ ⎯ h Sector erase time Chip erase time TA = +25 °C, VCC = 3.0 V Word (16-bit width) write time Number of write/erase cycles Flash memory data hold time Value Min Standard Max ⎯ 0.9 ⎯ * * : Value converted from the evaluation result of technology reliability (The Arrhenius equation is used to convert the high-temperature high-speed test result into the average temperature + 85 °C.) 72 DS07-13743-5E MB90880 Series ■ ORDERING INFORMATION Part number MB90F882APF MB90F883BPF MB90F883BHPF MB90F883CPF MB90F884BPF MB90F884BHPF MB90F884CPF MB90882PF MB90F882ASPF MB90F883BSPF MB90F883BHSPF MB90F883CSPF MB90F884BSPF MB90F884BHSPF MB90F884CSPF MB90882SPF MB90F882APMC MB90F883BPMC MB90F883BHPMC MB90F883CPMC MB90F884BPMC MB90F884BHPMC MB90F884CPMC MB90882PMC MB90F882SPMC MB90F882ASPMC MB90F883BSPMC MB90F883BHSPMC MB90F883CSPMC MB90F884BSPMC MB90F884BHSPMC MB90F884CSPMC MB90882SPMC MB90V880A-101CR-ES MB90V880A-102CR-ES DS07-13743-5E Package Remarks 100-pin plastic QFP (FPT-100P-M06) Products with S-suffix: Single clock product (without sub clock) Products without S-suffix: Dual clock product (with sub clock) 100-pin plastic LQFP (FPT-100P-M20) Products with S-suffix: Single clock product (without sub clock) Products without S-suffix: Dual clock product (with sub clock) 299-pin ceramic PGA (PGA-299C-A01) Evaluation product 101 : Single clock product (without sub clock) 102 : Dual clock product (with sub clock) 73 MB90880 Series ■ PACKAGE DIMENSIONS 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.0 mm × 14.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.65 g Code (Reference) P-LFQFP100-14×14-0.50 (FPT-100P-M20) 100-pin plastic LQFP (FPT-100P-M20) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part +0.20 26 100 1 25 C 0.20±0.05 (.008±.002) 0.08(.003) M 0.10±0.10 (.004±.004) (Stand off) 0°~8° "A" 0.50(.020) +.008 1.50 –0.10 .059 –.004 (Mounting height) INDEX 0.145±0.055 (.0057±.0022) 2005 -2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-3-3 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest Package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 74 DS07-13743-5E MB90880 Series (Continued) 100-pin plastic QFP Lead pitch 0.65 mm Package width × package length 14.00 × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 31 1 30 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M 0.17±0.06 (.007±.002) "A" ©2002-2008 FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6 C 2002 FUJITSU LIMITED F100008S-c-5-5 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest Package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS07-13743-5E 75 MB90880 Series ■ MAIN CHANGES IN THIS EDITION Page 45 Section ■ ELECTRICAL CHARACTERISTICS 2. Recommended operating conditions 4. AC characteristics (1) Clock timing ratings 50 73 ■ ORDERING INFORMATION Change Results Added “when external bus is in operation” in parameter “Operating temperature” to the table. Changed the footnote *1. “Observe the operating voltage with care. The maximum operating frequency is 25 MHz in MB90F883B(S), MB90F884B (S).” → “The maximum operating frequency is 25 MHz in MB90F883B(S), MB90F884B (S). The maximum operating frequency is 25 MHz in all models when external bus is in operation.” Deleted the part number: MB90F882SPF The vertical lines marked in the left side of the page show the changes. 76 DS07-13743-5E MB90880 Series MEMO DS07-13743-5E 77 MB90880 Series MEMO 78 DS07-13743-5E MB90880 Series MEMO DS07-13743-5E 79 MB90880 Series FUJITSU MICROELECTRONICS LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. 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