FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13716-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90440G Series
MB90443G/F443G/V440G
■ DESCRIPTION
The MB90440G series with FULL-CAN*2 and FLASH ROM is a line of general-purpose, Fujitsu 16-bit microcontrollers specially designed for automotive and industrial applications. Its main features are three on board CAN
Interfaces (generic type) , which conform to V2.0 Part A and Part B, supporting very flexible message buffering.
Thus, more functions than a normal full CAN approach is available.
While inheriting the AT architecture of the F2MC*1 family, the instruction set for the F2MC-16LX CPU core incorporates additional instructions for high-level languages, supports extended addressing modes, and contains
enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation
instructions. In addition, the MB90440G series has as on-chip 32-bit accumulator, which enables processing of
long-word data.
The peripheral resources integrated in the MB90440G series include; an 8/10-bit A/D converter, UARTs (SCI) ,
I/O extended serial interface, 8/16-bit PPG timer, input/output timer (input capture (ICU) , output compare (OCU) ) .
*1 : F2MC stands for FUJITUS Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
*2 : Controller Area Network (CAN) is a license of Robert Bosch GmbH..
■ PACKAGE
100-pin Plastic QFP
FPT-100P-M06
MB90440G Series
■ FEATURES
• Clock
Internal PLL clock multiplication circuit
Base oscillation divided into two or multiplied by one to four
Minimum execution time : 62.5 ns (4 MHz oscillation, PLL clock multiplication multiplier = 4, VCC = 5.0 V)
32 kHz subsystem clock
• Instruction set optimized for controller applications
Supported data types : bit, byte, word, and long-word types
Standard addressing modes : 23 types
Singed multiplication/division and extended RET1 instructions
32-bit accumulator enhancing high-precision operations
• Enhanced high level language (C) and multi-tasking support instructions
Use of a system stack pointer
Symmetrical instruction set and barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed : 4 byte instruction queue
• Enhanced interrupt function : 8 priority levels programmable and 34 causes
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS)
• Internal ROM size and type
FLASH ROM : 128 Kbytes
Internal RAM size : 6 Kbyte and 14 Kbyte (evaluation chip)
• FLASH ROM
Supports automatic programming function, Embedded Algorithm*
Writing command/erase command/erase suspend and resume command
Algorithms completion flag
Hardwire reset vector to show the fixed boot code sector
Can be erased by each sector
Sector protection by external programming voltage
• Low-power consumption (stand-by) modes
Sleep mode (CPU operating clock stops)
Stop mode (Main oscillation stops)
CPU intermittent operation mode
Watch mode
Time-base timer mode
• General-purpose I/O ports : 81 ports
• Timers
Watchdog timer : 1 channel
8/16-bit PPG timer : 8/16-bit × 4 channels
16-bit reload timer : 2 channels
* : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
(Continued)
2
MB90440G Series
(Continued)
• 16-bit I/O timers
16-bit free-run timers : 1 channel
16-bit input capture : 8 channels
16-bit output compare : 4 channels
• Extended I/O serial interfaces : 1 channel
• UART0
Full-duplex, double-buffered (8 bit)
Can be used for clock synchronous and asynchronous transfer (with start/stop bit)
• UART1 (SCI)
Full-duplex, double-buffered (8 bit)
Can be used for clock synchronous and asynchronous serial transfer (extended I/O serial)
• External interrupt inputs : 8 channels
Extended intelligent I/O service (EI2OS) is started by external input and external interrupt generation module
• Delayed interrupt generation module : interrupt request for task switching
• 8/10 bit A/D converter : 8 channels
8/10-bit resolution selectable
Can be started by external trigger input
Conversion time : 6.12 µs
• FULL-CAN interface
3 channels
Conform to V2.0 Part A and Part B
Supports very flexible message buffering (mail-box and FIFO buffering can be mixed)
• External bus interface : maximum 16 Mbyte address space
3
MB90440G Series
■ PRODUCT LINEUP
The following table provides a quick outlook of the MB90440G Series
Part number
MB90443G
MB90F443G
(under
development)
Parameter
MB90V440G
F2MC-16LX CPU
CPU
System clock
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, 1/2 when PLL stops)
Minimum instruction execution time : 62.5 ns (4 MHz osc. PLL ×4)
ROM size
Mask ROM
128 Kbytes
Flash memory
128 Kbytes
External
RAM size
6 Kbytes
6 Kbytes
14 Kbytes
*1
Operating
voltage range
5 V ± 10%
−40 °C to +105 °C
Temperature range
Package
Voltage dedicated for
emulator*2
QFP100
PGA-256
No
UART0
Full duplex double buffer
Supports clock asynchronous/synchronous (with start/stop bits) transfer
Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500 K/1 M/2 Mbps (synchronous) at System clock = 16 MHz
UART1
(SCI)
Full duplex double buffer
Asynchronized (start/stop bits synchronized) and CLK-synchronous communication
Baud rate : 601 bps to 250 kbps (asynchronous)
31.25 kbps to 2 Mbps (synchronous)
Serial IO
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and negative-edge clock synchronization
Baud rate : 31.25 K/62.5 K/125 K/500 K/1 M/2 Mbps at System clock = 16 MHz
8/10 bit
A/D Converter
10-bit or 8-bit resolution
8 input channels
Conversion time : 6.12 µs (per one channel)
16-bit Reload Timer
(2 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function
16-bit
I/O Timer
Signals an interrupt during overflow
Supports Timer Clear during a match with Output Compare (Channel 0)
Operation clock freq. : fsys/22, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.)
16-bit
Output Compare
(4 channels)
Signals an interrupt during a match with 16-bit I/O Timer
Four 16-bit compare registers
A pair of compare registers can be used to generate an output signal
(Continued)
4
MB90440G Series
(Continued)
Part number
Parameter
16-bit
Input Capture
(8 channels)
MB90443G
(under development)
MB90F443G
MB90V440G
Rising edge, falling edge or rising & falling edge sensitive
Four 16-bit capture registers
Signals an interrupt upon external event
Supports 8-bit and 16-bit operation modes
Eight 8-bit reload counters
Eight 8-bit reload registers for L pulse width
8/16-bit
Eight 8-bit reload registers for H pulse width
Programmable Pulse
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
Generator
8-bit prescaler plus 8-bit reload counter
(4 channels)
4 output pins
Operation clock frequency. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = System clock frequency, fosc = Oscillation clock frequency)
CAN Interface
3 channels :
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Supports prioritized 16 message buffers for data and ID
Flexible configuration of acceptance filtering :
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1 Mbps
External Interrupt
(8 channels)
Can be programmed edge detection or level detection
External bus interface
The external access used selective 8-bit bus or 16-bit bus is available.
(External bus mode)
I/O Ports
Virtually all external pins can be used as general purpose I/O
All push-pull outputs and schmitt trigger inputs
Bit-wise programmable as input/output or peripheral signal
32 kHz Subclock
Sub-clock for low power operation
Flash
Memory
Supports automatic programming, Embedded AlgorithmTM
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
*1 : Values with conditions such as the operating frequency (See section “ ELECTRICAL CHARACTERISTICS”) .
*2 : DIP switch S2 when using emulation pad MB2145-507.
The details are referred to hardware manual of MB2145-507.
5
MB90440G Series
■ PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P53/INT6
P54/INT7
P55/ADTG
AVCC
AVR+
AVRAVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
VSS
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P56/TIN0
P57/TOT0
MD0
MD1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P20/A16
P21/A17
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
VSS
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SOT0
P41/SCK0
P42/SIN0
P43/SIN1
P44/SCK1
VCC
P45/SOT1
P46/SOT2
P47/SCK2
C
P50/SIN2
P51/INT4
P52/INT5
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
(TOP VIEW)
(FPT-100P-M06)
6
X0A
X1A
PA0/INT3
RST
P97/RX1
P96/TX1
P95/INT2/RX0
P94/TX0
P93/RX2
P92/TX2
P91/INT1
P90/INT0
P87/TOT1
P87/TIN1
P85/OUT1
P84/OUT0
P83/PPG3
P82/PPG2
P81/PPG1
P80/PPG0
P77/OUT3/IN7
P76/OUT2/IN6
P75/IN5
P74/IN4
P73/IN3
P72/IN2
P71/IN1
P70/IN0
N.C.
MD2
MB90440G Series
■ PIN DESCRIPTION
Pin No.
Pin name
Circuit type
82
83
X0
X1
A
(Oscillation)
High speed oscillator input pins
80
79
X0A
X1A
A
(Oscillation)
Low speed oscillator input pins
77
RST
B
External reset request input
52
N.C.
not connected
P00 to P07
85 to 92
H
AD00 to AD07
P10 to P17
93 to 100
H
AD08 to AD15
P20 to P27
1 to 8
H
A16 to A23
P30
9
H
General I/O port with programmable pullup. This function is enabled in the single-chip mode.
I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled.
General I/O port with programmable pullup. This function is enabled in the single-chip mode.
I/O pins for 8 higher bits of the external address/data bus. This function is enabled when the external bus is enabled.
General I/O port with programmable pullup. This function is enabled in the single-chip mode.
I/O pins of 8 bits for A16 to A23 ot the external address bus. This
function is enabled when the external bus is enabled.
General I/O port with programmable pullup. This function is enabled in the single-chip mode.
ALE
Address latch enable output pin. This function is enabled when the
external bus is enabled.
P31
General I/O port with programmable pullup. This function is enabled in the single-chip mode.
10
12
Function
H
RD
Read strobe output pin for the data bus. This function is enabled
when the external bus is enabled.
P32
General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the WR/WRL pin output is
disabled.
WRL
H
WR
General I/O port with programmable pullup. This function is enabled in the single-chip mode or external bus 8-bit mode or when
WRH pin output is disabled.
P33
13
H
WRH
Write strobe output pin for the data bus. This function is enabled
when the external bus is in enable mode and the WR/WRL pin output is enabled. WRL is used as a write-strobe output pin for 8 lower
bits of the data bus in 16-bit access while WR is used as a writestrobe output pin for 8 bits of the data bus in 8-bit access.
Write strobe output pin for the 8 higher bits of the data bus. This
function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin
is enabled.
(Continued)
7
MB90440G Series
Pin No.
Pin name
Circuit type
P34
14
H
Hold request input pin. This function is enabled when the external
bus is in enable mode and the hold function is enabled.
P35
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when hold function is disabled.
H
HAK
Hold acknowledge output pin. This function is enabled when the external bus is in enable mode and the hold function is enabled.
P36
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when the external ready function is disabled.
16
H
RDY
Ready input pin. This function is enabled when the external bus is
in enable mode and the external ready function is enabled.
P37
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when CLK output is disabled.
17
H
CLK
CLK output pin. This function is enabled when the external bus is in
enable mode and CLK output is enabled.
P40
General I/O port. This function is enabled when serial data output
of UART0 is disabled.
18
G
SOT0
Serial data output pin for UART0. This function is enabled when
UART0 enables serial data output.
P41
General I/O port. This function is enabled when clock output of
UART0 is disabled.
19
G
SCK0
P42
SIN0
SIN1
G
G
G
SCK1
P45
24
G
SOT1
Serial data input pin for UART0. Set the corresponding DDR register to input if this function is used.
General I/O port. This function is always enabled.
P44
22
Serial clock I/O pin for UART0. This function is enabled when
UART0 enables serial clock output.
General I/O port. This function is always enabled.
P43
21
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when hold function is disabled.
HRQ
15
20
Function
Serial data input pin for UART1. Set the corresponding DDR register to input if this function is used.
General I/O port. This function is enabled when serial clock output
of UART1 is disabled.
Serial clock I/O pin for UART1. This function is enabled when
UART1 enables serial clock output.
General I/O port. This function is enabled when serial data output
of UART1 is disabled.
Serial data output pin for UART1. This function is enabled when
UART1 enables serial data output.
(Continued)
8
MB90440G Series
Pin No.
Pin name
Circuit type
General I/O port. This function is enabled when the extended serial
I/O interface disables serial data output.
P46
25
G
SOT2
Serial data output pin for the extended serial I/O interface. This
function is enabled when the extended serial I/O interface enables
serial data output.
P47
General I/O port. This function is enabled when the extended serial
I/O interface disables serial clock output.
26
G
SCK2
P50
28
SIN2
INT4 to INT7
D
ADTG
D
D
E
General I/O ports. The function is enabled when the analog input
enable register specifies port.
Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies A/D.
P64 to P67
General I/O ports. The function is enabled when the analog input
enable register specifies port.
E
AN4 to AN7
P56
TIN0
48
D
D
TOT0
P70 to P75
IN0 to IN5
Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies A/D.
General I/O port. This function is always enabled.
P57
53 to 58
External trigger input pin for the 8/10-bit A/D converter. Set the corresponding DDR register to input if this function is used.
AN0 to AN3
43 to 46
47
External interrupt request input pins for INT4 to INT7. Set the corresponding DDR register to input if this function is used.
General I/O port. This function is always enabled.
P60 to P63
38 to 41
Serial data input pin for the extended serial I/O interface. Set the
corresponidng DDR register to input if this function is used.
General I/O ports. This function is always enabled.
P55
33
Serial clock I/O pin for the extended serial I/O interface. This function is enabled when the extended serial I/O interface enables serial clock output.
General I/O port. This function is always enabled.
P51 to P54
29 to 32
Function
Event input pin for the 16-bit reload timers 0. Set the corresponding
DDR register to input if this function is used.
General I/O port. This function is enabled when the 16-bit reload
timers 0 disables output.
Output pin for the 16-bit reload timers 0. This function is enabled
when the 16-bit reload timers 0 enables output.
General I/O ports. This function is always enabled.
D
Trigger input pins for input captures ICU0 to ICU5. Set the corresponding DDR register to input if this function is used.
(Continued)
9
MB90440G Series
Pin No.
Pin name
Circuit type
General I/O ports. This function is enabled when the OCU disables
output.
P76 to P77
59 to 60
OUT2 to OUT3
D
Trigger input pins for input captures ICU6 and ICU7. Set the corresponiding DDR register to input and prohibit the OCU output if this
function is used.
P80 to P83
General I/O ports. This function is enabled when 8/16-bit PPG timer
disables waveform output.
D
PPG0 to PPG3
Output pins for 8/16-bit PPG timer. This function is enabled when
8/16-bit PPG timer enables waveform output.
P84 to P85
General I/O ports. This function is enabled when the OCU disables
output.
65 to 66
D
OUT0 to OUT1
P86
TIN1
68
D
D
TOT1
P90 to P91
INT0 to INT1
72
D
General I/O port. This function is enabled when the 16-bit reload
timers 0 disables output.
Output pin for the 16-bit reload timers 1. This function is enabled
when the reload timers 1 enables output.
D
External interrupt request input pins for INT0 to INT3. Set the corresponding DDR register to input if this function is used.
General I/O port. This function is enabled when CAN2 disables output.
TX2
TX output pin for CAN2. This function is enabled when CAN2 enables output.
P93
General I/O port. This function is always enabled.
RX2
D
P94
73
74
Input pin for the 16-bit reload timers 1. Set the corresponding DDR
register to input if this function is used.
General I/O ports. This function is always enabled.
P92
71
Event output pins for output compares OCU0 and OCU1. This function is enabled when the OCU enables output.
General I/O port. This function is always enabled.
P87
69 to 70
Event output pins for output compares OCU2 and OCU3. This
function is enabled when the OCU enables output.
IN6 to IN7
61 to 64
67
Function
D
RX input pin for CAN2 interface. When the CAN function is used,
output from the other functions must be stopped.
General I/O port. This function is enabled when CAN0 disables output.
TX0
TX output pin for CAN0. This function is enabled when CAN0 enables output.
P95
General I/O port. This function is always enabled.
INT2
RX0
D
External interrupt request input pin for INT2. Set the corresponding
DDR register to input if this function is used.
RX input pin for CAN0 interface. When the CAN function is used,
output from the other functions must be stopped.
(Continued)
10
MB90440G Series
(Continued)
Pin No.
Pin name
Circuit type
P96
75
76
D
General I/O port. This function is enabled when CAN1 disables output.
TX1
TX output pin for CAN1. This function is enabled when CAN1 enables output.
P97
General I/O port. This function is always enabled.
RX1
D
PA0
78
Function
INT3
RX input pin for CAN1 interface. When the CAN function is used,
output from the other functions must be stopped.
General I/O port. This function is always enabled.
D
External interrupt request input pin for INT2. Set the corresponding
DDR register to input if this function is used.
34
AVCC
Power supply pin for the A/D Converter. This power supply must be
Power supply turned on or off while a voltage higher than or equal to AVCC is applied to VCC.
37
AVSS
Power supply Dedicated ground pin for the A/D Converter
35
AVRH
External reference voltage pin for the A/D Converter. This power
Power supply supply must be turned on or off while a voltage higher than or equal
to AVRH is applied to AVCC.
36
AVRL
Power supply External reference voltage pin for the A/D Converter
49
to 50
MD0
to MD1
C
Input pins for specifying the operating mode. The pins must be directly connected to VCC or Vss.
51
MD2
F
Input pin for specifying the operating mode. The pin must be directly
connected to VCC or Vss.
27
C
This is the power supply stabilization capacitor pin. It should be connected externally to an 0.1 µF ceramic capacitor.
23, 84
VCC
Power supply Voltage (5.0 V) input pin
11, 42
81
VSS
Power supply Voltage (0.0 V) input pin
■ INPUT LEVELS
The input level of ports P00 to P37 can be selected to be either TTL- or CMOS - level. The initial setting is TTL
- level. These settings are global for all P00 to P37, it is not possible to set different levels to each port.
The input level of ports P40 to PA0 can be selected to be either CMOS- or AUTOMOTIVE - level. The initial
setting is CMOS - level. This settings can be done for each port individually.
11
MB90440G Series
■ I/O CIRCUIT TYPE
Circuit
type
Circuit
Remarks
• Oscillation feedback resistor :
1 MΩ approx. (High speed oscillator)
10MΩ approx. (Low speed oscillator)
X1, X1A
osillation feedback
resistor
A
X0,X0A
Standby control signal
• CMOS hysteresis input .
Pull-up resistor : 50 kΩ approx.
B
R (pull-up)
HYS
R
• CMOS hysteresis input
HYS
R
C
VCC
P-ch
• CMOS level output
• CMOS hysteresis input
• Automotive hysteresis input
(See “ INPUT LEVELS”.)
N-ch
D
R
CMOS HYS
R
AUTOM. HYS
(Continued)
12
MB90440G Series
Circuit
type
Circuit
Remarks
• CMOS level output
• CMOS hysteresis input
• Automotive hysteresis input
(See “ INPUT LEVELS”.)
• Analog input
VCC
P-ch
N-ch
E
P-ch
Analog input
N-ch
R
CMOS HYS
R
AUTOM. HYS
CMOS HYS
R
• CMOS hysteresis input
• Pull-down resistor : 50 kΩ approx.
(except FLASH devices)
F
R (pull-down)
VCC
P-ch
• CMOS level output
• CMOS hysteresis input
• Automotive hysteresis input
(See “ INPUT LEVELS”.)
• TTL input (FLASH devices in flash write
mode only)
N-ch
G
R
CMOS HYS
R
AUTOM. HYS
R
T
TTL
(Continued)
13
MB90440G Series
(Continued)
Circuit
type
Circuit
Remarks
VCC
CNTL
VCC
P-ch
H
N-ch
R
CMOS HYS
R
T
14
TTL
• CMOS level output
• CMOS hysteresis input
• TTL hysteresis input
(See “ INPUT LEVELS”.)
• Programmable pullup resistor :
50 kΩ approx.
MB90440G Series
■ HANDLING DEVICES
1. Preventing Latch-up
CMOS IC chips may suffer latch-up under the following conditions :
(1) A voltage higher than VCC or lower than VSS is applied to an input or output pin.
(2) A voltage higher than the rated voltage is applied to between VCC and Vss.
(3) The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
Always take sufficient precautions in using semiconductor devices to avoid this possibility.
Also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage
(VCC) when the analog system power-supply is turned on and off.
2. Handling Unused Input Pins
Do not leave unused input pins open, as doing so may cause misoperation of the device or latch-up leading to
permanent damage. Unused input pins should be pulled up or pulled down through at least 2 kΩ resistance.
Unused I/O pins may be left open in output state, but if such pins are in input state they should be handled in
the same way as input pins.
3. Use of the External Clock
To use the external clock, drive only the X0 pin and leave the X1 pin open.
A diagram of how to use an external clock is shown below.
MB90440G Series
X0
open
X1
4. Precautions for when not using a Sub Clock Signal
If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leave
the X1A pin open.
5. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to
lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in
the ground level, and to conform to the total current rating.
Make sure to connect VCC and VSS pins via lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pins near the device.
VCC
VSS
VCC
VSS
VSS
VCC
MB90440G
Series
VCC
VSS
VSS
VCC
15
MB90440G Series
6. Pull-up/down resistors
The MB90440G Series does not support internal pull-up/down resistors (except pull-up resistors of port 0 to
port 3) . Use external components needed.
7. Crystal Oscillator Circuit
Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via the
shortest distances from X0 and X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make
sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D and D/A converters power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to
AN7) after turning on the digital power supply (VCC) .
Turn off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that AVRH does not exceed AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) .
9. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D and D/A converters to AVCC = VCC, AVSS = AVRH = VSS.
10. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
11. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
µs or more (0.2 V to 2.7 V) .
12. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,
please turn on the power again.
13. Using REALOS
The use of (EI2OS) is not possible with the REALOS real time operation system.
14. Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the freerunning frequency of the automatic oscillating circuit in the PLL circuitly even if the oscillator is out of place or
the clock input is stopped. Performance of this operation, however, cannot be guaranteed.
16
MB90440G Series
■ BLOCK DIAGRAM
X0, X1
X0A, X1A
RST
Clock
Controller
F2MC 16LX
CPU
16 bit
I/O Timer
RAM 6 K
16 bit Input
Capture
8 ch
ROM
128 K
16 bit Output
Compare
4 ch
IN0 to IN5
IN6/OUT2,
IN7/OUT3
OUT0, OUT1
Prescaler
8/16-bit
PPG Timer
4 ch
SOT0
SCK0
UART0
PPG0 to PPG3
SIN0
CAN
Controller 3 ch
Prescaler
RX0 to RX2
TX0 to TX2
SOT1
SCK1
UART1
(SCI)
16-bit Reload
Timer 2 ch
SIN1
TIN0, TIN1
TOT0, TOT1
SCK2
SOT2
Serial I/O
SIN2
F 2 MC-16 Bus
Prescaler
AD00 to AD15
A16 to A23
ALE
RD
External
Bus
Interface
AVCC
AVSS
AN0 to AN7
AVRH
WRL/WR
WRH
HRQ
10-bit ADC
8 ch
HAK
RDY
AVRL
CLK
ADTG
External
Interrupt
Circuit 8 ch
INT0 to INT7
17
MB90440G Series
■ MEMORY MAP
MB90V440G
MB90F443G/
MB90443G (under development)
FFFFFFH
FFFFFFH
ROM (FF bank)
FF0000H
FEFFFFH
ROM (FF bank)
FF0000H
FEFFFFH
ROM (FE bank)
FE0000H
FDFFFF H
ROM (FE bank)
FE0000H
ROM (FD bank)
FD0000H
FCFFFF H
External
Access Memory
ROM (FC bank)
FC0000H
External
Access Memory
00FFFFH
004000H
003FFFH
ROM (Image of
FF bank)
00FFFFH
004000H
003FFFH
Peripheral
Peripheral
003900H
0038FFH
001FF5H
ROM (Image of
FF bank)
003900H
ROM correction
002000H
0018FFH
External
Access Memory
001FF0H
RAM 6 K
RAM 14 K
000100H
0000BFH
000000H
External
Access Memory
000100H
Peripheral
0000BFH
000000H
External
Access Memory
Peripheral
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same address, the table in ROM can be referenced
without using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF4000H and FFFFFFH is visible in bank 00, while the image between FF4000H and
FFFFFFH is visible only in bank FF. Thus, it is recommended that the ROM data table be stored in the area
of FF4000H and FFFFFFH .
18
MB90440G Series
■ I/O MAP
Address
Register
Abbreviation
Read/
Write
Resource
name
Initial value
00H
Port 0 data register
PDR0
R/W
Port 0
XXXXXXXXB
01H
Port 1 data register
PDR1
R/W
Port 1
XXXXXXXXB
02H
Port 2 data register
PDR2
R/W
Port 2
XXXXXXXXB
03H
Port 3 data register
PDR3
R/W
Port 3
XXXXXXXXB
04H
Port 4 data register
PDR4
R/W
Port 4
XXXXXXXXB
05H
Port 5 data register
PDR5
R/W
Port 5
XXXXXXXXB
06H
Port 6 data register
PDR6
R/W
Port 6
XXXXXXXXB
07H
Port 7 data register
PDR7
R/W
Port 7
XXXXXXXXB
08H
Port 8 data register
PDR8
R/W
Port 8
XXXXXXXXB
09H
Port 9 data register
PDR9
R/W
Port 9
XXXXXXXXB
0AH
Port A data register
PDRA
R/W
Port A
_______XB
0BH
Port input levels select register
PILR
R/W
Ports
00000000B
0CH
CAN2 RX/TX pin switching register
CANSWR
R/W
CAN1/2
______00B
0DH to 0FH
Reserved
10H
Port 0 direction register
DDR0
R/W
Port 0
00000000B
11H
Port 1 direction register
DDR1
R/W
Port 1
00000000B
12H
Port 2 direction register
DDR2
R/W
Port 2
00000000B
13H
Port 3 direction register
DDR3
R/W
Port 3
00000000B
14H
Port 4 direction register
DDR4
R/W
Port 4
00000000B
15H
Port 5 direction register
DDR5
R/W
Port 5
00000000B
16H
Port 6 direction register
DDR6
R/W
Port 6
00000000B
17H
Port 7 direction register
DDR7
R/W
Port 7
00000000B
18H
Port 8 direction register
DDR8
R/W
Port 8
00000000B
19H
Port 9 direction register
DDR9
R/W
Port 9
00000000B
1AH
Port A direction register
DDRA
R/W
Port A
_______0B
1BH
Analog input enable register
ADER
R/W
Port 6, A/D
11111111B
1CH
Port 0 pullup control register
PUCR0
R/W
Port 0
00000000B
1DH
Port 1 pullup control register
PUCR1
R/W
Port 1
00000000B
1EH
Port 2 pullup control register
PUCR2
R/W
Port 2
00000000B
1FH
Port 3 pullup control register
PUCR3
R/W
Port 3
00000000B
20H
Serial mode control register 0
UMC0
R/W
21H
Serial status register 0
USR0
R/W
22H
Serial input/output data register 0
UIDR0/UODR0
R/W
23H
Rate and data register 0
URD0
R/W
00000100B
UART0
00010000B
XXXXXXXXB
0000000XB
(Continued)
19
MB90440G Series
Address
Register
Abbreviation
Read/
Write
24H
Serial mode register 1
SMR1
R/W
00000000B
25H
Serial control register 1
SCR1
R/W
00000100B
26H
Serial input/output data register 1
SIDR1/SODR1
R/W
27H
Serial status register 1
SSR1
R/W
28H
UART1 prescaler control register
U1CDCR
R/W
0___1111B
29H
Serial edge selection registor
SES1
R/W
_______0B
2AH
Resource
name
UART1
Initial value
XXXXXXXXB
00001_00B
Reserved
2BH
Serial I/O prescaler
SCDCR
R/W
0___1111B
2CH
Serial mode control register
SMCS
R/W
____0000B
2DH
Serial mode control register
SMCS
R/W
2EH
Serial Data register
SDR
R/W
XXXXXXXXB
2FH
Serial edge selection registor 2
SES2
R/W
_______0B
30H
External interrupt enable register
ENIR
R/W
00000000B
31H
External interrupt request register
EIRR
R/W
External request level setting register
ELVR
R/W
34H
A/D control status register 0
ADCS0
R/W
35H
A/D control status register 1
ADCS1
R/W
36H
A/D data register 0
ADCR0
R
37H
A/D data register 1
ADCR1
R/W
38H
PPG0 operation mode control register
PPGC0
R/W
39H
PPG1 operation mode control register
PPGC1
R/W
3AH
PPG0 and PPG1 clock selection register
PPG01
R/W
32H
33H
3BH
External
interrupt
circuit
00000010B
XXXXXXXXB
00000000B
00000000B
00000000B
A/D
converter
00000000B
XXXXXXXXB
00001_XXB
16-bit Programable Pulse
Generator 0/1
0_000__1B
0_000001B
000000__B
Reserved
3CH
PPG2 operation mode control register
PPGC2
R/W
3DH
PPG3 operation mode control register
PPGC3
R/W
3EH
PPG2 and PPG3 clock selection register
PPG23
R/W
3FH
16-bit Programable Pulse
Generator 2/3
0_000__1B
0_000001B
000000__B
Reserved
40H
PPG4 operation mode control register
PPGC4
R/W
41H
PPG5 operation mode control register
PPGC5
R/W
42H
PPG4 and PPG5 clock selection register
PPG45
R/W
43H
Serial I/O
16-bit Programable Pulse
Generator 4/5
0_000__1B
0_000001B
000000__B
Reserved
(Continued)
20
MB90440G Series
Address
Register
Abbreviation
Read/
Write
Resource
name
44H
PPG6 operation mode control register
PPGC6
R/W
45H
PPG7 operation mode control register
PPGC7
R/W
46H
PPG6 and PPG7 clock selection register
PPG67
R/W
16-bit
Programable
Pulse
Generator 6/7
000000__B
47H to 4BH
Initial value
0_000__1B
0_000001B
Reserved
4CH
Input capture control status 0/1
ICS01
R/W
Input capture 0/1
00000000B
4DH
Input capture control status 2/3
ICS23
R/W
Input capture 2/3
00000000B
4EH
Input capture control status 4/5
ICS45
R/W
Input capture 4/5
00000000B
4FH
Input capture control status 6/7
ICS67
R/W
Input capture 6/7
00000000B
Timer control status register 0
TMCSR0
R/W
Timer register 0/reload register 0
TMR0/
TMRLR0
R/W
Timer control status register 1
TMCSR1
R/W
50H
51H
52H
53H
54H
55H
56H
TMR1/
TMRLR1
R/W
58H
Output compare control status register 0
OCS0
R/W
59H
Output compare control status register 1
OCS1
R/W
5AH
Output compare control status register 2
OCS2
R/W
5BH
Output compare control status register 3
OCS3
R/W
5CH to 6BH
6CH
XXXXXXXXB
00000000B
____0000B
XXXXXXXXB
XXXXXXXXB
Output
compare 0/1
Output
compare 2/3
0000__00B
___00000B
0000__00B
___00000B
Reserved for CAN 2 Interface
Timer data register
TCDT
R/W
6EH
Timer control status register
TCCS
R/W
6FH
ROM mirror function selection register
ROMM
R/W
6DH
____0000B
XXXXXXXXB
16-bit reload
timer 1
Timer register 1/Reload register 1
57H
00000000B
16-bit
reload
timer 0
70H to 7FH
Reserved for CAN 0 Interface
80H to 8FH
Reserved for CAN 1 Interface
90H to 9DH
Prohibited area
00000000B
I/O timer
00000000B
00000000B
ROM mirror
function selection module
_______1B
9EH
Program address detection control
status register
PACSR
R/W
Address match
detection
function
00000000B
9FH
Delayed interrupt/release register
DIRR
R/W
Delayed
interrupt generation module
_______0B
(Continued)
21
MB90440G Series
Address
Register
Abbreviation
Read/
Write
Resource name
Initial value
A0H
Low-power consumption mode
control register
LPMCR
R/W
Low power
consumption
(stand-by) mode
00011000B
A1H
Clock selection register
CKSCR
R/W
Low power
consumption
(stand-by) mode
11111100B
A2H to A4H
Prohibited area
A5H
Automatic ready function select
register
ARSR
W
A6H
External address output control
register
HACR
W
A7H
Bus control signal selection register
ECSR
W
A8H
Watchdog timer control register
WDTC
R/W
Watchdog
timer
XXXXX111B
A9H
Time base timer control register
TBTC
R/W
Time base
timer
1- -00100B
AAH
Watch timer control register
WTC
R/W
Watch timer
1X000000B
R/W
Flash Memory
000X0000B
ABH to ADH
AEH
0011__00B
External bus pin
00000000B
0000000_B
Prohibited area
Flash memory control status register
(Flash only, otherwise reserved)
AFH
FMCS
Prohibited area
B0H
Interrupt control register 00
ICR00
R/W
00000111B
B1H
Interrupt control register 01
ICR01
R/W
00000111B
B2H
Interrupt control register 02
ICR02
R/W
00000111B
B3H
Interrupt control register 03
ICR03
R/W
00000111B
B4H
Interrupt control register 04
ICR04
R/W
00000111B
B5H
Interrupt control register 05
ICR05
R/W
00000111B
B6H
Interrupt control register 06
ICR06
R/W
00000111B
B7H
Interrupt control register 07
ICR07
R/W
B8H
Interrupt control register 08
ICR08
R/W
B9H
Interrupt control register 09
ICR09
R/W
00000111B
BAH
Interrupt control register 10
ICR10
R/W
00000111B
BBH
Interrupt control register 11
ICR11
R/W
00000111B
BCH
Interrupt control register 12
ICR12
R/W
00000111B
BDH
Interrupt control register 13
ICR13
R/W
00000111B
BEH
Interrupt control register 14
ICR14
R/W
00000111B
BFH
Interrupt control register 15
ICR15
R/W
00000111B
COH to FFH
Interrupt
controller
00000111B
00000111B
External
(Continued)
22
MB90440G Series
(Continued)
Address
Register
Abbreviation
1FF0H
1FF1H
Program address detection register 0
PADR0
Read/
Write
XXXXXXXXB
R/W
XXXXXXXXB
R/W
1FF3H
R/W
Program address detection register 1
PADR1
1FF5H
Initial value
R/W
1FF2H
1FF4H
Resource name
Address match
detection function
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
Address
Register
Abbreviation
Read/
Write
3900H
Reload register L
PRLL0
R/W
3901H
Reload register H
PRLH0
R/W
3902H
Reload register L
PRLL1
R/W
3903H
Reload register H
PRLH1
R/W
XXXXXXXXB
3904H
Reload register L
PRLL2
R/W
XXXXXXXXB
3905H
Reload register H
PRLH2
R/W
3906H
Reload register L
PRLL3
R/W
3907H
Reload register H
PRLH3
R/W
XXXXXXXXB
3908H
Reload register L
PRLL4
R/W
XXXXXXXXB
3909H
Reload register H
PRLH4
R/W
390AH
Reload register L
PRLL5
R/W
390BH
Reload register H
PRLH5
R/W
XXXXXXXXB
390CH
Reload register L
PRLL6
R/W
XXXXXXXXB
390DH
Reload register H
PRLH6
R/W
390EH
Reload register L
PRLL7
R/W
390FH
Reload register H
PRLH7
R/W
XXXXXXXXB
XXXXXXXXB
3910H to
3917H
Resource name
Initial value
XXXXXXXXB
16-bit programable
pulse
generator 0/1
16-bit programable
pulse
generator 2/3
16-bit programable
pulse
generator 4/5
16-bit programable
pulse
generator 6/7
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved
3918H
Input capture register 0
IPCP0
R
3919H
Input capture register 0
IPCP0
R
391AH
Input capture register 1
IPCP1
R
391BH
Input capture register 1
IPCP1
R
XXXXXXXXB
391CH
Input capture register 2
IPCP2
R
XXXXXXXXB
391DH
Input capture register 2
IPCP2
R
391EH
Input capture register 3
IPCP3
R
391FH
Input capture register 3
IPCP3
R
Input captue 0/1
Input captue 2/3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
23
MB90440G Series
(Continued)
Address
Register
Abbreviation
Read/
Write
3920H
Input capture register 4
IPCP4
R
3921H
Input capture register 4
IPCP4
R
3922H
Input capture register 5
IPCP5
R
3923H
Input capture register 5
IPCP5
R
XXXXXXXXB
3924H
Input capture register 6
IPCP6
R
XXXXXXXXB
3925H
Input capture register 6
IPCP6
R
3926H
Input capture register 7
IPCP7
R
3927H
Input capture register 7
IPCP7
R
XXXXXXXXB
3928H
Output compare register 0
OCCP0
R/W
XXXXXXXXB
3929H
Output compare register 0
OCCP0
R/W
392AH
Output compare register 1
OCCP1
R/W
392BH
Output compare register 1
OCCP1
R/W
XXXXXXXXB
392CH
Output compare register 2
OCCP2
R/W
XXXXXXXXB
392DH
Output compare register 2
OCCP2
R/W
392EH
Output compare register 3
OCCP3
R/W
392FH
Output compare register 3
OCCP3
R/W
3930H to
39FFH
Reserved
3A00H to
3AFFH
Reserved for CAN 0 Interface
3B00H to
3BFFH
Reserved for CAN 0 Interface
3C00H to
3CFFH
Reserved for CAN 1 Interface
3D00H to
3DFFH
Reserved for CAN 1 Interface
3E00H to
3EFFH
Reserved for CAN 2 Interface
3F00H to
3FFFH
Reserved for CAN 2 Interface
Resource name
Initial value
XXXXXXXXB
Input captue 4/5
Input captue 6/7
Output compare 0/1
Output compare 2/3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
• Meaning of abbreviations used for reading and writing
R/W : Read and Write enabled
R
: Read only
W
: Write only
• Explanation of initial values
0
: The bit is initialized to 0.
1
: The bit is initialized to 1.
X
: The initial value of the bit is undefined.
_
: The bit is not used. Its initial value is undefined.
Note : Addresses in the range 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions
of the MCU. A read access to these reserved addresses results reading “X” and any write access should
not be performed.
24
MB90440G Series
■ CAN CONTROLLER
The MB90440G series contains three generic CAN controllers (CAN0, CAN1, CAN2) .
The CAN controller has the following features :
• Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats
• Supports transmission of data frames by receiving remote frames
• 16 transmission/reception message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbps to 1 Mbps (when input clock is at 16 MHz)
List of Control Registers
Address
CAN0
CAN1
CAN2
000070H 000080H 00005CH
000071H 000081H 00005DH
000072H 000082H 00005EH
000073H 000083H
00005FH
000074H 000084H
000060H
000075H 000085H
000061H
000076H 000086H
000062H
000077H 000087H
000063H
000078H 000088H
000064H
000079H 000089H
000065H
00007AH 00008AH 000066H
00007BH 00008BH 000067H
00007CH 00008CH 000068H
00007DH 00008DH 000069H
00007EH 00008EH 00006AH
00007FH 00008FH 00006BH
003B00H 003D00H 003F00H
003B01H 003D01H 003F01H
003B02H 003D02H 003F02H
003B03H 003D03H 003F03H
003B04H 003D04H 003F04H
003B05H 003D05H 003F05H
Register
Abbreviation
Read/
Write
Initial Value
Message buffer valid register
BVALR
R/W
00000000
00000000B
Transmit request register
TREQR
R/W
00000000
00000000B
Transmit cancel register
TCANR
W
00000000
00000000B
Transmit complete register
TCR
R/W
00000000
00000000B
Receive complete register
RCR
R/W
00000000
00000000B
Remote request receiving
register
RRTRR
R/W
00000000
00000000B
Receive overrun register
ROVRR
R/W
00000000
00000000B
Receive interrupt enable
register
RIER
R/W
00000000
00000000B
Control status register
CSR
R/W, R
00---000 0----01B
Last event indicator register
LEIR
R/W
-------- 0000000B
Receive/transmit error
counter
RTEC
R
00000000
00000000B
(Continued)
25
MB90440G Series
(Continued)
Address
CAN0
CAN1
CAN2
003B06H 003D06H
003F06H
003B07H 003D07H
003F07H
003B08H 003D08H
003F08H
003B09H 003D09H
003F09H
003B0AH 003D0AH 003F0AH
003B0BH 003D0BH 003F0BH
Register
Abbreviation
Read/
Write
Initial Value
Bit timing register
BTR
R/W
-1111111
11111111B
IDE register
IDER
R/W
XXXXXXXX
XXXXXXXXB
Transmit RTR register
TRTRR
R/W
00000000
00000000B
RFWTR
R/W
XXXXXXXX
XXXXXXXXB
TIER
R/W
00000000
00000000B
003B0CH 003D0CH 003F0CH Remote frame receive waiting
register
003B0DH 003D0DH 003F0DH
003B0EH 003D0EH 003F0EH
003B0FH 003D0FH 003F0FH
003B10H 003D10H
003F10H
003B11H 003D11H
003F11H
003B12H 003D12H
003F12H
003B13H 003D13H
003F13H
003B14H 003D14H
003F14H
003B15H 003D15H
003F15H
003B16H 003D16H
003F16H
003B17H 003D17H
003F17H
003B18H 003D18H
003F18H
003B19H 003D19H
003F19H
003B1AH 003D1AH 003F1AH
003B1BH 003D1BH 003F1BH
26
Transmit interrupt enable
register
Acceptance mask select
register
XXXXXXXX
XXXXXXXXB
AMSR
R/W
XXXXXXXX
XXXXXXXXB
XXXXXXXX
XXXXXXXXB
Acceptance mask register 0
AMR0
R/W
XXXXX--XXXXXXXXB
XXXXXXXX
XXXXXXXXB
Acceptance mask register 1
AMR1
R/W
XXXXX--XXXXXXXXB
MB90440G Series
List of Message Buffers (ID Registers)
Address
CAN0
CAN1
CAN2
003A00H 003C00H 003E00H
to
to
to
003A1FH 003C1FH 003E1FH
Register
Abbreviation
Read/
Write
Initial Value
RAM area
R/W
XXXXXXXXB
to
XXXXXXXXB
003A20H 003C20H 003E20H
003A21H 003C21H 003E21H
003A22H 003C22H 003E22H
XXXXXXXX
XXXXXXXXB
ID register 0
IDR0
R/W
XXXXX--XXXXXXXXB
003A23H 003C23H 003E23H
003A24H 003C24H 003E24H
003A25H 003C25H 003E25H
003A26H 003C26H 003E26H
XXXXXXXX
XXXXXXXXB
ID register 1
IDR1
R/W
XXXXX--XXXXXXXXB
003A27H 003C27H 003E27H
003A28H 003C28H 003E28H
003A29H 003C29H 003E29H
003A2AH 003C2AH 003E2AH
XXXXXXXX
XXXXXXXXB
ID register 2
IDR2
R/W
XXXXX--XXXXXXXXB
003A2BH 003C2BH 003E2BH
003A2CH 003C2CH 003E2CH
003A2DH 003C2DH 003E2DH
003A2EH 003C2EH 003E2EH
XXXXXXXX
XXXXXXXXB
ID register 3
IDR3
R/W
XXXXX--XXXXXXXXB
003A2FH 003C2FH 003E2FH
003A30H 003C30H 003E30H
003A31H 003C31H 003E31H
003A32H 003C32H 003E32H
XXXXXXXX
XXXXXXXXB
ID register 4
IDR4
R/W
XXXXX--XXXXXXXXB
003A33H 003C33H 003E33H
003A34H 003C34H 003E34H
003A35H 003C35H 003E35H
003A36H 003C36H 003E36H
XXXXXXXX
XXXXXXXXB
ID register 5
IDR5
R/W
XXXXX--XXXXXXXXB
003A37H 003C37H 003E37H
003A38H 003C38H 003E38H
003A39H 003C39H 003E39H
003A3AH 003C3AH 003E3AH
003A3BH 003C3BH 003E3BH
XXXXXXXX
XXXXXXXXB
ID register 6
IDR6
R/W
XXXXX--XXXXXXXXB
(Continued)
27
MB90440G Series
Address
CAN0
CAN1
CAN2
Register
Abbreviation
Read/
Write
003A3CH 003C3CH 003E3CH
003A3DH 003C3DH 003E3DH
003A3EH 003C3EH 003E3EH
XXXXXXXX
XXXXXXXXB
ID register 7
IDR7
R/W
XXXXX--XXXXXXXXB
003A3FH 003C3FH 003E3FH
003A40H 003C40H 003E40H
003A41H 003C41H 003E41H
003A42H 003C42H 003E42H
XXXXXXXX
XXXXXXXXB
ID register 8
IDR8
R/W
XXXXX--XXXXXXXXB
003A43H 003C43H 003E43H
003A44H 003C44H 003E44H
003A45H 003C45H 003E45H
003A46H 003C46H 003E46H
XXXXXXXX
XXXXXXXXB
ID register 9
IDR9
R/W
XXXXX--XXXXXXXXB
003A47H 003C47H 003E47H
003A48H 003C48H 003E48H
003A49H 003C49H 003E49H
003A4AH 003C4AH 003E4AH
XXXXXXXX
XXXXXXXXB
ID register 10
IDR10
R/W
XXXXX--XXXXXXXXB
003A4BH 003C4BH 003E4BH
003A4CH 003C4CH 003E4CH
003A4DH 003C4DH 003E4DH
003A4EH 003C4EH 003E4EH
XXXXXXXX
XXXXXXXXB
ID register 11
IDR11
R/W
XXXXX--XXXXXXXXB
003A4FH 003C4FH 003E4FH
003A50H 003C50H 003E50H
003A51H 003C51H 003E51H
003A52H 003C52H 003E52H
XXXXXXXX
XXXXXXXXB
ID register 12
IDR12
R/W
XXXXX--XXXXXXXXB
003A53H 003C53H 003E53H
003A54H 003C54H 003E54H
003A55H 003C55H 003E55H
003A56H 003C56H 003E56H
XXXXXXXX
XXXXXXXXB
ID register 13
IDR13
R/W
XXXXX--XXXXXXXXB
003A57H 003C57H 003E57H
003A58H 003C58H 003E58H
003A59H 003C59H 003E59H
003A5AH 003C5AH 003E5AH
003A5BH 003C5BH 003E5BH
Initial Value
XXXXXXXX
XXXXXXXXB
ID register 14
IDR14
R/W
XXXXX--XXXXXXXXB
(Continued)
28
MB90440G Series
(Continued)
Address
CAN0
CAN1
CAN2
Register
Abbreviation
Read/
Write
003A5CH 003C5CH 003E5CH
003A5DH 003C5DH 003E5DH
003A5EH 003C5EH 003E5EH
Initial Value
XXXXXXXX
XXXXXXXXB
ID register 15
IDR15
R/W
XXXXX--XXXXXXXXB
003A5FH 003C5FH 003E5FH
List of Message Buffers (DLC Registers and Data Registers)
Address
CAN0
CAN1
CAN2
003A60H 003C60H 003E60H
003A61H 003C61H 003E61H
003A62H 003C62H 003E62H
003A63H 003C63H 003E63H
003A64H 003C64H 003E64H
003A65H 003C65H 003E65H
003A66H 003C66H 003E66H
003A67H 003C67H 003E67H
003A68H 003C68H 003E68H
003A69H 003C69H 003E69H
003A6AH 003C6AH 003E6AH
003A6BH 003C6BH 003E6BH
003A6CH 003C6CH 003E6CH
003A6DH 003C6DH 003E6DH
003A6EH 003C6EH 003E6EH
003A6FH 003C6FH 003E6FH
003A70H 003C70H 003E70H
003A71H 003C71H 003E71H
003A72H 003C72H 003E72H
003A73H 003C73H 003E73H
003A74H 003C74H 003E74H
003A75H 003C75H 003E75H
003A76H 003C76H 003E76H
003A77H 003C77H 003E77H
Register
Abbreviation
Read/
Write
Initial Value
DLC register 0
DLCR0
R/W
----XXXXB
DLC register 1
DLCR1
R/W
----XXXXB
DLC register 2
DLCR2
R/W
----XXXXB
DLC register 3
DLCR3
R/W
----XXXXB
DLC register 4
DLCR4
R/W
----XXXXB
DLC register 5
DLCR5
R/W
----XXXXB
DLC register 6
DLCR6
R/W
----XXXXB
DLC register 7
DLCR7
R/W
----XXXXB
DLC register 8
DLCR8
R/W
----XXXXB
DLC register 9
DLCR9
R/W
----XXXXB
DLC register 10
DLCR10
R/W
----XXXXB
DLC register 11
DLCR11
R/W
----XXXXB
(Continued)
29
MB90440G Series
Address
Register
Abbreviation
Read/
Write
Initial Value
DLC register 12
DLCR12
R/W
----XXXXB
DLC register 13
DLCR13
R/W
----XXXXB
DLC register 14
DLCR14
R/W
----XXXXB
DLC register 15
DLCR15
R/W
----XXXXB
003A80H 003C80H 003E80H
to
to
to
003A87H 003C87H 003E87H
Data register 0 (8 bytes)
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
003A88H 003C88H 003E88H
to
to
to
003A8FH 003C8FH 003E8FH
Data register 1 (8 bytes)
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
003A90H 003C90H 003E90H
to
to
to
003A97H 003C97H 003E97H
Data register 2 (8 bytes)
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
003A98H 003C98H 003E98H
to
to
to
003A9FH 003C9FH 003E9FH
Data register 3 (8 bytes)
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
003AA0H 003CA0H 003EA0H
to
to
to
003AA7H 003CA7H 003EA7H
Data register 4 (8 bytes)
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
003AA8H 003CA8H 003EA8H
to
to
to
003AAFH 003CAFH 003EAFH
Data register 5 (8 bytes)
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
003AB0H 003CB0H 003EB0H
to
to
to
003AB7H 003CB7H 003EB7H
Data register 6 (8 bytes)
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN0
CAN1
CAN2
003A78H 003C78H 003E78H
003A79H 003C79H 003E79H
003A7AH 003C7AH 003E7AH
003A7BH 003C7BH 003E7BH
003A7CH 003C7CH 003E7CH
003A7DH 003C7DH 003E7DH
003A7EH 003C7EH 003E7EH
003A7FH 003C7FH 003E7FH
(Continued)
30
MB90440G Series
(Continued)
Address
Register
Abbreviation
Read/
Write
Initial Value
003AB8H 003CB8H 003EB8H
to
to
to
003ABFH 003CBFH 003EBFH
Data register 7 (8 bytes)
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
003AC0H 003CC0H 003EC0H
to
to
to
003AC7H 003CC7H 003EC7H
Data register 8 (8 bytes)
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
003AC8H 003CC8H 003EC8H
to
to
to
003ACFH 003CCFH 003ECFH
Data register 9 (8 bytes)
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
003AD0H 003CD0H 003ED0H
to
to
to
003AD7H 003CD7H 003ED7H
Data register 10 (8 bytes)
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
003AD8H 003CD8H 003ED8H
to
to
to
003ADFH 003CDFH 003EDFH
Data register 11 (8 bytes)
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
003AE0H 003CE0H 003EE0H
to
to
to
003AE7H 003CE7H 003EE7H
Data register 12 (8 bytes)
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
003AE8H 003CE8H 003EE8H
to
to
to
003AEFH 003CEFH 003EEFH
Data register 13 (8 bytes)
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
003AF0H
to
003AF7H
003EF0H
to
003EF7H
Data register 14 (8 bytes)
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
003AF8H 003CF8H 003EF8H
to
to
to
003AFFH 003CFFH 003EFFH
Data register 15 (8 bytes)
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN0
CAN1
003CF0H
to
003CF7H
CAN2
31
MB90440G Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt vector
Interrupt control register
EI2OS
support
Number
Address
Number
Address
Reset
N/A
#08
FFFFDCH
INT9 instruction
N/A
#09
FFFFD8H
Exception processing
N/A
#10
FFFFD4H
CAN 0 Receive
N/A
#11
FFFFD0H
CAN 0 Transmit/Node status
N/A
#12
FFFFCCH
ICR00
0000B0H
CAN 1 Receive
N/A
#13
FFFFC8H
CAN 1 Transmit/Node status
N/A
#14
FFFFC4H
ICR01
0000B1H
External interrupt (INT0/INT1)
*1
#15
FFFFC0H
N/A
#16
FFFFBCH
ICR02
0000B2H
16-bit reload timer 0
*1
#17
FFFFB8H
8/10-bit A/D converter
*1
#18
FFFFB4H
ICR03
0000B3H
N/A
#19
FFFFB0H
External interrupt (INT2/INT3)
*1
#20
FFFFACH
ICR04
0000B4H
Serial I/O
*1
#21
FFFFA8H
N/A
#22
FFFFA4H
ICR05
0000B5H
Input capture 0
*1
#23
FFFFA0H
External interrupt (INT4/INT5)
*1
#24
FFFF9CH
ICR06
0000B6H
CAN 2 Receive
N/A
#25
FFFF98H
CAN 2 Transmit/Node status
N/A
#26
FFFF94H
ICR07
0000B7H
External interrupt (INT6/INT7)
*1
#27
FFFF90H
Monitoring timer
N/A
#28
FFFF8CH
ICR08
0000B8H
Input capture 1
*1
#29
FFFF88H
Input capture 2/3
*1
#30
FFFF84H
ICR09
0000B9H
N/A
#31
FFFF80H
Output compare 0
*1
#32
FFFF7CH
ICR10
0000BAH
Output compare 1
*1
#33
FFFF78H
Input capture 4/5
*1
#34
FFFF74H
ICR11
0000BBH
Output compare 2/3-input capture 6/7
*1
#35
FFFF70H
16-bit reload timer 1
*1
#36
FFFF6CH
ICR12
0000BCH
UART 0 Receive
*2
#37
FFFF68H
UART 0 Transmit
*1
#38
FFFF64H
ICR13
0000BDH
UART 1 Receive
*2
#39
FFFF60H
UART 1 Transmit
*1
#40
FFFF5CH
ICR14
0000BEH
Interrupt cause
Timebase timer
Input/output timer
8/16-bit PPG timer 0/1/2/3
8/16-bit PPG timer 4/5/6/7
(Continued)
32
MB90440G Series
(Continued)
Interrupt vector
EI2OS
support
Number
Address
Flash memory
N/A
#41
FFFF58H
Delayed interrupt generation module
N/A
#42
FFFF54HH
Interrupt cause
*1
*2
Interrupt control register
Number
Address
ICR15
0000BFH
: The interrupt request flag is cleared by the EI2OS interrupt clear signal.
: The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.
Notes : • N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal.
• For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request
flags are cleared by the EI2OS interrupt clear signal.
• At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same
interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by
hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the
first event. So it is recommended not to use the EI2OS for this interrupt number.
• If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control
register (ICR) is asserted. This means that different interrupt causes share the same EI2OS descriptor
which should be unique for each interrupt cause. For this reason, when one interrupt cause uses the
EI2OS, the other interrupt should be disabled.
33
MB90440G Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
(VSS = AVSS = 0.0 V)
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
VCC = AVCC *1
AVRH,
AVRL
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVRH / AVRL,
AVRH ≥ AVRL*1
Input voltage
VI
VSS − 0.3
VSS + 6.0
V
*2
Output voltage
VO
VSS − 0.3
VSS + 6.0
V
*2
ICLAMP
− 2.0
+ 2.0
mA
*6
ΣICLAMP
20
mA
*6
IOL
15
mA
*3
“L” level average output current
IOLAV
4
mA
*4
“L” level total maximum output current
ΣIOL
100
mA
ΣIOLAV
50
mA
*5
IOH
−15
mA
*3
“H” level average output current
IOHAV
−4
mA
*4
“H” level total maximum output current
ΣIOH
−100
mA
ΣIOHAV
−50
mA
*5
500
mW
MB90F443G
400
mW
MB90F443G (under
development)
+ 105
+ 150
°C
Power supply voltage
Maximum clamp current
Total maximum clamp current
“L” level maximum output current
“L” level total average output current
“H” level maximum output current
“H” level total average output current
Power consumption
PD
Operating temperature
TA
−40
Tstg
−55
Storage temperature
°C
*1 : AVCC, AVRH, and AVRL shall never exceed VCC. AVRH, AVRL shall never exceed AVCC. Also, AVRL shall never
exceed AVRH.
*2 : VI and VO shall never exceed VCC + 0.3 V. VI shall never exceed the specified ratings. However if the maximum
current to/ from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating.
*3 : Maximum output current specifies the peak value of the corresponding pin.
*4 : The average output current specifies the average current of corresponding pins within 100 ms.
(operation current × operation rate = average value)
*5 : The total average output current specifies the average current of all corresponding pins within 100 ms.
(operation current × operation rate = average value)
*6 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0
• Use within recommended operating conditions.
• Use at DC voltage (current) .
(Continued)
34
MB90440G Series
(Continued)
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that +B signal is applied the input current to the
microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
• Sample recommended circuits.
• Input/Output equivalent circuits
Protective diode
Vcc
P-ch
Limiting
resistance
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
35
MB90440G Series
2. Recommended Operating Conditions
Parameter
Symbol
(VSS = AVSS = 0.0 V)
Value
Unit
Remarks
Min
Typ
Max
4.5
5.0
5.5
V
Under normal operation
3.0
5.5
V
Retains status at the time of operation stop
*
Power supply voltage
VCC,
AVCC
Smoothing capacitor
CS
0.022
0.1
1.0
µF
Operating temperature
TA
−40
+105
°C
* : Use a ceramic capacitor or capacitor of better AC characteristics. Capacitor at the VCC should be greater than
this capacitor.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
• C pin connection circuit
C
CS
36
MB90440G Series
3. DC Characteristics
Parameter
Symbol
Pin
(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Condition
Unit Remarks
Min
Typ
Max
VIHS
CMOS Hysteresis
input pin
0.8 VCC
VCC +
0.3
V
VIHA
AUTOMOTIVE
input pin
0.8 VCC
V
VIH
TTL input pin
2.0
V
VIHM
MD input pin
VCC −
0.3
VCC +
0.3
V
VILS
CMOS Hysteresis
input pin
VSS −
0.3
0.2 VCC
V
VILA
AUTOMOTIVE
input pin
0.5 VCC
V
VIL
TTL input pin
0.8
V
VILM
MD input pin
VSS −
0.3
VSS +
0.3
V
Output H voltage
VOH
All output pins
VCC = 4.5 V,
IOH = −4.0 mA
VCC −
0.5
V
Output L voltage
VOL
All output pins
VCC = 4.5 V,
IOL = 4.0 mA
0.4
V
Input leak current
IIL
VCC = 5.5 V,
VSS < VI < VCC
−5
+5
µA
Input H voltage
Input L voltage
(Continued)
37
MB90440G Series
(Continued)
Parameter
(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
VCC = 5.0 V
Internal frequency : 16 MHz,
At normal operating
45
60
mA
VCC = 5.0 V
Internal frequency : 16 MHz,
At flash programming /
erasing
50
70
mA
ICCS
VCC = 5.0 V
Internal frequency : 16 MHz,
At sleep
13
22
mA
ICCL
VCC = 5.0 V
Internal frequency : 8 kHz,
At sub operation
TA = + 25 °C
50
100
µA
MB90443G
(under development)
300
500
µA
MB90F443G
ICCLS
VCC = 5.0 V
Internal frequency : 8 kHz,
At sub sleep
TA = + 25 °C
15
40
µA
ICCT
VCC = 5.0 V
Internal frequency : 8 kHz,
At watch mode
TA = + 25 °C
7
25
µA
ICTS
VCC = 5.0 V
Internal frequency : 2 MHz,
At timer base timer mode
TA = + 25 °C
ICCH
At stop mode, TA = + 25 °C
5
20
µA
CIN
Other than
AVCC, AVSS,
AVRH,
AVRL, C,
VCC, VSS
10
15
pF
Pull-up
resistance
RUP
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
25
50
100
kΩ
Pull-down
resistance
RDOWN
MD2
25
50
100
kΩ
ICC
Power supply
current*
Input capacity
VCC
* : The power supply current is measured with an external clock.
38
Value
600 1200
µA
MB90440G Series
4. AC Characteristics
(1) Clock Timing
Parameter
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rise and fall
time
Internal operating clock
frequency
Internal operating clock
cycle time
(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Unit
Remarks
Min
Typ
Max
Symbol
Pin
fC
X0, X1
3
16
MHz
fCL
X0A, X1A
32.768
kHz
tCYL
X0, X1
62.5
333
ns
tLCYL
X0A, X1A
30.5
µs
PWH, PWL
X0
10
ns
PWLH, PWLL
X0A
15.2
µs
tCR, tCF
X0
5
ns
fCP
1.5
16
MHz When using main clock
fLCP
8.192
kHz When using sub-clock
tCP
62.5
666
ns
When using main clock
tLCP
122.1
µs
When using sub-clock
Duty ratio is about 30%
to 70%.
When using external
clock
• Clock Timing
tCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
tLCYL
0.8 VCC
X0A
0.2 VCC
PWLH
PWLL
tCF
tCR
39
MB90440G Series
• Guaranteed PLL operation range
Relationship between internal operation clock frequency and power supply voltage
Guaranteed operation range
Power supply voltage VCC (V)
5.5
4.5
Guaranteed PLL operation range
1.5
8
16
Internal clock fCP (MHz)
Relationship between oscillation frequency and internal operating clock frequency
×4
Internal clock fCP (MHz)
16
×3
×2
×1
12
9
8
Not multiplied
4
3
4
8
16
Oscillation frequency fC (MHz)
The AC ratings are measured for the following measurement reference voltages.
• Input signal waveform
CMOS Hysteresis Input Pin
Output Pin
0.8 VCC
2.4 V
0.2 VCC
0.8 V
TTL Input Pin
2.0 V
0.8 V
AUTOMOTIVE Input Pin
0.8 VCC
0.5 VCC
40
• Output signal waveform
MB90440G Series
(2) Clock Output Timing
Parameter
Symbol
Cycle time
tCYC
CLK ↑ → CLK ↓
tCHCL
Pin
CLK
(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Condition
Unit
Remarks
Min
Max
VCC = 5 V ± 10%
62.5
ns
20
ns
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
41
MB90440G Series
(3) Reset Input Timing and Hardware Stand-by Input Timing
(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Max
16 tCP
Reset input time
tRSTL
RST
Oscillation time of oscillator +
100 µs + 16 tCP
ns
Under normal operation
In stop mode,
watch mode,
sub-clock mode,
sub-sleep mode
Note: • Oscillator oscillation time is the time that amplitude reached 90%. For a crystal oscillator, the oscillation
time is between several ms to tens of ms; for a FAR/ceramic oscillator, the oscillation time is between
hundreds of µs to several ms, and for an external clock the oscillation time is 0 ms.
• Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm.
• Under normal operation :
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode :
tRSTL
RST
0.2 VCC
X0
Internal operation
clock
0.2 VCC
90% of
amplitude
Oscillator
oscillation time
100 µs +
16 tCP
Oscillation setting time
Instruction execution
Internal reset
42
MB90440G Series
(4) Power-on Reset
Parameter
Symbol
Pin
Power supply rising time
tR
VCC
Power supply cut-off time
tOFF
VCC
(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Condition
Unit
Remarks
Min
Max
0.05
30
ms
*
50
ms
Due to repeated operations
* : VCC must be kept lower than 0.2 V before power-on.
Note : The above values are used for causing a power-on reset.
Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn the
power supply on using the above values.
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power on reset. We
recommend to raise the voltage smoothly to suppress fluctuation during operation,
as shown in the figure below. Perform while not using the PLL clock. However, if
voltage drops are within 1 V/s, you can operate while using the PLL clock.
VCC
3V
VSS
RAM data Hold
We recommend rising speed
of the supply voltage at 50
mV/ms or slower
43
MB90440G Series
(5) Bus Timing (Read)
Parameter
44
Symbol
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Pin
Unit
Remarks
Min
Max
ALE pulse width
tLHLL
ALE
tCP / 2 − 20
ns
Valid address → ALE ↓ time
tAVLL
ALE, A16 to A23,
AD00 to AD15
tCP / 2 − 20
ns
ALE ↓ → Address valid time
tLLAX
ALE,
AD00 to AD15
tCP / 2 − 15
ns
Valid address → RD ↓ time
tAVRL
A16 to A23,
AD00 to AD15,
RD
tCP − 15
ns
Valid address → Valid data
input
tAVDV
A16 to A23,
AD00 to AD15
5 tCP / 2 − 60
ns
RD pulse width
tRLRH
RD
3 tCP / 2 − 20
ns
RD ↓ → Valid data input
tRLDV
RD,
AD00 to AD15
3 tCP / 2 − 60
ns
RD ↑ → Data hold time
tRHDX
RD,
AD00 to AD15
0
ns
RD ↓ → ALE ↑ time
tRHLH
RD, ALE
tCP / 2 − 15
ns
RD ↑ → Address valid time
tRHAX
RD, A16 to A23
tCP / 2 − 10
ns
Valid address → CLK ↑ time
tAVCH
A16 to A23,
AD00 to AD15,
CLK
tCP / 2 − 20
ns
RD ↓ → CLK ↑ time
tRLCH
RD, CLK
tCP / 2 − 20
ns
ALE ↓ → RD ↓ time
tLLRL
ALE, RD
tCP / 2 − 15
ns
MB90440G Series
• Bus Timing (Read)
tAVCH
tRLCH
2.4 V
2.4 V
CLK
tAVLL
ALE
tLLAX
tRHLH
2.4 V
2.4 V
2.4 V
tLHLL
0.8 V
tAVRL
tRLRH
2.4 V
RD
0.8 V
tLLRL
tRHAX
2.4 V
2.4 V
0.8 V
0.8 V
A23 to A16
tRLDV
tAVDV
AD15 to AD00
2.4 V
tRHDX
2.4 V
0.8 VCC
Address
0.8 V
0.8 VCC
Read data
0.8 V
0.2 VCC
0.2 VCC
45
MB90440G Series
(6) Bus Timing (Write)
Parameter
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Pin
Unit Remarks
Min
Max
Symbol
Valid address → WR ↓ time
tAVWL
A16 to A23,
AD00 to AD15,
WR
tCP − 15
ns
WR pulse width
tWLWH
WR
3 tCP / 2 − 20
ns
Valid data output → WR ↑ time
tDVWH
AD00 to AD15,
WR
3 tCP / 2 − 20
ns
WR ↑ → Data hold time
tWHDX
AD00 to AD15,
WR
20
ns
WR ↑ → Address valid time
tWHAX
A16 to A23, WR
tCP / 2 − 10
ns
WR ↑ → ALE ↑ time
tWHLH
WR, ALE
tCP / 2 − 15
ns
WR ↓ → CLK ↑ time
tWLCH
WR, CLK
tCP / 2 − 20
ns
• Bus Timing (Write)
tWLC
2.4 V
CLK
tWHL
2.4 V
ALE
tAVWL
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
2.4 V
2.4 V
0.8 V
0.8 V
A23 to A16
tDVWH
AD15 to AD00
2.4 V
Address
0.8 V
46
2.4 V
tWHDX
2.4 V
Write data
0.8 V
0.8 V
MB90440G Series
(7) Ready Input Timing
Parameter
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Unit
Remarks
Min
Max
Symbol
Pin
RDY setup time
tRYHS
RDY
45
ns
RDY hold time
tRYHH
RDY
0
ns
Note : If the RDY setup time is insufficient, use the auto-ready function.
• Ready Input Timing
2.4 V
CLK
ALE
RD/WR
tRYHS
RDY
no WAIT is used.
RDY
When WAIT is used
(1 cycle).
0.8 VCC
tRYHH
0.8 VCC
0.2 VCC
47
MB90440G Series
(8) Hold Timing
Parameter
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Pin
Unit
Remarks
Min
Max
Symbol
Pin floating → HAK ↓ time
tXHAL
HAK
30
tCP
ns
HAK ↑ → Pin valid time
tHAHV
HAK
tCP
2 tCP
ns
Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
• Hold Timing
2.4 V
HAK
0.8 V
tXHAL
Each pin
48
2.4 V
0.8 V
tHAHV
High impedance
2.4 V
0.8 V
MB90440G Series
(9) UART0/1, Serial I/O Timing
Parameter
Symbol
Pin
tSCYC
SCK0 to
SCK2
SCK ↓ → SOT delay time
tSLOV
SCK0 to
SCK2,
SOT0 to
SOT2
Valid SIN → SCK ↑
tIVSH
SCK0 to
SCK2,
SIN0 to SIN2
SCK ↑ → valid SIN hold time
tSHIX
SCK0 to
SCK2,
SIN0 to SIN2
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Condition
Unit
Remarks
Min
Max
8 tCP
ns
–80
+80
ns
100
ns
60
ns
SCK0 to
SCK2
4 tCP
ns
tSLSH
SCK0 to
SCK2
4 tCP
ns
SCK ↓ → SOT delay time
tSLOV
SCK0 to
SCK2,
SOT0 to
SOT2
150
ns
Valid SIN → SCK ↑
tIVSH
SCK0 to
SCK2,
SIN0 to SIN2
60
ns
SCK ↑ → valid SIN hold time
tSHIX
SCK0 to
SCK2,
SIN0 to SIN2
60
ns
Serial clock cycle time
An output pin of
internal sift clock
mode
CL = 80 pF + 1 TTL.
An output pin of
external sift clock
mode
CL = 80 pF + 1 TTL.
Notes : • AC ratings in CLK synchronous mode.
• CL is load capacitance value connected to pins when testing.
49
MB90440G Series
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External Shift Clock Mode
tSLSH
SCK
0.2 VCC
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
50
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
MB90440G Series
(10) Timer Related Resource Input Timing
Parameter
Input pulse width
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Condition
Unit
Remarks
Min
Max
Symbol
Pin
tTIWH
TIN0, TIN1
tTIWL
IN0 to IN7
4 tCP
ns
• Timer Input Timing
0.8 VCC
TIN0, TIN1
IN0 to IN7
0.8 VCC
0.2 VCC
tTIWH
0.2 VCC
tTIWL
51
MB90440G Series
(11) Timer Related Resource Output Timing
Parameter
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Condition
Unit Remarks
Min
Max
Symbol
Pin
tTO
TOT0 to TOT1,
PPG0 to PPG3
CLK ↑ → TOUT
transition time
30
ns
• Timer Output Timing
2.4 V
CLK
2.4 V
TOUT
0.8 V
tTO
(12) Trigger Input Timing
Parameter
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Condition
Unit
Remarks
Min
Max
Symbol
Pin
tTRGH
tTRGL
INT0 to INT7,
ADTG
Input pulse width
5 tCP
ns
normal operation
1
µs
stop mode
• Trigger Input Timing
0.8 VCC
INT0 to INT7
ADTG
52
0.8 VCC
0.2 VCC
tTRGH
0.2 VCC
tTRGL
MB90440G Series
5. A/D Converter
• Electrical Characteristics
(VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, 3.0 V ≤ AVRH − AVRL, TA = −40 °C to +105 °C)
Value
Parameter
Symbol Pin
Unit
Remarks
Min
Typ
Max
Resolution
10
bit
Total error
±5.0
LSB
Nonlinearity error
±2.5
LSB
Differential linearity error
±1.9
LSB
Zero transition voltage
VOT
AN0 to
AN7
AVRL −
3.5 LSB
AVRL +
0.5 LSB
AVRL +
4.5 LSB
V
Full scale transition voltage
VFST
AN0 to
AN7
AVRH −
6.5 LSB
AVRH –
1.5 LSB
AVRH +
1.5 LSB
V
Compare time
66 tCP
ns
Sampling time
32 tCP
ns
Analog port input current
IAIN
AN0 to
AN7
10
µA
Analog input voltage
VAIN
AN0 to
AN7
AVRL
AVRH
V
AVRH
AVRL +
2.7 LSB
AVCC
V
AVRL
0
AVRH −
2.7 LSB
V
IA
AVCC
2
6
mA
IAH
AVCC
5
µA
Reference voltage
Power supply current
Reference voltage supply
current
IR
AVRH
0.9
1.3
mA
IRH
AVRH
5
µA
Offset between channels
AN0 to
AN7
4
LSB
1 LSB = (AVRH
− AVRL) / 1024
[V]
Machine clock of
16 MHz
*
*
* : Specifies the power supply current (VCC = AVCC = AVRH = 5.0 V) when the A/D converter is inactive and the CPU
has been stopped.
53
MB90440G Series
• A/D Converter Glossary
Resolution
: Analog changes that are identifiable with the A/D converter
Linearity error
: The deviation of the straight line connecting the zero transition point
( “00 0000 0000” to “00 0000 0001” ) with the full-scale transition point
( “11 1111 1110” to “11 1111 1111” ) from actual conversion characteristics.
Differential
linearity error
: The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value.
Total error
: The difference between the actual value and the theoretical value, which includes
zero-transition error/full-scale transition error, and linearity error.
Total error
3FF
3FE
1.5 LSB
Actual conversion
characteristics
Digital output
3FD
{1 LSB × (N − 1) + 0.5 LSB}
004
VNT
(measured value)
003
Actual conversion
characteristics
Theoretical characteristics
002
001
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB x (N − 1) + 0.5 LSB}
1 LSB
1 LSB = (theoretical value) AVRH − AVRL [V]
1024
VOT (theoretical value) = AVRL + 0.5 LSB [V]
Total error of digital output N =
[LSB]
VFST (theoretical value) = AVRH − 1.5 LSB [V]
VNT : The voltage at a transition of digital output from (N − 1) to N.
(Continued)
54
MB90440G Series
(Continued)
Linearity error
Differential linearity error
Theoretical
characteristics
3FF
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
Digital output
3FD
N+1
VFST
(measured
value)
VNT
(measured
value)
004
Actual conversion
characteristics
003
Digital output
3FE
Actual conversion
characteristics
N
V (N + 1) T
(measured
value)
VNT (measured value)
N−1
002
Theoretical characteristics
001
Actual conversion
characteristics
N−2
VOT (measured value)
AVRL
AVRH
AVRL
AVRH
Analog input
Analog input
Linearity error of digital output N =
Differential linearity error of digital output N =
1 LSB =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N+1) T − VNT
1 LSB
VFST − VOT
1022
[LSB]
−1 LSB [LSB]
[V]
VOT : Voltage at transition of digital output 000H to 001H.
VFST : Voltage at transition of digital output 3FEH to 3FFH.
55
MB90440G Series
• Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions :
Output impedance values of the external circuit of about 5 kΩ or lower are recommended.
If external capacitors are used, a capacitance of several thousand times the internal capacitor value is recommended in order to minimize the effect of voltage distribution between the external and internal capacitor.
Note: If the output impedance of the external circuit is too high, the sampling time for analog voltages may not be
sufficient (sampling period = 2.00 µs @ machine clock of 16 MHz) . The output impedance of the external
circuit can be set to approx. 15kΩ or lower , when the sampling period is set to 4.00 µs.
• Analog Input Circuit Model
Comparator
R
Analog input
C
MB90F443G, MB90V440G
MB90443G
(Under development)
R =: 3.2 kΩ,
C =: 30 pF
R =: 2.6 kΩ,
C =: 28 pF
• About Error
The smaller the absolute value of | AVRH − AVRL | is, the greater the relative error is.
6. Flash Memory Program/Erase Characteristics
Parameter
Condition
Sector erase time
Chip erase time
TA = + 25 °C
VCC = 5.0 V
Word (16 bit width)
programming time
Erase/Program cycle
56
Value
Unit
Remarks
15
s
Excludes 00H programming prior
erasure
5
s
Excludes 00H programming prior
erasure
16
3,600
µs
Excludes system-level overhead
10,000
cycle
Min
Typ
Max
1
MB90440G Series
■ EXAMPLE CHARACTERISTICS
• “H” Level Output Voltage
• “L” Level Output Voltage
VOH – IOH
VOL – IOL
(Vcc = 4.5 V, Ta = +25˚C)
4.5
0.8
4
0.7
3.5
0.6
VOL [mV]
VOH [V]
3
2.5
(VCC = 4.5 V, Ta = +25˚C)
0.5
0.4
2
0.3
1.5
0.2
1
0.1
0.5
0
0.0
-2.0
-4.0
-6.0
IOH [mA]
-8.0
-10.0
0
0.0
2.0
4.0
6.0
8.0
10.0
IOL [mA]
57
MB90440G Series
• Power Supply Current (FLASH)
Iccs – Vcc
Icc – Vcc
(Ta = +25˚C)
(Ta = +25˚C)
20
50
fcp = 16 MHz
fcp = 16 MHz
18
45
16
40
fcp = 12 MHz
fcp = 12 MHz
14
fcp = 10 MHz
30
Iccs [mA]
Icc [mA]
35
fcp = 8 MHz
25
fcp = 10 MHz
12
fcp = 8 MHz
10
8
20
15
6
fcp = 4 MHz
10
4
fcp = 2 MHz
5
2
0
2.0
0
2.0
3.0
4.0
5.0
6.0
fcp = 4 MHz
7.0
fcp = 2 MHz
3.0
4.0
5.0
7.0
Vcc [V]
Vcc [V]
ICTS – VCC
ICCH – VCC
(Ta = +25˚C)
(fcp = 2 MHz, Ta = +25˚C)
600
6.0
20
18
500
16
14
ICCT [ A]
ICTS [ A]
400
300
12
10
8
200
6
4
100
2
0
0
2.0
3.0
4.0
5.0
6.0
7.0
2.0
3.0
4.0
5.0
Vcc [V]
Vcc [V]
58
6.0
7.0
MB90440G Series
■ ORDERING INFORMATION
Part number
MB90443GPF (under development)
MB90F443GPF
MB90V440GCR
Package
Remarks
100-pin Plastic QFP
(FPT-100P-M06)
256-pin Ceramic PGA
(PGA-256C-A01)
For evaluation
59
MB90440G Series
■ PACKAGE DIMENSIONS
100-pin Plastic QFP
(FPT-100P-M06)
Note : Pins width and pins thickness include plating thickness.
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8°
31
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
2001 FUJITSU LIMITED F100008S-c-4-4
Dimensions in mm (inches)
60
MB90440G Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0204
FUJITSU LIMITED Printed in Japan